diff options
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 11 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 14 |
3 files changed, 19 insertions, 8 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9698a0111ef..22beb0e00d1 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -116,6 +116,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v) case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_is_indexed_draw: case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_base_instance: @@ -2460,6 +2461,7 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld, } case nir_intrinsic_load_first_vertex: + case nir_intrinsic_load_is_indexed_draw: unreachable("lowered by brw_nir_lower_vs_inputs"); default: diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 16b0d86814f..a624deb6d2a 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -266,6 +266,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, case nir_intrinsic_load_base_instance: case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_instance_id: + case nir_intrinsic_load_is_indexed_draw: case nir_intrinsic_load_draw_id: { b.cursor = nir_after_instr(&intrin->instr); @@ -293,11 +294,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir, nir_intrinsic_set_component(load, 3); break; case nir_intrinsic_load_draw_id: - /* gl_DrawID is stored right after gl_VertexID and friends - * if any of them exist. + case nir_intrinsic_load_is_indexed_draw: + /* gl_DrawID and IsIndexedDraw are stored right after + * gl_VertexID and friends if any of them exist. */ nir_intrinsic_set_base(load, num_inputs + has_sgvs); - nir_intrinsic_set_component(load, 0); + if (intrin->intrinsic == nir_intrinsic_load_draw_id) + nir_intrinsic_set_component(load, 0); + else + nir_intrinsic_set_component(load, 1); break; default: unreachable("Invalid system value intrinsic"); diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index e583c549204..898df90225f 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2833,6 +2833,13 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, nr_attribute_slots++; } + /* gl_DrawID and IsIndexedDraw share its very own vec4 */ + if (shader->info.system_values_read & + (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) | + BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) { + nr_attribute_slots++; + } + if (shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) prog_data->uses_basevertex = true; @@ -2857,12 +2864,9 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)) prog_data->uses_instanceid = true; - /* gl_DrawID has its very own vec4 */ if (shader->info.system_values_read & - BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) { - prog_data->uses_drawid = true; - nr_attribute_slots++; - } + BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) + prog_data->uses_drawid = true; /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in |