summaryrefslogtreecommitdiffstats
path: root/src/intel/vulkan
diff options
context:
space:
mode:
Diffstat (limited to 'src/intel/vulkan')
-rw-r--r--src/intel/vulkan/anv_blorp.c2
-rw-r--r--src/intel/vulkan/anv_device.c6
-rw-r--r--src/intel/vulkan/anv_image.c57
-rw-r--r--src/intel/vulkan/anv_private.h4
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c4
5 files changed, 37 insertions, 36 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 9ab291eabec..a1c359cf461 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -168,7 +168,7 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = row_pitch,
+ .row_pitch_B = row_pitch,
.usage = ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_RENDER_TARGET_BIT,
.tiling_flags = ISL_TILING_LINEAR_BIT);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4219a073d2d..2286df6331a 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2279,7 +2279,7 @@ VkResult anv_AllocateMemory(
const uint32_t i915_tiling =
isl_tiling_to_i915_tiling(image->planes[0].surface.isl.tiling);
int ret = anv_gem_set_tiling(device, mem->bo->gem_handle,
- image->planes[0].surface.isl.row_pitch,
+ image->planes[0].surface.isl.row_pitch_B,
i915_tiling);
if (ret) {
anv_bo_cache_release(device, &device->bo_cache, mem->bo);
@@ -2897,9 +2897,9 @@ anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state state,
isl_buffer_fill_state(&device->isl_dev, state.map,
.address = anv_address_physical(address),
.mocs = device->default_mocs,
- .size = range,
+ .size_B = range,
.format = format,
- .stride = stride);
+ .stride_B = stride);
anv_state_flush(device, state);
}
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index a3aecb93901..b0d8c560adb 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -135,24 +135,25 @@ get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
static void
add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
{
- assert(surf->isl.size > 0); /* isl surface must be initialized */
+ assert(surf->isl.size_B > 0); /* isl surface must be initialized */
if (image->disjoint) {
- surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment);
+ surf->offset = align_u32(image->planes[plane].size,
+ surf->isl.alignment_B);
/* Plane offset is always 0 when it's disjoint. */
} else {
- surf->offset = align_u32(image->size, surf->isl.alignment);
+ surf->offset = align_u32(image->size, surf->isl.alignment_B);
/* Determine plane's offset only once when the first surface is added. */
if (image->planes[plane].size == 0)
image->planes[plane].offset = image->size;
}
- image->size = surf->offset + surf->isl.size;
- image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset;
+ image->size = surf->offset + surf->isl.size_B;
+ image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
- image->alignment = MAX2(image->alignment, surf->isl.alignment);
+ image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
- surf->isl.alignment);
+ surf->isl.alignment_B);
}
@@ -249,7 +250,7 @@ add_aux_state_tracking_buffer(struct anv_image *image,
const struct anv_device *device)
{
assert(image && device);
- assert(image->planes[plane].aux_surface.isl.size > 0 &&
+ assert(image->planes[plane].aux_surface.isl.size_B > 0 &&
image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
/* Compressed images must be tiled and therefore everything should be 4K
@@ -348,8 +349,8 @@ make_surface(const struct anv_device *dev,
.levels = vk_info->mipLevels,
.array_len = vk_info->arrayLayers,
.samples = vk_info->samples,
- .min_alignment = 0,
- .row_pitch = anv_info->stride,
+ .min_alignment_B = 0,
+ .row_pitch_B = anv_info->stride,
.usage = usage,
.tiling_flags = tiling_flags);
@@ -377,8 +378,8 @@ make_surface(const struct anv_device *dev,
.levels = vk_info->mipLevels,
.array_len = vk_info->arrayLayers,
.samples = vk_info->samples,
- .min_alignment = 0,
- .row_pitch = anv_info->stride,
+ .min_alignment_B = 0,
+ .row_pitch_B = anv_info->stride,
.usage = usage,
.tiling_flags = ISL_TILING_ANY_MASK);
@@ -413,7 +414,7 @@ make_surface(const struct anv_device *dev,
} else if (dev->info.gen == 8 && vk_info->samples > 1) {
anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ");
} else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_hiz_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl);
@@ -439,7 +440,7 @@ make_surface(const struct anv_device *dev,
likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
if (allow_compression) {
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_ccs_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl, 0);
@@ -457,7 +458,7 @@ make_surface(const struct anv_device *dev,
anv_perf_warn(dev->instance, image,
"This image format doesn't support rendering. "
"Not allocating an CCS buffer.");
- image->planes[plane].aux_surface.isl.size = 0;
+ image->planes[plane].aux_surface.isl.size_B = 0;
return VK_SUCCESS;
}
@@ -480,7 +481,7 @@ make_surface(const struct anv_device *dev,
}
} else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) {
assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
- assert(image->planes[plane].aux_surface.isl.size == 0);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
ok = isl_surf_get_mcs_surf(&dev->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].aux_surface.isl);
@@ -498,14 +499,14 @@ make_surface(const struct anv_device *dev,
*/
assert((MAX2(image->planes[plane].surface.offset,
image->planes[plane].aux_surface.offset) +
- (image->planes[plane].aux_surface.isl.size > 0 ?
- image->planes[plane].aux_surface.isl.size :
- image->planes[plane].surface.isl.size)) <=
+ (image->planes[plane].aux_surface.isl.size_B > 0 ?
+ image->planes[plane].aux_surface.isl.size_B :
+ image->planes[plane].surface.isl.size_B)) <=
(image->planes[plane].offset + image->planes[plane].size));
- if (image->planes[plane].aux_surface.isl.size) {
+ if (image->planes[plane].aux_surface.isl.size_B) {
/* assert(image->planes[plane].fast_clear_state_offset == */
- /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
+ /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
assert(image->planes[plane].fast_clear_state_offset <
(image->planes[plane].offset + image->planes[plane].size));
}
@@ -766,7 +767,7 @@ void anv_GetImageSubresourceLayout(
assert(__builtin_popcount(subresource->aspectMask) == 1);
layout->offset = surface->offset;
- layout->rowPitch = surface->isl.row_pitch;
+ layout->rowPitch = surface->isl.row_pitch_B;
layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
@@ -783,7 +784,7 @@ void anv_GetImageSubresourceLayout(
layout->size = layout->rowPitch * anv_minify(image->extent.height,
subresource->mipLevel);
} else {
- layout->size = surface->isl.size;
+ layout->size = surface->isl.size_B;
}
}
@@ -824,7 +825,7 @@ anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
/* If there is no auxiliary surface allocated, we must use the one and only
* main buffer.
*/
- if (image->planes[plane].aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
return ISL_AUX_USAGE_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
@@ -948,7 +949,7 @@ anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
/* If there is no auxiliary surface allocated, there are no fast-clears */
- if (image->planes[plane].aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
return ANV_FAST_CLEAR_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
@@ -1058,7 +1059,7 @@ anv_image_fill_surface_state(struct anv_device *device,
* the primary surface. The shadow surface will be tiled, unlike the main
* surface, so it should get significantly better performance.
*/
- if (image->planes[plane].shadow_surface.isl.size > 0 &&
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
isl_format_is_compressed(view.format) &&
(flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
assert(isl_format_is_compressed(surface->isl.format));
@@ -1093,9 +1094,9 @@ anv_image_fill_surface_state(struct anv_device *device,
assert(aux_usage == ISL_AUX_USAGE_NONE);
isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
.address = anv_address_physical(address),
- .size = surface->isl.size,
+ .size_B = surface->isl.size_B,
.format = ISL_FORMAT_RAW,
- .stride = 1,
+ .stride_B = 1,
.mocs = device->default_mocs);
state_inout->address = address,
state_inout->aux_address = ANV_NULL_ADDRESS;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d15a91dd014..60f40c7e2ae 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2615,7 +2615,7 @@ anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
* Subsurface of an anv_image.
*/
struct anv_surface {
- /** Valid only if isl_surf::size > 0. */
+ /** Valid only if isl_surf::size_B > 0. */
struct isl_surf isl;
/**
@@ -2764,7 +2764,7 @@ anv_image_aux_levels(const struct anv_image * const image,
VkImageAspectFlagBits aspect)
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- return image->planes[plane].aux_surface.isl.size > 0 ?
+ return image->planes[plane].aux_surface.isl.size_B > 0 ?
image->planes[plane].aux_surface.isl.levels : 0;
}
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a9a8a41ac9d..099c30f3d66 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -948,7 +948,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- if (image->planes[plane].shadow_surface.isl.size > 0 &&
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
/* This surface is a linear compressed image with a tiled shadow surface
* for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
@@ -3760,7 +3760,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
if (GEN_GEN < 10 &&
(att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
- image->planes[0].aux_surface.isl.size > 0 &&
+ image->planes[0].aux_surface.isl.size_B > 0 &&
iview->planes[0].isl.base_level == 0 &&
iview->planes[0].isl.base_array_layer == 0) {
if (att_state->aux_usage != ISL_AUX_USAGE_NONE) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 06:38:06 +0000