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-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 82959f3abf6..88cc13b580a 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -646,11 +646,12 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
*
* The PRM is wrong, though. The width and height must be programmed to
* actual framebuffer's width and height, even when neither depth buffer
- * nor stencil buffer is present.
+ * nor stencil buffer is present. Also, D16_UNORM is not allowed to
+ * be combined with a stencil buffer so we use D32_FLOAT instead.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
.SurfaceType = SURFTYPE_2D,
- .SurfaceFormat = D16_UNORM,
+ .SurfaceFormat = D32_FLOAT,
.Width = fb->width - 1,
.Height = fb->height - 1,
.StencilWriteEnable = has_stencil);