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-rw-r--r--src/intel/vulkan/gen8_pipeline.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index ecb8f6d7b09..e8a067851cc 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -227,6 +227,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
+ .StencilBufferWriteEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],