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-rw-r--r--src/intel/vulkan/gen7_pipeline.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 5c04fb749cc..d6d5ce6778f 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -54,7 +54,7 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
.CullMode = vk_to_gen_cullmode[info->cullMode],
/* uint32_t LineEndCapAntialiasingRegionWidth; */
- .ScissorRectangleEnable = !(extra && extra->disable_scissor),
+ .ScissorRectangleEnable = !(extra && extra->use_rectlist),
/* uint32_t MultisampleRasterizationMode; */
/* bool LastPixelEnable; */