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-rw-r--r--src/intel/vulkan/anv_private.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 62c563294f5..aff076a55d9 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1747,6 +1747,13 @@ enum anv_pipe_bits {
* we would have to CS stall on every flush which could be bad.
*/
ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
+
+ /* This bit does not exist directly in PIPE_CONTROL. It means that render
+ * target operations are ongoing. Some operations like copies on the
+ * command streamer might need to be aware of this to trigger the
+ * appropriate stall before they can proceed with the copy.
+ */
+ ANV_PIPE_RENDER_TARGET_WRITES = (1 << 22),
};
#define ANV_PIPE_FLUSH_BITS ( \