diff options
Diffstat (limited to 'src/intel/tools/tests/gen9')
84 files changed, 7393 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen9/add.asm b/src/intel/tools/tests/gen9/add.asm new file mode 100644 index 00000000000..5d751c29ab0 --- /dev/null +++ b/src/intel/tools/tests/gen9/add.asm @@ -0,0 +1,40 @@ +add(8) g124<1>F g7<8,8,1>D 1D { align1 1Q }; +add(16) g120<1>F g11<8,8,1>D 1D { align1 1H }; +add(16) g4<1>F g1<0,1,0>F -g1.4<0,1,0>F { align1 1H }; +add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; +add(16) g3<1>D g18<8,8,1>D g12<8,8,1>D { align1 1H }; +add(16) g6<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; +add(32) g10<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all }; +add(8) g2<1>D g96<8,8,1>D -1023D { align1 1Q }; +add(8) g4<1>F g5.6<0,1,0>F g7.2<0,1,0>F { align1 1Q }; +add(8) g53<1>DF g49<4,4,1>DF g51<4,4,1>DF { align1 1Q }; +add.sat(16) g5<1>UD g3<8,8,1>UD 0x00000001UD { align1 1H }; +add(1) g125.3<1>UD g0.3<0,1,0>UD g7<0,1,0>UD { align1 WE_all 1N }; +add(8) a0<1>UW g34<16,8,2>UW 0x0080UW { align1 1Q }; +add(8) g8<1>DF g2<0,1,0>DF g3.2<0,1,0>DF { align1 2Q }; +add(16) a0<1>UW g3<16,8,2>UW 0x0040UW { align1 1H }; +add.sat.le.f0.0(8) g125<1>F -g6<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +add.z.f0.0(8) g8<1>F g2<0,1,0>F -g2.4<0,1,0>F { align1 1Q }; +add.z.f0.0(16) g3<1>F g2<0,1,0>F -g2.1<0,1,0>F { align1 1H }; +add(8) g3<1>UD g2<8,8,1>UD 0xffffffffUD { align1 1Q }; +(+f0.0) add(8) g15<1>D -g15<8,8,1>D 31D { align1 1Q }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000200UD { align1 WE_all 1N }; +add.sat(8) g124<1>F g7<8,8,1>F -g6<8,8,1>F { align1 1Q }; +add(8) g8<1>UD g6<8,8,1>D 0x00000001UD { align1 1Q }; +add(16) g11<1>UD g9<8,8,1>D 0x00000001UD { align1 1H }; +(+f0.0) add(16) g8<1>D -g8<8,8,1>D 31D { align1 1H }; +add.sat(16) g126<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; +add.sat(8) g124<1>F g17<8,8,1>D 1D { align1 1Q }; +add(16) g114<1>D g118<8,8,1>D g116<8,8,1>D { align1 2H }; +add.z.f0.0(16) null<1>D g120<8,8,1>D 1D { align1 1H }; +add.z.f0.0(16) null<1>D g116<8,8,1>D 1D { align1 2H }; +add.z.f0.0(8) g3<1>D g5<8,8,1>D g4<8,8,1>D { align1 1Q }; +add(16) g20<1>UD g17<8,8,1>UD 1D { align1 1H }; +add(8) g7<1>F -g6<4>.xyxyF g6<4>.zwzwF { align16 1Q }; +add(16) g9<1>F -g7<4>.xyxyF g7<4>.zwzwF { align16 1H }; +add(8) g7<1>UD g2<8,8,1>UD -g6<8,8,1>UD { align1 WE_all 1Q }; +add.le.f0.0(16) g1<1>D g3.1<0,1,0>D -g6<8,8,1>D { align1 1H }; +add.sat(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; +add(1) g14<1>UD g14<0,1,0>UD 0x00000001UD { align1 WE_all 3N }; +add(8) g25<1>Q g22<4,4,1>Q -g24<4,4,1>Q { align1 1Q }; +add(8) g12<1>Q g5<4,4,1>Q -g11<4,4,1>Q { align1 2Q }; diff --git a/src/intel/tools/tests/gen9/add.expected b/src/intel/tools/tests/gen9/add.expected new file mode 100644 index 00000000000..438b6f14325 --- /dev/null +++ b/src/intel/tools/tests/gen9/add.expected @@ -0,0 +1,40 @@ +40 00 60 00 e8 0a 80 2f e0 00 8d 0e 01 00 00 00 +40 00 80 00 e8 0a 00 2f 60 01 8d 0e 01 00 00 00 +40 00 80 00 e8 3a 80 20 20 00 00 3a 30 40 00 00 +40 00 60 00 4c 12 70 20 60 00 8d 16 08 00 08 00 +40 00 80 00 28 0a 60 20 40 02 8d 0a 80 01 8d 00 +40 00 80 00 4c 12 c0 20 28 00 28 36 10 10 00 11 +40 00 a0 00 4c 12 40 21 28 00 28 36 10 10 00 11 +40 00 60 00 28 0a 40 20 00 0c 8d 0e 01 fc ff ff +40 00 60 00 e8 3a 80 20 b8 00 00 3a e8 00 00 00 +40 00 60 00 c8 32 a0 26 20 06 69 32 60 06 69 00 +40 00 80 80 08 02 a0 20 60 00 8d 06 01 00 00 00 +40 00 00 00 0c 02 ac 2f 0c 00 00 02 e0 00 00 00 +40 00 60 00 40 12 00 22 40 04 ae 16 80 00 80 00 +40 10 60 00 c8 32 00 21 40 00 00 32 70 00 00 00 +40 00 80 00 40 12 00 22 60 00 ae 16 40 00 40 00 +40 00 60 86 e8 3a a0 2f c0 40 8d 3e 00 00 00 3f +40 00 60 01 e8 3a 00 21 40 00 00 3a 50 40 00 00 +40 00 80 01 e8 3a 60 20 40 00 00 3a 44 40 00 00 +40 00 60 00 08 02 60 20 40 00 8d 06 ff ff ff ff +40 00 61 00 28 0a e0 21 e0 41 8d 0e 1f 00 00 00 +40 00 00 00 04 00 00 22 00 02 00 06 00 02 00 00 +40 00 60 80 e8 3a 80 2f e0 00 8d 3a c0 40 8d 00 +40 00 60 00 08 0a 00 21 c0 00 8d 06 01 00 00 00 +40 00 80 00 08 0a 60 21 20 01 8d 06 01 00 00 00 +40 00 81 00 28 0a 00 21 00 41 8d 0e 1f 00 00 00 +40 00 80 80 e8 3a c0 2f 40 00 00 3a 50 00 00 00 +40 00 60 80 e8 0a 80 2f 20 02 8d 0e 01 00 00 00 +40 20 80 00 28 0a 40 2e c0 0e 8d 0a 80 0e 8d 00 +40 00 80 01 20 0a 00 20 00 0f 8d 0e 01 00 00 00 +40 20 80 01 20 0a 00 20 80 0e 8d 0e 01 00 00 00 +40 00 60 01 28 0a 60 20 a0 00 8d 0a 80 00 8d 00 +40 00 80 00 08 02 80 22 20 02 8d 0e 01 00 00 00 +40 01 60 00 e8 3a ef 20 c4 40 64 3a ce 00 6e 00 +40 01 80 00 e8 3a 2f 21 e4 40 64 3a ee 00 6e 00 +40 00 60 00 0c 02 e0 20 40 00 8d 02 c0 40 8d 00 +40 00 80 06 28 0a 20 20 64 00 00 0a c0 40 8d 00 +40 00 60 80 08 02 40 21 20 01 8d 06 01 00 00 00 +40 10 00 00 0c 02 c0 21 c0 01 00 06 01 00 00 00 +40 00 60 00 28 4b 20 23 c0 02 69 4a 00 43 69 00 +40 10 60 00 28 4b 80 21 a0 00 69 4a 60 41 69 00 diff --git a/src/intel/tools/tests/gen9/and.asm b/src/intel/tools/tests/gen9/and.asm new file mode 100644 index 00000000000..2f5d123fc84 --- /dev/null +++ b/src/intel/tools/tests/gen9/and.asm @@ -0,0 +1,29 @@ +and(8) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1Q }; +and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H }; +and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q }; +and(16) g18<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H }; +and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N }; +and.nz.f0.0(8) null<1>UD g36<8,8,1>UD g37<8,8,1>UD { align1 1Q }; +and.nz.f0.0(16) null<1>UD g70<8,8,1>UD g72<8,8,1>UD { align1 1H }; +and.z.f0.0(16) g21<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1H }; +and(8) g61<1>UD g79<8,8,1>UD g32.1<8,4,2>UD { align1 2Q }; +and(8) g96<1>D ~g94<8,8,1>D ~g95<8,8,1>D { align1 1Q }; +and(16) g24<1>D ~g20<8,8,1>D ~g22<8,8,1>D { align1 1H }; +and(1) a0<1>UD g4<0,1,0>UD 0x000000ffUD { align1 WE_all 1N }; +and(16) g118<1>UD g114<8,8,1>UD 0x0000003fUD { align1 2H }; +and(1) g4<1>UD g20<0,1,0>UD 0x000000ffUD { align1 WE_all 3N }; +and.z.f0.0(8) null<1>D g13<8,8,1>UD 0x0000001fUD { align1 1Q }; +and(8) g21<1>UD g15<8,8,1>UD 0x00000003UD { align1 WE_all 1Q }; +and.z.f0.0(8) null<1>UD g20<8,8,1>UD 0x00000001UD { align1 1Q }; +and.z.f0.0(16) null<1>UD g45<8,8,1>UD 0x00000001UD { align1 1H }; +and(8) g4<1>UW g3<8,8,1>UW 0xfffcUW { align1 1Q }; +and(16) g13<1>UW g19<16,8,2>UW 0xfffcUW { align1 1H }; +and.nz.f0.0(8) null<1>UD ~g2.2<0,1,0>D g9<8,8,1>UD { align1 1Q }; +and(8) g18<1>UD ~g2.2<0,1,0>D g7<8,8,1>UD { align1 1Q }; +and.nz.f0.0(16) null<1>UD ~g2.2<0,1,0>D g14<8,8,1>UD { align1 1H }; +and(16) g30<1>UD ~g2.2<0,1,0>D g10<8,8,1>UD { align1 1H }; +and.nz.f0.0(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; +and.nz.f0.0(16) g16<1>UD g14<8,8,1>UD 0x00000001UD { align1 1H }; +and.z.f0.0(8) g9<1>UD g8<8,8,1>UD 0x00000003UD { align1 1Q }; +and(8) g12<1>UQ g9<4,4,1>UQ g11<4,4,1>UQ { align1 1Q }; +and(8) g26<1>UQ g18<4,4,1>UQ g22<4,4,1>UQ { align1 2Q }; diff --git a/src/intel/tools/tests/gen9/and.expected b/src/intel/tools/tests/gen9/and.expected new file mode 100644 index 00000000000..4f2b62ecd1a --- /dev/null +++ b/src/intel/tools/tests/gen9/and.expected @@ -0,0 +1,29 @@ +05 00 60 00 08 02 60 20 40 00 00 0a 48 40 00 00 +05 00 80 00 08 02 60 20 40 00 00 0a 48 40 00 00 +05 00 60 00 08 12 00 21 02 00 00 16 ff 07 ff 07 +05 00 80 00 08 12 40 22 02 00 00 16 ff 07 ff 07 +05 00 00 00 0c 02 e0 20 a0 00 00 06 f0 00 00 00 +05 00 60 02 00 02 00 20 80 04 8d 02 a0 04 8d 00 +05 00 80 02 00 02 00 20 c0 08 8d 02 00 09 8d 00 +05 00 80 01 08 02 a0 22 60 02 8d 02 20 02 8d 00 +05 10 60 00 08 02 a0 27 e0 09 8d 02 04 04 8a 00 +05 00 60 00 28 0a 00 2c c0 4b 8d 0a e0 4b 8d 00 +05 00 80 00 28 0a 00 23 80 42 8d 0a c0 42 8d 00 +05 00 00 00 04 02 00 22 80 00 00 06 ff 00 00 00 +05 20 80 00 08 02 c0 2e 40 0e 8d 06 3f 00 00 00 +05 10 00 00 0c 02 80 20 80 02 00 06 ff 00 00 00 +05 00 60 01 20 02 00 20 a0 01 8d 06 1f 00 00 00 +05 00 60 00 0c 02 a0 22 e0 01 8d 06 03 00 00 00 +05 00 60 01 00 02 00 20 80 02 8d 06 01 00 00 00 +05 00 80 01 00 02 00 20 a0 05 8d 06 01 00 00 00 +05 00 60 00 48 12 80 20 60 00 8d 16 fc ff fc ff +05 00 80 00 48 12 a0 21 60 02 ae 16 fc ff fc ff +05 00 60 02 00 0a 00 20 48 40 00 02 20 01 8d 00 +05 00 60 00 08 0a 40 22 48 40 00 02 e0 00 8d 00 +05 00 80 02 00 0a 00 20 48 40 00 02 c0 01 8d 00 +05 00 80 00 08 0a c0 23 48 40 00 02 40 01 8d 00 +05 00 60 02 08 02 40 21 20 01 8d 06 01 00 00 00 +05 00 80 02 08 02 00 22 c0 01 8d 06 01 00 00 00 +05 00 60 01 08 02 20 21 00 01 8d 06 03 00 00 00 +05 00 60 00 08 43 80 21 20 01 69 42 60 01 69 00 +05 10 60 00 08 43 40 23 40 02 69 42 c0 02 69 00 diff --git a/src/intel/tools/tests/gen9/asr.asm b/src/intel/tools/tests/gen9/asr.asm new file mode 100644 index 00000000000..9beabc9cc8b --- /dev/null +++ b/src/intel/tools/tests/gen9/asr.asm @@ -0,0 +1,6 @@ +asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q }; +asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H }; +asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q }; +asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H }; +asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q }; +asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H }; diff --git a/src/intel/tools/tests/gen9/asr.expected b/src/intel/tools/tests/gen9/asr.expected new file mode 100644 index 00000000000..f1832cd80d7 --- /dev/null +++ b/src/intel/tools/tests/gen9/asr.expected @@ -0,0 +1,6 @@ +0c 00 60 00 28 0a 60 22 e0 00 8d 06 01 00 00 00 +0c 00 80 00 28 0a 80 22 5c 00 00 06 1f 00 00 00 +0c 00 60 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 +0c 00 80 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 +0c 00 60 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 +0c 00 80 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 diff --git a/src/intel/tools/tests/gen9/bfe.asm b/src/intel/tools/tests/gen9/bfe.asm new file mode 100644 index 00000000000..93ec4fb18e9 --- /dev/null +++ b/src/intel/tools/tests/gen9/bfe.asm @@ -0,0 +1,4 @@ +bfe(8) g96<1>UD g89<4,4,1>UD g30<4,4,1>UD g91<4,4,1>UD { align16 1Q }; +bfe(16) g13<1>UD g44<4,4,1>UD g115<4,4,1>UD g126<4,4,1>UD { align16 1H }; +bfe(8) g18<1>D g17<4,4,1>D g16<4,4,1>D g49<4,4,1>D { align16 1Q }; +bfe(16) g13<1>D g11<4,4,1>D g42<4,4,1>D g5<4,4,1>D { align16 1H }; diff --git a/src/intel/tools/tests/gen9/bfe.expected b/src/intel/tools/tests/gen9/bfe.expected new file mode 100644 index 00000000000..d6a91b3c387 --- /dev/null +++ b/src/intel/tools/tests/gen9/bfe.expected @@ -0,0 +1,4 @@ +18 01 60 00 00 90 1e 60 c8 91 05 39 3c 20 c7 16 +18 01 80 00 00 90 1e 0d c8 c1 02 39 e6 20 87 1f +18 01 60 00 00 48 1e 12 c8 11 01 39 20 20 47 0c +18 01 80 00 00 48 1e 0d c8 b1 00 39 54 20 47 01 diff --git a/src/intel/tools/tests/gen9/bfi1.asm b/src/intel/tools/tests/gen9/bfi1.asm new file mode 100644 index 00000000000..d2bfa85d7ce --- /dev/null +++ b/src/intel/tools/tests/gen9/bfi1.asm @@ -0,0 +1,2 @@ +bfi1(8) g20<1>UD g19<8,8,1>D g18<8,8,1>D { align1 1Q }; +bfi1(16) g16<1>UD g14<8,8,1>D g12<8,8,1>D { align1 1H }; diff --git a/src/intel/tools/tests/gen9/bfi1.expected b/src/intel/tools/tests/gen9/bfi1.expected new file mode 100644 index 00000000000..d8b4474c53e --- /dev/null +++ b/src/intel/tools/tests/gen9/bfi1.expected @@ -0,0 +1,2 @@ +19 00 60 00 08 0a 80 22 60 02 8d 0a 40 02 8d 00 +19 00 80 00 08 0a 00 22 c0 01 8d 0a 80 01 8d 00 diff --git a/src/intel/tools/tests/gen9/bfi2.asm b/src/intel/tools/tests/gen9/bfi2.asm new file mode 100644 index 00000000000..1dadebe1753 --- /dev/null +++ b/src/intel/tools/tests/gen9/bfi2.asm @@ -0,0 +1,2 @@ +bfi2(8) g31<1>UD g88<4,4,1>UD g90<4,4,1>UD g91<4,4,1>UD { align16 1Q }; +bfi2(16) g5<1>UD g42<4,4,1>UD g40<4,4,1>UD g126<4,4,1>UD { align16 1H }; diff --git a/src/intel/tools/tests/gen9/bfi2.expected b/src/intel/tools/tests/gen9/bfi2.expected new file mode 100644 index 00000000000..61eda29eaf4 --- /dev/null +++ b/src/intel/tools/tests/gen9/bfi2.expected @@ -0,0 +1,2 @@ +1a 01 60 00 00 90 1e 1f c8 81 05 39 b4 20 c7 16 +1a 01 80 00 00 90 1e 05 c8 a1 02 39 50 20 87 1f diff --git a/src/intel/tools/tests/gen9/bfrev.asm b/src/intel/tools/tests/gen9/bfrev.asm new file mode 100644 index 00000000000..44b45c53bae --- /dev/null +++ b/src/intel/tools/tests/gen9/bfrev.asm @@ -0,0 +1,2 @@ +bfrev(8) g5<1>UD g5<8,8,1>UD { align1 1Q }; +bfrev(16) g6<1>UD g8<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen9/bfrev.expected b/src/intel/tools/tests/gen9/bfrev.expected new file mode 100644 index 00000000000..b4d7fb02205 --- /dev/null +++ b/src/intel/tools/tests/gen9/bfrev.expected @@ -0,0 +1,2 @@ +17 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00 +17 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/break.asm b/src/intel/tools/tests/gen9/break.asm new file mode 100644 index 00000000000..093ae61d513 --- /dev/null +++ b/src/intel/tools/tests/gen9/break.asm @@ -0,0 +1,4 @@ +break(8) JIP: 16 UIP: 64 { align1 1Q }; +break(16) JIP: 16 UIP: 64 { align1 1H }; +(+f0.0) break(8) JIP: 32 UIP: 80 { align1 1Q }; +(+f0.0) break(16) JIP: 32 UIP: 80 { align1 1H }; diff --git a/src/intel/tools/tests/gen9/break.expected b/src/intel/tools/tests/gen9/break.expected new file mode 100644 index 00000000000..305af58e2ce --- /dev/null +++ b/src/intel/tools/tests/gen9/break.expected @@ -0,0 +1,4 @@ +28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00 +28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00 +28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00 +28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00 diff --git a/src/intel/tools/tests/gen9/cbit.asm b/src/intel/tools/tests/gen9/cbit.asm new file mode 100644 index 00000000000..a48d5e29182 --- /dev/null +++ b/src/intel/tools/tests/gen9/cbit.asm @@ -0,0 +1,2 @@ +cbit(8) g9<1>UD g31<8,8,1>UD { align1 1Q }; +cbit(16) g6<1>UD g8<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen9/cbit.expected b/src/intel/tools/tests/gen9/cbit.expected new file mode 100644 index 00000000000..8cb5ca16d1c --- /dev/null +++ b/src/intel/tools/tests/gen9/cbit.expected @@ -0,0 +1,2 @@ +4d 00 60 00 08 02 20 21 e0 03 8d 00 00 00 00 00 +4d 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/cmp.asm b/src/intel/tools/tests/gen9/cmp.asm new file mode 100644 index 00000000000..669224dcd0d --- /dev/null +++ b/src/intel/tools/tests/gen9/cmp.asm @@ -0,0 +1,104 @@ +cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q }; +cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q }; +cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q }; +cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q }; +cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q }; +cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H }; +cmp.l.f0.0(16) g28<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; +cmp.ge.f0.0(16) g30<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; +cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q }; +cmp.z.f0.0(8) g86<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q }; +cmp.le.f0.0(8) g108<1>D g106<8,8,1>D 0D { align1 1Q }; +cmp.nz.f0.0(8) null<1>DF g6.2<0,1,0>DF g66<4,4,1>DF { align1 1Q }; +cmp.l.f0.0(8) g5<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; +cmp.ge.f0.0(8) g18<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; +cmp.z.f0.0(8) g34<1>DF (abs)g106<4,4,1>DF g52<4,4,1>DF { align1 2Q }; +cmp.le.f0.0(16) g35<1>D g21<8,8,1>D 0D { align1 1H }; +cmp.nz.f0.0(8) null<1>DF g106<4,4,1>DF g50<4,4,1>DF { align1 2Q }; +cmp.nz.f0.0(8) g113<1>DF g3.1<0,1,0>DF g59<4,4,1>DF { align1 2Q }; +cmp.l.f0.0(8) null<1>UD g12<8,8,1>UD 0x00000004UD { align1 1Q }; +cmp.l.f0.0(8) g53<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; +cmp.ge.f0.0(8) g55<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; +cmp.ge.f0.0(8) g15<1>D (abs)g12<8,8,1>D 1D { align1 1Q }; +cmp.l.f0.0(8) null<1>D g6<0,1,0>D 2D { align1 1Q }; +(+f0.1) cmp.z.f0.1(8) null<1>D g8<8,8,1>D 0D { align1 1Q }; +cmp.nz.f0.0(16) g11<1>D g9<8,8,1>D 3D { align1 1H }; +(+f0.1) cmp.z.f0.1(16) null<1>D g11<8,8,1>D 0D { align1 1H }; +cmp.z.f0.0(8) null<1>D g22<8,8,1>D 1D { align1 1Q }; +cmp.z.f0.0(16) null<1>D g47<8,8,1>D 1D { align1 1H }; +cmp.ge.f0.0(8) g30<1>UD g29<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; +cmp.l.f0.0(8) g31<1>UD g29<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; +cmp.ge.f0.0(16) g50<1>UD g48<8,8,1>UD g7.7<0,1,0>UD { align1 1H }; +cmp.l.f0.0(16) g52<1>UD g48<8,8,1>UD g7.3<0,1,0>UD { align1 1H }; +cmp.nz.f0.0(16) g9<1>F g2.5<0,1,0>F g1.1<0,1,0>F { align1 1H }; +cmp.ge.f0.0(8) null<1>D g38<8,8,1>D 32D { align1 1Q }; +cmp.ge.f0.0(8) null<1>DF g21<4,4,1>DF g13<4,4,1>DF { align1 1Q }; +cmp.ge.f0.0(16) g3<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; +cmp.l.f0.0(16) g5<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; +cmp.z.f0.0(8) g25<1>F g4.3<0,1,0>F g4.1<0,1,0>F { align1 1Q }; +cmp.l.f0.0(8) g33<1>D g5<0,1,0>D 1D { align1 1Q }; +cmp.l.f0.0(8) g43<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; +cmp.ge.f0.0(8) g46<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; +cmp.l.f0.0(16) null<1>D g6<0,1,0>D 1D { align1 1H }; +cmp.z.f0.0(16) g62<1>F g12<8,8,1>F g6.3<0,1,0>F { align1 1H }; +cmp.nz.f0.0(8) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.nz.f0.0(16) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.ge.f0.0(16) null<1>UD g46<8,8,1>UD 0x00000040UD { align1 1H }; +cmp.z.f0.0(16) null<1>F g14<8,8,1>F g6.1<0,1,0>F { align1 1H }; +cmp.nz.f0.0(16) null<1>D g6<0,1,0>D 0D { align1 1H }; +cmp.l.f0.0(16) null<1>UD g39<8,8,1>UD 0x00000004UD { align1 1H }; +cmp.le.f0.0(8) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +cmp.le.f0.0(16) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; +cmp.le.f0.0(8) g20<1>F g5.3<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.ge.f0.0(8) null<1>F (abs)g26<8,8,1>F 0x5d5e0b6bF /* 1e+18F */ { align1 1Q }; +cmp.g.f0.0(8) g80<1>F (abs)g44<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; +cmp.ge.f0.0(16) null<1>D g67<8,8,1>D 32D { align1 1H }; +cmp.g.f0.0(8) null<1>F g124<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +cmp.z.f0.0(8) g4<1>F g13<8,4,2>F g2.5<0,1,0>F { align1 2Q }; +cmp.g.f0.0(16) null<1>F g120<8,8,1>F 0x0F /* 0F */ { align1 1H }; +cmp.g.f0.0(16) g2<1>F (abs)g17<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +cmp.l.f0.0(8) null<1>DF (abs)g5<0,1,0>DF g20<4,4,1>DF { align1 1Q }; +cmp.nz.f0.0(8) g29<1>D g22.1<8,4,2>D g3.2<0,1,0>D { align1 2Q }; +cmp.l.f0.0(8) null<1>DF g11<4,4,1>DF g8<4,4,1>DF { align1 2Q }; +cmp.nz.f0.0(8) g73<1>F g6.1<0,1,0>F g14<8,4,2>F { align1 2Q }; +cmp.g.f0.0(8) g7<1>D g2<0,1,0>D 0D { align1 1Q }; +cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.le.f0.0(8) null<1>D g2<8,8,1>D 50D { align1 1Q }; +cmp.le.f0.0(16) null<1>D g2<8,8,1>D 50D { align1 1H }; +cmp.ge.f0.0(16) null<1>F g35<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; +cmp.le.f0.0(8) g4<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; +cmp.g.f0.0(8) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; +cmp.le.f0.0(16) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; +cmp.g.f0.0(16) g7<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; +cmp.le.f0.0(16) g121<1>F g27<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 1H }; +cmp.z.f0.0(8) g5<1>D g14<8,4,2>D g3.1<0,1,0>D { align1 2Q }; +cmp.g.f0.0(8) null<1>D g5.2<0,1,0>D 31D { align1 1Q }; +cmp.g.f0.0(8) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1Q }; +(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1Q }; +(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1H }; +cmp.z.f0.0(16) null<1>D g1<8,8,1>D 1024D { align1 2H }; +cmp.l.f0.0(16) null<1>D g118<8,8,1>D 32D { align1 2H }; +cmp.nz.f0.0(8) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1Q }; +cmp.nz.f0.0(16) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1H }; +cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 1H }; +cmp.nz.f0.0(8) null<1>Q g6<4,4,1>Q g3<4,4,1>Q { align1 1Q }; +cmp.z.f0.0(8) g8<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; +cmp.nz.f0.0(8) g2<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; +cmp.nz.f0.0(8) null<1>Q g9<4,4,1>Q g4<4,4,1>Q { align1 2Q }; +cmp.z.f0.0(8) g17<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; +cmp.nz.f0.0(8) g20<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; +cmp.z.f0.0(8) null<1>UD g5<8,8,1>UD 0x00000000UD { align1 1Q }; +cmp.z.f0.0(16) null<1>UD g15<8,8,1>UD 0x00000000UD { align1 1H }; +cmp.g.f0.0(16) g1<1>D g8<8,8,1>D 0D { align1 1H }; +cmp.ge.f0.0(8) null<1>UD g10<8,8,1>UD g8<8,8,1>UD { align1 1Q }; +cmp.ge.f0.0(8) null<1>DF g37<4,4,1>DF g26<4,4,1>DF { align1 2Q }; +cmp.l.f0.0(8) null<1>Q g20<4,4,1>Q g25<4,4,1>Q { align1 1Q }; +cmp.l.f0.0(8) null<1>Q g2<4,4,1>Q g12<4,4,1>Q { align1 2Q }; +cmp.ge.f0.0(8) null<1>Q g20<4,4,1>Q g27<4,4,1>Q { align1 1Q }; +cmp.ge.f0.0(8) null<1>Q g2<4,4,1>Q g8<4,4,1>Q { align1 2Q }; +cmp.le.f0.0(8) null<1>UD g18<8,8,1>UD 0x000000ffUD { align1 1Q }; +cmp.le.f0.0(16) null<1>UD g32<8,8,1>UD 0x000000ffUD { align1 1H }; +cmp.z.f0.0(8) null<1>Q g12<4,4,1>Q g7<4,4,1>Q { align1 1Q }; +cmp.z.f0.0(8) null<1>Q g26<4,4,1>Q g12<4,4,1>Q { align1 2Q }; +cmp.g.f0.0(16) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1H }; diff --git a/src/intel/tools/tests/gen9/cmp.expected b/src/intel/tools/tests/gen9/cmp.expected new file mode 100644 index 00000000000..9e13e8c926b --- /dev/null +++ b/src/intel/tools/tests/gen9/cmp.expected @@ -0,0 +1,104 @@ +10 00 60 01 e0 3a 00 20 80 02 8d 3e 00 00 80 bf +10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00 +10 00 60 02 e8 3a 20 26 e0 05 8d 3a c4 01 00 00 +10 00 60 02 20 0a 00 20 e0 00 8d 0e 00 00 00 00 +10 00 60 01 28 0a a0 20 80 00 8d 0a 54 00 00 00 +10 00 80 01 28 0a e0 20 a0 00 8d 0a 54 00 00 00 +10 00 80 05 e8 3a 80 23 40 03 8d 3a 00 03 8d 00 +10 00 80 04 e8 3a c0 23 40 03 8d 3a 00 03 8d 00 +10 00 60 02 28 0a 60 25 40 05 8d 0a 44 00 00 00 +10 00 60 01 c8 32 c0 2a d0 20 00 32 80 08 69 00 +10 00 60 06 28 0a 80 2d 40 0d 8d 0e 00 00 00 00 +10 00 60 02 c0 32 00 20 d0 00 00 32 40 08 69 00 +10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00 +10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00 +10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00 +10 00 80 06 28 0a 60 24 a0 02 8d 0e 00 00 00 00 +10 10 60 02 c0 32 00 20 40 0d 69 32 40 06 69 00 +10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00 +10 00 60 05 00 02 00 20 80 01 8d 06 04 00 00 00 +10 00 60 05 e8 3a a0 26 80 06 8d 3a 60 06 8d 00 +10 00 60 04 e8 3a e0 26 80 06 8d 3a 60 06 8d 00 +10 00 60 04 28 0a e0 21 80 21 8d 0e 01 00 00 00 +10 00 60 05 20 0a 00 20 c0 00 00 0e 02 00 00 00 +10 00 61 01 21 0a 00 20 00 01 8d 0e 00 00 00 00 +10 00 80 02 28 0a 60 21 20 01 8d 0e 03 00 00 00 +10 00 81 01 21 0a 00 20 60 01 8d 0e 00 00 00 00 +10 00 60 01 20 0a 00 20 c0 02 8d 0e 01 00 00 00 +10 00 80 01 20 0a 00 20 e0 05 8d 0e 01 00 00 00 +10 00 60 04 08 02 c0 23 a0 03 8d 02 bc 00 00 00 +10 00 60 05 08 02 e0 23 a0 03 8d 02 ac 00 00 00 +10 00 80 04 08 02 40 26 00 06 8d 02 fc 00 00 00 +10 00 80 05 08 02 80 26 00 06 8d 02 ec 00 00 00 +10 00 80 02 e8 3a 20 21 54 00 00 3a 24 00 00 00 +10 00 60 04 20 0a 00 20 c0 04 8d 0e 20 00 00 00 +10 00 60 04 c0 32 00 20 a0 02 69 32 a0 01 69 00 +10 00 80 04 28 0a 60 20 24 00 00 0a 20 00 00 00 +10 00 80 05 28 0a a0 20 24 00 00 0a 20 00 00 00 +10 00 60 01 e8 3a 20 23 8c 00 00 3a 84 00 00 00 +10 00 60 05 28 0a 20 24 a0 00 00 0e 01 00 00 00 +10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00 +10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00 +10 00 80 05 20 0a 00 20 c0 00 00 0e 01 00 00 00 +10 00 80 01 e8 3a c0 27 80 01 8d 3a cc 00 00 00 +10 00 60 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 +10 00 80 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 +10 00 80 04 00 02 00 20 c0 05 8d 06 40 00 00 00 +10 00 80 01 e0 3a 00 20 c0 01 8d 3a c4 00 00 00 +10 00 80 02 20 0a 00 20 c0 00 00 0e 00 00 00 00 +10 00 80 05 00 02 00 20 e0 04 8d 06 04 00 00 00 +10 00 60 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f +10 00 80 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f +10 00 60 06 e8 3a 80 22 ac 00 00 3e 00 00 00 00 +10 00 60 04 e0 3a 00 20 40 23 8d 3e 6b 0b 5e 5d +10 00 60 03 e8 3a 00 2a 80 25 8d 3e 00 00 80 3f +10 00 80 04 20 0a 00 20 60 08 8d 0e 20 00 00 00 +10 00 60 03 e0 3a 00 20 80 0f 8d 3e 00 00 00 00 +10 10 60 01 e8 3a 80 20 a0 01 8a 3a 54 00 00 00 +10 00 80 03 e0 3a 00 20 00 0f 8d 3e 00 00 00 00 +10 00 80 03 e8 3a 40 20 20 22 8d 3e 00 00 80 3f +10 00 60 05 c0 32 00 20 a0 20 00 32 80 02 69 00 +10 10 60 02 28 0a a0 23 c4 02 8a 0a 68 00 00 00 +10 10 60 05 c0 32 00 20 60 01 69 32 00 01 69 00 +10 10 60 02 e8 3a 20 29 c4 00 00 3a c0 01 8a 00 +10 00 60 03 28 0a e0 20 40 00 00 0e 00 00 00 00 +10 00 60 05 e0 3a 00 20 90 00 00 3e 00 00 00 00 +10 00 80 05 e0 3a 00 20 d0 00 00 3e 00 00 00 00 +10 00 60 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 +10 00 80 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 +10 00 80 04 e0 3a 00 20 60 04 8d 3e 00 00 00 3f +10 00 60 06 08 02 80 20 40 00 00 06 01 00 00 00 +10 00 60 03 08 02 a0 20 40 00 00 06 01 00 00 00 +10 00 80 06 08 02 a0 20 40 00 00 06 01 00 00 00 +10 00 80 03 08 02 e0 20 40 00 00 06 01 00 00 00 +10 00 80 06 e8 3a 20 2f 60 03 8d 3e 9a 3f 1c 46 +10 10 60 01 28 0a a0 20 c0 01 8a 0a 64 00 00 00 +10 00 60 03 20 0a 00 20 a8 00 00 0e 1f 00 00 00 +10 00 60 03 00 02 00 20 88 00 00 06 1f 00 00 00 +10 00 61 02 41 12 00 20 00 00 8d 12 00 00 8d 00 +10 00 81 02 41 12 00 20 00 00 8d 12 00 00 8d 00 +10 20 80 01 20 0a 00 20 20 00 8d 0e 00 04 00 00 +10 20 80 05 20 0a 00 20 c0 0e 8d 0e 20 00 00 00 +10 00 60 02 00 02 00 20 60 00 8d 06 00 00 00 00 +10 00 80 02 00 02 00 20 60 00 8d 06 00 00 00 00 +10 00 80 03 20 0a 00 20 44 00 00 0e 00 00 00 00 +10 00 60 02 20 4b 00 20 c0 00 69 4a 60 00 69 00 +10 00 60 01 28 4b 00 21 a0 00 69 4a 60 00 69 00 +10 00 60 02 28 4b 40 20 a0 00 69 4a 60 00 69 00 +10 10 60 02 20 4b 00 20 20 01 69 4a 80 00 69 00 +10 10 60 01 28 4b 20 22 60 01 69 4a 80 00 69 00 +10 10 60 02 28 4b 80 22 60 01 69 4a 80 00 69 00 +10 00 60 01 00 02 00 20 a0 00 8d 06 00 00 00 00 +10 00 80 01 00 02 00 20 e0 01 8d 06 00 00 00 00 +10 00 80 03 28 0a 20 20 00 01 8d 0e 00 00 00 00 +10 00 60 04 00 02 00 20 40 01 8d 02 00 01 8d 00 +10 10 60 04 c0 32 00 20 a0 04 69 32 40 03 69 00 +10 00 60 05 20 4b 00 20 80 02 69 4a 20 03 69 00 +10 10 60 05 20 4b 00 20 40 00 69 4a 80 01 69 00 +10 00 60 04 20 4b 00 20 80 02 69 4a 60 03 69 00 +10 10 60 04 20 4b 00 20 40 00 69 4a 00 01 69 00 +10 00 60 06 00 02 00 20 40 02 8d 06 ff 00 00 00 +10 00 80 06 00 02 00 20 00 04 8d 06 ff 00 00 00 +10 00 60 01 20 4b 00 20 80 01 69 4a e0 00 69 00 +10 10 60 01 20 4b 00 20 40 03 69 4a 80 01 69 00 +10 00 80 03 00 02 00 20 88 00 00 06 1f 00 00 00 diff --git a/src/intel/tools/tests/gen9/cont.asm b/src/intel/tools/tests/gen9/cont.asm new file mode 100644 index 00000000000..c5a194bace3 --- /dev/null +++ b/src/intel/tools/tests/gen9/cont.asm @@ -0,0 +1,2 @@ +cont(8) JIP: 16 UIP: 64 { align1 1Q }; +cont(16) JIP: 16 UIP: 64 { align1 1H }; diff --git a/src/intel/tools/tests/gen9/cont.expected b/src/intel/tools/tests/gen9/cont.expected new file mode 100644 index 00000000000..83aa4f5e5e5 --- /dev/null +++ b/src/intel/tools/tests/gen9/cont.expected @@ -0,0 +1,2 @@ +29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00 +29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00 diff --git a/src/intel/tools/tests/gen9/csel.asm b/src/intel/tools/tests/gen9/csel.asm new file mode 100644 index 00000000000..6030fb39f26 --- /dev/null +++ b/src/intel/tools/tests/gen9/csel.asm @@ -0,0 +1,13 @@ +csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q }; +csel.nz(16) g14<1>F g8<4,4,1>F (abs)g8<4,4,1>F g8<4,4,1>F { align16 1H }; +csel.le(8) g21<1>F (abs)g5.3<0,1,0>F g5.0<0,1,0>F g5.3<0,1,0>F { align16 1Q }; +csel.l(8) g107<1>F -g101<4,4,1>F g101<4,4,1>F g104<4,4,1>F { align16 1Q }; +csel.le(8) g21<1>F g5.0<0,1,0>F (abs)g5.1<0,1,0>F g5.1<0,1,0>F { align16 1Q }; +csel.l(8) g127<1>F g2<4,4,1>F g8<4,4,1>F g4.0<0,1,0>F { align16 1Q }; +csel.l(16) g126<1>F g2<4,4,1>F g13<4,4,1>F g6.0<0,1,0>F { align16 1H }; +csel.le(16) g13<1>F (abs)g73<4,4,1>F g58<4,4,1>F g73<4,4,1>F { align16 1H }; +csel.le(16) g15<1>F g58<4,4,1>F (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H }; +csel.l(16) g69<1>F -g65<4,4,1>F g65<4,4,1>F g67<4,4,1>F { align16 1H }; +csel.sat.g(8) g125<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1Q }; +csel.g(8) g125<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1Q }; +csel.g(16) g122<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1H }; diff --git a/src/intel/tools/tests/gen9/csel.expected b/src/intel/tools/tests/gen9/csel.expected new file mode 100644 index 00000000000..300b9154107 --- /dev/null +++ b/src/intel/tools/tests/gen9/csel.expected @@ -0,0 +1,13 @@ +12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02 +12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02 +12 01 60 06 20 00 1e 15 01 56 20 00 0a 04 58 01 +12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a +12 01 60 06 80 00 1e 15 01 50 20 40 0a 04 48 01 +12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01 +12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01 +12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12 +12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12 +12 01 80 05 40 00 1e 45 c8 11 04 39 82 20 c7 10 +12 01 60 83 00 00 1e 7d 01 26 20 80 04 04 80 00 +12 01 60 03 00 00 1e 7d 01 26 20 80 04 04 80 00 +12 01 80 03 00 00 1e 7a 01 26 20 80 04 04 80 00 diff --git a/src/intel/tools/tests/gen9/else.asm b/src/intel/tools/tests/gen9/else.asm new file mode 100644 index 00000000000..83246247c55 --- /dev/null +++ b/src/intel/tools/tests/gen9/else.asm @@ -0,0 +1,3 @@ +else(8) JIP: 288 UIP: 288 { align1 1Q }; +else(16) JIP: 240 UIP: 240 { align1 1H }; +else(32) JIP: 272 UIP: 272 { align1 }; diff --git a/src/intel/tools/tests/gen9/else.expected b/src/intel/tools/tests/gen9/else.expected new file mode 100644 index 00000000000..44503c7f427 --- /dev/null +++ b/src/intel/tools/tests/gen9/else.expected @@ -0,0 +1,3 @@ +24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00 +24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00 +24 00 a0 00 20 0e 00 20 10 01 00 00 10 01 00 00 diff --git a/src/intel/tools/tests/gen9/endif.asm b/src/intel/tools/tests/gen9/endif.asm new file mode 100644 index 00000000000..bfd04eab63f --- /dev/null +++ b/src/intel/tools/tests/gen9/endif.asm @@ -0,0 +1,3 @@ +endif(8) JIP: 80 { align1 1Q }; +endif(16) JIP: 48 { align1 1H }; +endif(32) JIP: 16 { align1 }; diff --git a/src/intel/tools/tests/gen9/endif.expected b/src/intel/tools/tests/gen9/endif.expected new file mode 100644 index 00000000000..898a1486c2d --- /dev/null +++ b/src/intel/tools/tests/gen9/endif.expected @@ -0,0 +1,3 @@ +25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00 +25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00 +25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00 diff --git a/src/intel/tools/tests/gen9/fbh.asm b/src/intel/tools/tests/gen9/fbh.asm new file mode 100644 index 00000000000..fb62e766685 --- /dev/null +++ b/src/intel/tools/tests/gen9/fbh.asm @@ -0,0 +1,2 @@ +fbh(8) g15<1>D g35<8,8,1>D { align1 1Q }; +fbh(16) g8<1>D g4<8,8,1>D { align1 1H }; diff --git a/src/intel/tools/tests/gen9/fbh.expected b/src/intel/tools/tests/gen9/fbh.expected new file mode 100644 index 00000000000..a3a1fcee746 --- /dev/null +++ b/src/intel/tools/tests/gen9/fbh.expected @@ -0,0 +1,2 @@ +4b 00 60 00 28 0a e0 21 60 04 8d 00 00 00 00 00 +4b 00 80 00 28 0a 00 21 80 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/fbl.asm b/src/intel/tools/tests/gen9/fbl.asm new file mode 100644 index 00000000000..e7f1c7020f5 --- /dev/null +++ b/src/intel/tools/tests/gen9/fbl.asm @@ -0,0 +1,3 @@ +fbl(8) g5<1>UD g5<8,8,1>UD { align1 1Q }; +fbl(16) g6<1>UD g8<8,8,1>UD { align1 1H }; +fbl(1) g43<1>UD mask0<0,1,0>UD { align1 WE_all 1N }; diff --git a/src/intel/tools/tests/gen9/fbl.expected b/src/intel/tools/tests/gen9/fbl.expected new file mode 100644 index 00000000000..60cb680a350 --- /dev/null +++ b/src/intel/tools/tests/gen9/fbl.expected @@ -0,0 +1,3 @@ +4c 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00 +4c 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 +4c 00 00 00 0c 00 60 25 00 08 00 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/frc.asm b/src/intel/tools/tests/gen9/frc.asm new file mode 100644 index 00000000000..910fbed5b59 --- /dev/null +++ b/src/intel/tools/tests/gen9/frc.asm @@ -0,0 +1,2 @@ +frc(8) g28<1>F g4<8,8,1>F { align1 1Q }; +frc(16) g3<1>F g1<0,1,0>F { align1 1H }; diff --git a/src/intel/tools/tests/gen9/frc.expected b/src/intel/tools/tests/gen9/frc.expected new file mode 100644 index 00000000000..00484ffedd3 --- /dev/null +++ b/src/intel/tools/tests/gen9/frc.expected @@ -0,0 +1,2 @@ +43 00 60 00 e8 3a 80 23 80 00 8d 00 00 00 00 00 +43 00 80 00 e8 3a 60 20 20 00 00 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/halt.asm b/src/intel/tools/tests/gen9/halt.asm new file mode 100644 index 00000000000..d84432603ea --- /dev/null +++ b/src/intel/tools/tests/gen9/halt.asm @@ -0,0 +1,4 @@ +(-f0.1.any4h) halt(8) JIP: 176 UIP: 192 { align1 1Q }; +halt(8) JIP: 16 UIP: 16 { align1 1Q }; +(-f0.1.any4h) halt(16) JIP: 176 UIP: 192 { align1 1H }; +halt(16) JIP: 16 UIP: 16 { align1 1H }; diff --git a/src/intel/tools/tests/gen9/halt.expected b/src/intel/tools/tests/gen9/halt.expected new file mode 100644 index 00000000000..4e4573db43d --- /dev/null +++ b/src/intel/tools/tests/gen9/halt.expected @@ -0,0 +1,4 @@ +2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00 +2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00 +2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00 +2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00 diff --git a/src/intel/tools/tests/gen9/if.asm b/src/intel/tools/tests/gen9/if.asm new file mode 100644 index 00000000000..5eb7b53fc64 --- /dev/null +++ b/src/intel/tools/tests/gen9/if.asm @@ -0,0 +1,5 @@ +(+f0.0) if(8) JIP: 1376 UIP: 1392 { align1 1Q }; +(-f0.0) if(8) JIP: 4704 UIP: 4704 { align1 1Q }; +(-f0.0) if(16) JIP: 64 UIP: 64 { align1 1H }; +(+f0.0) if(16) JIP: 96 UIP: 320 { align1 1H }; +(+f0.0) if(32) JIP: 80 UIP: 80 { align1 }; diff --git a/src/intel/tools/tests/gen9/if.expected b/src/intel/tools/tests/gen9/if.expected new file mode 100644 index 00000000000..b2fc2852e60 --- /dev/null +++ b/src/intel/tools/tests/gen9/if.expected @@ -0,0 +1,5 @@ +22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00 +22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00 +22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00 +22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00 +22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00 diff --git a/src/intel/tools/tests/gen9/lrp.asm b/src/intel/tools/tests/gen9/lrp.asm new file mode 100644 index 00000000000..d2445c6919b --- /dev/null +++ b/src/intel/tools/tests/gen9/lrp.asm @@ -0,0 +1,5 @@ +lrp(8) g4<1>F g16<4,4,1>F g7.2<0,1,0>F g6.6<0,1,0>F { align16 1Q }; +lrp(16) g4<1>F g2.4<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1H }; +lrp.z.f0.0(8) g8<1>F g3.2<0,1,0>F g3.1<0,1,0>F g3.0<0,1,0>F { align16 1Q }; +lrp.sat(8) g7<1>F g10<4,4,1>F g13<4,4,1>F g16<4,4,1>F { align16 1Q }; +lrp.sat(16) g18<1>F g20<4,4,1>F g26<4,4,1>F g32<4,4,1>F { align16 1H }; diff --git a/src/intel/tools/tests/gen9/lrp.expected b/src/intel/tools/tests/gen9/lrp.expected new file mode 100644 index 00000000000..b109e92a5be --- /dev/null +++ b/src/intel/tools/tests/gen9/lrp.expected @@ -0,0 +1,5 @@ +5c 01 60 00 00 00 1e 04 c8 01 21 80 0e 04 b0 01 +5c 01 80 00 00 00 1e 04 01 28 20 80 04 04 80 00 +5c 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00 +5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04 +5c 01 80 80 00 00 1e 12 c8 41 01 39 34 20 07 08 diff --git a/src/intel/tools/tests/gen9/lzd.asm b/src/intel/tools/tests/gen9/lzd.asm new file mode 100644 index 00000000000..2dba1a11453 --- /dev/null +++ b/src/intel/tools/tests/gen9/lzd.asm @@ -0,0 +1,2 @@ +lzd(8) g25<1>UD g3.1<0,1,0>UD { align1 1Q }; +lzd(16) g27<1>UD g3.1<0,1,0>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen9/lzd.expected b/src/intel/tools/tests/gen9/lzd.expected new file mode 100644 index 00000000000..74afe29080d --- /dev/null +++ b/src/intel/tools/tests/gen9/lzd.expected @@ -0,0 +1,2 @@ +4a 00 60 00 08 02 20 23 64 00 00 00 00 00 00 00 +4a 00 80 00 08 02 60 23 64 00 00 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/mach.asm b/src/intel/tools/tests/gen9/mach.asm new file mode 100644 index 00000000000..7f632bf16bf --- /dev/null +++ b/src/intel/tools/tests/gen9/mach.asm @@ -0,0 +1,4 @@ +mach(8) g19<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable }; +mach(8) g23<1>D g17<8,8,1>D 1431655766D { align1 1Q AccWrEnable }; +mach(8) g42<1>UD g39<8,8,1>UD 0xaaaaaaabUD { align1 2Q AccWrEnable }; +mach(8) g50<1>D g39<8,8,1>D 1431655766D { align1 2Q AccWrEnable }; diff --git a/src/intel/tools/tests/gen9/mach.expected b/src/intel/tools/tests/gen9/mach.expected new file mode 100644 index 00000000000..d90d46e56ef --- /dev/null +++ b/src/intel/tools/tests/gen9/mach.expected @@ -0,0 +1,4 @@ +49 00 60 10 08 02 60 22 20 02 8d 06 ab aa aa aa +49 00 60 10 28 0a e0 22 20 02 8d 0e 56 55 55 55 +49 10 60 10 08 02 40 25 e0 04 8d 06 ab aa aa aa +49 10 60 10 28 0a 40 26 e0 04 8d 0e 56 55 55 55 diff --git a/src/intel/tools/tests/gen9/mad.asm b/src/intel/tools/tests/gen9/mad.asm new file mode 100644 index 00000000000..a48131f21a1 --- /dev/null +++ b/src/intel/tools/tests/gen9/mad.asm @@ -0,0 +1,43 @@ +mad(8) g26<1>F g22<4,4,1>F g2.4<0,1,0>F g5<4,4,1>F { align16 1Q }; +mad(16) g14<1>F g12<4,4,1>F g4<4,4,1>F g4<4,4,1>F { align16 1H }; +mad(8) g64<1>DF g62<4,4,1>DF g40<4,4,1>DF g92<4,4,1>DF { align16 1Q }; +mad(8) g80<1>DF -g50<4,4,1>DF g24<4,4,1>DF g80<4,4,1>DF { align16 1Q }; +mad(8) g27<1>DF g48<4,4,1>DF g106<4,4,1>DF g25<4,4,1>DF { align16 2Q }; +mad(8) g13<1>F -g14.0<0,1,0>F g11<4,4,1>F g6<4,4,1>F { align16 1Q }; +mad(16) g29<1>F -g33.0<0,1,0>F g25<4,4,1>F g15<4,4,1>F { align16 1H }; +mad(8) g29<1>DF g23<4,4,1>DF g27<4,4,1>DF -g25<4,4,1>DF { align16 1Q }; +mad.le.f0.0(8) g5<1>F g3<4,4,1>F g4.2<0,1,0>F g64<4,4,1>F { align16 1Q }; +mad.le.f0.0(16) g7<1>F g4<4,4,1>F g6.2<0,1,0>F g16<4,4,1>F { align16 1H }; +mad(8) g32<1>F g31<4,4,1>F g2.3<0,1,0>F -g15<4,4,1>F { align16 1Q }; +mad(16) g56<1>F g54<4,4,1>F g2.3<0,1,0>F -g5<4,4,1>F { align16 1H }; +mad.sat(8) g12<1>F g4.1<0,1,0>F g4.0<0,1,0>F g8<4,4,1>F { align16 1Q }; +mad.sat(16) g18<1>F g6.1<0,1,0>F g6.0<0,1,0>F g10<4,4,1>F { align16 1H }; +mad(8) g86<1>F g88.6<0,1,0>F -g88.7<0,1,0>F g77<4,4,1>F { align16 1Q }; +mad(8) g85<1>DF g28<4,4,1>DF g83<4,4,1>DF -g81<4,4,1>DF { align16 2Q }; +mad(8) g11<1>F -g2.0<0,1,0>F g10<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q }; +mad(8) g15<1>F g2.1<0,1,0>F g11<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q }; +mad.l.f0.0(8) g2<1>F g22<4,4,1>F g5.7<0,1,0>F g6.3<0,1,0>F { align16 1Q }; +mad(8) g79<1>DF -g39<4,4,1>DF g21<4,4,1>DF g79<4,4,1>DF { align16 2Q }; +mad(8) g117<1>F -g116<4,4,1>F g9.0<0,1,0>F -g113<4,4,1>F { align16 1Q }; +mad.ge.f0.0(8) g13<1>F g28.0<0,1,0>F g9<4,4,1>F -g2.4<0,1,0>F { align16 1Q }; +mad.ge.f0.0(16) g23<1>F g17.0<0,1,0>F g6<4,4,1>F -g3.0<0,1,0>F { align16 1H }; +mad(8) g26<1>F g2.0<0,1,0>F -g2.1<0,1,0>F (abs)g5.6<0,1,0>F { align16 1Q }; +mad(8) g70<1>F -g13<4,4,1>F -g2.1<0,1,0>F -g47<4,4,1>F { align16 1Q }; +mad(16) g95<1>F -g93<4,4,1>F g85<4,4,1>F -g85<4,4,1>F { align16 1H }; +mad(16) g5<1>F -g21<4,4,1>F -g2.1<0,1,0>F -g85<4,4,1>F { align16 1H }; +mad(16) g56<1>F g6.4<0,1,0>F -g6.5<0,1,0>F g51<4,4,1>F { align16 1H }; +mad.sat(8) g124<1>F -g7<4,4,1>F g2.6<0,1,0>F g2.1<0,1,0>F { align16 1Q }; +mad(16) g71<1>F g55.0<0,1,0>F -g55.1<0,1,0>F (abs)g1.0<0,1,0>F { align16 1H }; +mad(16) g77<1>F -g55.2<0,1,0>F g71<4,4,1>F (abs)g1.0<0,1,0>F { align16 1H }; +mad(16) g37<1>F g55.3<0,1,0>F g77<4,4,1>F (abs)g1.0<0,1,0>F { align16 1H }; +mad(8) g43<1>DF g42<4,4,1>DF -g34<4,4,1>DF g7<4,4,1>DF { align16 1Q }; +mad(8) g3<1>DF g2<4,4,1>DF -g111<4,4,1>DF g39<4,4,1>DF { align16 2Q }; +mad(8) g12<1>F -g17<4,4,1>F (abs)g7<4,4,1>F g4.0<0,1,0>F { align16 1Q }; +mad(16) g27<1>F -g22<4,4,1>F (abs)g19<4,4,1>F g29.0<0,1,0>F { align16 1H }; +mad.sat(8) g125<1>F g9<4,4,1>F g6<4,4,1>F -g64.0<0,1,0>F { align16 1Q }; +mad.l.f0.0(16) g5<1>F g9<4,4,1>F g2.7<0,1,0>F g3.3<0,1,0>F { align16 1H }; +mad(8) g6<1>DF -g55<4,4,1>DF g2<4,4,1>DF -g47<4,4,1>DF { align16 1Q }; +mad.z.f0.0(8) g8<1>F g3.2<0,1,0>F g3.1<0,1,0>F g3.0<0,1,0>F { align16 1Q }; +mad(8) g63<1>DF -g48<4,4,1>DF g56<4,4,1>DF -g44<4,4,1>DF { align16 2Q }; +mad.nz.f0.0(8) g10<1>F -g12.0<0,1,0>F g7<4,4,1>F g10<4,4,1>F { align16 1Q }; +mad.nz.f0.0(16) g15<1>F -g33.0<0,1,0>F g9<4,4,1>F g17<4,4,1>F { align16 1H }; diff --git a/src/intel/tools/tests/gen9/mad.expected b/src/intel/tools/tests/gen9/mad.expected new file mode 100644 index 00000000000..76df668b448 --- /dev/null +++ b/src/intel/tools/tests/gen9/mad.expected @@ -0,0 +1,43 @@ +5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01 +5b 01 80 00 00 00 1e 0e c8 c1 00 39 08 20 07 01 +5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17 +5b 01 60 00 40 d8 1e 50 c8 21 03 39 30 20 07 14 +5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06 +5b 01 60 00 40 00 1e 0d 01 e0 00 39 16 20 87 01 +5b 01 80 00 40 00 1e 1d 01 10 02 39 32 20 c7 03 +5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06 +5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 07 10 +5b 01 80 06 00 00 1e 07 c8 41 20 80 0c 20 07 04 +5b 01 60 00 00 04 1e 20 c8 f1 21 c0 04 20 c7 03 +5b 01 80 00 00 04 1e 38 c8 61 23 c0 04 20 47 01 +5b 01 60 80 00 00 1e 0c 01 42 20 00 08 20 07 02 +5b 01 80 80 00 00 1e 12 01 62 20 00 0c 20 87 02 +5b 01 60 00 00 01 1e 56 01 8c 25 c0 b1 20 47 13 +5b 11 60 00 00 dc 1e 55 c8 c1 01 39 a6 20 47 14 +5b 01 60 00 40 02 1e 0b 01 20 00 39 14 04 70 01 +5b 01 60 00 00 02 1e 0f 01 22 00 39 16 04 70 01 +5b 01 60 05 00 00 1e 02 c8 61 21 c0 0b 04 98 01 +5b 11 60 00 40 d8 1e 4f c8 71 02 39 2a 20 c7 13 +5b 01 60 00 40 04 1e 75 c8 41 27 00 12 20 47 1c +5b 01 60 04 00 04 1e 0d 01 c0 01 39 12 04 a0 00 +5b 01 80 04 00 04 1e 17 01 10 01 39 0c 04 c0 00 +5b 01 60 00 00 03 1e 1a 01 20 20 40 04 04 70 01 +5b 01 60 00 40 05 1e 46 c8 d1 20 40 04 20 c7 0b +5b 01 80 00 40 04 1e 5f c8 d1 05 39 aa 20 47 15 +5b 01 80 00 40 05 1e 05 c8 51 21 40 04 20 47 15 +5b 01 80 00 00 01 1e 38 01 68 20 40 0d 20 c7 0c +5b 01 60 80 40 00 1e 7c c8 71 20 80 05 04 88 00 +5b 01 80 00 00 03 1e 47 01 70 23 40 6e 04 40 00 +5b 01 80 00 40 02 1e 4d 01 74 03 39 8e 04 40 00 +5b 01 80 00 00 02 1e 25 01 76 03 39 9a 04 40 00 +5b 01 60 00 00 d9 1e 2b c8 a1 02 39 44 20 c7 01 +5b 11 60 00 00 d9 1e 03 c8 21 00 39 de 20 c7 09 +5b 01 60 00 c0 00 1e 0c c8 11 01 39 0e 04 00 01 +5b 01 80 00 c0 00 1e 1b c8 61 01 39 26 04 40 07 +5b 01 60 80 00 04 1e 7d c8 91 00 39 0c 04 00 10 +5b 01 80 05 00 00 1e 05 c8 91 20 c0 05 04 d8 00 +5b 01 60 00 40 dc 1e 06 c8 71 03 39 04 20 c7 0b +5b 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00 +5b 11 60 00 40 dc 1e 3f c8 01 03 39 70 20 07 0b +5b 01 60 02 40 00 1e 0a 01 c0 00 39 0e 20 87 02 +5b 01 80 02 40 00 1e 0f 01 10 02 39 12 20 47 04 diff --git a/src/intel/tools/tests/gen9/math.asm b/src/intel/tools/tests/gen9/math.asm new file mode 100644 index 00000000000..d6a54d2c389 --- /dev/null +++ b/src/intel/tools/tests/gen9/math.asm @@ -0,0 +1,31 @@ +math sqrt(16) g20<1>F g18<8,8,1>F null<8,8,1>F { align1 1H }; +math inv(8) g95<1>F g94<8,8,1>F null<8,8,1>F { align1 1Q }; +math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 1H }; +math intmod(8) g3<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 1Q }; +math intmod(8) g4<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 2Q }; +math sqrt(8) g24<1>F g23<8,8,1>F null<8,8,1>F { align1 1Q }; +math rsq(8) g5<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; +math pow(8) g11<1>F g10<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1Q }; +math pow(16) g18<1>F g16<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1H }; +math log(8) g7<1>F g6<8,8,1>F null<8,8,1>F { align1 1Q }; +math log(16) g11<1>F g9<8,8,1>F null<8,8,1>F { align1 1H }; +math cos(8) g3<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; +math cos(16) g4<1>F g2<8,8,1>F null<8,8,1>F { align1 1H }; +math intdiv(8) g4<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 1Q }; +math intdiv(8) g5<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 2Q }; +math intdiv(8) g24<1>D g4<0,1,0>D g2.2<0,1,0>D { align1 1Q }; +math sin(8) g10<1>F g9<8,8,1>F null<8,8,1>F { align1 1Q }; +math rsq(16) g68<1>F g66<8,8,1>F null<8,8,1>F { align1 1H }; +math exp(8) g124<1>F g10<8,8,1>F null<8,8,1>F { align1 1Q }; +math exp(16) g120<1>F g7<8,8,1>F null<8,8,1>F { align1 1H }; +math intdiv(8) g5<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 2Q }; +math sin(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; +math.sat pow(8) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1Q }; +math.sat pow(16) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; +math.sat sqrt(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; +math.sat sqrt(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; +math.sat exp(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; +math.sat exp(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; +math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F null<8,8,1>F { align1 1Q }; +math.sat inv(8) g124<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; +math.sat log(8) g127<1>F g7<8,8,1>F null<8,8,1>F { align1 1Q }; diff --git a/src/intel/tools/tests/gen9/math.expected b/src/intel/tools/tests/gen9/math.expected new file mode 100644 index 00000000000..9837a7cee3f --- /dev/null +++ b/src/intel/tools/tests/gen9/math.expected @@ -0,0 +1,31 @@ +38 00 80 04 e8 3a 80 22 40 02 8d 38 00 00 8d 00 +38 00 60 01 e8 3a e0 2b c0 0b 8d 38 00 00 8d 00 +38 00 80 01 e8 3a 40 21 00 01 8d 38 00 00 8d 00 +38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00 +38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00 +38 00 60 04 e8 3a 00 23 e0 02 8d 38 00 00 8d 00 +38 00 60 05 e8 3a a0 20 40 00 8d 38 00 00 8d 00 +38 00 60 0a e8 3a 60 21 40 01 8d 3e 66 66 fc 42 +38 00 80 0a e8 3a 40 22 00 02 8d 3e 66 66 fc 42 +38 00 60 02 e8 3a e0 20 c0 00 8d 38 00 00 8d 00 +38 00 80 02 e8 3a 60 21 20 01 8d 38 00 00 8d 00 +38 00 60 07 e8 3a 60 20 40 00 8d 38 00 00 8d 00 +38 00 80 07 e8 3a 80 20 40 00 8d 38 00 00 8d 00 +38 00 60 0c 08 02 80 20 20 00 00 02 30 00 00 00 +38 10 60 0c 08 02 a0 20 20 00 00 02 30 00 00 00 +38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00 +38 00 60 06 e8 3a 40 21 20 01 8d 38 00 00 8d 00 +38 00 80 05 e8 3a 80 28 40 08 8d 38 00 00 8d 00 +38 00 60 03 e8 3a 80 2f 40 01 8d 38 00 00 8d 00 +38 00 80 03 e8 3a 00 2f e0 00 8d 38 00 00 8d 00 +38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00 +38 00 80 06 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 +38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 +38 00 60 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 80 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 60 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 80 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 60 85 e8 3a e0 2f e0 20 8d 38 00 00 8d 00 +38 00 60 81 e8 3a 80 2f 40 00 00 38 00 00 8d 00 +38 00 60 82 e8 3a e0 2f e0 00 8d 38 00 00 8d 00 diff --git a/src/intel/tools/tests/gen9/mov.asm b/src/intel/tools/tests/gen9/mov.asm new file mode 100644 index 00000000000..833631bb9e2 --- /dev/null +++ b/src/intel/tools/tests/gen9/mov.asm @@ -0,0 +1,139 @@ +mov(8) g123<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; +mov(8) g124<1>F 0x40c00000F /* 6F */ { align1 1Q }; +mov(8) g14<1>UD 0x00000000UD { align1 1Q }; +mov(8) g17<1>F g12<8,8,1>F { align1 1Q }; +mov.sat(8) g124<1>F g8<8,8,1>F { align1 1Q }; +mov(8) g61<2>D g22<8,8,1>D { align1 1Q }; +mov(8) g21<1>D g59<8,4,2>UD { align1 1Q }; +mov(8) g4<1>D -1D { align1 1Q }; +mov.nz.f0.0(8) null<1>D g4<8,8,1>D { align1 1Q }; +mov(1) g2.2<1>UD 0x00000000UD { align1 WE_all 1N }; +mov(4) g114<1>F g2.3<8,2,4>F { align1 WE_all 1N }; +mov(8) g126<1>F g4<8,8,1>D { align1 1Q }; +mov(16) g124<1>F g4<8,8,1>D { align1 1H }; +mov(16) g120<1>F g124<8,8,1>F { align1 1H }; +mov(16) g124<1>F 0x0F /* 0F */ { align1 1H }; +mov(16) g124<1>D 1065353216D { align1 1H }; +mov.nz.f0.0(16) null<1>D g2<0,1,0>D { align1 1H }; +mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; +mov(16) g20<1>UD g0.1<0,1,0>UD { align1 1H }; +mov(16) g6<1>D g3<8,8,1>UW { align1 1H }; +mov(8) g1<1>D g4<8,8,1>D { align1 2Q }; +mov(8) g5<1>D 0D { align1 2Q }; +mov(8) g2<1>F g6<8,4,1>UW { align1 1Q }; +mov(8) g7<1>D g2<8,8,1>F { align1 1Q }; +mov(16) g2<1>F g10<8,4,1>UW { align1 1H }; +mov(16) g11<1>D g2<8,8,1>F { align1 1H }; +mov(8) g80<1>DF g5<0,1,0>DF { align1 1Q }; +mov(8) g92<2>UD g6.4<0,1,0>UD { align1 1Q }; +mov(8) g62<1>Q 0xbff0000000000000Q { align1 1Q }; +mov(8) g92<2>F g92<4,4,1>DF { align1 1Q }; +mov(8) g92<1>DF g95<4,4,1>F { align1 1Q }; +mov(8) g106<1>DF g2<0,1,0>F { align1 2Q }; +mov(8) g48<1>Q 0xbff0000000000000Q { align1 2Q }; +mov(8) g127<1>UD g106.1<8,4,2>UD { align1 2Q }; +mov(8) g11<2>F g7<4,4,1>DF { align1 2Q }; +mov(8) g33<1>D g34<8,4,2>UD { align1 2Q }; +mov(8) g6<2>UD 0x00000000UD { align1 2Q }; +mov(8) g2<1>UW 0x76543210UV { align1 1Q }; +mov(8) g12<1>UD g2<8,8,1>UW { align1 1Q }; +mov(8) g7<1>UD 0x00080000UD { align1 WE_all 1Q }; +mov(1) g2<1>F 0x3e800000F /* 0.25F */ { align1 WE_all 1N }; +mov(8) g15<1>F g11<8,8,1>UD { align1 1Q }; +mov(1) f0.1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; +mov(8) g18<1>UD g2<8,8,1>D { align1 1Q }; +mov(16) g18<1>UD g26<8,8,1>D { align1 1H }; +mov(16) g120<1>D g34<8,8,1>D { align1 1H }; +mov(8) g8<1>Q g13<4,4,1>Q { align1 1Q }; +mov(8) g21<1>UD g0<8,8,1>UD { align1 WE_all 2Q }; +mov(8) g23<1>F g6<0,1,0>F { align1 2Q }; +mov(1) g21.2<1>UD 0x000003f2UD { align1 WE_all 3N }; +mov.nz.f0.0(8) g19<1>D g3<8,4,2>UD { align1 1Q }; +mov(1) f1<1>UD g1.7<0,1,0>UD { align1 WE_all 1N }; +mov.sat(8) g126<1>F 0x0F /* 0F */ { align1 1Q }; +mov.sat(8) g124<1>F -g36<8,8,1>D { align1 1Q }; +mov(8) g41<1>F 0x0F /* 0F */ { align1 2Q }; +mov(8) g42<1>UD g11<8,8,1>D { align1 2Q }; +mov(16) g86<1>UD g88<8,8,1>UD { align1 WE_all 1H }; +mov.sat(16) g120<1>F g2<0,1,0>F { align1 1H }; +mov(16) g2<1>F g18<8,8,1>UD { align1 1H }; +mov(8) g4<1>UD 0x0F /* 0F */ { align1 1Q }; +mov(8) g8<1>DF g2<0,1,0>D { align1 1Q }; +mov(16) g8<1>UD 0x00000000UD { align1 1H }; +mov.nz.f0.0(8) g4<1>F -(abs)g2<0,1,0>F { align1 1Q }; +(+f0.0) mov(8) g4<1>F 0xbf800000F /* -1F */ { align1 1Q }; +mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 1H }; +(+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 1H }; +mov(1) f1<1>UD g1.7<0,1,0>UD { align1 WE_all 3N }; +mov(8) g32<1>DF g2<0,1,0>DF { align1 2Q }; +mov(8) g5<1>F g2<0,1,0>HF { align1 1Q }; +mov(16) g6<1>F g2<0,1,0>HF { align1 1H }; +mov(8) g7<1>UD g2<0,1,0>F { align1 1Q }; +mov(16) g15<1>UD g11<8,8,1>F { align1 1H }; +mov(16) g19<1>UD g15<16,8,2>UW { align1 1H }; +mov(1) g19<1>UD g[a0 64]<0,1,0>UD { align1 WE_all 1N }; +mov(16) g23<1>UD g21<32,8,4>UB { align1 1H }; +mov(8) g7<1>DF 0x0000000000000000DF /* 0DF */ { align1 1Q }; +mov(8) g5<1>F 0x0F /* 0F */ { align1 WE_all 1Q }; +mov(16) g4<1>UD 0x00000000UD { align1 WE_all 1H }; +mov(8) g5<2>UD g2<0,1,0>DF { align1 1Q }; +mov(8) g10<2>UD g2<0,1,0>DF { align1 2Q }; +mov(8) g3<1>DF g2<0,1,0>UD { align1 1Q }; +mov(8) g3<1>DF g2<0,1,0>UD { align1 2Q }; +mov(1) f0<1>UW 0x0000UW { align1 WE_all 1N }; +mov(1) g1<1>D 0D { align1 WE_all 1N }; +(+f0.0.any16h) mov(1) g1<1>D -1D { align1 WE_all 1N }; +mov(8) g9<1>F g2<0,1,0>W { align1 1Q }; +mov(8) g7<1>UQ g4<4,4,1>UQ { align1 1Q }; +mov(16) g11<1>UD 0x0F /* 0F */ { align1 1H }; +mov(8) g5<2>D g2<0,1,0>DF { align1 1Q }; +mov(8) g10<2>D g2<0,1,0>DF { align1 2Q }; +mov(1) f1<1>UW f0.1<0,1,0>UW { align1 WE_all 1N }; +mov(1) f1<1>UW f0.1<0,1,0>UW { align1 WE_all 3N }; +mov(16) g4<1>D 0D { align1 2H }; +mov(8) g14<1>UD g13<32,8,4>UB { align1 1Q }; +mov(16) g124<1>UD g15<8,8,1>UD { align1 2H }; +mov(16) g118<1>D g122<8,8,1>UW { align1 2H }; +mov(16) g101<1>UD 0x00000001UD { align1 2H }; +mov(1) g4<2>UW 0x00000000UD { align1 WE_all 1N }; +mov(8) g4<1>UD f0<0,1,0>UW { align1 1Q }; +mov(8) g8<1>D g2<8,8,1>UW { align1 1Q }; +mov(16) g4<1>UD f0<0,1,0>UW { align1 1H }; +mov(8) g3<1>DF -g2<0,1,0>D { align1 2Q }; +mov(8) g5<1>F g2<0,1,0>B { align1 1Q }; +mov(16) g6<1>F g2<0,1,0>B { align1 1H }; +mov(8) g4<1>DF 0x0000000000000000DF /* 0DF */ { align1 2Q }; +mov.nz.f0.0(8) g16<1>D g17<8,4,2>UD { align1 2Q }; +mov(8) g34<1>UW 0x76543210V { align1 1Q }; +mov(8) g8<1>UD 48D { align1 1Q }; +mov(16) g8<1>UD 0D { align1 1H }; +mov(8) g7<2>HF g2.1<0,1,0>F { align1 1Q }; +mov(1) g5<1>D g[a0 96]<0,1,0>D { align1 WE_all 1N }; +(+f0.0.any8h) mov(1) g2<1>D -1D { align1 WE_all 1N }; +mov(8) g9<1>UD 0D { align1 WE_all 1Q }; +mov(8) g2<2>UW g9<8,8,1>F { align1 1Q }; +mov(8) g3<1>UW g2<16,8,2>UW { align1 1Q }; +mov(8) g12<1>UW g8<16,8,2>UW { align1 WE_all 1Q }; +mov.sat(16) g13<1>F 0x3f800000F /* 1F */ { align1 1H }; +mov(16) g19<2>UW g17<8,8,1>F { align1 1H }; +mov(16) g4<1>UW g13<16,8,2>UW { align1 WE_all 1H }; +mov.nz.f0.0(8) null<1>D 0x00000000UD { align1 1Q }; +mov.nz.f0.0(16) null<1>D 0x00000000UD { align1 1H }; +mov(4) g3<1>UD tm0<4,4,1>UD { align1 WE_all 1N }; +(+f0.0.all16h) mov(1) g1<1>D -1D { align1 WE_all 1N }; +mov(8) g9<1>F g2<0,1,0>UB { align1 1Q }; +mov(16) g6<1>F g2<0,1,0>UB { align1 1H }; +mov(16) g10<2>HF g4<8,8,1>F { align1 1H }; +mov.z.f0.0(8) null<1>UD g2<8,8,1>UD { align1 1Q }; +mov.sat(8) g125<1>F g9<8,8,1>UD { align1 1Q }; +mov.z.f0.0(16) g1<1>UD g0.7<0,1,0>UD { align1 1H }; +mov.z.f0.0(8) g18<1>D g17<8,8,1>F { align1 1Q }; +mov(16) g35<1>F g15<16,8,2>W { align1 1H }; +mov(8) g23<1>Q g26<4,4,1>Q { align1 2Q }; +mov(8) g2<1>D 0x00000000UD { align1 1Q }; +mov(16) g2<1>D 0x00000000UD { align1 1H }; +(+f0.0.all8h) mov(1) g7<1>D -1D { align1 WE_all 1N }; +mov(8) g127<1>UB g2<0,1,0>UB { align1 WE_all 1Q }; +mov.z.f0.0(8) null<1>D g24<8,8,1>F { align1 1Q }; +mov.z.f0.0(16) null<1>D g76<8,8,1>F { align1 1H }; +mov(16) g7<1>D g2<16,8,2>B { align1 1H }; diff --git a/src/intel/tools/tests/gen9/mov.expected b/src/intel/tools/tests/gen9/mov.expected new file mode 100644 index 00000000000..c1dc96d9d60 --- /dev/null +++ b/src/intel/tools/tests/gen9/mov.expected @@ -0,0 +1,139 @@ +01 00 60 00 0c 02 60 2f 20 00 8d 00 00 00 00 00 +01 00 60 00 e8 3e 80 2f 00 00 00 38 00 00 c0 40 +01 00 60 00 08 06 c0 21 00 00 00 00 00 00 00 00 +01 00 60 00 e8 3a 20 22 80 01 8d 00 00 00 00 00 +01 00 60 80 e8 3a 80 2f 00 01 8d 00 00 00 00 00 +01 00 60 00 28 0a a0 47 c0 02 8d 00 00 00 00 00 +01 00 60 00 28 02 a0 22 60 07 8a 00 00 00 00 00 +01 00 60 00 28 0e 80 20 00 00 00 08 ff ff ff ff +01 00 60 02 20 0a 00 20 80 00 8d 00 00 00 00 00 +01 00 00 00 0c 06 48 20 00 00 00 00 00 00 00 00 +01 00 40 00 ec 3a 40 2e 4c 00 87 00 00 00 00 00 +01 00 60 00 e8 0a c0 2f 80 00 8d 00 00 00 00 00 +01 00 80 00 e8 0a 80 2f 80 00 8d 00 00 00 00 00 +01 00 80 00 e8 3a 00 2f 80 0f 8d 00 00 00 00 00 +01 00 80 00 e8 3e 80 2f 00 00 00 38 00 00 00 00 +01 00 80 00 28 0e 80 2f 00 00 00 08 00 00 80 3f +01 00 80 02 20 0a 00 20 40 00 00 00 00 00 00 00 +01 00 60 00 4c 36 60 20 00 00 00 30 10 32 54 76 +01 00 80 00 08 02 80 22 04 00 00 00 00 00 00 00 +01 00 80 00 28 12 c0 20 60 00 8d 00 00 00 00 00 +01 10 60 00 28 0a 20 20 80 00 8d 00 00 00 00 00 +01 10 60 00 28 0e a0 20 00 00 00 08 00 00 00 00 +01 00 60 00 e8 12 40 20 c0 00 89 00 00 00 00 00 +01 00 60 00 28 3a e0 20 40 00 8d 00 00 00 00 00 +01 00 80 00 e8 12 40 20 40 01 89 00 00 00 00 00 +01 00 80 00 28 3a 60 21 40 00 8d 00 00 00 00 00 +01 00 60 00 c8 32 00 2a a0 00 00 00 00 00 00 00 +01 00 60 00 08 02 80 4b d0 00 00 00 00 00 00 00 +01 00 60 00 28 4f c0 27 00 00 00 00 00 00 f0 bf +01 00 60 00 e8 32 80 4b 80 0b 69 00 00 00 00 00 +01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00 +01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00 +01 10 60 00 28 4f 00 26 00 00 00 00 00 00 f0 bf +01 10 60 00 08 02 e0 2f 44 0d 8a 00 00 00 00 00 +01 10 60 00 e8 32 60 41 e0 00 69 00 00 00 00 00 +01 10 60 00 28 02 20 24 40 04 8a 00 00 00 00 00 +01 10 60 00 08 06 c0 40 00 00 00 00 00 00 00 00 +01 00 60 00 48 26 40 20 00 00 00 20 10 32 54 76 +01 00 60 00 08 12 80 21 40 00 8d 00 00 00 00 00 +01 00 60 00 0c 06 e0 20 00 00 00 00 00 00 08 00 +01 00 00 00 ec 3e 40 20 00 00 00 38 00 00 80 3e +01 00 60 00 e8 02 e0 21 60 01 8d 00 00 00 00 00 +01 00 00 00 44 12 02 26 3c 00 00 00 00 00 00 00 +01 00 60 00 08 0a 40 22 40 00 8d 00 00 00 00 00 +01 00 80 00 08 0a 40 22 40 03 8d 00 00 00 00 00 +01 00 80 00 28 0a 00 2f 40 04 8d 00 00 00 00 00 +01 00 60 00 28 4b 00 21 a0 01 69 00 00 00 00 00 +01 10 60 00 0c 02 a0 22 00 00 8d 00 00 00 00 00 +01 10 60 00 e8 3a e0 22 c0 00 00 00 00 00 00 00 +01 10 00 00 0c 06 a8 22 00 00 00 00 f2 03 00 00 +01 00 60 02 28 02 60 22 60 00 8a 00 00 00 00 00 +01 00 00 00 04 02 20 26 3c 00 00 00 00 00 00 00 +01 00 60 80 e8 3e c0 2f 00 00 00 38 00 00 00 00 +01 00 60 80 e8 0a 80 2f 80 44 8d 00 00 00 00 00 +01 10 60 00 e8 3e 20 25 00 00 00 38 00 00 00 00 +01 10 60 00 08 0a 40 25 60 01 8d 00 00 00 00 00 +01 00 80 00 0c 02 c0 2a 00 0b 8d 00 00 00 00 00 +01 00 80 80 e8 3a 00 2f 40 00 00 00 00 00 00 00 +01 00 80 00 e8 02 40 20 40 02 8d 00 00 00 00 00 +01 00 60 00 08 3e 80 20 00 00 00 38 00 00 00 00 +01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00 +01 00 80 00 08 06 00 21 00 00 00 00 00 00 00 00 +01 00 60 02 e8 3a 80 20 40 60 00 00 00 00 00 00 +01 00 61 00 e8 3e 80 20 00 00 00 38 00 00 80 bf +01 00 80 02 e8 3a 80 20 40 60 00 00 00 00 00 00 +01 00 81 00 e8 3e 80 20 00 00 00 38 00 00 80 bf +01 10 00 00 04 02 20 26 3c 00 00 00 00 00 00 00 +01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00 +01 00 60 00 e8 52 a0 20 40 00 00 00 00 00 00 00 +01 00 80 00 e8 52 c0 20 40 00 00 00 00 00 00 00 +01 00 60 00 08 3a e0 20 40 00 00 00 00 00 00 00 +01 00 80 00 08 3a e0 21 60 01 8d 00 00 00 00 00 +01 00 80 00 08 12 60 22 e0 01 ae 00 00 00 00 00 +01 00 00 00 0c 02 60 22 40 80 00 00 00 00 00 00 +01 00 80 00 08 22 e0 22 a0 02 cf 00 00 00 00 00 +01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00 +01 00 60 00 ec 3e a0 20 00 00 00 38 00 00 00 00 +01 00 80 00 0c 06 80 20 00 00 00 00 00 00 00 00 +01 00 60 00 08 32 a0 40 40 00 00 00 00 00 00 00 +01 10 60 00 08 32 40 41 40 00 00 00 00 00 00 00 +01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00 +01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00 +01 00 00 00 44 16 00 26 00 00 00 10 00 00 00 00 +01 00 00 00 2c 0e 20 20 00 00 00 08 00 00 00 00 +01 00 0a 00 2c 0e 20 20 00 00 00 08 ff ff ff ff +01 00 60 00 e8 1a 20 21 40 00 00 00 00 00 00 00 +01 00 60 00 08 43 e0 20 80 00 69 00 00 00 00 00 +01 00 80 00 08 3e 60 21 00 00 00 38 00 00 00 00 +01 00 60 00 28 32 a0 40 40 00 00 00 00 00 00 00 +01 10 60 00 28 32 40 41 40 00 00 00 00 00 00 00 +01 00 00 00 44 10 20 26 02 06 00 00 00 00 00 00 +01 10 00 00 44 10 20 26 02 06 00 00 00 00 00 00 +01 20 80 00 28 0e 80 20 00 00 00 08 00 00 00 00 +01 00 60 00 08 22 c0 21 a0 01 cf 00 00 00 00 00 +01 20 80 00 08 02 80 2f e0 01 8d 00 00 00 00 00 +01 20 80 00 28 12 c0 2e 40 0f 8d 00 00 00 00 00 +01 20 80 00 08 06 a0 2c 00 00 00 00 01 00 00 00 +01 00 00 00 4c 06 80 40 00 00 00 00 00 00 00 00 +01 00 60 00 08 10 80 20 00 06 00 00 00 00 00 00 +01 00 60 00 28 12 00 21 40 00 8d 00 00 00 00 00 +01 00 80 00 08 10 80 20 00 06 00 00 00 00 00 00 +01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00 +01 00 60 00 e8 2a a0 20 40 00 00 00 00 00 00 00 +01 00 80 00 e8 2a c0 20 40 00 00 00 00 00 00 00 +01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00 +01 10 60 02 28 02 00 22 20 02 8a 00 00 00 00 00 +01 00 60 00 48 36 40 24 00 00 00 30 10 32 54 76 +01 00 60 00 08 0e 00 21 00 00 00 08 30 00 00 00 +01 00 80 00 08 0e 00 21 00 00 00 08 00 00 00 00 +01 00 60 00 48 3b e0 40 44 00 00 00 00 00 00 00 +01 00 00 00 2c 0a a0 20 60 80 00 00 00 00 00 00 +01 00 08 00 2c 0e 40 20 00 00 00 08 ff ff ff ff +01 00 60 00 0c 0e 20 21 00 00 00 08 00 00 00 00 +01 00 60 00 48 3a 40 40 20 01 8d 00 00 00 00 00 +01 00 60 00 48 12 60 20 40 00 ae 00 00 00 00 00 +01 00 60 00 4c 12 80 21 00 01 ae 00 00 00 00 00 +01 00 80 80 e8 3e a0 21 00 00 00 38 00 00 80 3f +01 00 80 00 48 3a 60 42 20 02 8d 00 00 00 00 00 +01 00 80 00 4c 12 80 20 a0 01 ae 00 00 00 00 00 +01 00 60 02 20 06 00 20 00 00 00 00 00 00 00 00 +01 00 80 02 20 06 00 20 00 00 00 00 00 00 00 00 +01 00 40 00 0c 00 60 20 00 18 69 00 00 00 00 00 +01 00 0b 00 2c 0e 20 20 00 00 00 08 ff ff ff ff +01 00 60 00 e8 22 20 21 40 00 00 00 00 00 00 00 +01 00 80 00 e8 22 c0 20 40 00 00 00 00 00 00 00 +01 00 80 00 48 3b 40 41 80 00 8d 00 00 00 00 00 +01 00 60 01 00 02 00 20 40 00 8d 00 00 00 00 00 +01 00 60 80 e8 02 a0 2f 20 01 8d 00 00 00 00 00 +01 00 80 01 08 02 20 20 1c 00 00 00 00 00 00 00 +01 00 60 01 28 3a 40 22 20 02 8d 00 00 00 00 00 +01 00 80 00 e8 1a 60 24 e0 01 ae 00 00 00 00 00 +01 10 60 00 28 4b e0 22 40 03 69 00 00 00 00 00 +01 00 60 00 28 06 40 20 00 00 00 00 00 00 00 00 +01 00 80 00 28 06 40 20 00 00 00 00 00 00 00 00 +01 00 09 00 2c 0e e0 20 00 00 00 08 ff ff ff ff +01 00 60 00 8c 22 e0 2f 40 00 00 00 00 00 00 00 +01 00 60 01 20 3a 00 20 00 03 8d 00 00 00 00 00 +01 00 80 01 20 3a 00 20 80 09 8d 00 00 00 00 00 +01 00 80 00 28 2a e0 20 40 00 ae 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/mul.asm b/src/intel/tools/tests/gen9/mul.asm new file mode 100644 index 00000000000..36f4a1bcf57 --- /dev/null +++ b/src/intel/tools/tests/gen9/mul.asm @@ -0,0 +1,31 @@ +mul(8) g22<1>F g4<8,8,1>F g2<0,1,0>F { align1 1Q }; +mul(16) g26<1>F g2<0,1,0>F g2<0,1,0>F { align1 1H }; +mul(8) g36<1>DF g8<0,1,0>DF g8<0,1,0>DF { align1 1Q }; +mul(8) g9<1>UD g86<8,8,1>UD 0x00000004UD { align1 1Q }; +mul(8) acc0<1>UD g17<8,8,1>UD 0xaaabUW { align1 1Q }; +mul(8) acc0<1>D g17<8,8,1>D 0x5556UW { align1 1Q }; +mul(8) g21<1>D g20<8,8,1>D 3D { align1 1Q }; +mul(8) acc0<1>UD g39<8,8,1>UD 0xaaabUW { align1 2Q }; +mul(16) g45<1>D g43<8,8,1>D 3D { align1 1H }; +mul(8) acc0<1>D g39<8,8,1>D 0x5556UW { align1 2Q }; +mul.z.f0.0(8) g10<1>F g5<0,1,0>F g9<8,8,1>F { align1 1Q }; +mul(8) g39<1>DF g3.3<0,1,0>DF g3.3<0,1,0>DF { align1 2Q }; +mul.z.f0.0(16) g6<1>F g2<0,1,0>F g4<8,8,1>F { align1 1H }; +mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q }; +mul.sat(16) g9<1>F g3<8,8,1>F g7<8,8,1>F { align1 1H }; +mul.l.f0.0(8) null<1>F g6<0,1,0>F g5.7<0,1,0>F { align1 1Q }; +mul.sat(8) g8<1>DF g34<4,4,1>DF g5<4,4,1>DF { align1 1Q }; +mul(8) g4<1>UQ g8<4,4,1>UD g12<4,4,1>UD { align1 1Q }; +mul(8) g20<1>UQ g5<4,4,1>UD g13<4,4,1>UD { align1 2Q }; +mul(8) g5<1>Q g9<4,4,1>D g13<4,4,1>D { align1 1Q }; +mul.sat(8) g10<1>DF g10<4,4,1>DF g16<4,4,1>DF { align1 2Q }; +mul.l.f0.0(8) g20<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1Q }; +mul.l.f0.0(16) g32<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1H }; +mul(1) g6<1>UD g12<0,1,0>UD 0x00000101UD { align1 WE_all 1N }; +mul(8) g21<1>Q g6<4,4,1>D g14<4,4,1>D { align1 2Q }; +mul.l.f0.0(16) null<1>F g2.2<0,1,0>F g2.1<0,1,0>F { align1 1H }; +mul(8) g6<1>UW g6<8,8,1>UW 0x0808UW { align1 1Q }; +mul(16) g15<1>UW g14<16,16,1>UW 0x0808UW { align1 1H }; +mul.nz.f0.0(8) g6<1>F g12<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1Q }; +mul.nz.f0.0(16) g9<1>F g7<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1H }; +mul(1) g4<1>UD g4<0,1,0>UD 0x00000101UD { align1 WE_all 3N }; diff --git a/src/intel/tools/tests/gen9/mul.expected b/src/intel/tools/tests/gen9/mul.expected new file mode 100644 index 00000000000..1a1a79c6467 --- /dev/null +++ b/src/intel/tools/tests/gen9/mul.expected @@ -0,0 +1,31 @@ +41 00 60 00 e8 3a c0 22 80 00 8d 3a 40 00 00 00 +41 00 80 00 e8 3a 40 23 40 00 00 3a 40 00 00 00 +41 00 60 00 c8 32 80 24 00 01 00 32 00 01 00 00 +41 00 60 00 08 02 20 21 c0 0a 8d 06 04 00 00 00 +41 00 60 00 00 02 00 24 20 02 8d 16 ab aa ab aa +41 00 60 00 20 0a 00 24 20 02 8d 16 56 55 56 55 +41 00 60 00 28 0a a0 22 80 02 8d 0e 03 00 00 00 +41 10 60 00 00 02 00 24 e0 04 8d 16 ab aa ab aa +41 00 80 00 28 0a a0 25 60 05 8d 0e 03 00 00 00 +41 10 60 00 20 0a 00 24 e0 04 8d 16 56 55 56 55 +41 00 60 01 e8 3a 40 21 a0 00 00 3a 20 01 8d 00 +41 10 60 00 c8 32 e0 24 78 00 00 32 78 00 00 00 +41 00 80 01 e8 3a c0 20 40 00 00 3a 80 00 8d 00 +41 00 60 80 e8 3a 20 22 80 00 8d 3a 00 02 8d 00 +41 00 80 80 e8 3a 20 21 60 00 8d 3a e0 00 8d 00 +41 00 60 05 e0 3a 00 20 c0 00 00 3a bc 00 00 00 +41 00 60 80 c8 32 00 21 40 04 69 32 a0 00 69 00 +41 00 60 00 08 03 80 20 00 01 69 02 80 01 69 00 +41 10 60 00 08 03 80 22 a0 00 69 02 a0 01 69 00 +41 00 60 00 28 0b a0 20 20 01 69 0a a0 01 69 00 +41 10 60 80 c8 32 40 21 40 01 69 32 00 02 69 00 +41 00 60 05 e8 3a 80 22 40 00 8d 3e 00 00 70 42 +41 00 80 05 e8 3a 00 24 40 00 8d 3e 00 00 70 42 +41 00 00 00 0c 02 c0 20 80 01 00 06 01 01 00 00 +41 10 60 00 28 0b a0 22 c0 00 69 0a c0 01 69 00 +41 00 80 05 e0 3a 00 20 48 00 00 3a 44 00 00 00 +41 00 60 00 48 12 c0 20 c0 00 8d 16 08 08 08 08 +41 00 80 00 48 12 e0 21 c0 01 b1 16 08 08 08 08 +41 00 60 02 e8 3a c0 20 80 01 8d 3e 00 80 80 3f +41 00 80 02 e8 3a 20 21 e0 00 8d 3e 00 80 80 3f +41 10 00 00 0c 02 80 20 80 00 00 06 01 01 00 00 diff --git a/src/intel/tools/tests/gen9/nop.asm b/src/intel/tools/tests/gen9/nop.asm new file mode 100644 index 00000000000..0b66395094f --- /dev/null +++ b/src/intel/tools/tests/gen9/nop.asm @@ -0,0 +1 @@ +nop ; diff --git a/src/intel/tools/tests/gen9/nop.expected b/src/intel/tools/tests/gen9/nop.expected new file mode 100644 index 00000000000..9a3dcf265b5 --- /dev/null +++ b/src/intel/tools/tests/gen9/nop.expected @@ -0,0 +1 @@ +7e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/not.asm b/src/intel/tools/tests/gen9/not.asm new file mode 100644 index 00000000000..ce4592bd74f --- /dev/null +++ b/src/intel/tools/tests/gen9/not.asm @@ -0,0 +1,2 @@ +not(16) g3<1>D g1.2<0,1,0>D { align1 1H }; +not(8) g4<1>D g8<8,8,1>D { align1 1Q }; diff --git a/src/intel/tools/tests/gen9/not.expected b/src/intel/tools/tests/gen9/not.expected new file mode 100644 index 00000000000..3a66a221c46 --- /dev/null +++ b/src/intel/tools/tests/gen9/not.expected @@ -0,0 +1,2 @@ +04 00 80 00 28 0a 60 20 28 00 00 00 00 00 00 00 +04 00 60 00 28 0a 80 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/or.asm b/src/intel/tools/tests/gen9/or.asm new file mode 100644 index 00000000000..3bfcc980749 --- /dev/null +++ b/src/intel/tools/tests/gen9/or.asm @@ -0,0 +1,23 @@ +or(8) g53<1>UD g49<8,8,1>UD g21<8,8,1>UD { align1 1Q }; +or.nz.f0.0(8) null<1>UD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q }; +or.nz.f0.0(8) g5<1>UD g62<8,8,1>UD g67<8,8,1>UD { align1 1Q }; +or(8) g5<1>UD g106.1<8,4,2>UD 0x7ff00000UD { align1 2Q }; +or.nz.f0.0(16) null<1>UD g35<8,8,1>UD g32<8,8,1>UD { align1 1H }; +or(16) g36<1>UD g34<8,8,1>UD g20<8,8,1>UD { align1 1H }; +or.nz.f0.0(16) g53<1>UD g51<8,8,1>UD g49<8,8,1>UD { align1 1H }; +or(1) g8<1>UD g8<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N }; +or(1) a0<1>UD g8<0,1,0>UD 0x060ba000UD { align1 WE_all 1N }; +(+f0.0) or(8) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1Q }; +(+f0.0) or(16) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1H }; +or(1) a0<1>UD a0<0,1,0>UD 0x02280300UD { align1 WE_all 1N }; +or(1) a0<1>UD g4<0,1,0>UD 0x04036000UD { align1 WE_all 3N }; +(+f0.0) or(8) g17.1<2>UD g17.1<8,4,2>UD 0x3ff00000UD { align1 2Q }; +or(8) g4<1>UW g4<8,8,1>UW g6<8,8,1>UW { align1 1Q }; +or(16) g16<1>UW g14<16,16,1>UW g15<16,16,1>UW { align1 1H }; +or(8) g22<1>UD ~g2.2<0,1,0>D g21<8,8,1>UD { align1 1Q }; +or(16) g37<1>UD ~g2.2<0,1,0>D g35<8,8,1>UD { align1 1H }; +or(8) g9<1>D ~g8<8,8,1>D ~g7<8,8,1>D { align1 1Q }; +or(16) g13<1>D ~g11<8,8,1>D ~g9<8,8,1>D { align1 1H }; +or(1) g14<1>UD g14<0,1,0>UD g19<0,1,0>UD { align1 WE_all 3N }; +or.z.f0.0(8) null<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 1Q }; +or.z.f0.0(16) null<1>UD g17<8,8,1>UD g19<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen9/or.expected b/src/intel/tools/tests/gen9/or.expected new file mode 100644 index 00000000000..61e2fccc15c --- /dev/null +++ b/src/intel/tools/tests/gen9/or.expected @@ -0,0 +1,23 @@ +06 00 60 00 08 02 a0 26 20 06 8d 02 a0 02 8d 00 +06 00 60 02 00 02 00 20 a0 02 8d 02 40 00 8d 00 +06 00 60 02 08 02 a0 20 c0 07 8d 02 60 08 8d 00 +06 10 60 00 08 02 a0 20 44 0d 8a 06 00 00 f0 7f +06 00 80 02 00 02 00 20 60 04 8d 02 00 04 8d 00 +06 00 80 00 08 02 80 24 40 04 8d 02 80 02 8d 00 +06 00 80 02 08 02 a0 26 60 06 8d 02 20 06 8d 00 +06 00 00 00 0c 02 00 21 00 01 00 02 80 00 00 00 +06 00 00 00 04 02 00 22 00 01 00 06 00 a0 0b 06 +06 00 61 00 08 02 60 20 60 00 8d 06 00 00 80 3f +06 00 81 00 08 02 60 20 60 00 8d 06 00 00 80 3f +06 00 00 00 04 00 00 22 00 02 00 06 00 03 28 02 +06 10 00 00 04 02 00 22 80 00 00 06 00 60 03 04 +06 10 61 00 08 02 24 42 24 02 8a 06 00 00 f0 3f +06 00 60 00 48 12 80 20 80 00 8d 12 c0 00 8d 00 +06 00 80 00 48 12 00 22 c0 01 b1 12 e0 01 b1 00 +06 00 60 00 08 0a c0 22 48 40 00 02 a0 02 8d 00 +06 00 80 00 08 0a a0 24 48 40 00 02 60 04 8d 00 +06 00 60 00 28 0a 20 21 00 41 8d 0a e0 40 8d 00 +06 00 80 00 28 0a a0 21 60 41 8d 0a 20 41 8d 00 +06 10 00 00 0c 02 c0 21 c0 01 00 02 60 02 00 00 +06 00 60 01 00 02 00 20 a0 00 8d 02 c0 00 8d 00 +06 00 80 01 00 02 00 20 20 02 8d 02 60 02 8d 00 diff --git a/src/intel/tools/tests/gen9/pln.asm b/src/intel/tools/tests/gen9/pln.asm new file mode 100644 index 00000000000..5b0adcf28cd --- /dev/null +++ b/src/intel/tools/tests/gen9/pln.asm @@ -0,0 +1,10 @@ +pln(8) g124<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln(16) g120<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.sat(8) g9<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.sat(16) g12<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.g.f0.0(8) g7<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.g.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.l.f0.0(8) g8<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.l.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.nz.f0.0(8) g18<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.nz.f0.0(16) g14<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen9/pln.expected b/src/intel/tools/tests/gen9/pln.expected new file mode 100644 index 00000000000..eb77b2a434f --- /dev/null +++ b/src/intel/tools/tests/gen9/pln.expected @@ -0,0 +1,10 @@ +5a 00 60 00 e8 3a 80 2f 80 00 00 3a 40 00 8d 00 +5a 00 80 00 e8 3a 00 2f c0 00 00 3a 40 00 8d 00 +5a 00 60 80 e8 3a 20 21 a0 00 00 3a 40 00 8d 00 +5a 00 80 80 e8 3a 80 21 e0 00 00 3a 40 00 8d 00 +5a 00 60 03 e8 3a e0 20 80 00 00 3a 40 00 8d 00 +5a 00 80 03 e8 3a 60 21 c0 00 00 3a 40 00 8d 00 +5a 00 60 05 e8 3a 00 21 80 00 00 3a 40 00 8d 00 +5a 00 80 05 e8 3a 60 21 c0 00 00 3a 40 00 8d 00 +5a 00 60 02 e8 3a 40 22 a0 00 00 3a 40 00 8d 00 +5a 00 80 02 e8 3a c0 21 e0 00 00 3a 40 00 8d 00 diff --git a/src/intel/tools/tests/gen9/rndd.asm b/src/intel/tools/tests/gen9/rndd.asm new file mode 100644 index 00000000000..463ef808ca9 --- /dev/null +++ b/src/intel/tools/tests/gen9/rndd.asm @@ -0,0 +1,5 @@ +rndd(8) g22<1>F g17<0,1,0>F { align1 1Q }; +rndd(16) g7<1>F g5<8,8,1>F { align1 1H }; +rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q }; +rndd.z.f0.0(16) null<1>F g39<8,8,1>F { align1 1H }; +rndd.sat(8) g124<1>F g10<8,8,1>F { align1 1Q }; diff --git a/src/intel/tools/tests/gen9/rndd.expected b/src/intel/tools/tests/gen9/rndd.expected new file mode 100644 index 00000000000..ff7ca82d09f --- /dev/null +++ b/src/intel/tools/tests/gen9/rndd.expected @@ -0,0 +1,5 @@ +45 00 60 00 e8 3a c0 22 20 02 00 00 00 00 00 00 +45 00 80 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00 +45 00 60 01 e0 3a 00 20 20 02 8d 00 00 00 00 00 +45 00 80 01 e0 3a 00 20 e0 04 8d 00 00 00 00 00 +45 00 60 80 e8 3a 80 2f 40 01 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/rnde.asm b/src/intel/tools/tests/gen9/rnde.asm new file mode 100644 index 00000000000..bc65bbcc02d --- /dev/null +++ b/src/intel/tools/tests/gen9/rnde.asm @@ -0,0 +1,2 @@ +rnde(8) g7<1>F g5<8,8,1>F { align1 1Q }; +rnde(16) g11<1>F g7<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen9/rnde.expected b/src/intel/tools/tests/gen9/rnde.expected new file mode 100644 index 00000000000..edac496ec93 --- /dev/null +++ b/src/intel/tools/tests/gen9/rnde.expected @@ -0,0 +1,2 @@ +46 00 60 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00 +46 00 80 00 e8 3a 60 21 e0 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/rndz.asm b/src/intel/tools/tests/gen9/rndz.asm new file mode 100644 index 00000000000..4b082d0539b --- /dev/null +++ b/src/intel/tools/tests/gen9/rndz.asm @@ -0,0 +1,2 @@ +rndz(8) g7<1>F g2<0,1,0>F { align1 1Q }; +rndz(16) g102<1>F g99<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen9/rndz.expected b/src/intel/tools/tests/gen9/rndz.expected new file mode 100644 index 00000000000..2a79a2372d9 --- /dev/null +++ b/src/intel/tools/tests/gen9/rndz.expected @@ -0,0 +1,2 @@ +47 00 60 00 e8 3a e0 20 40 00 00 00 00 00 00 00 +47 00 80 00 e8 3a c0 2c 60 0c 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen9/sel.asm b/src/intel/tools/tests/gen9/sel.asm new file mode 100644 index 00000000000..6047c31b517 --- /dev/null +++ b/src/intel/tools/tests/gen9/sel.asm @@ -0,0 +1,33 @@ +(-f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x3f800000UD { align1 1Q }; +(+f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x00000000UD { align1 1Q }; +(+f0.0) sel(8) g24<1>UQ g66<4,4,1>UQ g40<4,4,1>UQ { align1 1Q }; +(+f0.0) sel(8) g36<1>UQ g50<4,4,1>UQ g31<4,4,1>UQ { align1 2Q }; +sel.ge(8) g17<1>F (abs)g16<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; +sel.ge(16) g37<1>F (abs)g35<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +(+f0.0) sel(16) g26<1>UD g31<8,8,1>UD g33<8,8,1>UD { align1 1H }; +(-f0.0) sel(16) g1<1>UD g55<8,8,1>UD 0x00000000UD { align1 1H }; +sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q }; +sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H }; +sel.ge(8) g3<1>D g2<0,1,0>D -1D { align1 1Q }; +sel.l(8) g4<1>D g3<8,8,1>D 1D { align1 1Q }; +sel.ge(16) g3<1>D g2<0,1,0>D -1D { align1 1H }; +sel.l(16) g5<1>D g3<8,8,1>D 1D { align1 1H }; +sel.l(8) g8<1>F g7<8,8,1>F 0x43000000F /* 128F */ { align1 1Q }; +(-f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +sel.l(8) g18<1>DF g5<0,1,0>DF g5.1<0,1,0>DF { align1 1Q }; +sel.ge(16) g37<1>UD g9<8,8,1>UD g13<8,8,1>UD { align1 1H }; +sel.ge(8) g19<1>UD g5<0,1,0>UD g5.4<0,1,0>UD { align1 1Q }; +sel.sat.l(8) g124<1>F g6<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +(+f0.0) sel(8) g26<1>F g5<0,1,0>F (abs)g5.3<0,1,0>F { align1 1Q }; +(-f0.0) sel(8) g44<1>F (abs)g41<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; +sel.l(16) g120<1>F g2.3<0,1,0>F g2.2<0,1,0>F { align1 1H }; +(+f0.0) sel(8) g9<1>DF g2<0,1,0>DF -g2<0,1,0>DF { align1 1Q }; +(+f0.0) sel(8) g12<1>DF g2<0,1,0>DF -g2<0,1,0>DF { align1 2Q }; +sel.ge(8) g5<1>DF g2<0,1,0>DF g2.2<0,1,0>DF { align1 1Q }; +sel.ge(8) g35<1>DF g2<0,1,0>DF g2.2<0,1,0>DF { align1 2Q }; +sel.l(8) g11<1>DF g35<4,4,1>DF g3<0,1,0>DF { align1 2Q }; +(+f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +(-f0.0) sel(16) g27<1>F (abs)g25<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +(+f0.0) sel(16) g36<1>F g2<0,1,0>F (abs)g2.4<0,1,0>F { align1 1H }; +(+f0.0) sel(16) g116<1>UD g112<8,8,1>UD g114<8,8,1>UD { align1 2H }; +sel.sat.l(16) g8<1>F g83<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; diff --git a/src/intel/tools/tests/gen9/sel.expected b/src/intel/tools/tests/gen9/sel.expected new file mode 100644 index 00000000000..aba34ca3d75 --- /dev/null +++ b/src/intel/tools/tests/gen9/sel.expected @@ -0,0 +1,33 @@ +02 00 71 00 08 02 80 2f 80 0f 8d 06 00 00 80 3f +02 00 61 00 08 02 80 2f 80 0f 8d 06 00 00 00 00 +02 00 61 00 08 43 00 23 40 08 69 42 00 05 69 00 +02 10 61 00 08 43 80 24 40 06 69 42 e0 03 69 00 +02 00 60 04 e8 3a 20 22 00 22 8d 3e 00 00 80 3f +02 00 80 04 e8 3a a0 24 60 24 8d 3e 00 00 80 3f +02 00 81 00 08 02 40 23 e0 03 8d 02 20 04 8d 00 +02 00 91 00 08 02 20 20 e0 06 8d 06 00 00 00 00 +02 00 60 05 08 02 60 20 44 00 00 06 01 00 00 00 +02 00 80 05 08 02 60 20 44 00 00 06 01 00 00 00 +02 00 60 04 28 0a 60 20 40 00 00 0e ff ff ff ff +02 00 60 05 28 0a 80 20 60 00 8d 0e 01 00 00 00 +02 00 80 04 28 0a 60 20 40 00 00 0e ff ff ff ff +02 00 80 05 28 0a a0 20 60 00 8d 0e 01 00 00 00 +02 00 60 05 e8 3a 00 21 e0 00 8d 3e 00 00 00 43 +02 00 71 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00 +02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00 +02 00 80 04 08 02 a0 24 20 01 8d 02 a0 01 8d 00 +02 00 60 04 08 02 60 22 a0 00 00 02 b0 00 00 00 +02 00 60 85 e8 3a 80 2f c0 00 8d 3e 00 00 00 3f +02 00 61 00 e8 3a 40 23 a0 00 00 3a ac 20 00 00 +02 00 71 00 e8 3a 80 25 20 25 8d 3e 00 00 80 3f +02 00 80 05 e8 3a 00 2f 4c 00 00 3a 48 00 00 00 +02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00 +02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00 +02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00 +02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00 +02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00 +02 00 61 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00 +02 00 91 00 e8 3a 60 23 20 23 8d 3e 00 00 80 3f +02 00 81 00 e8 3a 80 24 40 00 00 3a 50 20 00 00 +02 20 81 00 08 02 80 2e 00 0e 8d 02 40 0e 8d 00 +02 00 80 85 e8 3a 00 21 60 0a 8d 3e 00 00 00 3f diff --git a/src/intel/tools/tests/gen9/send.asm b/src/intel/tools/tests/gen9/send.asm new file mode 100644 index 00000000000..918859e7d52 --- /dev/null +++ b/src/intel/tools/tests/gen9/send.asm @@ -0,0 +1,3606 @@ +send(8) null<1>F g123<8,8,1>F 0x8a080017 + urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g13<8,8,1>F 0x12080007 + urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080027 + urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(16) g9<1>UD g2<0,1,0>UD 0x02280300 + const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) null<1>F g119<8,8,1>F 0x92080017 + urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(16) null<1>UW g127<8,8,1>UW 0x82000010 + thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; +send(8) g124<1>UW g13<8,8,1>UD 0x0643a001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g120<1>UW g23<8,8,1>UD 0x0c85a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) g10<1>UD g2<8,8,1>UD 0x02480028 + urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g8<8,8,1>F 0x140a0017 + urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g118<8,8,1>F 0x940a0017 + urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) g2<1>UW g10<8,8,1>UD 0x08427001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW g18<8,8,1>UD 0x10847001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) null<1>F g11<8,8,1>UD 0x0c0a0037 + urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0a080027 + urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0c088017 + urb MsgDesc: 1 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0a088017 + urb MsgDesc: 1 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x08088017 + urb MsgDesc: 1 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g2<8,8,1>UD 0x06088017 + urb MsgDesc: 1 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0c088007 + urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0a088007 + urb MsgDesc: 0 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g125<8,8,1>UD 0x86088007 + urb MsgDesc: 0 SIMD8 write masked mlen 3 rlen 0 { align1 1Q EOT }; +send(8) g7<1>UW g7<8,8,1>UD 0x0443a000 + sampler MsgDesc: ld_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g10<1>UW g6<8,8,1>UD 0x0222a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; +send(8) g2<1>UW g19<8,8,1>UD 0x084a8001 + sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g25<1>UW g16<8,8,1>UD 0x0444a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; +send(16) g14<1>UW g7<8,8,1>UD 0x0e8c8001 + sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; +send(8) null<1>F g11<8,8,1>F 0x12080017 + urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>F 0x12080037 + urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080057 + urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g9<1>UW g6<8,8,1>UD 0x0613d001 + sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(16) g12<1>UW g14<8,8,1>UD 0x0c25d001 + sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; +send(8) g2<1>UW g14<8,8,1>UD 0x0643d001 + sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g8<1>UW g17<8,8,1>UD 0x0a43e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g26<1>UW g10<8,8,1>UD 0x0c85d001 + sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(16) g34<1>UW g16<8,8,1>UD 0x1485e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(8) g5<1>UW g2<8,8,1>UD 0x04320001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; +send(16) g7<1>UW g2<8,8,1>UD 0x08640001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H }; +send(8) g12<1>UW g10<8,8,1>UD 0x0a33e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q }; +send(16) g2<1>UW g18<8,8,1>UD 0x1465e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H }; +send(8) g5<1>UW g2<8,8,1>UD 0x04420001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g7<1>UW g2<8,8,1>UD 0x08840001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g11<1>UW g9<8,8,1>UD 0x0222a000 + sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; +send(8) g124<1>UW g13<8,8,1>UD 0x064a8000 + sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g12<1>UW g5<8,8,1>UD 0x02427000 + sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080037 + urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g6<1>UW g11<8,8,1>UD 0x144a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q }; +(+f1.0) send(8) g125<1>UW g3<8,8,1>UD 0x0210b501 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; +(+f1.0) send(16) g122<1>UW g4<8,8,1>UD 0x0420a501 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; +send(8) g6<1>UW g12<8,8,1>UD 0x084a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g98<1>UW g17<8,8,1>UD 0x0c43c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g124<1>UW g8<8,8,1>UD 0x064a8001 + sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g120<1>UW g12<8,8,1>UD 0x0a8c8001 + sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x0a1a6001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g7<1>UW g12<8,8,1>UD 0x0a1a6102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(16) g10<1>UW g12<8,8,1>UD 0x122c6001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H }; +send(16) g12<1>UW g21<8,8,1>UD 0x122c6102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H }; +send(8) g124<1>UW g3<8,8,1>UD 0x0a43e000 + sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080027 + urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g2<1>UW g3<8,8,1>UD 0x0643d000 + sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) null<1>F g7<8,8,1>UD 0x0a080037 + urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g8<8,8,1>UD 0x0a080047 + urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>F 0x0c0a0017 + urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g122<8,8,1>F 0x8c0a0017 + urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g13<1>UW g10<8,8,1>UD 0x02320001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; +send(16) g22<1>UW g18<8,8,1>UD 0x04640001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x0232a000 + sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x0c4b1001 + sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(16) g18<1>UW g7<8,8,1>UD 0x168d1001 + sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(8) null<1>F g6<8,8,1>UD 0x0a088027 + urb MsgDesc: 2 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g7<8,8,1>UD 0x0a088037 + urb MsgDesc: 3 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g8<8,8,1>UD 0x0a088047 + urb MsgDesc: 4 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g9<8,8,1>UD 0x0a088057 + urb MsgDesc: 5 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) g124<1>UW g3<8,8,1>UD 0x06427000 + sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x06427001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g18<8,8,1>UD 0x0c847001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) g6<1>UW g10<8,8,1>UD 0x0c424001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g2<1>UW g7<8,8,1>UD 0x0c4b1000 + sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g2<1>UW g4<8,8,1>UD 0x0242a000 + sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x0242a101 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; +send(8) g10<1>UW g10<8,8,1>UD 0x0242a202 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UW g14<8,8,1>UD 0x0242a303 + sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 4 { align1 1Q }; +send(8) g18<1>UW g18<8,8,1>UD 0x0242a404 + sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UW g22<8,8,1>UD 0x0242a505 + sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UW g26<8,8,1>UD 0x0242a606 + sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 6 mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UD g15<8,8,1>UD 0x042a0318 + urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g8<1>UD g15<8,8,1>UD 0x042a0518 + urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g10<1>UD g15<8,8,1>UD 0x042a0718 + urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g12<1>UD g15<8,8,1>UD 0x042a0918 + urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g14<1>UD g15<8,8,1>UD 0x042a0128 + urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g16<1>UD g14<8,8,1>UD 0x042a0218 + urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g18<1>UD g14<8,8,1>UD 0x042a0418 + urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g20<1>UD g14<8,8,1>UD 0x042a0618 + urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g22<1>UD g14<8,8,1>UD 0x042a0818 + urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g13<1>UD g14<8,8,1>UD 0x042a0028 + urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g30<8,8,1>UD 0x02480208 + urb MsgDesc: 32 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UD g30<8,8,1>UD 0x02480408 + urb MsgDesc: 64 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g18<1>UD g30<8,8,1>UD 0x02480608 + urb MsgDesc: 96 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g30<8,8,1>UD 0x02480808 + urb MsgDesc: 128 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0a0a8217 + urb MsgDesc: 33 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x0a0a8227 + urb MsgDesc: 34 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0a0a8237 + urb MsgDesc: 35 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x0a0a8247 + urb MsgDesc: 36 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x0a0a8257 + urb MsgDesc: 37 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0a0a8267 + urb MsgDesc: 38 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0a0a8277 + urb MsgDesc: 39 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0a0a8287 + urb MsgDesc: 40 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0a0a8297 + urb MsgDesc: 41 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0a0a82a7 + urb MsgDesc: 42 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0a0a82b7 + urb MsgDesc: 43 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0a0a82c7 + urb MsgDesc: 44 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0a0a82d7 + urb MsgDesc: 45 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0a0a82e7 + urb MsgDesc: 46 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0a0a82f7 + urb MsgDesc: 47 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0a0a8307 + urb MsgDesc: 48 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0a0a8317 + urb MsgDesc: 49 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0a0a8327 + urb MsgDesc: 50 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0a0a8337 + urb MsgDesc: 51 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0a0a8347 + urb MsgDesc: 52 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0a0a8357 + urb MsgDesc: 53 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0a0a8367 + urb MsgDesc: 54 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0a0a8377 + urb MsgDesc: 55 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0a0a8387 + urb MsgDesc: 56 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0a0a8397 + urb MsgDesc: 57 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0a0a83a7 + urb MsgDesc: 58 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0a0a83b7 + urb MsgDesc: 59 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0a0a83c7 + urb MsgDesc: 60 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0a0a83d7 + urb MsgDesc: 61 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0a0a83e7 + urb MsgDesc: 62 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0a0a83f7 + urb MsgDesc: 63 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x08088027 + urb MsgDesc: 2 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x08088037 + urb MsgDesc: 3 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x08088047 + urb MsgDesc: 4 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x08088057 + urb MsgDesc: 5 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x08088067 + urb MsgDesc: 6 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x08088077 + urb MsgDesc: 7 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x08088087 + urb MsgDesc: 8 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x08088097 + urb MsgDesc: 9 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x080880a7 + urb MsgDesc: 10 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x080880b7 + urb MsgDesc: 11 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x080880c7 + urb MsgDesc: 12 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x080880d7 + urb MsgDesc: 13 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x080880e7 + urb MsgDesc: 14 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x080880f7 + urb MsgDesc: 15 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x08088107 + urb MsgDesc: 16 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x08088117 + urb MsgDesc: 17 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x08088127 + urb MsgDesc: 18 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x08088137 + urb MsgDesc: 19 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x08088147 + urb MsgDesc: 20 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x08088157 + urb MsgDesc: 21 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x08088167 + urb MsgDesc: 22 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x08088177 + urb MsgDesc: 23 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x08088187 + urb MsgDesc: 24 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x08088197 + urb MsgDesc: 25 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x080881a7 + urb MsgDesc: 26 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x080881b7 + urb MsgDesc: 27 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x080881c7 + urb MsgDesc: 28 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x080881d7 + urb MsgDesc: 29 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x080881e7 + urb MsgDesc: 30 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x080881f7 + urb MsgDesc: 31 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x02480018 + urb MsgDesc: 1 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x0c0a0207 + urb MsgDesc: 32 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080057 + urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g10<1>UW g18<8,8,1>UD 0x084a8000 + sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g124<1>UW g2<8,8,1>UD 0x04229001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x08449001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; +send(16) g32<1>UW g44<8,8,1>UD 0x0865a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H }; +send(16) null<1>UW g5<8,8,1>UD 0x04008502 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(8) g5<1>UW g3<8,8,1>UD 0x02427001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(16) g8<1>UW g5<8,8,1>UD 0x04847001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(8) null<1>F g119<8,8,1>F 0x92080007 + urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g126<8,8,1>UD 0x84080017 + urb MsgDesc: 1 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; +send(8) g2<1>UW g13<8,8,1>UD 0x0a4b1001 + sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g16<1>UW g7<8,8,1>UD 0x128d1001 + sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; +send(8) g38<1>UD g1<8,8,1>UD 0x02180028 + urb MsgDesc: 2 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g40<1>UD g1<8,8,1>UD 0x02180038 + urb MsgDesc: 3 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g42<1>UD g1<8,8,1>UD 0x02180048 + urb MsgDesc: 4 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g44<1>UD g1<8,8,1>UD 0x02180058 + urb MsgDesc: 5 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g46<1>UD g1<8,8,1>UD 0x02180068 + urb MsgDesc: 6 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g48<1>UD g1<8,8,1>UD 0x02180078 + urb MsgDesc: 7 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g50<1>UD g1<8,8,1>UD 0x02180088 + urb MsgDesc: 8 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g52<1>UD g1<8,8,1>UD 0x02180098 + urb MsgDesc: 9 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g54<1>UD g1<8,8,1>UD 0x021800a8 + urb MsgDesc: 10 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g56<1>UD g1<8,8,1>UD 0x021800b8 + urb MsgDesc: 11 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g58<1>UD g1<8,8,1>UD 0x021800c8 + urb MsgDesc: 12 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g60<1>UD g1<8,8,1>UD 0x021800d8 + urb MsgDesc: 13 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g62<1>UD g1<8,8,1>UD 0x021800e8 + urb MsgDesc: 14 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g64<1>UD g1<8,8,1>UD 0x021800f8 + urb MsgDesc: 15 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g66<1>UD g1<8,8,1>UD 0x02180108 + urb MsgDesc: 16 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g68<1>UD g1<8,8,1>UD 0x02180118 + urb MsgDesc: 17 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g70<1>UD g1<8,8,1>UD 0x02180128 + urb MsgDesc: 18 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g72<1>UD g1<8,8,1>UD 0x02180138 + urb MsgDesc: 19 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g74<1>UD g1<8,8,1>UD 0x02180148 + urb MsgDesc: 20 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g76<1>UD g1<8,8,1>UD 0x02180158 + urb MsgDesc: 21 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g78<1>UD g1<8,8,1>UD 0x02180168 + urb MsgDesc: 22 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g80<1>UD g1<8,8,1>UD 0x02180178 + urb MsgDesc: 23 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g82<1>UD g1<8,8,1>UD 0x02180188 + urb MsgDesc: 24 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g84<1>UD g1<8,8,1>UD 0x02180198 + urb MsgDesc: 25 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g86<1>UD g1<8,8,1>UD 0x021801a8 + urb MsgDesc: 26 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g88<1>UD g1<8,8,1>UD 0x021801b8 + urb MsgDesc: 27 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g90<1>UD g1<8,8,1>UD 0x021801c8 + urb MsgDesc: 28 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g92<1>UD g1<8,8,1>UD 0x021801d8 + urb MsgDesc: 29 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g94<1>UD g1<8,8,1>UD 0x021801e8 + urb MsgDesc: 30 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g96<1>UD g1<8,8,1>UD 0x021801f8 + urb MsgDesc: 31 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g98<1>UD g1<8,8,1>UD 0x02180208 + urb MsgDesc: 32 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0c0a0027 + urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>UW g126<0,1,0>UD 0x040a02fd + data MsgDesc: ( DC OWORD block write, 253, 2) mlen 2 rlen 0 { align1 1Q }; +send(8) g115<1>UW g115<0,1,0>UD 0x021802fd + data MsgDesc: ( DC OWORD block read, 253, 2) mlen 1 rlen 1 { align1 WE_all 1Q }; +send(8) null<1>F g25<8,8,1>F 0x12080057 + urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>F 0x12080077 + urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g43<8,8,1>F 0x12080097 + urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g52<8,8,1>F 0x120800b7 + urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g61<8,8,1>F 0x120800d7 + urb MsgDesc: 13 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g70<8,8,1>F 0x120800f7 + urb MsgDesc: 15 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g2<8,8,1>F 0x12080117 + urb MsgDesc: 17 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g2<8,8,1>F 0x12080137 + urb MsgDesc: 19 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g2<8,8,1>F 0x12080157 + urb MsgDesc: 21 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g79<8,8,1>F 0x12080177 + urb MsgDesc: 23 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g88<8,8,1>F 0x12080197 + urb MsgDesc: 25 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g97<8,8,1>F 0x120801b7 + urb MsgDesc: 27 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g106<8,8,1>F 0x120801d7 + urb MsgDesc: 29 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g117<8,8,1>F 0x920801f7 + urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g11<8,8,1>UD 0x02229001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; +send(16) g120<1>UW g11<8,8,1>UD 0x04449001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; +send(8) g124<1>UW g3<8,8,1>UD 0x08427000 + sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) null<1>UW g40<8,8,1>UD 0x04008501 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(8) null<1>F g127<8,8,1>UD 0x82080007 + urb MsgDesc: 0 SIMD8 write mlen 1 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g9<8,8,1>UD 0x0a4a8000 + sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) g2<1>UW g23<8,8,1>UD 0x0633a001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; +send(16) g4<1>UW g12<8,8,1>UD 0x0c65a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; +send(8) g2<1>UW g16<8,8,1>UD 0x0e434001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 2Q }; +(+f1.0) send(8) null<1>UW g4<8,8,1>UD 0x02009501 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; +send(8) g6<1>UW g9<8,8,1>UD 0x08434001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) null<1>F g102<8,8,1>F 0x120801f7 + urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g121<8,8,1>F 0x8a080217 + urb MsgDesc: 33 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(16) null<1>UW g3<0,1,0>UD 0x02008004 + gateway MsgDesc: (barrier msg) mlen 1 rlen 0 { align1 WE_all 1H }; +send(16) g3<1>UW g14<8,8,1>UD 0x04205efe + dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(8) null<1>F g30<8,8,1>F 0x140a0027 + urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>F 0x0c0a0047 + urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g126<8,8,1>UD 0x84080007 + urb MsgDesc: 0 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; +send(8) g5<1>UW g11<8,8,1>UD 0x04415001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g3<8,8,1>UD 0x04416001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; +send(8) g13<1>UD g3<8,8,1>UD 0x02480038 + urb MsgDesc: 3 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g7<8,8,1>F 0x140a0037 + urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) g15<1>UD g2<8,8,1>UD 0x02280038 + urb MsgDesc: 3 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080037 + urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g8<8,8,1>F 0x140a0007 + urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g118<8,8,1>F 0x940a0007 + urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g12<8,8,1>UD a0<0,1,0>UD 0x00000200 + sampler MsgDesc: indirect { align1 1Q }; +send(8) g10<1>UD g2<8,8,1>UD 0x02480048 + urb MsgDesc: 4 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UD g2<8,8,1>UD 0x02480088 + urb MsgDesc: 8 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UD g2<8,8,1>UD 0x02480058 + urb MsgDesc: 5 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g11<1>UD g2<8,8,1>UD 0x024800a8 + urb MsgDesc: 10 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g18<1>UD g2<8,8,1>UD 0x02480068 + urb MsgDesc: 6 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g2<8,8,1>UD 0x023800c8 + urb MsgDesc: 12 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g2<8,8,1>UD 0x02480078 + urb MsgDesc: 7 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x024800b8 + urb MsgDesc: 11 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g7<1>UD g2<8,8,1>UD 0x02480098 + urb MsgDesc: 9 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x920800b7 + urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g6<1>UW g8<8,8,1>UD 0x084b0000 + sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g7<1>UW g0<8,8,1>UD 0x02200008 + pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 2 { align1 1Q }; +send(16) g9<1>UW g0<8,8,1>UD 0x02410008 + pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 4 { align1 1H }; +send(8) g2<1>UW g11<8,8,1>UD 0x0443d001 + sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g9<8,8,1>UD 0x0843e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW g15<8,8,1>UD 0x0885d001 + sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g43<1>UW g11<8,8,1>UD 0x1085e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) g2<1>UW g6<8,8,1>UD 0x0a4b1000 + sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) g74<1>UD g2<8,8,1>UD 0x02280028 + urb MsgDesc: 2 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g7<1>UD g2<8,8,1>UD 0x02380028 + urb MsgDesc: 2 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g15<1>UD g2<8,8,1>UD 0x02380038 + urb MsgDesc: 3 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g124<1>UW g3<8,8,1>UD 0x0843e000 + sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g2<1>UW g3<8,8,1>UD 0x0443d000 + sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g19<8,8,1>UD 0x0a4a8001 + sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g7<1>UW g16<8,8,1>UD 0x128c8001 + sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; +send(8) null<1>F g2<8,8,1>F 0x0c0a0057 + urb MsgDesc: 5 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g9<8,8,1>UD 0x04080027 + urb MsgDesc: 2 SIMD8 write mlen 2 rlen 0 { align1 1Q }; +send(8) g6<1>UW g7<8,8,1>UD 0x08134001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g7<1>UW g11<8,8,1>UD 0x08134102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(8) g13<1>UW g17<8,8,1>UD 0x021ab000 + sampler MsgDesc: sampleinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>F g50<8,8,1>F 0x140a0057 + urb MsgDesc: 5 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g60<8,8,1>F 0x140a0077 + urb MsgDesc: 7 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g70<8,8,1>F 0x0c0a0097 + urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g122<8,8,1>F 0x8c0a0097 + urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g6<8,8,1>UD 0x0a4b0000 + sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) g5<1>UW g6<8,8,1>UD 0x061a3001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(8) g6<1>UW g9<8,8,1>UD 0x061a3102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; +send(16) g9<1>UW g11<8,8,1>UD 0x0a2c3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1H }; +send(16) g11<1>UW g2<8,8,1>UD 0x0a2c3102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 2 { align1 1H }; +send(8) null<1>F g123<8,8,1>F 0x8a080077 + urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g30<8,8,1>UD 0x0c0a0067 + urb MsgDesc: 6 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0c0a0077 + urb MsgDesc: 7 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g42<8,8,1>UD 0x0c0a0087 + urb MsgDesc: 8 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x06420102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(16) g10<1>UW g18<8,8,1>UD 0x0c840102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; +send(8) g2<1>UW g2<8,8,1>UD 0x04420102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x06420304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g10<8,8,1>UD 0x08840102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(16) g10<1>UW g18<8,8,1>UD 0x0c840304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 6 rlen 8 { align1 1H }; +send(8) g2<1>UW g2<8,8,1>UD 0x04420304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x06420708 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g10<8,8,1>UD 0x08840304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H }; +send(16) g10<1>UW g18<8,8,1>UD 0x0c840708 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 6 rlen 8 { align1 1H }; +send(8) g3<1>UW g11<8,8,1>UD 0x0a43c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g16<1>UW g5<8,8,1>UD 0x1485c001 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(16) g4<1>UD g13<0,1,0>UD 0x02280301 + const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g2<1>UW g2<8,8,1>UD 0x0443a001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW g10<8,8,1>UD 0x0885a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g12<1>UW g12<8,8,1>UD 0x06125001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(8) g13<1>UW g15<8,8,1>UD 0x06125102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; +send(16) g20<1>UW g22<8,8,1>UD 0x0c245001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; +send(16) g22<1>UW g28<8,8,1>UD 0x0c245102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; +send(8) g38<1>UD g2<8,8,1>UD 0x024800c8 + urb MsgDesc: 12 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g39<1>UD g2<8,8,1>UD 0x024800d8 + urb MsgDesc: 13 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g40<1>UD g2<8,8,1>UD 0x024800e8 + urb MsgDesc: 14 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g41<1>UD g2<8,8,1>UD 0x024800f8 + urb MsgDesc: 15 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g42<1>UD g2<8,8,1>UD 0x02480108 + urb MsgDesc: 16 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g43<1>UD g2<8,8,1>UD 0x02480118 + urb MsgDesc: 17 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g44<1>UD g2<8,8,1>UD 0x02480128 + urb MsgDesc: 18 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g45<1>UD g2<8,8,1>UD 0x02480138 + urb MsgDesc: 19 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g46<1>UD g2<8,8,1>UD 0x02480148 + urb MsgDesc: 20 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g47<1>UD g2<8,8,1>UD 0x02480158 + urb MsgDesc: 21 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g48<1>UD g2<8,8,1>UD 0x02480168 + urb MsgDesc: 22 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g49<1>UD g2<8,8,1>UD 0x02480178 + urb MsgDesc: 23 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g50<1>UD g2<8,8,1>UD 0x02480188 + urb MsgDesc: 24 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g51<1>UD g2<8,8,1>UD 0x02480198 + urb MsgDesc: 25 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g52<1>UD g2<8,8,1>UD 0x024801a8 + urb MsgDesc: 26 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g53<1>UD g2<8,8,1>UD 0x024801b8 + urb MsgDesc: 27 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g54<1>UD g2<8,8,1>UD 0x024801c8 + urb MsgDesc: 28 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g55<1>UD g2<8,8,1>UD 0x024801d8 + urb MsgDesc: 29 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g56<1>UD g2<8,8,1>UD 0x024801e8 + urb MsgDesc: 30 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g57<1>UD g2<8,8,1>UD 0x024801f8 + urb MsgDesc: 31 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x080a8027 + urb MsgDesc: 2 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g8<8,8,1>UD 0x0a0a8027 + urb MsgDesc: 2 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) g6<1>UW g11<8,8,1>UD 0x0e424001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g124<1>UW g7<8,8,1>UD 0x0212a000 + sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; +send(8) g8<1>UD g14<8,8,1>UD 0x044a0128 + urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g22<1>UD g16<8,8,1>UD 0x044a0028 + urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x0a080017 + urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g7<8,8,1>F 0x0a080057 + urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) g4<1>UW g2<8,8,1>UD 0x02406001 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; +send(16) g5<1>UW g2<8,8,1>UD 0x04805001 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H }; +send(8) g124<1>UW g13<8,8,1>UD 0x084b0001 + sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g120<1>UW g7<8,8,1>UD 0x0e8d0001 + sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; +send(8) g10<1>UW g10<8,8,1>UD 0x0e134001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 1 { align1 1Q }; +send(8) g11<1>UW g17<8,8,1>UD 0x0e134102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 1 { align1 1Q }; +send(8) g14<1>UW g10<8,8,1>UD 0x064a8202 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x084a8101 + sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(8) g5<1>UW g6<8,8,1>UD 0x021ab001 + sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; +send(16) g6<1>UW g3<8,8,1>UD 0x022cb001 + sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1H }; +send(8) null<1>F g122<8,8,1>F 0x8c0a0037 + urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g10<8,8,1>F 0x12080027 + urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080047 + urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g14<1>UW g2<8,8,1>UD 0x04438000 + sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g61<1>UD g107<8,8,1>UD 0x02380048 + urb MsgDesc: 4 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g64<1>UD g113<8,8,1>UD 0x02380058 + urb MsgDesc: 5 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080047 + urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g5<1>UW g4<8,8,1>UD 0x06415001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x06416001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q }; +send(8) null<1>F g119<8,8,1>F 0x92080077 + urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g12<1>UD g8<4,4,1>UD 0x044a0038 + urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g21<1>UD g8<4,4,1>UD 0x044a0048 + urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0c0a00a7 + urb MsgDesc: 10 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(16) g1<1>UW g9<8,8,1>UD 0x08858001 + sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) null<1>F g56<8,8,1>F 0x140a0097 + urb MsgDesc: 9 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g76<8,8,1>F 0x0c0a00b7 + urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g122<8,8,1>F 0x8c0a00b7 + urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g4<1>UW g3<8,8,1>UD 0x0232a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; +send(16) g8<1>UW g3<8,8,1>UD 0x0464a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H }; +send(8) null<1>F g6<8,8,1>UD 0x0a080007 + urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) g126<1>UW g10<8,8,1>UD 0x08123001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(16) g124<1>UW g8<8,8,1>UD 0x10243001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; +send(8) g12<1>UW g12<8,8,1>UD 0x06126001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(8) g13<1>UW g15<8,8,1>UD 0x06126102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; +send(16) g20<1>UW g22<8,8,1>UD 0x0c246001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; +send(16) g22<1>UW g28<8,8,1>UD 0x0c246102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; +send(8) g4<1>UW g0<8,8,1>UD 0x02201000 + pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 2 { align1 1Q }; +send(16) g6<1>UW g0<8,8,1>UD 0x02411000 + pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 4 { align1 1H }; +send(8) g124<1>UW g19<8,8,1>UD 0x0a4b0001 + sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g120<1>UW g7<8,8,1>UD 0x128d0001 + sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; +send(8) g2<1>UW g15<8,8,1>UD 0x06422001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g14<1>UW g8<8,8,1>UD 0x0c842001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) null<1>F g118<8,8,1>F 0x940a0037 + urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) g4<1>UW g5<8,8,1>UD 0x0212a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; +send(16) g4<1>UW g6<8,8,1>UD 0x0424a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1H }; +send(8) g8<1>UD g15<8,8,1>UD 0x042a0138 + urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g10<1>UD g15<8,8,1>UD 0x042a0338 + urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g12<1>UD g15<8,8,1>UD 0x042a0538 + urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g14<1>UD g15<8,8,1>UD 0x042a0738 + urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g8<1>UD g15<8,8,1>UD 0x042a0038 + urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g10<1>UD g15<8,8,1>UD 0x042a0238 + urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g12<1>UD g15<8,8,1>UD 0x042a0438 + urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g14<1>UD g15<8,8,1>UD 0x042a0638 + urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g35<8,8,1>UD 0x02480228 + urb MsgDesc: 34 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g35<8,8,1>UD 0x02480428 + urb MsgDesc: 66 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g35<8,8,1>UD 0x02480628 + urb MsgDesc: 98 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0a0a8037 + urb MsgDesc: 3 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x0a0a8047 + urb MsgDesc: 4 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0a0a8057 + urb MsgDesc: 5 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x0a0a8067 + urb MsgDesc: 6 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x0a0a8077 + urb MsgDesc: 7 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0a0a8087 + urb MsgDesc: 8 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0a0a8097 + urb MsgDesc: 9 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0a0a80a7 + urb MsgDesc: 10 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0a0a80b7 + urb MsgDesc: 11 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0a0a80c7 + urb MsgDesc: 12 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0a0a80d7 + urb MsgDesc: 13 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0a0a80e7 + urb MsgDesc: 14 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0a0a80f7 + urb MsgDesc: 15 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0a0a8107 + urb MsgDesc: 16 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0a0a8117 + urb MsgDesc: 17 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0a0a8127 + urb MsgDesc: 18 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0a0a8137 + urb MsgDesc: 19 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0a0a8147 + urb MsgDesc: 20 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0a0a8157 + urb MsgDesc: 21 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0a0a8167 + urb MsgDesc: 22 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0a0a8177 + urb MsgDesc: 23 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0a0a8187 + urb MsgDesc: 24 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0a0a8197 + urb MsgDesc: 25 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0a0a81a7 + urb MsgDesc: 26 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0a0a81b7 + urb MsgDesc: 27 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0a0a81c7 + urb MsgDesc: 28 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0a0a81d7 + urb MsgDesc: 29 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0a0a81e7 + urb MsgDesc: 30 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0a0a81f7 + urb MsgDesc: 31 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0a0a8207 + urb MsgDesc: 32 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g122<8,8,1>F 0x8c0a0027 + urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g2<8,8,1>UD 0x06424001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g124<1>UW g2<8,8,1>UD 0x06229001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; +send(16) g120<1>UW g12<8,8,1>UD 0x0c449001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; +send(8) g5<1>UW g19<8,8,1>UD 0x0443a102 + sampler MsgDesc: ld_lz SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(16) g15<1>UW g11<8,8,1>UD 0x0885a102 + sampler MsgDesc: ld_lz SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(8) g124<1>UW g12<8,8,1>UD 0x0a43c000 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) g4<1>UW g5<8,8,1>UD 0x04120001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(16) g4<1>UW g7<8,8,1>UD 0x08240001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(8) null<1>F g118<8,8,1>F 0x940a0027 + urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g2<8,8,1>F 0x12080067 + urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080087 + urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g21<1>UD g2<8,8,1>UD 0x02380068 + urb MsgDesc: 6 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g35<1>UD g2<8,8,1>UD 0x02380088 + urb MsgDesc: 8 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) null<1>F g5<8,8,1>F 0x140a0067 + urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g118<8,8,1>F 0x940a0067 + urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) g2<1>UW g8<8,8,1>UD 0x04220001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; +send(16) g2<1>UW g14<8,8,1>UD 0x08440001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; +send(8) null<1>F g123<8,8,1>F 0x8a0800d7 + urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g22<1>UW g14<8,8,1>UD 0x064a8405 + sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x084a8102 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(8) g14<1>UW g10<8,8,1>UD 0x084a8203 + sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; +send(8) g18<1>UW g26<8,8,1>UD 0x0a4a8304 + sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 5 rlen 4 { align1 1Q }; +send(16) g18<1>UW g43<8,8,1>UD 0x0a8c8405 + sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 5 rlen 8 { align1 1H }; +send(16) g43<1>UW g7<8,8,1>UD 0x0e8c8102 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H }; +send(16) g2<1>UW g51<8,8,1>UD 0x0e8c8203 + sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H }; +send(16) g10<1>UW g26<8,8,1>UD 0x128c8304 + sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 9 rlen 8 { align1 1H }; +send(8) g6<1>UW g15<8,8,1>UD 0x0e4a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(16) null<1>UW g2<8,8,1>UD 0x04008601 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x08422001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x10842001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x08126001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g7<1>UW g11<8,8,1>UD 0x08126102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g10<1>UW g12<8,8,1>UD 0x10246001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; +send(16) g12<1>UW g20<8,8,1>UD 0x10246102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; +send(8) null<1>F g18<8,8,1>UD 0x0e0a8047 + urb MsgDesc: 4 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(8) g9<1>UD g34<8,8,1>UD 0x02480218 + urb MsgDesc: 33 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g17<1>UD g34<8,8,1>UD 0x02480238 + urb MsgDesc: 35 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g2<1>UD g6<8,8,1>UD 0x041a0128 + urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g22<1>UD g8<8,8,1>UD 0x041a0028 + urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) null<1>F g2<8,8,1>UD 0x06088027 + urb MsgDesc: 2 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x06088037 + urb MsgDesc: 3 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x06088047 + urb MsgDesc: 4 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x06088057 + urb MsgDesc: 5 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x06088067 + urb MsgDesc: 6 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x06088077 + urb MsgDesc: 7 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x06088087 + urb MsgDesc: 8 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x06088097 + urb MsgDesc: 9 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x060880a7 + urb MsgDesc: 10 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x060880b7 + urb MsgDesc: 11 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x060880c7 + urb MsgDesc: 12 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x060880d7 + urb MsgDesc: 13 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x060880e7 + urb MsgDesc: 14 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x060880f7 + urb MsgDesc: 15 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x06088107 + urb MsgDesc: 16 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x06088117 + urb MsgDesc: 17 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x06088127 + urb MsgDesc: 18 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x06088137 + urb MsgDesc: 19 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x06088147 + urb MsgDesc: 20 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x06088157 + urb MsgDesc: 21 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x06088167 + urb MsgDesc: 22 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x06088177 + urb MsgDesc: 23 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x06088187 + urb MsgDesc: 24 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x06088197 + urb MsgDesc: 25 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x060881a7 + urb MsgDesc: 26 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x060881b7 + urb MsgDesc: 27 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x060881c7 + urb MsgDesc: 28 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x060881d7 + urb MsgDesc: 29 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x060881e7 + urb MsgDesc: 30 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x060881f7 + urb MsgDesc: 31 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; +send(8) g3<1>UW g10<8,8,1>UD 0x0242a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(16) g3<1>UW g11<8,8,1>UD 0x0484a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(8) g124<1>UW g6<8,8,1>UD 0x06320001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; +send(16) g120<1>UW g8<8,8,1>UD 0x0c640001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x02406000 + dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; +send(8) g127<1>UW g6<8,8,1>UD 0x06120001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(16) g126<1>UW g8<8,8,1>UD 0x0c240001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; +send(8) g23<1>UW g2<8,8,1>UD 0x04115e01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; +send(8) g39<1>UW g45<8,8,1>UD 0x04116e01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q }; +(+f1.0) send(8) null<1>UW g2<8,8,1>UD 0x04018501 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1Q }; +(+f1.0) send(8) null<1>UW g42<8,8,1>UD 0x04019501 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 0 { align1 2Q }; +send(8) g2<1>UW g6<8,8,1>UD 0x04423001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g6<1>UW g8<8,8,1>UD 0x04423102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW g10<8,8,1>UD 0x08843001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g10<1>UW g18<8,8,1>UD 0x08843102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(8) g6<1>UD g22<8,8,1>UD 0x044a0318 + urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g10<1>UD g22<8,8,1>UD 0x044a0518 + urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g14<1>UD g22<8,8,1>UD 0x044a0718 + urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g18<1>UD g22<8,8,1>UD 0x044a0918 + urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g13<1>UD g29<8,8,1>UD 0x044a0218 + urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g17<1>UD g29<8,8,1>UD 0x044a0418 + urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g21<1>UD g29<8,8,1>UD 0x044a0618 + urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g25<1>UD g29<8,8,1>UD 0x044a0818 + urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0c0a0217 + urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0c0a0227 + urb MsgDesc: 34 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x0c0a0237 + urb MsgDesc: 35 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x0c0a0247 + urb MsgDesc: 36 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0c0a0257 + urb MsgDesc: 37 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0c0a0267 + urb MsgDesc: 38 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0c0a0277 + urb MsgDesc: 39 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0c0a0287 + urb MsgDesc: 40 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0c0a0297 + urb MsgDesc: 41 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0c0a02a7 + urb MsgDesc: 42 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0c0a02b7 + urb MsgDesc: 43 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0c0a02c7 + urb MsgDesc: 44 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0c0a02d7 + urb MsgDesc: 45 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0c0a02e7 + urb MsgDesc: 46 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0c0a02f7 + urb MsgDesc: 47 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0c0a0307 + urb MsgDesc: 48 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0c0a0317 + urb MsgDesc: 49 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0c0a0327 + urb MsgDesc: 50 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0c0a0337 + urb MsgDesc: 51 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0c0a0347 + urb MsgDesc: 52 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0c0a0357 + urb MsgDesc: 53 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0c0a0367 + urb MsgDesc: 54 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0c0a0377 + urb MsgDesc: 55 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0c0a0387 + urb MsgDesc: 56 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0c0a0397 + urb MsgDesc: 57 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0c0a03a7 + urb MsgDesc: 58 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0c0a03b7 + urb MsgDesc: 59 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0c0a03c7 + urb MsgDesc: 60 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0c0a03d7 + urb MsgDesc: 61 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0c0a03e7 + urb MsgDesc: 62 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g41<8,8,1>UD 0x0c0a03f7 + urb MsgDesc: 63 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0a080067 + urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0a080077 + urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0a080087 + urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0a080097 + urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0a0800a7 + urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0a0800b7 + urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0a0800c7 + urb MsgDesc: 12 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0a0800d7 + urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0a0800e7 + urb MsgDesc: 14 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0a0800f7 + urb MsgDesc: 15 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0a080107 + urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0a080117 + urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0a080127 + urb MsgDesc: 18 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0a080137 + urb MsgDesc: 19 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0a080147 + urb MsgDesc: 20 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0a080157 + urb MsgDesc: 21 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0a080167 + urb MsgDesc: 22 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0a080177 + urb MsgDesc: 23 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0a080187 + urb MsgDesc: 24 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0a080197 + urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0a0801a7 + urb MsgDesc: 26 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0a0801b7 + urb MsgDesc: 27 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0a0801c7 + urb MsgDesc: 28 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0a0801d7 + urb MsgDesc: 29 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0a0801e7 + urb MsgDesc: 30 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g41<8,8,1>UD 0x0a0801f7 + urb MsgDesc: 31 SIMD8 write mlen 5 rlen 0 { align1 1Q }; +send(8) g13<1>UW g2<8,8,1>UD 0x06123001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; +send(8) g14<1>UW g5<8,8,1>UD 0x06123102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; +send(16) g22<1>UW g2<8,8,1>UD 0x0c243001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; +send(16) g24<1>UW g16<8,8,1>UD 0x0c243102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; +send(8) g5<1>UW g15<8,8,1>UD 0x04420203 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(16) g7<1>UW g27<8,8,1>UD 0x08840203 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H }; +send(16) g4<1>UW g17<8,8,1>UD 0x0420a503 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; +send(16) null<1>UW g18<8,8,1>UD 0x04008504 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 4, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(16) g11<1>UW g19<8,8,1>UD 0x0420a602 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; +send(16) null<1>UW g20<8,8,1>UD 0x04008505 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 5, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(16) g16<1>UW g21<8,8,1>UD 0x04205e01 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(16) null<1>UW g22<8,8,1>UD 0x04008506 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 6, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(8) g26<1>UW g26<8,8,1>UD 0x0242a203 + sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UW g30<8,8,1>UD 0x0242a304 + sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q }; +send(8) g34<1>UW g34<8,8,1>UD 0x0242a405 + sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q }; +send(8) g38<1>UW g38<8,8,1>UD 0x0242a506 + sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UW g25<8,8,1>UD 0x0242a102 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; +send(8) g42<1>UW g42<8,8,1>UD 0x0242a607 + sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q }; +send(8) g46<1>UW g46<8,8,1>UD 0x0242a708 + sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q }; +send(8) g50<1>UW g50<8,8,1>UD 0x0242a809 + sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q }; +send(8) g2<1>UW g54<8,8,1>UD 0x0242a90a + sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UW g55<8,8,1>UD 0x0242aa0b + sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q }; +send(8) g10<1>UW g56<8,8,1>UD 0x0242ab0c + sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UW g57<8,8,1>UD 0x0242ac0d + sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; +send(16) g10<1>UW g18<8,8,1>UD 0x0484a102 + sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H }; +send(16) g82<1>UW g110<8,8,1>UD 0x0484aa0b + sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H }; +send(16) g18<1>UW g26<8,8,1>UD 0x0484a203 + sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H }; +send(16) g90<1>UW g112<8,8,1>UD 0x0484ab0c + sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H }; +send(16) g98<1>UW g106<8,8,1>UD 0x0484ac0d + sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H }; +send(16) g26<1>UW g34<8,8,1>UD 0x0484a304 + sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H }; +send(16) g34<1>UW g42<8,8,1>UD 0x0484a405 + sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H }; +send(16) g42<1>UW g50<8,8,1>UD 0x0484a506 + sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H }; +send(16) g50<1>UW g58<8,8,1>UD 0x0484a607 + sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H }; +send(16) g58<1>UW g66<8,8,1>UD 0x0484a708 + sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H }; +send(16) g66<1>UW g74<8,8,1>UD 0x0484a809 + sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H }; +send(16) g74<1>UW g108<8,8,1>UD 0x0484a90a + sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H }; +send(16) null<1>UW g3<8,8,1>UD 0x040085fe + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(8) null<1>F g119<8,8,1>F 0x92080067 + urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g6<1>UW g20<8,8,1>UD 0x12424001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q }; +send(8) g17<1>UW g2<8,8,1>UD 0x0413a001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(16) g2<1>UW g7<8,8,1>UD 0x0825a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(8) g9<1>UW g17<8,8,1>UD 0x06422000 + sampler MsgDesc: sample_l SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) null<1>UW g123<0,1,0>UD 0x060a03fd + data MsgDesc: ( DC OWORD block write, 253, 3) mlen 3 rlen 0 { align1 1H }; +send(16) g114<1>UW g114<0,1,0>UD 0x022803fd + data MsgDesc: ( DC OWORD block read, 253, 3) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) null<1>F g12<8,8,1>UD 0x0c0a0127 + urb MsgDesc: 18 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) g2<1>UW g11<8,8,1>UD 0x04420405 + sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g12<8,8,1>UD 0x04420506 + sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x04420607 + sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g14<8,8,1>UD 0x04420708 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g15<8,8,1>UD 0x04420809 + sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g16<8,8,1>UD 0x0442090a + sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g17<8,8,1>UD 0x04420a0b + sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g18<8,8,1>UD 0x04420b0c + sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g19<8,8,1>UD 0x04420c0d + sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g20<8,8,1>UD 0x04420d0e + sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g21<8,8,1>UD 0x04420e0f + sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g22<8,8,1>UD 0x04420f10 + sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0011 + sampler MsgDesc: sample SIMD8 Surface = 17 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0112 + sampler MsgDesc: sample SIMD8 Surface = 18 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0213 + sampler MsgDesc: sample SIMD8 Surface = 19 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0314 + sampler MsgDesc: sample SIMD8 Surface = 20 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0415 + sampler MsgDesc: sample SIMD8 Surface = 21 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0516 + sampler MsgDesc: sample SIMD8 Surface = 22 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0617 + sampler MsgDesc: sample SIMD8 Surface = 23 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0718 + sampler MsgDesc: sample SIMD8 Surface = 24 Sampler = 7 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0819 + sampler MsgDesc: sample SIMD8 Surface = 25 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a091a + sampler MsgDesc: sample SIMD8 Surface = 26 Sampler = 9 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0a1b + sampler MsgDesc: sample SIMD8 Surface = 27 Sampler = 10 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0b1c + sampler MsgDesc: sample SIMD8 Surface = 28 Sampler = 11 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0c1d + sampler MsgDesc: sample SIMD8 Surface = 29 Sampler = 12 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0d1e + sampler MsgDesc: sample SIMD8 Surface = 30 Sampler = 13 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g10<8,8,1>UD 0x064a0e1f + sampler MsgDesc: sample SIMD8 Surface = 31 Sampler = 14 mlen 3 rlen 4 { align1 1Q }; +send(8) g2<1>UW g13<8,8,1>UD 0x064a0f20 + sampler MsgDesc: sample SIMD8 Surface = 32 Sampler = 15 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g28<8,8,1>UD 0x08840405 + sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g29<8,8,1>UD 0x08840506 + sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g30<8,8,1>UD 0x08840607 + sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g31<8,8,1>UD 0x08840708 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g32<8,8,1>UD 0x08840809 + sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g33<8,8,1>UD 0x0884090a + sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g34<8,8,1>UD 0x08840a0b + sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g35<8,8,1>UD 0x08840b0c + sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g36<8,8,1>UD 0x08840c0d + sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW g37<8,8,1>UD 0x08840d0e + sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H }; +send(16) g7<1>UW g38<8,8,1>UD 0x08840e0f + sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H }; +send(16) g23<1>UW g39<8,8,1>UD 0x08840f10 + sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H }; +send(16) g17<1>UW g2<8,8,1>UD 0x0a8c0011 + sampler MsgDesc: sample SIMD16 Surface = 17 Sampler = 0 mlen 5 rlen 8 { align1 1H }; +send(16) g29<1>UW g7<8,8,1>UD 0x0a8c0112 + sampler MsgDesc: sample SIMD16 Surface = 18 Sampler = 1 mlen 5 rlen 8 { align1 1H }; +send(16) g27<1>UW g12<8,8,1>UD 0x0a8c0213 + sampler MsgDesc: sample SIMD16 Surface = 19 Sampler = 2 mlen 5 rlen 8 { align1 1H }; +send(16) g32<1>UW g17<8,8,1>UD 0x0a8c0314 + sampler MsgDesc: sample SIMD16 Surface = 20 Sampler = 3 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g22<8,8,1>UD 0x0a8c0415 + sampler MsgDesc: sample SIMD16 Surface = 21 Sampler = 4 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g27<8,8,1>UD 0x0a8c0516 + sampler MsgDesc: sample SIMD16 Surface = 22 Sampler = 5 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g32<8,8,1>UD 0x0a8c0617 + sampler MsgDesc: sample SIMD16 Surface = 23 Sampler = 6 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g37<8,8,1>UD 0x0a8c0718 + sampler MsgDesc: sample SIMD16 Surface = 24 Sampler = 7 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g42<8,8,1>UD 0x0a8c0819 + sampler MsgDesc: sample SIMD16 Surface = 25 Sampler = 8 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g47<8,8,1>UD 0x0a8c091a + sampler MsgDesc: sample SIMD16 Surface = 26 Sampler = 9 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g52<8,8,1>UD 0x0a8c0a1b + sampler MsgDesc: sample SIMD16 Surface = 27 Sampler = 10 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g57<8,8,1>UD 0x0a8c0b1c + sampler MsgDesc: sample SIMD16 Surface = 28 Sampler = 11 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g62<8,8,1>UD 0x0a8c0c1d + sampler MsgDesc: sample SIMD16 Surface = 29 Sampler = 12 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g67<8,8,1>UD 0x0a8c0d1e + sampler MsgDesc: sample SIMD16 Surface = 30 Sampler = 13 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g72<8,8,1>UD 0x0a8c0e1f + sampler MsgDesc: sample SIMD16 Surface = 31 Sampler = 14 mlen 5 rlen 8 { align1 1H }; +send(16) g2<1>UW g77<8,8,1>UD 0x0a8c0f20 + sampler MsgDesc: sample SIMD16 Surface = 32 Sampler = 15 mlen 5 rlen 8 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x02120102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; +send(8) g6<1>UW g3<8,8,1>UD 0x02220102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UW g4<8,8,1>UD 0x02320102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 3 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x04240102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H }; +send(16) g10<1>UW g4<8,8,1>UD 0x04440102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1H }; +send(16) g14<1>UW g6<8,8,1>UD 0x04640102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 6 { align1 1H }; +send(8) null<1>F g8<8,8,1>UD 0x0c0a8027 + urb MsgDesc: 2 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>F 0x12080047 + urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080087 + urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g5<1>UW g10<8,8,1>UD 0x06420001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g7<1>UW g19<8,8,1>UD 0x0c840001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) g1<1>UW g125<8,8,1>UD 0x02106e02 + dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) g8<1>UW g22<8,8,1>UD 0x02106efe + dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080097 + urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g29<1>UW g5<8,8,1>UD 0x0e4b2001 + sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g68<1>UW g72<8,8,1>UD 0x0212a102 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; +send(8) g67<1>UW g5<8,8,1>UD 0x0a126001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g69<1>UW g10<8,8,1>UD 0x0a126102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(16) g36<1>UW g40<8,8,1>UD 0x0424a102 + sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H }; +send(16) g2<1>UW g7<8,8,1>UD 0x14246001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; +send(16) g37<1>UW g17<8,8,1>UD 0x14246102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; +send(8) g125<1>UW g5<8,8,1>UD 0x04220102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1Q }; +send(16) g122<1>UW g7<8,8,1>UD 0x08440102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1H }; +send(8) null<1>F g14<8,8,1>UD 0x0c0a8037 + urb MsgDesc: 3 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0c0a8047 + urb MsgDesc: 4 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0c0a8057 + urb MsgDesc: 5 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) g6<1>UW g7<8,8,1>UD 0x081a5001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g7<1>UW g11<8,8,1>UD 0x081a5102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g10<1>UW g12<8,8,1>UD 0x0e2c5001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; +send(16) g12<1>UW g19<8,8,1>UD 0x0e2c5102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; +send(8) g5<1>UW g6<8,8,1>UD 0x081a3001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g6<1>UW g10<8,8,1>UD 0x081a3102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g9<1>UW g11<8,8,1>UD 0x0e2c3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; +send(16) g11<1>UW g18<8,8,1>UD 0x0e2c3102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; +send(8) g5<1>UW g7<8,8,1>UD 0x04320102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 3 { align1 1Q }; +send(16) g8<1>UW g14<8,8,1>UD 0x08640102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 6 { align1 1H }; +send(8) g19<1>UW g12<8,8,1>UD 0x04320003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; +send(16) g34<1>UW g41<8,8,1>UD 0x08640003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 6 { align1 1H }; +send(8) g11<1>UW g2<8,8,1>UD 0x0443a008 + sampler MsgDesc: ld_lz SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g15<1>UW g2<8,8,1>UD 0x0443a109 + sampler MsgDesc: ld_lz SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(8) g19<1>UW g2<8,8,1>UD 0x0443a20a + sampler MsgDesc: ld_lz SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(8) g23<1>UW g2<8,8,1>UD 0x0443a30b + sampler MsgDesc: ld_lz SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(8) g27<1>UW g2<8,8,1>UD 0x0443a40c + sampler MsgDesc: ld_lz SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g31<1>UW g2<8,8,1>UD 0x0443a50d + sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) g35<1>UW g2<8,8,1>UD 0x0443a60e + sampler MsgDesc: ld_lz SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g39<1>UW g2<8,8,1>UD 0x0443a70f + sampler MsgDesc: ld_lz SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(16) g93<1>UW g2<8,8,1>UD 0x0885a008 + sampler MsgDesc: ld_lz SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g27<1>UW g2<8,8,1>UD 0x0885a109 + sampler MsgDesc: ld_lz SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(16) g37<1>UW g2<8,8,1>UD 0x0885a20a + sampler MsgDesc: ld_lz SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H }; +send(16) g47<1>UW g2<8,8,1>UD 0x0885a30b + sampler MsgDesc: ld_lz SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H }; +send(16) g57<1>UW g2<8,8,1>UD 0x0885a40c + sampler MsgDesc: ld_lz SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H }; +send(16) g67<1>UW g2<8,8,1>UD 0x0885a50d + sampler MsgDesc: ld_lz SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H }; +send(16) g85<1>UW g2<8,8,1>UD 0x0885a60e + sampler MsgDesc: ld_lz SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H }; +send(16) g77<1>UW g2<8,8,1>UD 0x0885a70f + sampler MsgDesc: ld_lz SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; +send(16) g83<1>UW g86<8,8,1>UD 0x04205e00 + dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(8) null<1>F g122<8,8,1>F 0x8c0a0047 + urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g14<1>UW g11<8,8,1>UD 0x084b0202 + sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x0a4b0101 + sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; +send(8) null<1>F g3<8,8,1>F 0x12080087 + urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a0800a7 + urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g6<1>UW g7<8,8,1>UD 0x081a6001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g7<1>UW g11<8,8,1>UD 0x081a6102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g10<1>UW g12<8,8,1>UD 0x0e2c6001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; +send(16) g12<1>UW g19<8,8,1>UD 0x0e2c6102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; +send(8) g31<1>UD g28<8,8,1>UD 0x02380238 + urb MsgDesc: 35 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g34<1>UD g28<8,8,1>UD 0x02380438 + urb MsgDesc: 67 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g37<1>UD g28<8,8,1>UD 0x02380638 + urb MsgDesc: 99 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g28<8,8,1>UD 0x02380248 + urb MsgDesc: 36 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g28<8,8,1>UD 0x02380448 + urb MsgDesc: 68 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g28<8,8,1>UD 0x02380648 + urb MsgDesc: 100 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g29<8,8,1>UD 0x02380258 + urb MsgDesc: 37 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g29<8,8,1>UD 0x02380458 + urb MsgDesc: 69 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g29<8,8,1>UD 0x02380658 + urb MsgDesc: 101 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g30<8,8,1>UD 0x02380268 + urb MsgDesc: 38 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g30<8,8,1>UD 0x02380468 + urb MsgDesc: 70 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g30<8,8,1>UD 0x02380668 + urb MsgDesc: 102 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g31<8,8,1>UD 0x02380278 + urb MsgDesc: 39 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g31<8,8,1>UD 0x02380478 + urb MsgDesc: 71 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g31<8,8,1>UD 0x02380678 + urb MsgDesc: 103 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g32<8,8,1>UD 0x02380488 + urb MsgDesc: 72 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g32<8,8,1>UD 0x02380288 + urb MsgDesc: 40 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g32<8,8,1>UD 0x02380688 + urb MsgDesc: 104 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g33<8,8,1>UD 0x02380498 + urb MsgDesc: 73 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g33<8,8,1>UD 0x02380298 + urb MsgDesc: 41 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g28<1>UD g33<8,8,1>UD 0x02380698 + urb MsgDesc: 105 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g34<8,8,1>UD 0x023806a8 + urb MsgDesc: 106 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g34<8,8,1>UD 0x023802a8 + urb MsgDesc: 42 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g34<8,8,1>UD 0x023804a8 + urb MsgDesc: 74 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g35<8,8,1>UD 0x023802b8 + urb MsgDesc: 43 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g35<8,8,1>UD 0x023804b8 + urb MsgDesc: 75 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g35<8,8,1>UD 0x023806b8 + urb MsgDesc: 107 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g36<8,8,1>UD 0x023802c8 + urb MsgDesc: 44 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g36<8,8,1>UD 0x023804c8 + urb MsgDesc: 76 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g36<8,8,1>UD 0x023806c8 + urb MsgDesc: 108 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g37<8,8,1>UD 0x023802d8 + urb MsgDesc: 45 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g37<8,8,1>UD 0x023804d8 + urb MsgDesc: 77 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g37<8,8,1>UD 0x023806d8 + urb MsgDesc: 109 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g38<8,8,1>UD 0x023802e8 + urb MsgDesc: 46 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g38<8,8,1>UD 0x023804e8 + urb MsgDesc: 78 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g38<8,8,1>UD 0x023806e8 + urb MsgDesc: 110 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g39<8,8,1>UD 0x023802f8 + urb MsgDesc: 47 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g39<8,8,1>UD 0x023804f8 + urb MsgDesc: 79 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g25<1>UD g39<8,8,1>UD 0x023806f8 + urb MsgDesc: 111 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g40<8,8,1>UD 0x02380308 + urb MsgDesc: 48 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g40<8,8,1>UD 0x02380508 + urb MsgDesc: 80 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g40<8,8,1>UD 0x02380708 + urb MsgDesc: 112 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g41<8,8,1>UD 0x02380318 + urb MsgDesc: 49 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g41<8,8,1>UD 0x02380518 + urb MsgDesc: 81 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g41<8,8,1>UD 0x02380718 + urb MsgDesc: 113 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g3<8,8,1>UD 0x02380328 + urb MsgDesc: 50 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g3<8,8,1>UD 0x02380528 + urb MsgDesc: 82 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g3<8,8,1>UD 0x02380728 + urb MsgDesc: 114 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g43<8,8,1>UD 0x02380338 + urb MsgDesc: 51 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g43<8,8,1>UD 0x02380538 + urb MsgDesc: 83 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g43<8,8,1>UD 0x02380738 + urb MsgDesc: 115 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g44<8,8,1>UD 0x02380348 + urb MsgDesc: 52 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g44<8,8,1>UD 0x02380548 + urb MsgDesc: 84 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g44<8,8,1>UD 0x02380748 + urb MsgDesc: 116 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g45<8,8,1>UD 0x02380358 + urb MsgDesc: 53 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g45<8,8,1>UD 0x02380558 + urb MsgDesc: 85 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g22<1>UD g45<8,8,1>UD 0x02380758 + urb MsgDesc: 117 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g46<8,8,1>UD 0x02380368 + urb MsgDesc: 54 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g46<8,8,1>UD 0x02380568 + urb MsgDesc: 86 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g46<8,8,1>UD 0x02380768 + urb MsgDesc: 118 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g47<8,8,1>UD 0x02380378 + urb MsgDesc: 55 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g47<8,8,1>UD 0x02380578 + urb MsgDesc: 87 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g47<8,8,1>UD 0x02380778 + urb MsgDesc: 119 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g48<8,8,1>UD 0x02380388 + urb MsgDesc: 56 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g48<8,8,1>UD 0x02380588 + urb MsgDesc: 88 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g48<8,8,1>UD 0x02380788 + urb MsgDesc: 120 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g49<8,8,1>UD 0x02380398 + urb MsgDesc: 57 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g49<8,8,1>UD 0x02380598 + urb MsgDesc: 89 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g49<8,8,1>UD 0x02380798 + urb MsgDesc: 121 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g50<8,8,1>UD 0x023803a8 + urb MsgDesc: 58 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g50<8,8,1>UD 0x023805a8 + urb MsgDesc: 90 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g50<8,8,1>UD 0x023807a8 + urb MsgDesc: 122 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g54<8,8,1>UD 0x023803b8 + urb MsgDesc: 59 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g54<8,8,1>UD 0x023805b8 + urb MsgDesc: 91 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g54<8,8,1>UD 0x023807b8 + urb MsgDesc: 123 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g55<8,8,1>UD 0x023803c8 + urb MsgDesc: 60 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g55<8,8,1>UD 0x023805c8 + urb MsgDesc: 92 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g55<8,8,1>UD 0x023807c8 + urb MsgDesc: 124 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g56<8,8,1>UD 0x023803d8 + urb MsgDesc: 61 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g56<8,8,1>UD 0x023805d8 + urb MsgDesc: 93 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g56<8,8,1>UD 0x023807d8 + urb MsgDesc: 125 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g57<8,8,1>UD 0x023803e8 + urb MsgDesc: 62 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g57<8,8,1>UD 0x023805e8 + urb MsgDesc: 94 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g57<8,8,1>UD 0x023807e8 + urb MsgDesc: 126 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g58<8,8,1>UD 0x023803f8 + urb MsgDesc: 63 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g58<8,8,1>UD 0x023805f8 + urb MsgDesc: 95 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g58<8,8,1>UD 0x023807f8 + urb MsgDesc: 127 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g59<8,8,1>UD 0x02380208 + urb MsgDesc: 32 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g59<8,8,1>UD 0x02380408 + urb MsgDesc: 64 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g59<8,8,1>UD 0x02380608 + urb MsgDesc: 96 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g17<1>UD g59<8,8,1>UD 0x02380808 + urb MsgDesc: 128 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g8<1>UD g60<8,8,1>UD 0x02380218 + urb MsgDesc: 33 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g60<8,8,1>UD 0x02380418 + urb MsgDesc: 65 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UD g60<8,8,1>UD 0x02380618 + urb MsgDesc: 97 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g17<1>UD g60<8,8,1>UD 0x02380818 + urb MsgDesc: 129 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x0c0a8067 + urb MsgDesc: 6 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0c0a8077 + urb MsgDesc: 7 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0c0a8087 + urb MsgDesc: 8 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0c0a8097 + urb MsgDesc: 9 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0c0a80a7 + urb MsgDesc: 10 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0c0a80b7 + urb MsgDesc: 11 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0c0a80c7 + urb MsgDesc: 12 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0c0a80d7 + urb MsgDesc: 13 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0c0a80e7 + urb MsgDesc: 14 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0c0a80f7 + urb MsgDesc: 15 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0c0a8107 + urb MsgDesc: 16 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0c0a8117 + urb MsgDesc: 17 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0c0a8127 + urb MsgDesc: 18 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0c0a8137 + urb MsgDesc: 19 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0c0a8147 + urb MsgDesc: 20 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0c0a8157 + urb MsgDesc: 21 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0c0a8167 + urb MsgDesc: 22 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0c0a8177 + urb MsgDesc: 23 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0c0a8187 + urb MsgDesc: 24 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0c0a8197 + urb MsgDesc: 25 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0c0a81a7 + urb MsgDesc: 26 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0c0a81b7 + urb MsgDesc: 27 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0c0a81c7 + urb MsgDesc: 28 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0c0a81d7 + urb MsgDesc: 29 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0c0a81e7 + urb MsgDesc: 30 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0c0a81f7 + urb MsgDesc: 31 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0c0a8207 + urb MsgDesc: 32 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g41<8,8,1>UD 0x0c0a8217 + urb MsgDesc: 33 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) g124<1>UW g2<8,8,1>UD 0x02106e01 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(16) g11<1>UW g19<8,8,1>UD 0x0420a601 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; +send(16) null<1>UW g20<8,8,1>UD 0x04008503 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; +send(8) g17<1>UW g11<8,8,1>UD 0x0813e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(16) g22<1>UW g2<8,8,1>UD 0x1025e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; +send(8) null<1>F g122<8,8,1>UD 0x8c088007 + urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g2<1>UW g2<8,8,1>UD 0x06423001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x06423102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g20<8,8,1>UD 0x0c843001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(16) g10<1>UW g26<8,8,1>UD 0x0c843102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; +send(8) g14<1>UW g14<8,8,1>UD 0x0a1a5001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g15<1>UW g19<8,8,1>UD 0x0a1a5102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(16) g39<1>UW g7<8,8,1>UD 0x122c5001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H }; +send(16) g41<1>UW g16<8,8,1>UD 0x122c5102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H }; +send(8) g2<1>UW g13<8,8,1>UD 0x0c4b2001 + sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(16) g43<1>UW g7<8,8,1>UD 0x168d2001 + sampler MsgDesc: gather4_po_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(8) g54<1>UD g7<8,8,1>UD 0x02280048 + urb MsgDesc: 4 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g2<1>UW g8<8,8,1>UD 0x02420001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(16) g2<1>UW g15<8,8,1>UD 0x04840001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(8) g7<1>UW g44<8,8,1>UD 0x02106e00 + dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>UW g44<8,8,1>UD 0x02009500 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; +send(8) g7<1>UD g37<8,8,1>UD 0x02480438 + urb MsgDesc: 67 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g11<1>UD g37<8,8,1>UD 0x02480638 + urb MsgDesc: 99 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g13<1>UD g14<8,8,1>UD 0x042a0148 + urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g14<8,8,1>UD 0x042a0048 + urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g124<1>UW g13<8,8,1>UD 0x0c43c000 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g22<1>UW g14<8,8,1>UD 0x064a8404 + sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; +send(8) g14<1>UW g10<8,8,1>UD 0x084a8202 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; +send(8) g18<1>UW g26<8,8,1>UD 0x0a4a8303 + sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 5 rlen 4 { align1 1Q }; +send(8) g6<1>UW g14<8,8,1>UD 0x0e434102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q }; +send(8) g8<1>UW g7<8,8,1>UD 0x121b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 1 { align1 1Q }; +send(8) g9<1>UW g16<8,8,1>UD 0x121b4102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 9 rlen 1 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x02380078 + urb MsgDesc: 7 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g14<1>UW g10<8,8,1>UD 0x064a8203 + sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; +send(16) g26<1>UW g34<8,8,1>UD 0x0a8c8203 + sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 5 rlen 8 { align1 1H }; +send(8) g50<1>UD g51<8,8,1>UD 0x02180018 + urb MsgDesc: 1 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g59<1>UW g64<8,8,1>UD 0x02427002 + sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g2<1>UW g64<8,8,1>UD 0x02427003 + sampler MsgDesc: ld SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UW g64<8,8,1>UD 0x02427004 + sampler MsgDesc: ld SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g10<1>UW g64<8,8,1>UD 0x02427005 + sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UW g64<8,8,1>UD 0x02427006 + sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g18<1>UW g64<8,8,1>UD 0x02427007 + sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UW g64<8,8,1>UD 0x02427008 + sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UW g64<8,8,1>UD 0x02427009 + sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UW g64<8,8,1>UD 0x0242700a + sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g34<1>UW g64<8,8,1>UD 0x0242700b + sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g38<1>UW g64<8,8,1>UD 0x0242700c + sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g42<1>UW g64<8,8,1>UD 0x0242700d + sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g124<1>UW g6<8,8,1>UD 0x04438505 + sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0a088067 + urb MsgDesc: 6 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0a088077 + urb MsgDesc: 7 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0a088087 + urb MsgDesc: 8 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0a088097 + urb MsgDesc: 9 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0a0880a7 + urb MsgDesc: 10 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0a0880b7 + urb MsgDesc: 11 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0a0880c7 + urb MsgDesc: 12 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0a0880d7 + urb MsgDesc: 13 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0a0880e7 + urb MsgDesc: 14 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0a0880f7 + urb MsgDesc: 15 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0a088107 + urb MsgDesc: 16 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0a088117 + urb MsgDesc: 17 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0a088127 + urb MsgDesc: 18 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0a088137 + urb MsgDesc: 19 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0a088147 + urb MsgDesc: 20 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0a088157 + urb MsgDesc: 21 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0a088167 + urb MsgDesc: 22 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0a088177 + urb MsgDesc: 23 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0a088187 + urb MsgDesc: 24 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0a088197 + urb MsgDesc: 25 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0a0881a7 + urb MsgDesc: 26 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0a0881b7 + urb MsgDesc: 27 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0a0881c7 + urb MsgDesc: 28 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0a0881d7 + urb MsgDesc: 29 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0a0881e7 + urb MsgDesc: 30 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g41<8,8,1>UD 0x0a0881f7 + urb MsgDesc: 31 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; +send(8) null<1>F g4<8,8,1>UD 0x0e0a8027 + urb MsgDesc: 2 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(8) g5<1>UW g6<8,8,1>UD 0x04123001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(8) g6<1>UW g2<8,8,1>UD 0x04123102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q }; +send(16) g9<1>UW g11<8,8,1>UD 0x08243001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(16) g11<1>UW g2<8,8,1>UD 0x08243102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H }; +send(8) g2<1>UW g2<8,8,1>UD 0x0443d002 + sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g3<1>UW g14<8,8,1>UD 0x0a43c102 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; +send(16) g2<1>UW g10<8,8,1>UD 0x0885d002 + sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g3<1>UW g25<8,8,1>UD 0x1485c102 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H }; +send(8) g10<1>UW g11<8,8,1>UD 0x0a123001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g11<1>UW g16<8,8,1>UD 0x0a123102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(16) g34<1>UW g9<8,8,1>UD 0x14243001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; +send(16) g36<1>UW g19<8,8,1>UD 0x14243102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; +send(8) g2<1>UW g7<8,8,1>UD 0x08426001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g6<1>UW g11<8,8,1>UD 0x08426102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW g11<8,8,1>UD 0x10846001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(16) g10<1>UW g19<8,8,1>UD 0x10846102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; +(+f1.0) send(8) g4<1>UW g10<8,8,1>UD 0x0210b502 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; +(+f1.0) send(16) g5<1>UW g13<8,8,1>UD 0x0420a502 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; +send(8) g8<1>UW g9<8,8,1>UD 0x06321001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; +send(16) g2<1>UW g14<8,8,1>UD 0x0c641001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; +send(8) g124<1>UW g6<8,8,1>UD 0x04338000 + sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; +send(8) g12<1>UD g1<8,8,1>UD 0x02280058 + urb MsgDesc: 5 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0e0a8067 + urb MsgDesc: 6 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(8) g12<1>UD g1<8,8,1>UD 0x02280078 + urb MsgDesc: 7 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0e0a8087 + urb MsgDesc: 8 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(8) g12<1>UD g1<8,8,1>UD 0x02280098 + urb MsgDesc: 9 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0e0a80a7 + urb MsgDesc: 10 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(16) g9<1>UW g17<8,8,1>UD 0x04847002 + sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(16) g23<1>UW g32<8,8,1>UD 0x04205e02 + dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280068 + urb MsgDesc: 6 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280088 + urb MsgDesc: 8 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800a8 + urb MsgDesc: 10 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800b8 + urb MsgDesc: 11 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800c8 + urb MsgDesc: 12 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800d8 + urb MsgDesc: 13 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800e8 + urb MsgDesc: 14 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022800f8 + urb MsgDesc: 15 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280108 + urb MsgDesc: 16 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280118 + urb MsgDesc: 17 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280128 + urb MsgDesc: 18 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280138 + urb MsgDesc: 19 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280148 + urb MsgDesc: 20 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280158 + urb MsgDesc: 21 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280168 + urb MsgDesc: 22 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280178 + urb MsgDesc: 23 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280188 + urb MsgDesc: 24 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280198 + urb MsgDesc: 25 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801a8 + urb MsgDesc: 26 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801b8 + urb MsgDesc: 27 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801c8 + urb MsgDesc: 28 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801d8 + urb MsgDesc: 29 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801e8 + urb MsgDesc: 30 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x022801f8 + urb MsgDesc: 31 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g1<8,8,1>UD 0x02280208 + urb MsgDesc: 32 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g2<1>UW g3<8,8,1>UD 0x04203000 + pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 2 rlen 2 { align1 1Q }; +send(16) g2<1>UW g11<8,8,1>UD 0x08413000 + pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 4 rlen 4 { align1 1H }; +send(8) g2<1>UW g0<8,8,1>UD 0x02201010 + pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 2 { align1 1Q }; +send(16) g2<1>UW g0<8,8,1>UD 0x02411010 + pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 4 { align1 1H }; +send(8) g2<1>UW g0<8,8,1>UD 0x02201020 + pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 2 { align1 1Q }; +send(16) g2<1>UW g0<8,8,1>UD 0x02411020 + pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 4 { align1 1H }; +send(8) g2<1>UW g0<8,8,1>UD 0x02201030 + pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 2 { align1 1Q }; +send(16) g2<1>UW g0<8,8,1>UD 0x02411030 + pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 4 { align1 1H }; +send(8) g20<1>UW g15<8,8,1>UD 0x04320203 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 3 { align1 1Q }; +send(8) g11<1>UW g26<8,8,1>UD 0x04320405 + sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 3 { align1 1Q }; +send(8) g8<1>UW g24<8,8,1>UD 0x04320304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 3 { align1 1Q }; +send(16) g26<1>UW g21<8,8,1>UD 0x08640203 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 6 { align1 1H }; +send(16) g12<1>UW g48<8,8,1>UD 0x08640405 + sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 6 { align1 1H }; +send(16) g38<1>UW g44<8,8,1>UD 0x08640304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 6 { align1 1H }; +(+f1.0) send(8) null<1>UW g94<8,8,1>UD 0x02009601 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; +(+f1.0) send(8) g47<1>UW g94<8,8,1>UD 0x0210b601 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; +send(16) g4<1>UW g1<8,8,1>UD 0x04405c02 + dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xc) mlen 2 rlen 4 { align1 1H }; +send(8) null<1>UW g100<8,8,1>UD 0x02009600 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; +send(8) g51<1>UW g100<8,8,1>UD 0x0210b600 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; +send(8) g5<1>UW g11<8,8,1>UD 0x064a0001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g7<1>UW g19<8,8,1>UD 0x0a8c0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; +send(8) null<1>F g123<8,8,1>F 0x8a080117 + urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g3<1>UW g3<8,8,1>UD 0x02415002 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; +send(8) g5<1>UW g4<8,8,1>UD 0x02416002 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q }; +send(8) g6<1>UW g16<8,8,1>UD 0x0210b500 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080097 + urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g4<8,8,1>F 0x120800c7 + urb MsgDesc: 12 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g5<8,8,1>F 0x120800e7 + urb MsgDesc: 14 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080107 + urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g6<1>UW g11<8,8,1>UD 0x08434102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(8) g67<1>UW g36<8,8,1>UD 0x0823e000 + sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 2 { align1 1Q }; +send(8) g2<1>UW g2<8,8,1>UD 0x0a23c000 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 2 { align1 1Q }; +send(8) g9<1>UW g15<8,8,1>UD 0x021ab101 + sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; +send(8) g10<1>UW g16<8,8,1>UD 0x021ab202 + sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align1 1Q }; +send(8) g11<1>UW g17<8,8,1>UD 0x021ab303 + sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align1 1Q }; +send(8) g12<1>UW g18<8,8,1>UD 0x021ab404 + sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align1 1Q }; +send(8) g13<1>UW g19<8,8,1>UD 0x021ab505 + sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align1 1Q }; +send(8) g14<1>UW g18<8,8,1>UD 0x08123102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g24<1>UW g32<8,8,1>UD 0x10243102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; +send(8) g5<1>UW g5<8,8,1>UD 0x04415000 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UD g9<8,8,1>UD 0x043a0028 + urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x02380098 + urb MsgDesc: 9 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x023800a8 + urb MsgDesc: 10 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x023800b8 + urb MsgDesc: 11 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x023800d8 + urb MsgDesc: 13 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x023800e8 + urb MsgDesc: 14 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x023800f8 + urb MsgDesc: 15 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x02380108 + urb MsgDesc: 16 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g13<1>UD g1<8,8,1>UD 0x02380118 + urb MsgDesc: 17 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) null<1>F g60<8,8,1>F 0x120800a7 + urb MsgDesc: 10 SIMD8 write mlen 9 rlen 0 { align1 1Q }; +send(8) null<1>F g119<8,8,1>F 0x92080107 + urb MsgDesc: 16 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; +send(8) g3<1>UW g7<8,8,1>UD 0x02115e01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) g5<1>UW g11<8,8,1>UD 0x02116e01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 2Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080067 + urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g80<8,8,1>F 0x140a00b7 + urb MsgDesc: 11 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a00d7 + urb MsgDesc: 13 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a00f7 + urb MsgDesc: 15 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a0117 + urb MsgDesc: 17 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a0137 + urb MsgDesc: 19 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g90<8,8,1>F 0x140a0157 + urb MsgDesc: 21 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g100<8,8,1>F 0x140a0177 + urb MsgDesc: 23 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g110<8,8,1>F 0x0c0a0197 + urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g120<8,8,1>F 0x8c0a0197 + urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) null<1>F g123<8,8,1>F 0x8a0800b7 + urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g22<1>UD g53<8,8,1>UD 0x02180238 + urb MsgDesc: 35 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g54<1>UD g53<8,8,1>UD 0x02180438 + urb MsgDesc: 67 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g67<1>UD g53<8,8,1>UD 0x02180638 + urb MsgDesc: 99 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g61<1>UD g53<8,8,1>UD 0x02180248 + urb MsgDesc: 36 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g66<1>UD g53<8,8,1>UD 0x02180448 + urb MsgDesc: 68 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g63<1>UD g53<8,8,1>UD 0x02180648 + urb MsgDesc: 100 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g68<1>UD g65<8,8,1>UD 0x02180258 + urb MsgDesc: 37 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g69<1>UD g65<8,8,1>UD 0x02180458 + urb MsgDesc: 69 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g70<1>UD g65<8,8,1>UD 0x02180658 + urb MsgDesc: 101 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g75<1>UD g24<8,8,1>UD 0x02180268 + urb MsgDesc: 38 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g76<1>UD g24<8,8,1>UD 0x02180468 + urb MsgDesc: 70 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g77<1>UD g24<8,8,1>UD 0x02180668 + urb MsgDesc: 102 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g82<1>UD g25<8,8,1>UD 0x02180278 + urb MsgDesc: 39 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g83<1>UD g25<8,8,1>UD 0x02180478 + urb MsgDesc: 71 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g84<1>UD g25<8,8,1>UD 0x02180678 + urb MsgDesc: 103 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g89<1>UD g26<8,8,1>UD 0x02180288 + urb MsgDesc: 40 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g90<1>UD g26<8,8,1>UD 0x02180488 + urb MsgDesc: 72 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g91<1>UD g26<8,8,1>UD 0x02180688 + urb MsgDesc: 104 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g96<1>UD g27<8,8,1>UD 0x02180298 + urb MsgDesc: 41 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g97<1>UD g27<8,8,1>UD 0x02180498 + urb MsgDesc: 73 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g98<1>UD g27<8,8,1>UD 0x02180698 + urb MsgDesc: 105 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g103<1>UD g28<8,8,1>UD 0x021802a8 + urb MsgDesc: 42 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g104<1>UD g28<8,8,1>UD 0x021804a8 + urb MsgDesc: 74 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g105<1>UD g28<8,8,1>UD 0x021806a8 + urb MsgDesc: 106 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g110<1>UD g29<8,8,1>UD 0x021802b8 + urb MsgDesc: 43 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g111<1>UD g29<8,8,1>UD 0x021804b8 + urb MsgDesc: 75 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g112<1>UD g29<8,8,1>UD 0x021806b8 + urb MsgDesc: 107 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g117<1>UD g30<8,8,1>UD 0x021802c8 + urb MsgDesc: 44 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g118<1>UD g30<8,8,1>UD 0x021804c8 + urb MsgDesc: 76 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g119<1>UD g30<8,8,1>UD 0x021806c8 + urb MsgDesc: 108 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g124<1>UD g31<8,8,1>UD 0x021802d8 + urb MsgDesc: 45 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g125<1>UD g31<8,8,1>UD 0x021804d8 + urb MsgDesc: 77 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g126<1>UD g31<8,8,1>UD 0x021806d8 + urb MsgDesc: 109 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g10<1>UD g32<8,8,1>UD 0x021802e8 + urb MsgDesc: 46 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g11<1>UD g32<8,8,1>UD 0x021804e8 + urb MsgDesc: 78 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g12<1>UD g32<8,8,1>UD 0x021806e8 + urb MsgDesc: 110 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g26<1>UD g33<8,8,1>UD 0x021802f8 + urb MsgDesc: 47 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g27<1>UD g33<8,8,1>UD 0x021804f8 + urb MsgDesc: 79 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g28<1>UD g33<8,8,1>UD 0x021806f8 + urb MsgDesc: 111 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g33<1>UD g35<8,8,1>UD 0x02180308 + urb MsgDesc: 48 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g34<1>UD g35<8,8,1>UD 0x02180508 + urb MsgDesc: 80 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g35<1>UD g35<8,8,1>UD 0x02180708 + urb MsgDesc: 112 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g64<1>UD g36<8,8,1>UD 0x02180318 + urb MsgDesc: 49 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g41<1>UD g36<8,8,1>UD 0x02180518 + urb MsgDesc: 81 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g42<1>UD g36<8,8,1>UD 0x02180718 + urb MsgDesc: 113 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g6<1>UD g37<8,8,1>UD 0x02180328 + urb MsgDesc: 50 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g48<1>UD g37<8,8,1>UD 0x02180528 + urb MsgDesc: 82 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g49<1>UD g37<8,8,1>UD 0x02180728 + urb MsgDesc: 114 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g67<1>UD g38<8,8,1>UD 0x02180338 + urb MsgDesc: 51 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g56<1>UD g38<8,8,1>UD 0x02180538 + urb MsgDesc: 83 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g57<1>UD g38<8,8,1>UD 0x02180738 + urb MsgDesc: 115 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g66<1>UD g39<8,8,1>UD 0x02180348 + urb MsgDesc: 52 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g63<1>UD g39<8,8,1>UD 0x02180548 + urb MsgDesc: 84 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g40<1>UD g39<8,8,1>UD 0x02180748 + urb MsgDesc: 116 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g69<1>UD g64<8,8,1>UD 0x02180358 + urb MsgDesc: 53 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g70<1>UD g64<8,8,1>UD 0x02180558 + urb MsgDesc: 85 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g71<1>UD g64<8,8,1>UD 0x02180758 + urb MsgDesc: 117 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g76<1>UD g41<8,8,1>UD 0x02180368 + urb MsgDesc: 54 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g77<1>UD g41<8,8,1>UD 0x02180568 + urb MsgDesc: 86 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g78<1>UD g41<8,8,1>UD 0x02180768 + urb MsgDesc: 118 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g83<1>UD g42<8,8,1>UD 0x02180378 + urb MsgDesc: 55 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g84<1>UD g42<8,8,1>UD 0x02180578 + urb MsgDesc: 87 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g85<1>UD g42<8,8,1>UD 0x02180778 + urb MsgDesc: 119 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g90<1>UD g43<8,8,1>UD 0x02180388 + urb MsgDesc: 56 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g91<1>UD g43<8,8,1>UD 0x02180588 + urb MsgDesc: 88 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g92<1>UD g43<8,8,1>UD 0x02180788 + urb MsgDesc: 120 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g97<1>UD g44<8,8,1>UD 0x02180398 + urb MsgDesc: 57 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g98<1>UD g44<8,8,1>UD 0x02180598 + urb MsgDesc: 89 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g99<1>UD g44<8,8,1>UD 0x02180798 + urb MsgDesc: 121 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g104<1>UD g45<8,8,1>UD 0x021803a8 + urb MsgDesc: 58 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g105<1>UD g45<8,8,1>UD 0x021805a8 + urb MsgDesc: 90 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g106<1>UD g45<8,8,1>UD 0x021807a8 + urb MsgDesc: 122 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g111<1>UD g46<8,8,1>UD 0x021803b8 + urb MsgDesc: 59 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g112<1>UD g46<8,8,1>UD 0x021805b8 + urb MsgDesc: 91 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g113<1>UD g46<8,8,1>UD 0x021807b8 + urb MsgDesc: 123 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g118<1>UD g6<8,8,1>UD 0x021803c8 + urb MsgDesc: 60 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g119<1>UD g6<8,8,1>UD 0x021805c8 + urb MsgDesc: 92 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g120<1>UD g6<8,8,1>UD 0x021807c8 + urb MsgDesc: 124 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g125<1>UD g48<8,8,1>UD 0x021803d8 + urb MsgDesc: 61 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g126<1>UD g48<8,8,1>UD 0x021805d8 + urb MsgDesc: 93 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g2<1>UD g48<8,8,1>UD 0x021807d8 + urb MsgDesc: 125 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g12<1>UD g49<8,8,1>UD 0x021803e8 + urb MsgDesc: 62 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g13<1>UD g49<8,8,1>UD 0x021805e8 + urb MsgDesc: 94 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g14<1>UD g49<8,8,1>UD 0x021807e8 + urb MsgDesc: 126 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g19<1>UD g50<8,8,1>UD 0x021803f8 + urb MsgDesc: 63 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g20<1>UD g50<8,8,1>UD 0x021805f8 + urb MsgDesc: 95 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g53<1>UD g50<8,8,1>UD 0x021807f8 + urb MsgDesc: 127 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g28<1>UD g51<8,8,1>UD 0x02180408 + urb MsgDesc: 64 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g29<1>UD g51<8,8,1>UD 0x02180608 + urb MsgDesc: 96 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g30<1>UD g51<8,8,1>UD 0x02180808 + urb MsgDesc: 128 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g35<1>UD g22<8,8,1>UD 0x02180218 + urb MsgDesc: 33 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g36<1>UD g22<8,8,1>UD 0x02180418 + urb MsgDesc: 65 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g37<1>UD g22<8,8,1>UD 0x02180618 + urb MsgDesc: 97 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) g38<1>UD g22<8,8,1>UD 0x02180818 + urb MsgDesc: 129 SIMD8 read mlen 1 rlen 1 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x080a8037 + urb MsgDesc: 3 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g10<8,8,1>UD 0x080a8047 + urb MsgDesc: 4 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x080a8057 + urb MsgDesc: 5 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x080a8067 + urb MsgDesc: 6 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x080a8077 + urb MsgDesc: 7 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x080a8087 + urb MsgDesc: 8 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x080a8097 + urb MsgDesc: 9 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x080a80a7 + urb MsgDesc: 10 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x080a80b7 + urb MsgDesc: 11 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x080a80c7 + urb MsgDesc: 12 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x080a80d7 + urb MsgDesc: 13 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x080a80e7 + urb MsgDesc: 14 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x080a80f7 + urb MsgDesc: 15 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x080a8107 + urb MsgDesc: 16 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x080a8117 + urb MsgDesc: 17 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x080a8127 + urb MsgDesc: 18 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x080a8137 + urb MsgDesc: 19 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x080a8147 + urb MsgDesc: 20 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x080a8157 + urb MsgDesc: 21 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x080a8167 + urb MsgDesc: 22 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x080a8177 + urb MsgDesc: 23 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x080a8187 + urb MsgDesc: 24 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x080a8197 + urb MsgDesc: 25 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x080a81a7 + urb MsgDesc: 26 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x080a81b7 + urb MsgDesc: 27 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x080a81c7 + urb MsgDesc: 28 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x080a81d7 + urb MsgDesc: 29 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x080a81e7 + urb MsgDesc: 30 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x080a81f7 + urb MsgDesc: 31 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x080a8207 + urb MsgDesc: 32 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x080a8217 + urb MsgDesc: 33 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) g18<1>UW g19<8,8,1>UD 0x04115e00 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; +send(8) g2<1>UW g6<8,8,1>UD 0x0623d001 + sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; +send(16) g2<1>UW g8<8,8,1>UD 0x0c45d001 + sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; +send(8) g101<1>UW g10<8,8,1>UD 0x0c33c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 3 { align1 1Q }; +send(8) g14<1>UW g11<8,8,1>UD 0x084b0203 + sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x0a4b0102 + sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; +send(16) g26<1>UW g2<8,8,1>UD 0x0e8d0203 + sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H }; +send(16) g10<1>UW g34<8,8,1>UD 0x128d0102 + sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x0a1b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g7<1>UW g12<8,8,1>UD 0x0a1b4102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(8) g34<1>UD g42<8,8,1>UD 0x02480248 + urb MsgDesc: 36 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g38<1>UD g42<8,8,1>UD 0x02480448 + urb MsgDesc: 68 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g42<1>UD g42<8,8,1>UD 0x02480648 + urb MsgDesc: 100 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g43<8,8,1>UD 0x02480258 + urb MsgDesc: 37 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g43<8,8,1>UD 0x02480458 + urb MsgDesc: 69 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g43<8,8,1>UD 0x02480658 + urb MsgDesc: 101 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g44<8,8,1>UD 0x02480268 + urb MsgDesc: 38 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g44<8,8,1>UD 0x02480468 + urb MsgDesc: 70 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g44<8,8,1>UD 0x02480668 + urb MsgDesc: 102 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g45<8,8,1>UD 0x02480278 + urb MsgDesc: 39 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g45<8,8,1>UD 0x02480478 + urb MsgDesc: 71 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g45<8,8,1>UD 0x02480678 + urb MsgDesc: 103 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g55<8,8,1>UD 0x02480288 + urb MsgDesc: 40 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g55<8,8,1>UD 0x02480488 + urb MsgDesc: 72 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g55<8,8,1>UD 0x02480688 + urb MsgDesc: 104 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g56<8,8,1>UD 0x02480498 + urb MsgDesc: 73 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g56<8,8,1>UD 0x02480298 + urb MsgDesc: 41 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g56<8,8,1>UD 0x02480698 + urb MsgDesc: 105 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g82<8,8,1>UD 0x024804a8 + urb MsgDesc: 74 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g82<8,8,1>UD 0x024802a8 + urb MsgDesc: 42 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g82<8,8,1>UD 0x024806a8 + urb MsgDesc: 106 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g83<8,8,1>UD 0x024804b8 + urb MsgDesc: 75 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g83<8,8,1>UD 0x024802b8 + urb MsgDesc: 43 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g30<1>UD g83<8,8,1>UD 0x024806b8 + urb MsgDesc: 107 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g84<8,8,1>UD 0x024806c8 + urb MsgDesc: 108 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g84<8,8,1>UD 0x024802c8 + urb MsgDesc: 44 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g84<8,8,1>UD 0x024804c8 + urb MsgDesc: 76 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g85<8,8,1>UD 0x024802d8 + urb MsgDesc: 45 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g85<8,8,1>UD 0x024804d8 + urb MsgDesc: 77 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g85<8,8,1>UD 0x024806d8 + urb MsgDesc: 109 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g6<8,8,1>UD 0x024802e8 + urb MsgDesc: 46 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g6<8,8,1>UD 0x024804e8 + urb MsgDesc: 78 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g6<8,8,1>UD 0x024806e8 + urb MsgDesc: 110 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g3<8,8,1>UD 0x024802f8 + urb MsgDesc: 47 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g3<8,8,1>UD 0x024804f8 + urb MsgDesc: 79 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g3<8,8,1>UD 0x024806f8 + urb MsgDesc: 111 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g46<8,8,1>UD 0x02480308 + urb MsgDesc: 48 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g46<8,8,1>UD 0x02480508 + urb MsgDesc: 80 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g46<8,8,1>UD 0x02480708 + urb MsgDesc: 112 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g47<8,8,1>UD 0x02480318 + urb MsgDesc: 49 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g47<8,8,1>UD 0x02480518 + urb MsgDesc: 81 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g47<8,8,1>UD 0x02480718 + urb MsgDesc: 113 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g57<8,8,1>UD 0x02480328 + urb MsgDesc: 50 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g57<8,8,1>UD 0x02480528 + urb MsgDesc: 82 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g57<8,8,1>UD 0x02480728 + urb MsgDesc: 114 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g58<8,8,1>UD 0x02480338 + urb MsgDesc: 51 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g58<8,8,1>UD 0x02480538 + urb MsgDesc: 83 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g26<1>UD g58<8,8,1>UD 0x02480738 + urb MsgDesc: 115 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g59<8,8,1>UD 0x02480348 + urb MsgDesc: 52 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g59<8,8,1>UD 0x02480548 + urb MsgDesc: 84 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g59<8,8,1>UD 0x02480748 + urb MsgDesc: 116 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g60<8,8,1>UD 0x02480358 + urb MsgDesc: 53 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g60<8,8,1>UD 0x02480558 + urb MsgDesc: 85 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g60<8,8,1>UD 0x02480758 + urb MsgDesc: 117 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g61<8,8,1>UD 0x02480368 + urb MsgDesc: 54 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g61<8,8,1>UD 0x02480568 + urb MsgDesc: 86 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g61<8,8,1>UD 0x02480768 + urb MsgDesc: 118 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g62<8,8,1>UD 0x02480378 + urb MsgDesc: 55 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g62<8,8,1>UD 0x02480578 + urb MsgDesc: 87 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g62<8,8,1>UD 0x02480778 + urb MsgDesc: 119 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g63<8,8,1>UD 0x02480388 + urb MsgDesc: 56 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g63<8,8,1>UD 0x02480588 + urb MsgDesc: 88 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g63<8,8,1>UD 0x02480788 + urb MsgDesc: 120 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g64<8,8,1>UD 0x02480398 + urb MsgDesc: 57 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g64<8,8,1>UD 0x02480598 + urb MsgDesc: 89 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g64<8,8,1>UD 0x02480798 + urb MsgDesc: 121 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g68<8,8,1>UD 0x024803a8 + urb MsgDesc: 58 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g68<8,8,1>UD 0x024805a8 + urb MsgDesc: 90 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g68<8,8,1>UD 0x024807a8 + urb MsgDesc: 122 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g69<8,8,1>UD 0x024803b8 + urb MsgDesc: 59 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g69<8,8,1>UD 0x024805b8 + urb MsgDesc: 91 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UD g69<8,8,1>UD 0x024807b8 + urb MsgDesc: 123 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g70<8,8,1>UD 0x024803c8 + urb MsgDesc: 60 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g70<8,8,1>UD 0x024805c8 + urb MsgDesc: 92 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g70<8,8,1>UD 0x024807c8 + urb MsgDesc: 124 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g71<8,8,1>UD 0x024803d8 + urb MsgDesc: 61 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g71<8,8,1>UD 0x024805d8 + urb MsgDesc: 93 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g71<8,8,1>UD 0x024807d8 + urb MsgDesc: 125 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g72<8,8,1>UD 0x024803e8 + urb MsgDesc: 62 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g72<8,8,1>UD 0x024805e8 + urb MsgDesc: 94 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g72<8,8,1>UD 0x024807e8 + urb MsgDesc: 126 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g8<1>UD g73<8,8,1>UD 0x024803f8 + urb MsgDesc: 63 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g73<8,8,1>UD 0x024805f8 + urb MsgDesc: 95 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g73<8,8,1>UD 0x024807f8 + urb MsgDesc: 127 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g12<1>UD g75<8,8,1>UD 0x02480418 + urb MsgDesc: 65 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g16<1>UD g75<8,8,1>UD 0x02480618 + urb MsgDesc: 97 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) g20<1>UD g75<8,8,1>UD 0x02480818 + urb MsgDesc: 129 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0c0a00c7 + urb MsgDesc: 12 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0c0a00d7 + urb MsgDesc: 13 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0c0a00e7 + urb MsgDesc: 14 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0c0a00f7 + urb MsgDesc: 15 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0c0a0107 + urb MsgDesc: 16 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0c0a0117 + urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0c0a0137 + urb MsgDesc: 19 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0c0a0147 + urb MsgDesc: 20 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0c0a0157 + urb MsgDesc: 21 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0c0a0167 + urb MsgDesc: 22 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0c0a0177 + urb MsgDesc: 23 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0c0a0187 + urb MsgDesc: 24 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0c0a01a7 + urb MsgDesc: 26 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0c0a01b7 + urb MsgDesc: 27 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0c0a01c7 + urb MsgDesc: 28 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0c0a01d7 + urb MsgDesc: 29 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0c0a01e7 + urb MsgDesc: 30 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0c0a01f7 + urb MsgDesc: 31 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; +send(16) g46<1>UD g12<0,1,0>UD 0x02280302 + const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g50<1>UD g15<0,1,0>UD 0x02280304 + const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g34<1>UD g20<0,1,0>UD 0x02280303 + const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g16<1>UD g21<0,1,0>UD 0x02280306 + const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g5<1>UW g19<8,8,1>UD 0x02106e03 + dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) g8<1>UW g21<8,8,1>UD 0x02106e04 + dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(16) g8<1>UW g34<8,8,1>UD 0x04205e03 + dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(16) g14<1>UW g37<8,8,1>UD 0x04205e04 + dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; +send(8) g15<1>UD g12<8,8,1>UD 0x041a0038 + urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g2<1>UW g54<8,8,1>UD 0x0242a707 + sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 7 mlen 1 rlen 4 { align1 1Q }; +send(8) g6<1>UW g55<8,8,1>UD 0x0242a808 + sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 8 mlen 1 rlen 4 { align1 1Q }; +send(8) g10<1>UW g56<8,8,1>UD 0x0242a909 + sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 9 mlen 1 rlen 4 { align1 1Q }; +send(8) g14<1>UW g57<8,8,1>UD 0x0242aa0a + sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 10 mlen 1 rlen 4 { align1 1Q }; +send(8) g18<1>UW g58<8,8,1>UD 0x0242ab0b + sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; +send(8) g22<1>UW g59<8,8,1>UD 0x0242ac0c + sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g9<8,8,1>UD 0x0c088027 + urb MsgDesc: 2 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g10<8,8,1>UD 0x0c088047 + urb MsgDesc: 4 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x0c088067 + urb MsgDesc: 6 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>UD 0x0c088037 + urb MsgDesc: 3 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g7<8,8,1>UD 0x0c088057 + urb MsgDesc: 5 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g8<8,8,1>UD 0x0c088077 + urb MsgDesc: 7 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a0197 + urb MsgDesc: 25 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a01b7 + urb MsgDesc: 27 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a01d7 + urb MsgDesc: 29 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g6<8,8,1>F 0x140a01f7 + urb MsgDesc: 31 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g120<8,8,1>F 0x8c0a0217 + urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g8<1>UD g6<8,8,1>UD 0x041a0318 + urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g9<1>UD g6<8,8,1>UD 0x041a0518 + urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g10<1>UD g6<8,8,1>UD 0x041a0718 + urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g11<1>UD g6<8,8,1>UD 0x041a0918 + urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g7<1>UD g11<8,8,1>UD 0x041a0218 + urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g8<1>UD g11<8,8,1>UD 0x041a0418 + urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g9<1>UD g11<8,8,1>UD 0x041a0618 + urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g10<1>UD g11<8,8,1>UD 0x041a0818 + urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) null<1>F g10<8,8,1>UD 0x080a8227 + urb MsgDesc: 34 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g11<8,8,1>UD 0x080a8237 + urb MsgDesc: 35 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x080a8247 + urb MsgDesc: 36 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x080a8257 + urb MsgDesc: 37 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x080a8267 + urb MsgDesc: 38 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x080a8277 + urb MsgDesc: 39 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x080a8287 + urb MsgDesc: 40 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x080a8297 + urb MsgDesc: 41 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x080a82a7 + urb MsgDesc: 42 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x080a82b7 + urb MsgDesc: 43 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x080a82c7 + urb MsgDesc: 44 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x080a82d7 + urb MsgDesc: 45 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x080a82e7 + urb MsgDesc: 46 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x080a82f7 + urb MsgDesc: 47 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x080a8307 + urb MsgDesc: 48 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x080a8317 + urb MsgDesc: 49 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x080a8327 + urb MsgDesc: 50 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x080a8337 + urb MsgDesc: 51 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x080a8347 + urb MsgDesc: 52 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x080a8357 + urb MsgDesc: 53 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x080a8367 + urb MsgDesc: 54 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x080a8377 + urb MsgDesc: 55 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x080a8387 + urb MsgDesc: 56 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x080a8397 + urb MsgDesc: 57 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x080a83a7 + urb MsgDesc: 58 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x080a83b7 + urb MsgDesc: 59 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x080a83c7 + urb MsgDesc: 60 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x080a83d7 + urb MsgDesc: 61 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x080a83e7 + urb MsgDesc: 62 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x080a83f7 + urb MsgDesc: 63 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; +send(8) g8<1>UD g9<8,8,1>UD 0x02480008 + urb MsgDesc: 0 SIMD8 read mlen 1 rlen 4 { align1 1Q }; +send(8) null<1>F g123<8,8,1>F 0x8a080007 + urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g4<1>UW g2<8,8,1>UD 0x04215c01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q }; +send(8) g40<1>UW g38<8,8,1>UD 0x04216c01 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 2 rlen 2 { align1 2Q }; +send(8) g6<1>UW g11<8,8,1>UD 0x104a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q }; +send(8) g124<1>UW g2<8,8,1>UD 0x04422001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x08842001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g2<1>UW g7<8,8,1>UD 0x06425001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g6<1>UW g10<8,8,1>UD 0x06425102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g11<8,8,1>UD 0x0c845001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(16) g10<1>UW g18<8,8,1>UD 0x0c845102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; +send(8) null<1>F g121<8,8,1>F 0x8a080197 + urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; +send(8) g124<1>UW g6<8,8,1>UD 0x02415000 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; +send(8) g124<1>UW g6<8,8,1>UD 0x06415000 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q }; +send(8) g124<1>UW g6<8,8,1>UD 0x02215c00 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xc) mlen 1 rlen 2 { align1 1Q }; +send(8) g17<1>UW g27<8,8,1>UD 0x02115e00 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; +send(8) g124<1>UW g2<8,8,1>UD 0x02415001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; +send(8) g2<1>UW g29<8,8,1>UD 0x02416001 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q }; +send(8) g9<1>UW g19<8,8,1>UD 0x0843e102 + sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(16) g23<1>UW g7<8,8,1>UD 0x1085e102 + sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; +send(8) g124<1>UW g5<8,8,1>UD 0x0c4b0001 + sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(16) g120<1>UW g7<8,8,1>UD 0x168d0001 + sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x0a134001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g7<1>UW g12<8,8,1>UD 0x0a134102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(8) g22<1>UD g10<8,8,1>UD 0x041a0138 + urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g21<1>UD g10<8,8,1>UD 0x041a0338 + urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g65<1>UD g10<8,8,1>UD 0x041a0538 + urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g10<1>UD g10<8,8,1>UD 0x041a0738 + urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g65<1>UD g11<8,8,1>UD 0x041a0238 + urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g10<1>UD g11<8,8,1>UD 0x041a0438 + urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g11<1>UD g11<8,8,1>UD 0x041a0638 + urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g8<1>UD g7<8,8,1>UD 0x041a0048 + urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g6<1>UW g10<8,8,1>UD 0x0a4a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(8) g2<1>UW g7<8,8,1>UD 0x06426001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(8) g6<1>UW g10<8,8,1>UD 0x06426102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW g11<8,8,1>UD 0x0c846001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(16) g10<1>UW g18<8,8,1>UD 0x0c846102 + sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x08320001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x10640001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x0c1b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 1 { align1 1Q }; +send(8) g7<1>UW g13<8,8,1>UD 0x0c1b4102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 1 { align1 1Q }; +send(8) g2<1>UW g7<8,8,1>UD 0x08425001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g6<1>UW g11<8,8,1>UD 0x08425102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW g11<8,8,1>UD 0x10845001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(16) g10<1>UW g19<8,8,1>UD 0x10845102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; +send(8) g124<1>UW g2<8,8,1>UD 0x02306801 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x8) mlen 1 rlen 3 { align1 1Q }; +send(16) g120<1>UW g2<8,8,1>UD 0x04605801 + dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x8) mlen 2 rlen 6 { align1 1H }; +send(8) g8<1>UD g7<8,8,1>UD 0x043a0128 + urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g12<1>UW g5<8,8,1>UD 0x0833e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q }; +send(8) g15<1>UW g17<8,8,1>UD 0x0823e001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1Q }; +send(16) g7<1>UW g13<8,8,1>UD 0x1065e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H }; +send(16) g33<1>UW g21<8,8,1>UD 0x1045e001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1H }; +send(8) g14<1>UW g14<8,8,1>UD 0x101b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q }; +send(8) g15<1>UW g22<8,8,1>UD 0x101b4102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q }; +send(8) g8<1>UD g20<8,8,1>UD 0x044a0138 + urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g20<8,8,1>UD 0x044a0338 + urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g16<1>UD g20<8,8,1>UD 0x044a0538 + urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g20<1>UD g20<8,8,1>UD 0x044a0738 + urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g14<1>UD g22<8,8,1>UD 0x044a0238 + urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g18<1>UD g22<8,8,1>UD 0x044a0438 + urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g22<1>UD g22<8,8,1>UD 0x044a0638 + urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g11<1>UW g5<8,8,1>UD 0x04120003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(8) g12<1>UW g5<8,8,1>UD 0x04120004 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(16) g8<1>UW g12<8,8,1>UD 0x08240003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(16) g10<1>UW g12<8,8,1>UD 0x08240004 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(8) g6<1>UW g7<8,8,1>UD 0x08125001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; +send(8) g7<1>UW g11<8,8,1>UD 0x08125102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; +send(16) g10<1>UW g12<8,8,1>UD 0x10245001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; +send(16) g12<1>UW g20<8,8,1>UD 0x10245102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; +send(8) g2<1>UW g13<8,8,1>UD 0x0623a001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; +send(16) g6<1>UW g23<8,8,1>UD 0x0c45a001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; +send(8) g124<1>UW g7<8,8,1>UD 0x0c4b2000 + sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g13<1>UD g39<8,8,1>UD 0x041a0058 + urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g10<8,8,1>UD 0x041a0068 + urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a0078 + urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a0088 + urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a0098 + urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a00a8 + urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a00b8 + urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g4<1>UD g3<8,8,1>UD 0x041a00c8 + urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a00d8 + urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a00e8 + urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a00f8 + urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0108 + urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0118 + urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0148 + urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0158 + urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0168 + urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0178 + urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0188 + urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0198 + urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01a8 + urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01b8 + urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01c8 + urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01d8 + urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01e8 + urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a01f8 + urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g3<1>UD g2<8,8,1>UD 0x041a0208 + urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; +send(8) g38<1>UW g38<8,8,1>UD 0x084a8405 + sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; +send(8) g46<1>UW g23<8,8,1>UD 0x064a8304 + sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; +send(8) g28<1>UW g28<8,8,1>UD 0x064a8506 + sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; +send(8) g12<1>UW g23<8,8,1>UD 0x064a8607 + sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; +send(8) g12<1>UW g32<8,8,1>UD 0x084a8708 + sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 7 mlen 4 rlen 4 { align1 1Q }; +send(8) g26<1>UW g13<8,8,1>UD 0x064a8809 + sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; +send(8) g26<1>UW g26<8,8,1>UD 0x084b090a + sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 9 mlen 4 rlen 4 { align1 1Q }; +send(8) g2<1>UW g2<8,8,1>UD 0x0a4b0a0b + sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 10 mlen 5 rlen 4 { align1 1Q }; +send(8) g6<1>UW g6<8,8,1>UD 0x084b0b0c + sampler MsgDesc: gather4_c SIMD8 Surface = 12 Sampler = 11 mlen 4 rlen 4 { align1 1Q }; +send(16) g30<1>UW g73<8,8,1>UD 0x0a8c8304 + sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 8 { align1 1H }; +send(16) g40<1>UW g2<8,8,1>UD 0x0e8c8405 + sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H }; +send(16) g5<1>UW g33<8,8,1>UD 0x0a8c8506 + sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 8 { align1 1H }; +send(16) g32<1>UW g55<8,8,1>UD 0x0a8c8607 + sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 6 mlen 5 rlen 8 { align1 1H }; +send(16) g30<1>UW g23<8,8,1>UD 0x0e8c8708 + sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 7 mlen 7 rlen 8 { align1 1H }; +send(16) g5<1>UW g40<8,8,1>UD 0x0a8c8809 + sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 8 mlen 5 rlen 8 { align1 1H }; +send(16) g38<1>UW g67<8,8,1>UD 0x0e8d090a + sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 9 mlen 7 rlen 8 { align1 1H }; +send(16) g38<1>UW g2<8,8,1>UD 0x128d0a0b + sampler MsgDesc: gather4_c SIMD16 Surface = 11 Sampler = 10 mlen 9 rlen 8 { align1 1H }; +send(16) g10<1>UW g39<8,8,1>UD 0x0e8d0b0c + sampler MsgDesc: gather4_c SIMD16 Surface = 12 Sampler = 11 mlen 7 rlen 8 { align1 1H }; +send(8) g2<1>UW g6<8,8,1>UD 0x0e4b2000 + sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g11<1>UW g7<8,8,1>UD 0x04120102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q }; +send(8) g12<1>UW g7<8,8,1>UD 0x04120203 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 1 { align1 1Q }; +send(16) g6<1>UW g11<8,8,1>UD 0x08240102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H }; +send(16) g8<1>UW g11<8,8,1>UD 0x08240203 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 2 { align1 1H }; +send(8) g5<1>UW g6<8,8,1>UD 0x04220003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; +send(16) g8<1>UW g12<8,8,1>UD 0x08440003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 4 { align1 1H }; +send(8) g5<1>UW g2<8,8,1>UD 0x04129001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; +send(16) g6<1>UW g2<8,8,1>UD 0x08249001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; +send(8) g11<1>UW g4<8,8,1>UD 0x04415002 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; +send(8) g7<1>UW g5<8,8,1>UD 0x04416002 + dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; +send(8) null<1>F g16<8,8,1>UD 0x0e0a8057 + urb MsgDesc: 5 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; +send(8) g6<1>UD g18<8,8,1>UD 0x043a0318 + urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g9<1>UD g18<8,8,1>UD 0x043a0518 + urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g12<1>UD g18<8,8,1>UD 0x043a0718 + urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g15<1>UD g18<8,8,1>UD 0x043a0918 + urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g11<1>UD g23<8,8,1>UD 0x043a0218 + urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g14<1>UD g23<8,8,1>UD 0x043a0418 + urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g17<1>UD g23<8,8,1>UD 0x043a0618 + urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g20<1>UD g23<8,8,1>UD 0x043a0818 + urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) null<1>F g12<8,8,1>UD 0x0c0a8227 + urb MsgDesc: 34 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g13<8,8,1>UD 0x0c0a8237 + urb MsgDesc: 35 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g14<8,8,1>UD 0x0c0a8247 + urb MsgDesc: 36 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g15<8,8,1>UD 0x0c0a8257 + urb MsgDesc: 37 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g16<8,8,1>UD 0x0c0a8267 + urb MsgDesc: 38 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g17<8,8,1>UD 0x0c0a8277 + urb MsgDesc: 39 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g18<8,8,1>UD 0x0c0a8287 + urb MsgDesc: 40 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g19<8,8,1>UD 0x0c0a8297 + urb MsgDesc: 41 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g20<8,8,1>UD 0x0c0a82a7 + urb MsgDesc: 42 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g21<8,8,1>UD 0x0c0a82b7 + urb MsgDesc: 43 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g22<8,8,1>UD 0x0c0a82c7 + urb MsgDesc: 44 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g23<8,8,1>UD 0x0c0a82d7 + urb MsgDesc: 45 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g24<8,8,1>UD 0x0c0a82e7 + urb MsgDesc: 46 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g25<8,8,1>UD 0x0c0a82f7 + urb MsgDesc: 47 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g26<8,8,1>UD 0x0c0a8307 + urb MsgDesc: 48 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g27<8,8,1>UD 0x0c0a8317 + urb MsgDesc: 49 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g28<8,8,1>UD 0x0c0a8327 + urb MsgDesc: 50 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g29<8,8,1>UD 0x0c0a8337 + urb MsgDesc: 51 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g30<8,8,1>UD 0x0c0a8347 + urb MsgDesc: 52 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>UD 0x0c0a8357 + urb MsgDesc: 53 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g32<8,8,1>UD 0x0c0a8367 + urb MsgDesc: 54 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g33<8,8,1>UD 0x0c0a8377 + urb MsgDesc: 55 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g34<8,8,1>UD 0x0c0a8387 + urb MsgDesc: 56 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g35<8,8,1>UD 0x0c0a8397 + urb MsgDesc: 57 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g36<8,8,1>UD 0x0c0a83a7 + urb MsgDesc: 58 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g37<8,8,1>UD 0x0c0a83b7 + urb MsgDesc: 59 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g38<8,8,1>UD 0x0c0a83c7 + urb MsgDesc: 60 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g39<8,8,1>UD 0x0c0a83d7 + urb MsgDesc: 61 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g40<8,8,1>UD 0x0c0a83e7 + urb MsgDesc: 62 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) null<1>F g41<8,8,1>UD 0x0c0a83f7 + urb MsgDesc: 63 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; +send(8) g8<1>UW g7<8,8,1>UD 0x10134001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q }; +send(8) g9<1>UW g15<8,8,1>UD 0x10134102 + sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q }; +send(8) g16<1>UD g16<8,8,1>UD 0x044a0148 + urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g38<1>UW g38<8,8,1>UD 0x084a8404 + sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; +send(8) g46<1>UW g23<8,8,1>UD 0x064a8303 + sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; +send(8) g28<1>UW g28<8,8,1>UD 0x064a8505 + sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; +send(8) g12<1>UW g23<8,8,1>UD 0x064a8606 + sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; +send(8) g12<1>UW g32<8,8,1>UD 0x084a8707 + sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 7 mlen 4 rlen 4 { align1 1Q }; +send(8) g26<1>UW g13<8,8,1>UD 0x064a8808 + sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; +send(8) g26<1>UW g26<8,8,1>UD 0x084b0909 + sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 9 mlen 4 rlen 4 { align1 1Q }; +send(8) g2<1>UW g2<8,8,1>UD 0x0a4b0a0a + sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 10 mlen 5 rlen 4 { align1 1Q }; +send(8) g10<1>UW g10<8,8,1>UD 0x084b0b0b + sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 11 mlen 4 rlen 4 { align1 1Q }; +send(8) g2<1>UD g15<8,8,1>UD 0x043a0048 + urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g12<1>UD g15<8,8,1>UD 0x043a0058 + urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0068 + urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0078 + urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0088 + urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0098 + urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00a8 + urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00b8 + urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00c8 + urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00d8 + urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00e8 + urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a00f8 + urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0108 + urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0118 + urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0138 + urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0148 + urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0158 + urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0168 + urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0178 + urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0188 + urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0198 + urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01a8 + urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01b8 + urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01c8 + urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01d8 + urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01e8 + urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a01f8 + urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g2<1>UD g2<8,8,1>UD 0x043a0208 + urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) null<1>F g11<8,8,1>F 0x140a0047 + urb MsgDesc: 4 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g31<8,8,1>F 0x140a0087 + urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; +send(8) null<1>F g118<8,8,1>F 0x940a0087 + urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; +send(8) g14<1>UW g11<8,8,1>UD 0x0a4b0202 + sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; +send(8) g18<1>UW g18<8,8,1>UD 0x0c4b0303 + sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 3 mlen 6 rlen 4 { align1 1Q }; +send(8) g22<1>UW g24<8,8,1>UD 0x084b0404 + sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; +send(8) g15<1>UW g2<8,8,1>UD 0x06423203 + sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; +send(16) g19<1>UW g27<8,8,1>UD 0x0c843203 + sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 6 rlen 8 { align1 1H }; +send(8) g7<1>UW g9<8,8,1>UD 0x0a13c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(16) g20<1>UW g7<8,8,1>UD 0x1425c001 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; +send(8) g21<1>UW g5<8,8,1>UD 0x0a33c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q }; +send(8) g18<1>UW g24<8,8,1>UD 0x0a23c001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1Q }; +send(16) g15<1>UW g21<8,8,1>UD 0x1465c001 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H }; +send(16) g7<1>UW g31<8,8,1>UD 0x1445c001 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1H }; +send(8) g124<1>UW g6<8,8,1>UD 0x04438303 + sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(8) g11<1>UD g17<8,8,1>UD 0x043a0338 + urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g14<1>UD g17<8,8,1>UD 0x043a0538 + urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g17<1>UD g17<8,8,1>UD 0x043a0738 + urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g9<1>UD g18<8,8,1>UD 0x043a0038 + urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g12<1>UD g18<8,8,1>UD 0x043a0238 + urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g15<1>UD g18<8,8,1>UD 0x043a0438 + urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g18<1>UD g18<8,8,1>UD 0x043a0638 + urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; +send(8) g6<1>UW g10<8,8,1>UD 0x08424001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g9<1>UW g5<8,8,1>UD 0x04420002 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g13<1>UW g7<8,8,1>UD 0x08840002 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +(+f1.0) send(8) g124<1>UW g2<8,8,1>UD 0x0211a501 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 1 rlen 1 { align1 1Q }; +(+f1.0) send(8) g121<1>UW g3<8,8,1>UD 0x0211b501 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 2Q }; +send(8) g22<1>UD g32<8,8,1>UD 0x02280238 + urb MsgDesc: 35 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g32<8,8,1>UD 0x02280438 + urb MsgDesc: 67 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g26<1>UD g32<8,8,1>UD 0x02280638 + urb MsgDesc: 99 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g28<1>UD g32<8,8,1>UD 0x02280248 + urb MsgDesc: 36 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g30<1>UD g32<8,8,1>UD 0x02280448 + urb MsgDesc: 68 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g32<1>UD g32<8,8,1>UD 0x02280648 + urb MsgDesc: 100 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g33<8,8,1>UD 0x02280258 + urb MsgDesc: 37 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g33<8,8,1>UD 0x02280458 + urb MsgDesc: 69 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g26<1>UD g33<8,8,1>UD 0x02280658 + urb MsgDesc: 101 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g34<8,8,1>UD 0x02280268 + urb MsgDesc: 38 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g34<8,8,1>UD 0x02280468 + urb MsgDesc: 70 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g26<1>UD g34<8,8,1>UD 0x02280668 + urb MsgDesc: 102 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g35<8,8,1>UD 0x02280478 + urb MsgDesc: 71 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g35<8,8,1>UD 0x02280278 + urb MsgDesc: 39 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g26<1>UD g35<8,8,1>UD 0x02280678 + urb MsgDesc: 103 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g36<8,8,1>UD 0x02280688 + urb MsgDesc: 104 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g36<8,8,1>UD 0x02280288 + urb MsgDesc: 40 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g36<8,8,1>UD 0x02280488 + urb MsgDesc: 72 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g37<8,8,1>UD 0x02280298 + urb MsgDesc: 41 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g37<8,8,1>UD 0x02280498 + urb MsgDesc: 73 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g37<8,8,1>UD 0x02280698 + urb MsgDesc: 105 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g38<8,8,1>UD 0x022802a8 + urb MsgDesc: 42 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g38<8,8,1>UD 0x022804a8 + urb MsgDesc: 74 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g38<8,8,1>UD 0x022806a8 + urb MsgDesc: 106 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g39<8,8,1>UD 0x022802b8 + urb MsgDesc: 43 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g39<8,8,1>UD 0x022804b8 + urb MsgDesc: 75 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g24<1>UD g39<8,8,1>UD 0x022806b8 + urb MsgDesc: 107 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g40<8,8,1>UD 0x022802c8 + urb MsgDesc: 44 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g40<8,8,1>UD 0x022804c8 + urb MsgDesc: 76 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g40<8,8,1>UD 0x022806c8 + urb MsgDesc: 108 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g41<8,8,1>UD 0x022802d8 + urb MsgDesc: 45 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g41<8,8,1>UD 0x022804d8 + urb MsgDesc: 77 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g41<8,8,1>UD 0x022806d8 + urb MsgDesc: 109 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g42<8,8,1>UD 0x022802e8 + urb MsgDesc: 46 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g42<8,8,1>UD 0x022804e8 + urb MsgDesc: 78 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g42<8,8,1>UD 0x022806e8 + urb MsgDesc: 110 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g43<8,8,1>UD 0x022802f8 + urb MsgDesc: 47 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g43<8,8,1>UD 0x022804f8 + urb MsgDesc: 79 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g22<1>UD g43<8,8,1>UD 0x022806f8 + urb MsgDesc: 111 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g44<8,8,1>UD 0x02280308 + urb MsgDesc: 48 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g44<8,8,1>UD 0x02280508 + urb MsgDesc: 80 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g44<8,8,1>UD 0x02280708 + urb MsgDesc: 112 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g45<8,8,1>UD 0x02280318 + urb MsgDesc: 49 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g45<8,8,1>UD 0x02280518 + urb MsgDesc: 81 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g45<8,8,1>UD 0x02280718 + urb MsgDesc: 113 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g46<8,8,1>UD 0x02280328 + urb MsgDesc: 50 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g46<8,8,1>UD 0x02280528 + urb MsgDesc: 82 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g46<8,8,1>UD 0x02280728 + urb MsgDesc: 114 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g47<8,8,1>UD 0x02280338 + urb MsgDesc: 51 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g47<8,8,1>UD 0x02280538 + urb MsgDesc: 83 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g47<8,8,1>UD 0x02280738 + urb MsgDesc: 115 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g48<8,8,1>UD 0x02280348 + urb MsgDesc: 52 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g48<8,8,1>UD 0x02280548 + urb MsgDesc: 84 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g48<8,8,1>UD 0x02280748 + urb MsgDesc: 116 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g49<8,8,1>UD 0x02280358 + urb MsgDesc: 53 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g49<8,8,1>UD 0x02280558 + urb MsgDesc: 85 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g49<8,8,1>UD 0x02280758 + urb MsgDesc: 117 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g50<8,8,1>UD 0x02280368 + urb MsgDesc: 54 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g50<8,8,1>UD 0x02280568 + urb MsgDesc: 86 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g50<8,8,1>UD 0x02280768 + urb MsgDesc: 118 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g53<8,8,1>UD 0x02280378 + urb MsgDesc: 55 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g53<8,8,1>UD 0x02280578 + urb MsgDesc: 87 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g53<8,8,1>UD 0x02280778 + urb MsgDesc: 119 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g54<8,8,1>UD 0x02280388 + urb MsgDesc: 56 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g54<8,8,1>UD 0x02280588 + urb MsgDesc: 88 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g54<8,8,1>UD 0x02280788 + urb MsgDesc: 120 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g55<8,8,1>UD 0x02280398 + urb MsgDesc: 57 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g55<8,8,1>UD 0x02280598 + urb MsgDesc: 89 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g55<8,8,1>UD 0x02280798 + urb MsgDesc: 121 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g56<8,8,1>UD 0x022803a8 + urb MsgDesc: 58 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g56<8,8,1>UD 0x022805a8 + urb MsgDesc: 90 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g56<8,8,1>UD 0x022807a8 + urb MsgDesc: 122 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g57<8,8,1>UD 0x022803b8 + urb MsgDesc: 59 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g57<8,8,1>UD 0x022805b8 + urb MsgDesc: 91 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g57<8,8,1>UD 0x022807b8 + urb MsgDesc: 123 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g58<8,8,1>UD 0x022803c8 + urb MsgDesc: 60 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g58<8,8,1>UD 0x022805c8 + urb MsgDesc: 92 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g58<8,8,1>UD 0x022807c8 + urb MsgDesc: 124 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g59<8,8,1>UD 0x022803d8 + urb MsgDesc: 61 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g59<8,8,1>UD 0x022805d8 + urb MsgDesc: 93 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g59<8,8,1>UD 0x022807d8 + urb MsgDesc: 125 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g60<8,8,1>UD 0x022803e8 + urb MsgDesc: 62 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g60<8,8,1>UD 0x022805e8 + urb MsgDesc: 94 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g60<8,8,1>UD 0x022807e8 + urb MsgDesc: 126 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g61<8,8,1>UD 0x022803f8 + urb MsgDesc: 63 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g61<8,8,1>UD 0x022805f8 + urb MsgDesc: 95 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g61<8,8,1>UD 0x022807f8 + urb MsgDesc: 127 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g62<8,8,1>UD 0x02280408 + urb MsgDesc: 64 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g62<8,8,1>UD 0x02280608 + urb MsgDesc: 96 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g14<1>UD g62<8,8,1>UD 0x02280808 + urb MsgDesc: 128 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g8<1>UD g63<8,8,1>UD 0x02280218 + urb MsgDesc: 33 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g10<1>UD g63<8,8,1>UD 0x02280418 + urb MsgDesc: 65 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g12<1>UD g63<8,8,1>UD 0x02280618 + urb MsgDesc: 97 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g14<1>UD g63<8,8,1>UD 0x02280818 + urb MsgDesc: 129 SIMD8 read mlen 1 rlen 2 { align1 1Q }; +send(8) g29<1>UW g18<8,8,1>UD 0x04420008 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g35<1>UW g18<8,8,1>UD 0x04420109 + sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(8) g41<1>UW g18<8,8,1>UD 0x0442020a + sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW g18<8,8,1>UD 0x0442030b + sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(8) g6<1>UW g18<8,8,1>UD 0x0442040c + sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g10<1>UW g18<8,8,1>UD 0x0442050d + sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) g14<1>UW g18<8,8,1>UD 0x0442060e + sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g18<1>UW g18<8,8,1>UD 0x0442070f + sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(16) g32<1>UW g22<8,8,1>UD 0x08840008 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g42<1>UW g22<8,8,1>UD 0x08840109 + sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(16) g60<1>UW g22<8,8,1>UD 0x0884020a + sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H }; +send(16) g70<1>UW g22<8,8,1>UD 0x0884030b + sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H }; +send(16) g78<1>UW g22<8,8,1>UD 0x0884040c + sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H }; +send(16) g86<1>UW g22<8,8,1>UD 0x0884050d + sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H }; +send(16) g94<1>UW g22<8,8,1>UD 0x0884060e + sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H }; +send(16) g52<1>UW g22<8,8,1>UD 0x0884070f + sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; +send(8) g16<1>UW g42<8,8,1>UD 0x04438101 + sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(8) g20<1>UW g42<8,8,1>UD 0x04438202 + sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(8) g29<1>UW g42<8,8,1>UD 0x04438404 + sampler MsgDesc: sample_lz SIMD8 Surface = 4 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g38<1>UW g42<8,8,1>UD 0x04438606 + sampler MsgDesc: sample_lz SIMD8 Surface = 6 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g124<1>UW g42<8,8,1>UD 0x04438707 + sampler MsgDesc: sample_lz SIMD8 Surface = 7 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g16<8,8,1>UD 0x044a0058 + urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0068 + urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0078 + urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0088 + urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0098 + urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00a8 + urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00b8 + urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00c8 + urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00d8 + urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00e8 + urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a00f8 + urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0108 + urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0118 + urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0158 + urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0168 + urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0178 + urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0188 + urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0198 + urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01a8 + urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01b8 + urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01c8 + urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01d8 + urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01e8 + urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a01f8 + urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g12<1>UD g2<8,8,1>UD 0x044a0208 + urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; +send(8) g14<1>UW g15<8,8,1>UD 0x0a125001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; +send(8) g15<1>UW g20<8,8,1>UD 0x0a125102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; +send(16) g41<1>UW g7<8,8,1>UD 0x14245001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; +send(16) g43<1>UW g17<8,8,1>UD 0x14245102 + sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; +send(8) g2<1>UW g5<8,8,1>UD 0x06223001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; +send(16) g2<1>UW g7<8,8,1>UD 0x0c443001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; +send(8) g2<1>UW g2<8,8,1>UD 0x06323001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; +send(16) g2<1>UW g24<8,8,1>UD 0x0c643001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; +send(8) null<1>F g120<8,8,1>F 0x8c0a0117 + urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380128 + urb MsgDesc: 18 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380138 + urb MsgDesc: 19 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380148 + urb MsgDesc: 20 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380158 + urb MsgDesc: 21 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380168 + urb MsgDesc: 22 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380178 + urb MsgDesc: 23 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380188 + urb MsgDesc: 24 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x02380198 + urb MsgDesc: 25 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801a8 + urb MsgDesc: 26 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801b8 + urb MsgDesc: 27 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801c8 + urb MsgDesc: 28 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801d8 + urb MsgDesc: 29 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801e8 + urb MsgDesc: 30 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g11<1>UD g1<8,8,1>UD 0x023801f8 + urb MsgDesc: 31 SIMD8 read mlen 1 rlen 3 { align1 1Q }; +send(8) g10<1>UW g2<8,8,1>UD 0x04420004 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g18<1>UW g2<8,8,1>UD 0x08840004 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g10<1>UW g2<8,8,1>UD 0x04420003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g18<1>UW g2<8,8,1>UD 0x08840003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g11<1>UD g13<8,8,1>UD 0x042a0058 + urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0068 + urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0078 + urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0088 + urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0098 + urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00a8 + urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00b8 + urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00c8 + urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00d8 + urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00e8 + urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a00f8 + urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0108 + urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g11<8,8,1>UD 0x042a0118 + urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0158 + urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0168 + urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0178 + urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0188 + urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0198 + urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01a8 + urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01b8 + urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01c8 + urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01d8 + urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01e8 + urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a01f8 + urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g2<1>UD g3<8,8,1>UD 0x042a0208 + urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; +send(8) g9<1>UW g15<8,8,1>UD 0x021ab102 + sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; +send(8) g10<1>UW g16<8,8,1>UD 0x021ab203 + sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 1 { align1 1Q }; +send(8) g11<1>UW g17<8,8,1>UD 0x021ab304 + sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 1 { align1 1Q }; +send(8) g12<1>UW g18<8,8,1>UD 0x021ab405 + sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 1 { align1 1Q }; +send(8) g13<1>UW g19<8,8,1>UD 0x021ab506 + sampler MsgDesc: sampleinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 1 { align1 1Q }; +send(16) g14<1>UW g16<8,8,1>UD 0x022cb102 + sampler MsgDesc: sampleinfo SIMD16 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1H }; +send(16) g16<1>UW g18<8,8,1>UD 0x022cb203 + sampler MsgDesc: sampleinfo SIMD16 Surface = 3 Sampler = 2 mlen 1 rlen 2 { align1 1H }; +send(16) g18<1>UW g20<8,8,1>UD 0x022cb304 + sampler MsgDesc: sampleinfo SIMD16 Surface = 4 Sampler = 3 mlen 1 rlen 2 { align1 1H }; +send(16) g20<1>UW g22<8,8,1>UD 0x022cb405 + sampler MsgDesc: sampleinfo SIMD16 Surface = 5 Sampler = 4 mlen 1 rlen 2 { align1 1H }; +send(16) g22<1>UW g24<8,8,1>UD 0x022cb506 + sampler MsgDesc: sampleinfo SIMD16 Surface = 6 Sampler = 5 mlen 1 rlen 2 { align1 1H }; +send(8) g14<1>UW g11<8,8,1>UD 0x0a4b0203 + sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; +send(8) g18<1>UW g18<8,8,1>UD 0x0c4b0304 + sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 3 mlen 6 rlen 4 { align1 1Q }; +send(8) g22<1>UW g24<8,8,1>UD 0x084b0405 + sampler MsgDesc: gather4_c SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; +send(16) g18<1>UW g26<8,8,1>UD 0x128d0203 + sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 9 rlen 8 { align1 1H }; +send(16) g26<1>UW g35<8,8,1>UD 0x168d0304 + sampler MsgDesc: gather4_c SIMD16 Surface = 4 Sampler = 3 mlen 11 rlen 8 { align1 1H }; +send(16) g34<1>UW g46<8,8,1>UD 0x0e8d0405 + sampler MsgDesc: gather4_c SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H }; +send(8) g124<1>UW g9<8,8,1>UD 0x0c4b0000 + sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; diff --git a/src/intel/tools/tests/gen9/send.expected b/src/intel/tools/tests/gen9/send.expected new file mode 100644 index 00000000000..9ed63c758f3 --- /dev/null +++ b/src/intel/tools/tests/gen9/send.expected @@ -0,0 +1,1803 @@ +31 00 60 06 e0 3a 00 20 60 0f 8d 06 17 00 08 8a +31 00 60 06 e0 3a 00 20 a0 01 8d 06 07 00 08 12 +31 00 60 06 e0 3a 00 20 60 0f 8d 06 27 00 08 8a +31 00 80 09 0c 02 20 21 40 00 00 06 00 03 28 02 +31 00 60 06 e0 3a 00 20 e0 0e 8d 06 17 00 08 92 +31 00 80 07 44 12 00 20 e0 0f 8d 06 10 00 00 82 +31 00 60 02 48 02 80 2f a0 01 8d 06 01 a0 43 06 +31 00 80 02 48 02 00 2f e0 02 8d 06 01 a0 85 0c +31 00 60 06 08 02 40 21 40 00 8d 06 28 00 48 02 +31 00 60 06 e0 3a 00 20 00 01 8d 06 17 00 0a 14 +31 00 60 06 e0 3a 00 20 c0 0e 8d 06 17 00 0a 94 +31 00 60 02 48 02 40 20 40 01 8d 06 01 70 42 08 +31 00 80 02 48 02 40 20 40 02 8d 06 01 70 84 10 +31 00 60 06 e0 02 00 20 60 01 8d 06 37 00 0a 0c +31 00 60 06 e0 02 00 20 c0 00 8d 06 27 00 08 0a +31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0c +31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0a +31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 08 +31 00 60 06 e0 02 00 20 40 00 8d 06 17 80 08 06 +31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0c +31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0a +31 00 60 06 e0 02 00 20 a0 0f 8d 06 07 80 08 86 +31 00 60 02 48 02 e0 20 e0 00 8d 06 00 a0 43 04 +31 00 60 02 48 02 40 21 c0 00 8d 06 01 a0 22 02 +31 00 60 02 48 02 40 20 60 02 8d 06 01 80 4a 08 +31 00 80 02 48 02 20 23 00 02 8d 06 01 a0 44 04 +31 00 80 02 48 02 c0 21 e0 00 8d 06 01 80 8c 0e +31 00 60 06 e0 3a 00 20 60 01 8d 06 17 00 08 12 +31 00 60 06 e0 3a 00 20 80 02 8d 06 37 00 08 12 +31 00 60 06 e0 3a 00 20 60 0f 8d 06 57 00 08 8a +31 00 60 02 48 02 20 21 c0 00 8d 06 01 d0 13 06 +31 00 80 02 48 02 80 21 c0 01 8d 06 01 d0 25 0c +31 00 60 02 48 02 40 20 c0 01 8d 06 01 d0 43 06 +31 00 60 02 48 02 00 21 20 02 8d 06 01 e0 43 0a +31 00 80 02 48 02 40 23 40 01 8d 06 01 d0 85 0c +31 00 80 02 48 02 40 24 00 02 8d 06 01 e0 85 14 +31 00 60 02 48 02 a0 20 40 00 8d 06 01 00 32 04 +31 00 80 02 48 02 e0 20 40 00 8d 06 01 00 64 08 +31 00 60 02 48 02 80 21 40 01 8d 06 01 e0 33 0a +31 00 80 02 48 02 40 20 40 02 8d 06 01 e0 65 14 +31 00 60 02 48 02 a0 20 40 00 8d 06 01 00 42 04 +31 00 80 02 48 02 e0 20 40 00 8d 06 01 00 84 08 +31 00 60 02 48 02 60 21 20 01 8d 06 00 a0 22 02 +31 00 60 02 48 02 80 2f a0 01 8d 06 00 80 4a 06 +31 00 60 02 48 02 80 21 a0 00 8d 06 00 70 42 02 +31 00 60 06 e0 3a 00 20 60 0f 8d 06 37 00 08 8a +31 00 60 02 48 02 c0 20 60 01 8d 06 01 40 4a 14 +31 00 61 0c 4a 02 a0 2f 60 00 8d 06 01 b5 10 02 +31 00 81 0c 4a 02 40 2f 80 00 8d 06 01 a5 20 04 +31 00 60 02 48 02 c0 20 80 01 8d 06 01 40 4a 08 +31 00 60 02 48 02 40 2c 20 02 8d 06 01 c0 43 0c +31 00 60 02 48 02 80 2f 00 01 8d 06 01 80 4a 06 +31 00 80 02 48 02 00 2f 80 01 8d 06 01 80 8c 0a +31 00 60 02 48 02 c0 20 e0 00 8d 06 01 60 1a 0a +31 00 60 02 48 02 e0 20 80 01 8d 06 02 61 1a 0a +31 00 80 02 48 02 40 21 80 01 8d 06 01 60 2c 12 +31 00 80 02 48 02 80 21 a0 02 8d 06 02 61 2c 12 +31 00 60 02 48 02 80 2f 60 00 8d 06 00 e0 43 0a +31 00 60 06 e0 3a 00 20 e0 0e 8d 06 27 00 08 92 +31 00 60 02 48 02 40 20 60 00 8d 06 00 d0 43 06 +31 00 60 06 e0 02 00 20 e0 00 8d 06 37 00 08 0a +31 00 60 06 e0 02 00 20 00 01 8d 06 47 00 08 0a +31 00 60 06 e0 3a 00 20 a0 03 8d 06 17 00 0a 0c +31 00 60 06 e0 3a 00 20 40 0f 8d 06 17 00 0a 8c +31 00 60 02 48 02 a0 21 40 01 8d 06 01 00 32 02 +31 00 80 02 48 02 c0 22 40 02 8d 06 01 00 64 04 +31 00 60 02 48 02 80 2f 40 00 8d 06 00 a0 32 02 +31 00 60 02 48 02 40 20 a0 01 8d 06 01 10 4b 0c +31 00 80 02 48 02 40 22 e0 00 8d 06 01 10 8d 16 +31 00 60 06 e0 02 00 20 c0 00 8d 06 27 80 08 0a +31 00 60 06 e0 02 00 20 e0 00 8d 06 37 80 08 0a +31 00 60 06 e0 02 00 20 00 01 8d 06 47 80 08 0a +31 00 60 06 e0 02 00 20 20 01 8d 06 57 80 08 0a +31 00 60 02 48 02 80 2f 60 00 8d 06 00 70 42 06 +31 00 60 02 48 02 40 20 40 01 8d 06 01 70 42 06 +31 00 80 02 48 02 40 20 40 02 8d 06 01 70 84 0c +31 00 60 02 48 02 c0 20 40 01 8d 06 01 40 42 0c +31 00 60 02 48 02 40 20 e0 00 8d 06 00 10 4b 0c +31 00 60 02 48 02 40 20 80 00 8d 06 00 a0 42 02 +31 00 60 02 48 02 c0 20 c0 00 8d 06 01 a1 42 02 +31 00 60 02 48 02 40 21 40 01 8d 06 02 a2 42 02 +31 00 60 02 48 02 c0 21 c0 01 8d 06 03 a3 42 02 +31 00 60 02 48 02 40 22 40 02 8d 06 04 a4 42 02 +31 00 60 02 48 02 c0 22 c0 02 8d 06 05 a5 42 02 +31 00 60 02 48 02 40 23 40 03 8d 06 06 a6 42 02 +31 00 60 06 08 02 c0 20 e0 01 8d 06 18 03 2a 04 +31 00 60 06 08 02 00 21 e0 01 8d 06 18 05 2a 04 +31 00 60 06 08 02 40 21 e0 01 8d 06 18 07 2a 04 +31 00 60 06 08 02 80 21 e0 01 8d 06 18 09 2a 04 +31 00 60 06 08 02 c0 21 e0 01 8d 06 28 01 2a 04 +31 00 60 06 08 02 00 22 c0 01 8d 06 18 02 2a 04 +31 00 60 06 08 02 40 22 c0 01 8d 06 18 04 2a 04 +31 00 60 06 08 02 80 22 c0 01 8d 06 18 06 2a 04 +31 00 60 06 08 02 c0 22 c0 01 8d 06 18 08 2a 04 +31 00 60 06 08 02 a0 21 c0 01 8d 06 28 00 2a 04 +31 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8d 06 88 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 98 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 a8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 b8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 c8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 d8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 e8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 f8 00 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 08 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 18 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 38 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 48 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 58 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 68 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 78 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 88 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 98 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 a8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 b8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 c8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 d8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 e8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 f8 01 3a 04 +31 00 60 06 08 02 40 20 40 00 8d 06 08 02 3a 04 +31 00 60 06 e0 3a 00 20 60 01 8d 06 47 00 0a 14 +31 00 60 06 e0 3a 00 20 e0 03 8d 06 87 00 0a 14 +31 00 60 06 e0 3a 00 20 c0 0e 8d 06 87 00 0a 94 +31 00 60 02 48 02 c0 21 60 01 8d 06 02 02 4b 0a +31 00 60 02 48 02 40 22 40 02 8d 06 03 03 4b 0c +31 00 60 02 48 02 c0 22 00 03 8d 06 04 04 4b 08 +31 00 60 02 48 02 e0 21 40 00 8d 06 03 32 42 06 +31 00 80 02 48 02 60 22 60 03 8d 06 03 32 84 0c +31 00 60 02 48 02 e0 20 20 01 8d 06 01 c0 13 0a +31 00 80 02 48 02 80 22 e0 00 8d 06 01 c0 25 14 +31 00 60 02 48 02 a0 22 a0 00 8d 06 01 c0 33 0a +31 00 60 02 48 02 40 22 00 03 8d 06 01 c0 23 0a +31 00 80 02 48 02 e0 21 a0 02 8d 06 01 c0 65 14 +31 00 80 02 48 02 e0 20 e0 03 8d 06 01 c0 45 14 +31 00 60 02 48 02 80 2f c0 00 8d 06 03 83 43 04 +31 00 60 06 08 02 60 21 20 02 8d 06 38 03 3a 04 +31 00 60 06 08 02 c0 21 20 02 8d 06 38 05 3a 04 +31 00 60 06 08 02 20 22 20 02 8d 06 38 07 3a 04 +31 00 60 06 08 02 20 21 40 02 8d 06 38 00 3a 04 +31 00 60 06 08 02 80 21 40 02 8d 06 38 02 3a 04 +31 00 60 06 08 02 e0 21 40 02 8d 06 38 04 3a 04 +31 00 60 06 08 02 40 22 40 02 8d 06 38 06 3a 04 +31 00 60 02 48 02 c0 20 40 01 8d 06 01 40 42 08 +31 00 60 02 48 02 20 21 a0 00 8d 06 02 00 42 04 +31 00 80 02 48 02 a0 21 e0 00 8d 06 02 00 84 08 +31 00 61 0c 4a 02 80 2f 40 00 8d 06 01 a5 11 02 +31 10 61 0c 4a 02 20 2f 60 00 8d 06 01 b5 11 02 +31 00 60 06 08 02 c0 22 00 04 8d 06 38 02 28 02 +31 00 60 06 08 02 00 23 00 04 8d 06 38 04 28 02 +31 00 60 06 08 02 40 23 00 04 8d 06 38 06 28 02 +31 00 60 06 08 02 80 23 00 04 8d 06 48 02 28 02 +31 00 60 06 08 02 c0 23 00 04 8d 06 48 04 28 02 +31 00 60 06 08 02 00 24 00 04 8d 06 48 06 28 02 +31 00 60 06 08 02 c0 22 20 04 8d 06 58 02 28 02 +31 00 60 06 08 02 00 23 20 04 8d 06 58 04 28 02 +31 00 60 06 08 02 40 23 20 04 8d 06 58 06 28 02 +31 00 60 06 08 02 c0 22 40 04 8d 06 68 02 28 02 +31 00 60 06 08 02 00 23 40 04 8d 06 68 04 28 02 +31 00 60 06 08 02 40 23 40 04 8d 06 68 06 28 02 +31 00 60 06 08 02 00 23 60 04 8d 06 78 04 28 02 +31 00 60 06 08 02 c0 22 60 04 8d 06 78 02 28 02 +31 00 60 06 08 02 40 23 60 04 8d 06 78 06 28 02 +31 00 60 06 08 02 00 23 80 04 8d 06 88 06 28 02 +31 00 60 06 08 02 00 21 80 04 8d 06 88 02 28 02 +31 00 60 06 08 02 c0 22 80 04 8d 06 88 04 28 02 +31 00 60 06 08 02 00 21 a0 04 8d 06 98 02 28 02 +31 00 60 06 08 02 c0 22 a0 04 8d 06 98 04 28 02 +31 00 60 06 08 02 00 23 a0 04 8d 06 98 06 28 02 +31 00 60 06 08 02 00 21 c0 04 8d 06 a8 02 28 02 +31 00 60 06 08 02 c0 22 c0 04 8d 06 a8 04 28 02 +31 00 60 06 08 02 00 23 c0 04 8d 06 a8 06 28 02 +31 00 60 06 08 02 00 21 e0 04 8d 06 b8 02 28 02 +31 00 60 06 08 02 c0 22 e0 04 8d 06 b8 04 28 02 +31 00 60 06 08 02 00 23 e0 04 8d 06 b8 06 28 02 +31 00 60 06 08 02 00 21 00 05 8d 06 c8 02 28 02 +31 00 60 06 08 02 40 21 00 05 8d 06 c8 04 28 02 +31 00 60 06 08 02 c0 22 00 05 8d 06 c8 06 28 02 +31 00 60 06 08 02 00 21 20 05 8d 06 d8 02 28 02 +31 00 60 06 08 02 40 21 20 05 8d 06 d8 04 28 02 +31 00 60 06 08 02 c0 22 20 05 8d 06 d8 06 28 02 +31 00 60 06 08 02 00 21 40 05 8d 06 e8 02 28 02 +31 00 60 06 08 02 40 21 40 05 8d 06 e8 04 28 02 +31 00 60 06 08 02 c0 22 40 05 8d 06 e8 06 28 02 +31 00 60 06 08 02 00 21 60 05 8d 06 f8 02 28 02 +31 00 60 06 08 02 40 21 60 05 8d 06 f8 04 28 02 +31 00 60 06 08 02 c0 22 60 05 8d 06 f8 06 28 02 +31 00 60 06 08 02 00 21 80 05 8d 06 08 03 28 02 +31 00 60 06 08 02 40 21 80 05 8d 06 08 05 28 02 +31 00 60 06 08 02 80 21 80 05 8d 06 08 07 28 02 +31 00 60 06 08 02 00 21 a0 05 8d 06 18 03 28 02 +31 00 60 06 08 02 40 21 a0 05 8d 06 18 05 28 02 +31 00 60 06 08 02 80 21 a0 05 8d 06 18 07 28 02 +31 00 60 06 08 02 00 21 c0 05 8d 06 28 03 28 02 +31 00 60 06 08 02 40 21 c0 05 8d 06 28 05 28 02 +31 00 60 06 08 02 80 21 c0 05 8d 06 28 07 28 02 +31 00 60 06 08 02 00 21 e0 05 8d 06 38 03 28 02 +31 00 60 06 08 02 40 21 e0 05 8d 06 38 05 28 02 +31 00 60 06 08 02 80 21 e0 05 8d 06 38 07 28 02 +31 00 60 06 08 02 00 21 00 06 8d 06 48 03 28 02 +31 00 60 06 08 02 40 21 00 06 8d 06 48 05 28 02 +31 00 60 06 08 02 80 21 00 06 8d 06 48 07 28 02 +31 00 60 06 08 02 00 21 20 06 8d 06 58 03 28 02 +31 00 60 06 08 02 40 21 20 06 8d 06 58 05 28 02 +31 00 60 06 08 02 80 21 20 06 8d 06 58 07 28 02 +31 00 60 06 08 02 00 21 40 06 8d 06 68 03 28 02 +31 00 60 06 08 02 40 21 40 06 8d 06 68 05 28 02 +31 00 60 06 08 02 80 21 40 06 8d 06 68 07 28 02 +31 00 60 06 08 02 00 21 a0 06 8d 06 78 03 28 02 +31 00 60 06 08 02 40 21 a0 06 8d 06 78 05 28 02 +31 00 60 06 08 02 80 21 a0 06 8d 06 78 07 28 02 +31 00 60 06 08 02 00 21 c0 06 8d 06 88 03 28 02 +31 00 60 06 08 02 40 21 c0 06 8d 06 88 05 28 02 +31 00 60 06 08 02 80 21 c0 06 8d 06 88 07 28 02 +31 00 60 06 08 02 00 21 e0 06 8d 06 98 03 28 02 +31 00 60 06 08 02 40 21 e0 06 8d 06 98 05 28 02 +31 00 60 06 08 02 80 21 e0 06 8d 06 98 07 28 02 +31 00 60 06 08 02 00 21 00 07 8d 06 a8 03 28 02 +31 00 60 06 08 02 40 21 00 07 8d 06 a8 05 28 02 +31 00 60 06 08 02 80 21 00 07 8d 06 a8 07 28 02 +31 00 60 06 08 02 00 21 20 07 8d 06 b8 03 28 02 +31 00 60 06 08 02 40 21 20 07 8d 06 b8 05 28 02 +31 00 60 06 08 02 80 21 20 07 8d 06 b8 07 28 02 +31 00 60 06 08 02 00 21 40 07 8d 06 c8 03 28 02 +31 00 60 06 08 02 40 21 40 07 8d 06 c8 05 28 02 +31 00 60 06 08 02 80 21 40 07 8d 06 c8 07 28 02 +31 00 60 06 08 02 00 21 60 07 8d 06 d8 03 28 02 +31 00 60 06 08 02 40 21 60 07 8d 06 d8 05 28 02 +31 00 60 06 08 02 80 21 60 07 8d 06 d8 07 28 02 +31 00 60 06 08 02 00 21 80 07 8d 06 e8 03 28 02 +31 00 60 06 08 02 40 21 80 07 8d 06 e8 05 28 02 +31 00 60 06 08 02 80 21 80 07 8d 06 e8 07 28 02 +31 00 60 06 08 02 00 21 a0 07 8d 06 f8 03 28 02 +31 00 60 06 08 02 40 21 a0 07 8d 06 f8 05 28 02 +31 00 60 06 08 02 80 21 a0 07 8d 06 f8 07 28 02 +31 00 60 06 08 02 40 21 c0 07 8d 06 08 04 28 02 +31 00 60 06 08 02 80 21 c0 07 8d 06 08 06 28 02 +31 00 60 06 08 02 c0 21 c0 07 8d 06 08 08 28 02 +31 00 60 06 08 02 00 21 e0 07 8d 06 18 02 28 02 +31 00 60 06 08 02 40 21 e0 07 8d 06 18 04 28 02 +31 00 60 06 08 02 80 21 e0 07 8d 06 18 06 28 02 +31 00 60 06 08 02 c0 21 e0 07 8d 06 18 08 28 02 +31 00 60 02 48 02 a0 23 40 02 8d 06 08 00 42 04 +31 00 60 02 48 02 60 24 40 02 8d 06 09 01 42 04 +31 00 60 02 48 02 20 25 40 02 8d 06 0a 02 42 04 +31 00 60 02 48 02 40 20 40 02 8d 06 0b 03 42 04 +31 00 60 02 48 02 c0 20 40 02 8d 06 0c 04 42 04 +31 00 60 02 48 02 40 21 40 02 8d 06 0d 05 42 04 +31 00 60 02 48 02 c0 21 40 02 8d 06 0e 06 42 04 +31 00 60 02 48 02 40 22 40 02 8d 06 0f 07 42 04 +31 00 80 02 48 02 00 24 c0 02 8d 06 08 00 84 08 +31 00 80 02 48 02 40 25 c0 02 8d 06 09 01 84 08 +31 00 80 02 48 02 80 27 c0 02 8d 06 0a 02 84 08 +31 00 80 02 48 02 c0 28 c0 02 8d 06 0b 03 84 08 +31 00 80 02 48 02 c0 29 c0 02 8d 06 0c 04 84 08 +31 00 80 02 48 02 c0 2a c0 02 8d 06 0d 05 84 08 +31 00 80 02 48 02 c0 2b c0 02 8d 06 0e 06 84 08 +31 00 80 02 48 02 80 26 c0 02 8d 06 0f 07 84 08 +31 00 60 02 48 02 00 22 40 05 8d 06 01 81 43 04 +31 00 60 02 48 02 80 22 40 05 8d 06 02 82 43 04 +31 00 60 02 48 02 a0 23 40 05 8d 06 04 84 43 04 +31 00 60 02 48 02 c0 24 40 05 8d 06 06 86 43 04 +31 00 60 02 48 02 80 2f 40 05 8d 06 07 87 43 04 +31 00 60 06 08 02 80 21 00 02 8d 06 58 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 68 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 78 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 88 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 98 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 a8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 b8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 c8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 d8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 e8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 f8 00 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 08 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 18 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 58 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 68 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 78 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 88 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 98 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 a8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 b8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 c8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 d8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 e8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 f8 01 4a 04 +31 00 60 06 08 02 80 21 40 00 8d 06 08 02 4a 04 +31 00 60 02 48 02 c0 21 e0 01 8d 06 01 50 12 0a +31 00 60 02 48 02 e0 21 80 02 8d 06 02 51 12 0a +31 00 80 02 48 02 20 25 e0 00 8d 06 01 50 24 14 +31 00 80 02 48 02 60 25 20 02 8d 06 02 51 24 14 +31 00 60 02 48 02 40 20 a0 00 8d 06 01 30 22 06 +31 00 80 02 48 02 40 20 e0 00 8d 06 01 30 44 0c +31 00 60 02 48 02 40 20 40 00 8d 06 01 30 32 06 +31 00 80 02 48 02 40 20 00 03 8d 06 01 30 64 0c +31 00 60 06 e0 3a 00 20 00 0f 8d 06 17 01 0a 8c +31 00 60 06 08 02 60 21 20 00 8d 06 28 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 38 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 48 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 58 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 68 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 78 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 88 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 98 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 a8 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 b8 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 c8 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 d8 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 e8 01 38 02 +31 00 60 06 08 02 60 21 20 00 8d 06 f8 01 38 02 +31 00 60 02 48 02 40 21 40 00 8d 06 04 00 42 04 +31 00 80 02 48 02 40 22 40 00 8d 06 04 00 84 08 +31 00 60 02 48 02 40 21 40 00 8d 06 03 00 42 04 +31 00 80 02 48 02 40 22 40 00 8d 06 03 00 84 08 +31 00 60 06 08 02 60 21 a0 01 8d 06 58 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 68 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 78 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 88 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 98 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 a8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 b8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 c8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 d8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 e8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 f8 00 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 08 01 2a 04 +31 00 60 06 08 02 40 20 60 01 8d 06 18 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 58 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 68 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 78 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 88 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 98 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 a8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 b8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 c8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 d8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 e8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 f8 01 2a 04 +31 00 60 06 08 02 40 20 60 00 8d 06 08 02 2a 04 +31 00 60 02 48 02 20 21 e0 01 8d 06 02 b1 1a 02 +31 00 60 02 48 02 40 21 00 02 8d 06 03 b2 1a 02 +31 00 60 02 48 02 60 21 20 02 8d 06 04 b3 1a 02 +31 00 60 02 48 02 80 21 40 02 8d 06 05 b4 1a 02 +31 00 60 02 48 02 a0 21 60 02 8d 06 06 b5 1a 02 +31 00 80 02 48 02 c0 21 00 02 8d 06 02 b1 2c 02 +31 00 80 02 48 02 00 22 40 02 8d 06 03 b2 2c 02 +31 00 80 02 48 02 40 22 80 02 8d 06 04 b3 2c 02 +31 00 80 02 48 02 80 22 c0 02 8d 06 05 b4 2c 02 +31 00 80 02 48 02 c0 22 00 03 8d 06 06 b5 2c 02 +31 00 60 02 48 02 c0 21 60 01 8d 06 03 02 4b 0a +31 00 60 02 48 02 40 22 40 02 8d 06 04 03 4b 0c +31 00 60 02 48 02 c0 22 00 03 8d 06 05 04 4b 08 +31 00 80 02 48 02 40 22 40 03 8d 06 03 02 8d 12 +31 00 80 02 48 02 40 23 60 04 8d 06 04 03 8d 16 +31 00 80 02 48 02 40 24 c0 05 8d 06 05 04 8d 0e +31 00 60 02 48 02 80 2f 20 01 8d 06 00 00 4b 0c diff --git a/src/intel/tools/tests/gen9/sendc.asm b/src/intel/tools/tests/gen9/sendc.asm new file mode 100644 index 00000000000..c340cb510a6 --- /dev/null +++ b/src/intel/tools/tests/gen9/sendc.asm @@ -0,0 +1,264 @@ +sendc(8) null<1>UW g124<0,1,0>F 0x88031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g120<0,1,0>F 0x90031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g114<0,1,0>F 0x82031100 + render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880ba001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0da001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a0001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; +(+f0.1) sendc(8) null<1>UW g124<0,1,0>F 0x88031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g122<8,8,1>UD 0x8c0be001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g117<8,8,1>UD 0x960de001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a0001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g118<8,8,1>UD 0x940a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g125<8,8,1>UD a0<0,1,0>UD 0x80000200 + sampler MsgDesc: indirect { align1 1Q EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g121<8,8,1>UD 0x8e0bc001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g121<8,8,1>UD 0x8e0a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a2001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c2001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g13<0,1,0>F 0x0e0b0401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g7<0,1,0>F 0x180b0001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H }; +sendc(16) null<1>UW g116<0,1,0>F 0x980b1002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a1001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c1001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(1) g2<1>UW g2<0,1,0>UW 0x0209c000 + data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0 { align1 WE_all 1N }; +sendc(8) null<1>UW g120<8,8,1>UD 0x900b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0b4001 + sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(8) g6<1>F g2<0,1,0>UD 0x044b4100 + render MsgDesc: RT read MsgCtrl = 0x1 Surface = 0 mlen 2 rlen 4 { align1 1Q }; +sendc(16) g9<1>F g27<0,1,0>UD 0x048b4000 + render MsgDesc: RT read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 8 { align1 1H }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a3001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<0,1,0>F 0x8a031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x94031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0402 + render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0403 + render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0404 + render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1405 + render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g5<0,1,0>F 0x140b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<0,1,0>F 0x140b0001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<0,1,0>F 0x140b0002 + render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<0,1,0>F 0x140b0003 + render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<0,1,0>F 0x140b0004 + render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1005 + render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) g6<1>F g6<0,1,0>UD 0x044b4101 + render MsgDesc: RT read MsgCtrl = 0x1 Surface = 1 mlen 2 rlen 4 { align1 1Q }; +sendc(8) g10<1>F g10<0,1,0>UD 0x044b4102 + render MsgDesc: RT read MsgCtrl = 0x1 Surface = 2 mlen 2 rlen 4 { align1 1Q }; +sendc(8) g14<1>F g14<0,1,0>UD 0x044b4103 + render MsgDesc: RT read MsgCtrl = 0x1 Surface = 3 mlen 2 rlen 4 { align1 1Q }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1403 + render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) g32<1>F g14<0,1,0>UD 0x048b4001 + render MsgDesc: RT read MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 8 { align1 1H }; +sendc(16) g40<1>F g16<0,1,0>UD 0x048b4002 + render MsgDesc: RT read MsgCtrl = 0x0 Surface = 2 mlen 2 rlen 8 { align1 1H }; +sendc(16) g48<1>F g18<0,1,0>UD 0x048b4003 + render MsgDesc: RT read MsgCtrl = 0x0 Surface = 3 mlen 2 rlen 8 { align1 1H }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1003 + render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a1001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c1001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860ba001 + sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0da001 + sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g126<8,8,1>UD 0x840a0001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g125<8,8,1>UD 0x860c0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a2001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c2001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0be001 + sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920de001 + sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g120<8,8,1>UD 0x900a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a2001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c2001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a0304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a1001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g117<8,8,1>UD 0x960c1001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a3001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a6001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c6001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a5001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c5001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a2001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g117<8,8,1>UD 0x960c2001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>UD 0x8c0bc001 + sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g117<8,8,1>UD 0x960dc001 + sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a7001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c7001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g118<0,1,0>F 0x940b1200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g3<0,1,0>F 0x140b1200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g118<0,1,0>F 0x940b1300 + render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a0001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(16) g11<1>F g37<0,1,0>UD 0x048b6000 + render MsgDesc: RT read MsgCtrl = 0x32 Surface = 0 mlen 2 rlen 8 { align1 1H }; +sendc(8) null<1>UW g23<0,1,0>F 0x0c0b0405 + render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g29<0,1,0>F 0x0c0b0406 + render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1407 + render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g57<0,1,0>F 0x140b0005 + render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g67<0,1,0>F 0x140b0006 + render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1007 + render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a1001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c1001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g10<0,1,0>F 0x0e0b0400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g2<0,1,0>F 0x160b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H }; +sendc(16) null<1>UW g117<0,1,0>F 0x960b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1404 + render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1004 + render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1406 + render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<0,1,0>F 0x940b1006 + render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g119<0,1,0>F 0x92031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g116<0,1,0>F 0x980b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a6001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c6001 + sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a0102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g124<8,8,1>UD 0x880a5001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c5001 + sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a4001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a3001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g119<8,8,1>UD 0x920c3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a0f10 + sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0f10 + sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g126<8,8,1>UD 0x840a0102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g125<8,8,1>UD 0x860c0102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g11<0,1,0>F 0x180b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H }; +sendc(8) null<1>UW g122<0,1,0>F 0x8c031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860a0506 + sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0506 + sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g125<8,8,1>UD 0x860b8001 + sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g123<8,8,1>UD 0x8a0d8001 + sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; diff --git a/src/intel/tools/tests/gen9/sendc.expected b/src/intel/tools/tests/gen9/sendc.expected new file mode 100644 index 00000000000..b4c30df0df2 --- /dev/null +++ b/src/intel/tools/tests/gen9/sendc.expected @@ -0,0 +1,132 @@ +32 00 60 05 40 3a 00 20 80 0f 00 06 00 14 03 88 +32 00 80 05 40 3a 00 20 00 0f 00 06 00 10 03 90 +32 00 80 05 40 3a 00 20 40 0e 00 06 00 11 03 82 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 a0 0b 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 a0 0d 8e +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 00 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 00 0c 8a +32 00 61 05 41 3a 00 20 80 0f 00 06 00 14 03 88 +32 00 60 02 40 02 00 20 40 0f 8d 06 01 e0 0b 8c +32 00 80 02 40 02 00 20 a0 0e 8d 06 01 e0 0d 96 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 00 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 00 0c 8e +32 00 60 02 40 02 00 20 c0 0e 8d 06 01 40 0a 94 +32 00 60 02 40 02 00 20 a0 0f 8d 00 00 02 00 80 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 40 0a 88 +32 00 60 02 40 02 00 20 20 0f 8d 06 01 c0 0b 8e +32 00 60 02 40 02 00 20 20 0f 8d 06 01 40 0a 8e +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 20 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 20 0c 8a +32 00 60 05 40 3a 00 20 40 0f 00 06 01 14 0b 8c +32 00 80 05 40 3a 00 20 c0 0e 00 06 01 10 0b 94 +32 00 60 05 40 3a 00 20 a0 01 00 06 01 04 0b 0e +32 00 60 05 40 3a 00 20 20 0f 00 06 02 14 0b 8e +32 00 80 05 40 3a 00 20 e0 00 00 06 01 00 0b 18 +32 00 80 05 40 3a 00 20 80 0e 00 06 02 10 0b 98 +32 00 60 02 40 02 00 20 60 0f 8d 06 01 10 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 10 0c 92 +32 00 00 0a 4c 12 40 20 40 00 00 06 00 c0 09 02 +32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0b 90 +32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0b 8a +32 00 60 05 e8 02 c0 20 40 00 00 06 00 41 4b 04 +32 00 80 05 e8 02 20 21 60 03 00 06 00 40 8b 04 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 30 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 30 0c 8e +32 00 60 05 40 3a 00 20 60 0f 00 06 00 14 03 8a +32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 03 94 +32 00 60 05 40 3a 00 20 a0 00 00 06 00 04 0b 0c +32 00 60 05 40 3a 00 20 a0 00 00 06 01 04 0b 0c +32 00 60 05 40 3a 00 20 a0 00 00 06 02 04 0b 0c +32 00 60 05 40 3a 00 20 a0 00 00 06 03 04 0b 0c +32 00 60 05 40 3a 00 20 a0 00 00 06 04 04 0b 0c +32 00 60 05 40 3a 00 20 40 0f 00 06 05 14 0b 8c +32 00 80 05 40 3a 00 20 a0 00 00 06 00 00 0b 14 +32 00 80 05 40 3a 00 20 a0 00 00 06 01 00 0b 14 +32 00 80 05 40 3a 00 20 a0 00 00 06 02 00 0b 14 +32 00 80 05 40 3a 00 20 a0 00 00 06 03 00 0b 14 +32 00 80 05 40 3a 00 20 a0 00 00 06 04 00 0b 14 +32 00 80 05 40 3a 00 20 c0 0e 00 06 05 10 0b 94 +32 00 60 05 e8 02 c0 20 c0 00 00 06 01 41 4b 04 +32 00 60 05 e8 02 40 21 40 01 00 06 02 41 4b 04 +32 00 60 05 e8 02 c0 21 c0 01 00 06 03 41 4b 04 +32 00 60 05 40 3a 00 20 40 0f 00 06 03 14 0b 8c +32 00 80 05 e8 02 00 24 c0 01 00 06 01 40 8b 04 +32 00 80 05 e8 02 00 25 00 02 00 06 02 40 8b 04 +32 00 80 05 e8 02 00 26 40 02 00 06 03 40 8b 04 +32 00 80 05 40 3a 00 20 c0 0e 00 06 03 10 0b 94 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 10 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 10 0c 8e +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 a0 0b 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 a0 0d 8a +32 00 60 02 40 02 00 20 c0 0f 8d 06 01 00 0a 84 +32 00 80 02 40 02 00 20 a0 0f 8d 06 01 00 0c 86 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 20 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 20 0c 8e +32 00 60 02 40 02 00 20 60 0f 8d 06 01 e0 0b 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 e0 0d 92 +32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0a 90 +32 00 60 02 40 02 00 20 60 0f 8d 06 01 20 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 20 0c 92 +32 00 60 02 40 02 00 20 a0 0f 8d 06 04 03 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 04 03 0c 8a +32 00 60 02 40 02 00 20 40 0f 8d 06 01 10 0a 8c +32 00 80 02 40 02 00 20 a0 0e 8d 06 01 10 0c 96 +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 30 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 30 0c 8a +32 00 60 05 40 3a 00 20 40 0f 00 06 02 14 0b 8c +32 00 80 05 40 3a 00 20 c0 0e 00 06 02 10 0b 94 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 60 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 60 0c 8e +32 00 60 02 40 02 00 20 60 0f 8d 06 01 50 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 50 0c 92 +32 00 60 02 40 02 00 20 40 0f 8d 06 01 20 0a 8c +32 00 80 02 40 02 00 20 a0 0e 8d 06 01 20 0c 96 +32 00 60 02 40 02 00 20 40 0f 8d 06 01 c0 0b 8c +32 00 80 02 40 02 00 20 a0 0e 8d 06 01 c0 0d 96 +32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 0b 8c +32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 0b 94 +32 00 60 02 40 02 00 20 80 0f 8d 06 01 70 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 70 0c 8e +32 00 60 05 40 3a 00 20 c0 0e 00 06 00 12 0b 94 +32 00 60 05 40 3a 00 20 60 00 00 06 00 12 0b 14 +32 10 60 05 40 3a 00 20 c0 0e 00 06 00 13 0b 94 +32 00 60 02 40 02 00 20 60 0f 8d 06 01 00 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 00 0c 92 +32 00 80 05 e8 02 60 21 a0 04 00 06 00 60 8b 04 +32 00 60 05 40 3a 00 20 e0 02 00 06 05 04 0b 0c +32 00 60 05 40 3a 00 20 a0 03 00 06 06 04 0b 0c +32 00 60 05 40 3a 00 20 40 0f 00 06 07 14 0b 8c +32 00 80 05 40 3a 00 20 20 07 00 06 05 00 0b 14 +32 00 80 05 40 3a 00 20 60 08 00 06 06 00 0b 14 +32 00 80 05 40 3a 00 20 c0 0e 00 06 07 10 0b 94 +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 10 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 10 0c 8a +32 00 60 05 40 3a 00 20 40 01 00 06 00 04 0b 0e +32 00 60 05 40 3a 00 20 20 0f 00 06 01 14 0b 8e +32 00 80 05 40 3a 00 20 40 00 00 06 00 00 0b 16 +32 00 80 05 40 3a 00 20 a0 0e 00 06 01 10 0b 96 +32 00 60 05 40 3a 00 20 40 0f 00 06 04 14 0b 8c +32 00 80 05 40 3a 00 20 c0 0e 00 06 04 10 0b 94 +32 00 60 05 40 3a 00 20 40 0f 00 06 06 14 0b 8c +32 00 80 05 40 3a 00 20 c0 0e 00 06 06 10 0b 94 +32 00 80 05 40 3a 00 20 e0 0e 00 06 00 10 03 92 +32 00 80 05 40 3a 00 20 80 0e 00 06 01 10 0b 98 +32 00 60 02 40 02 00 20 60 0f 8d 06 01 60 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 60 0c 92 +32 00 60 02 40 02 00 20 a0 0f 8d 06 02 01 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 02 01 0c 8a +32 00 60 02 40 02 00 20 80 0f 8d 06 01 50 0a 88 +32 00 80 02 40 02 00 20 20 0f 8d 06 01 50 0c 8e +32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0a 8a +32 00 60 02 40 02 00 20 60 0f 8d 06 01 30 0a 8a +32 00 80 02 40 02 00 20 e0 0e 8d 06 01 30 0c 92 +32 00 60 02 40 02 00 20 a0 0f 8d 06 10 0f 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 10 0f 0c 8a +32 00 60 02 40 02 00 20 c0 0f 8d 06 02 01 0a 84 +32 00 80 02 40 02 00 20 a0 0f 8d 06 02 01 0c 86 +32 00 80 05 40 3a 00 20 60 01 00 06 00 00 0b 18 +32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 03 8c +32 00 60 02 40 02 00 20 a0 0f 8d 06 06 05 0a 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 06 05 0c 8a +32 00 60 02 40 02 00 20 a0 0f 8d 06 01 80 0b 86 +32 00 80 02 40 02 00 20 60 0f 8d 06 01 80 0d 8a diff --git a/src/intel/tools/tests/gen9/sends.asm b/src/intel/tools/tests/gen9/sends.asm new file mode 100644 index 00000000000..b803f4fce40 --- /dev/null +++ b/src/intel/tools/tests/gen9/sends.asm @@ -0,0 +1,268 @@ +sends(8) nullUD g34UD g36UD 0x04035001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; +sends(8) nullUD g1UD g3UD 0x04036001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; +sends(8) nullUD g21UD g23UD 0x04035001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) g9UD g2UD g3UD 0x0210b201 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(16) g11UD g2UD g6UD 0x0420a201 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +sends(16) nullUD g6UD g8UD 0x04025efe 0x00000080 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g10UD g12UD 0x040087fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(8) nullUD g11UD g5UD 0x04035002 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g11UD 0x04036002 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g3UD g4UD 0x02026001 0x00000100 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g3UD g5UD 0x04025001 0x00000200 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 8 rlen 0 { align1 1H }; +sends(8) nullUD g2UD g3UD 0x02009b00 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, imin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04035e01 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g45UD g41UD 0x04036e01 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04018c01 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g45UD g41UD 0x04019c01 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04018401 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g45UD g41UD 0x04019401 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04018e01 0x00000080 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g11UD g13UD 0x04019e01 0x00000080 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 2Q }; +sends(16) nullUD g3UD g1UD 0x04008dfe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g5UD g1UD 0x04008bfe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g1UD 0x04008cfe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g5UD g1UD 0x04008afe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g1UD 0x040081fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g1UD 0x040082fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g1UD 0x040083fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g1UD 0x040084fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(16) nullUD g3UD g7UD 0x04008efe 0x00000100 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; +sends(16) g1UD g19UD g21UD 0x0420a4fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +sends(16) g13UD g23UD g25UD 0x0420a2fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +sends(8) nullUD g14UD g10UD 0x02026000 0x00000100 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +sends(8) nullUD g4UD g2UD 0x02026efe 0x00000040 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +sends(8) g7UD g19UD g20UD 0x0210bdfe 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g11UD g25UD g26UD 0x0210b4fe 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(16) g1UD g14UD g16UD 0x0420a7fe 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(8) nullUD g2UD g13UD g[a0]UD 0x00000100 + dp data 1 MsgDesc: indirect ex_mlen 4 { align1 1Q }; +(+f1.0) sends(8) nullUD g5UD g6UD 0x02026e01 0x00000040 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g5UD g6UD 0x02026e02 0x00000040 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g6UD g8UD 0x04025e01 0x00000080 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g6UD g8UD 0x04025e02 0x00000080 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(8) g3UD g8UD g9UD 0x0210b702 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(16) g4UD g11UD g13UD 0x0420a702 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(8) nullUD g5UD g3UD 0x02026c01 0x00000080 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g19UD g21UD 0x04025c01 0x00000100 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; +sends(8) nullUD g14UD g15UD 0x02026e00 0x00000040 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +sends(8) nullUD g16UD g9UD 0x02026c00 0x00000080 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g15UD g18UD 0x06035001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g34UD g11UD 0x06036001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) g13UD g18UD g19UD 0x0210bb02 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g16UD g25UD g30UD 0x0210b402 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(16) g22UD g27UD g29UD 0x0420ab02 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, imin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g25UD g37UD g2UD 0x0420a402 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +sends(16) nullUD g8UD g10UD 0x04025c02 0x00000100 + dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; +(+f1.0) sends(8) g127UD g2UD g9UD 0x0411a401 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g127UD g2UD g4UD 0x0411b401 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 1 { align1 2Q }; +(+f1.0) sends(8) nullUD g14UD g15UD 0x02009201 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g24UD g26UD 0x04008201 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(8) nullUD g124UD g11UD 0x04035000 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g5UD g6UD 0x02035e02 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g7UD g9UD 0x02036e02 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; +sends(8) nullUD g11UD g21UD 0x04035e00 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +sends(8) nullUD g15UD g27UD 0x04035e02 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +sends(8) nullUD g16UD g28UD 0x04036e02 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) g13UD g19UD g20UD 0x0210bd02 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(16) g22UD g28UD g30UD 0x0420ad02 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04035c02 0x00000080 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g38UD g40UD 0x04036c02 0x00000080 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 2Q }; +sends(8) nullUD g17UD g6UD 0x02035000 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211a700 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211ad00 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211ac00 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211a100 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211a200 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211a300 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g20UD g21UD 0x0211a400 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) g124UD g21UD g6UD 0x0211ae00 0x00000080 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q }; +(+f1.0) sends(8) nullUD g16UD g2UD 0x02035001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g29UD g8UD 0x02036001 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g14UD g18UD 0x02035e01 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g23UD g7UD 0x02036e01 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g17UD g2UD 0x02035002 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g28UD g3UD 0x02036002 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g17UD g2UD 0x02035003 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g23UD g6UD 0x02036003 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g12UD g13UD 0x02009701 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g20UD g22UD 0x04008701 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +sends(8) g7UD g18UD g19UD 0x0210bbfe 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +sends(8) nullUD g6UD g1UD 0x04035003 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; +sends(8) nullUD g8UD g10UD 0x04036003 0x00000100 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; +(+f1.0) sends(8) g3UD g21UD g20UD 0x0210b701 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g5UD g21UD g20UD 0x0210bd01 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g6UD g21UD g20UD 0x0210bc01 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g7UD g21UD g20UD 0x0210b101 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g9UD g21UD g20UD 0x0210b301 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g10UD g21UD g20UD 0x0210b401 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; +(+f1.0) sends(8) g11UD g21UD g11UD 0x0210be01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q }; +(+f1.0) sends(16) g3UD g38UD g36UD 0x0420a701 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g7UD g38UD g36UD 0x0420ad01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g9UD g38UD g36UD 0x0420ac01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g11UD g38UD g36UD 0x0420a101 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g15UD g38UD g36UD 0x0420a301 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g17UD g38UD g36UD 0x0420a401 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; +(+f1.0) sends(16) g19UD g38UD g21UD 0x0420ae01 0x00000100 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 2 { align1 1H }; +sends(8) nullUD g4UD g12UD 0x04035e09 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +sends(8) nullUD g5UD g13UD 0x04036e09 0x00000040 + dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g14UD g18UD 0x02009d01 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g17UD g19UD 0x02009c01 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g19UD g20UD 0x02009101 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g27UD g22UD 0x02009301 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g29UD g23UD 0x02009401 0x00000040 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g32UD g2UD 0x02009e01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; +(+f1.0) sends(16) nullUD g18UD g32UD 0x04008d01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g24UD g33UD 0x04008c01 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g30UD g34UD 0x04008101 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g46UD g36UD 0x04008301 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g49UD g37UD 0x04008401 0x00000080 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; +(+f1.0) sends(16) nullUD g56UD g2UD 0x04008e01 0x00000100 + dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; +(+f1.0) sends(8) nullUD g20UD g21UD 0x02018101 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g3UD g38UD 0x02019101 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g19UD g20UD 0x02018201 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g3UD g36UD 0x02019201 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g19UD g20UD 0x02018301 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g3UD g36UD 0x02019301 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g18UD 0x04018701 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04019701 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g18UD 0x04018d01 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04019d01 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g18UD 0x04018101 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04019101 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g18UD 0x04018201 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04019201 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; +(+f1.0) sends(8) nullUD g2UD g18UD 0x04018301 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; +(+f1.0) sends(8) nullUD g2UD g4UD 0x04019301 0x00000040 + dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; diff --git a/src/intel/tools/tests/gen9/sends.expected b/src/intel/tools/tests/gen9/sends.expected new file mode 100644 index 00000000000..ff7a1235086 --- /dev/null +++ b/src/intel/tools/tests/gen9/sends.expected @@ -0,0 +1,134 @@ +33 00 60 0c 10 40 02 00 44 04 00 00 01 50 03 04 +33 10 60 0c 10 30 00 00 24 00 00 00 01 60 03 04 +33 00 60 0c 10 70 01 00 a4 02 00 00 01 50 03 04 +33 00 61 0c 1a 30 20 01 41 00 00 00 01 b2 10 02 +33 00 81 0c 1a 60 60 01 42 00 00 00 01 a2 20 04 +33 00 80 0c 10 80 00 00 c2 00 00 00 fe 5e 02 04 +33 00 80 0c 10 c0 00 00 42 01 00 00 fe 87 00 04 +33 00 61 0c 12 50 00 00 64 01 00 00 02 50 03 04 +33 10 61 0c 12 b0 00 00 44 00 00 00 02 60 03 04 +33 00 61 0c 12 40 00 00 64 00 00 00 01 60 02 02 +33 00 81 0c 12 50 00 00 68 00 00 00 01 50 02 04 +33 00 60 0c 10 30 00 00 41 00 00 00 00 9b 00 02 +33 00 61 0c 12 40 00 00 41 00 00 00 01 5e 03 04 +33 10 61 0c 12 90 02 00 a1 05 00 00 01 6e 03 04 +33 00 61 0c 12 40 00 00 41 00 00 00 01 8c 01 04 +33 10 61 0c 12 90 02 00 a1 05 00 00 01 9c 01 04 +33 00 61 0c 12 40 00 00 41 00 00 00 01 84 01 04 +33 10 61 0c 12 90 02 00 a1 05 00 00 01 94 01 04 +33 00 61 0c 12 40 00 00 42 00 00 00 01 8e 01 04 +33 10 61 0c 12 d0 00 00 62 01 00 00 01 9e 01 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 8d 00 04 +33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8b 00 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 8c 00 04 +33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8a 00 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 81 00 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 82 00 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 83 00 04 +33 00 80 0c 10 10 00 00 62 00 00 00 fe 84 00 04 +33 00 80 0c 10 70 00 00 64 00 00 00 fe 8e 00 04 +33 00 80 0c 18 50 21 00 62 02 00 00 fe a4 20 04 +33 00 80 0c 18 90 a1 01 e2 02 00 00 fe a2 20 04 +33 00 60 0c 10 a0 00 00 c4 01 00 00 00 60 02 02 +33 00 60 0c 10 20 00 00 81 00 00 00 fe 6e 02 02 +33 00 60 0c 18 40 e1 00 61 02 00 00 fe bd 10 02 +33 00 60 0c 18 a0 61 01 21 03 00 00 fe b4 10 02 +33 00 80 0c 18 00 21 00 c2 01 00 00 fe a7 20 04 +33 00 61 0c 12 d0 00 00 44 20 00 00 00 00 00 00 +33 00 61 0c 12 60 00 00 a1 00 00 00 01 6e 02 02 +33 00 61 0c 12 60 00 00 a1 00 00 00 02 6e 02 02 +33 00 81 0c 12 80 00 00 c2 00 00 00 01 5e 02 04 +33 00 81 0c 12 80 00 00 c2 00 00 00 02 5e 02 04 +33 00 61 0c 1a 90 60 00 01 01 00 00 02 b7 10 02 +33 00 81 0c 1a d0 80 00 62 01 00 00 02 a7 20 04 +33 00 61 0c 12 30 00 00 a2 00 00 00 01 6c 02 02 +33 00 81 0c 12 50 01 00 64 02 00 00 01 5c 02 04 +33 00 60 0c 10 f0 00 00 c1 01 00 00 00 6e 02 02 +33 00 60 0c 10 90 00 00 02 02 00 00 00 6c 02 02 +33 00 61 0c 12 20 01 00 e4 01 00 00 01 50 03 06 +33 10 61 0c 12 b0 00 00 44 04 00 00 01 60 03 06 +33 00 61 0c 1a 30 a1 01 41 02 00 00 02 bb 10 02 +33 00 61 0c 1a e0 01 02 21 03 00 00 02 b4 10 02 +33 00 81 0c 1a d0 c1 02 62 03 00 00 02 ab 20 04 +33 00 81 0c 1a 20 20 03 a2 04 00 00 02 a4 20 04 +33 00 80 0c 10 a0 00 00 04 01 00 00 02 5c 02 04 +33 00 61 0c 1a 90 e0 0f 41 00 00 00 01 a4 11 04 +33 10 61 0c 1a 40 e0 0f 41 00 00 00 01 b4 11 04 +33 00 61 0c 12 f0 00 00 c1 01 00 00 01 92 00 02 +33 00 81 0c 12 a0 01 00 02 03 00 00 01 82 00 04 +33 00 60 0c 10 b0 00 00 84 0f 00 00 00 50 03 04 +33 00 61 0c 12 60 00 00 a1 00 00 00 02 5e 03 02 +33 10 61 0c 12 90 00 00 e1 00 00 00 02 6e 03 02 +33 00 60 0c 10 50 01 00 61 01 00 00 00 5e 03 04 +33 00 60 0c 10 b0 01 00 e1 01 00 00 02 5e 03 04 +33 10 60 0c 10 c0 01 00 01 02 00 00 02 6e 03 04 +33 00 61 0c 1a 40 a1 01 61 02 00 00 02 bd 10 02 +33 00 81 0c 1a e0 c1 02 82 03 00 00 02 ad 20 04 +33 00 61 0c 12 40 00 00 42 00 00 00 02 5c 03 04 +33 10 61 0c 12 80 02 00 c2 04 00 00 02 6c 03 04 +33 00 60 0c 10 60 00 00 24 02 00 00 00 50 03 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 a7 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 ad 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 ac 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 a1 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 a2 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 a3 11 02 +33 00 60 0c 18 50 81 0f 81 02 00 00 00 a4 11 02 +33 00 60 0c 18 60 80 0f a2 02 00 00 00 ae 11 02 +33 00 61 0c 12 20 00 00 04 02 00 00 01 50 03 02 +33 10 61 0c 12 80 00 00 a4 03 00 00 01 60 03 02 +33 00 61 0c 12 20 01 00 c1 01 00 00 01 5e 03 02 +33 10 61 0c 12 70 00 00 e1 02 00 00 01 6e 03 02 +33 00 61 0c 12 20 00 00 24 02 00 00 02 50 03 02 +33 10 61 0c 12 30 00 00 84 03 00 00 02 60 03 02 +33 00 61 0c 12 20 00 00 24 02 00 00 03 50 03 02 +33 10 61 0c 12 60 00 00 e4 02 00 00 03 60 03 02 +33 00 61 0c 12 d0 00 00 81 01 00 00 01 97 00 02 +33 00 81 0c 12 60 01 00 82 02 00 00 01 87 00 04 +33 00 60 0c 18 30 e1 00 41 02 00 00 fe bb 10 02 +33 00 60 0c 10 10 00 00 c4 00 00 00 03 50 03 04 +33 10 60 0c 10 a0 00 00 04 01 00 00 03 60 03 04 +33 00 61 0c 1a 40 61 00 a1 02 00 00 01 b7 10 02 +33 00 61 0c 1a 40 a1 00 a1 02 00 00 01 bd 10 02 +33 00 61 0c 1a 40 c1 00 a1 02 00 00 01 bc 10 02 +33 00 61 0c 1a 40 e1 00 a1 02 00 00 01 b1 10 02 +33 00 61 0c 1a 40 21 01 a1 02 00 00 01 b3 10 02 +33 00 61 0c 1a 40 41 01 a1 02 00 00 01 b4 10 02 +33 00 61 0c 1a b0 60 01 a2 02 00 00 01 be 10 02 +33 00 81 0c 1a 40 62 00 c2 04 00 00 01 a7 20 04 +33 00 81 0c 1a 40 e2 00 c2 04 00 00 01 ad 20 04 +33 00 81 0c 1a 40 22 01 c2 04 00 00 01 ac 20 04 +33 00 81 0c 1a 40 62 01 c2 04 00 00 01 a1 20 04 +33 00 81 0c 1a 40 e2 01 c2 04 00 00 01 a3 20 04 +33 00 81 0c 1a 40 22 02 c2 04 00 00 01 a4 20 04 +33 00 81 0c 1a 50 61 02 c4 04 00 00 01 ae 20 04 +33 00 60 0c 10 c0 00 00 81 00 00 00 09 5e 03 04 +33 10 60 0c 10 d0 00 00 a1 00 00 00 09 6e 03 04 +33 00 61 0c 12 20 01 00 c1 01 00 00 01 9d 00 02 +33 00 61 0c 12 30 01 00 21 02 00 00 01 9c 00 02 +33 00 61 0c 12 40 01 00 61 02 00 00 01 91 00 02 +33 00 61 0c 12 60 01 00 61 03 00 00 01 93 00 02 +33 00 61 0c 12 70 01 00 a1 03 00 00 01 94 00 02 +33 00 61 0c 12 20 00 00 02 04 00 00 01 9e 00 02 +33 00 81 0c 12 00 02 00 42 02 00 00 01 8d 00 04 +33 00 81 0c 12 10 02 00 02 03 00 00 01 8c 00 04 +33 00 81 0c 12 20 02 00 c2 03 00 00 01 81 00 04 +33 00 81 0c 12 40 02 00 c2 05 00 00 01 83 00 04 +33 00 81 0c 12 50 02 00 22 06 00 00 01 84 00 04 +33 00 81 0c 12 20 00 00 04 07 00 00 01 8e 00 04 +33 00 61 0c 12 50 01 00 81 02 00 00 01 81 01 02 +33 10 61 0c 12 60 02 00 61 00 00 00 01 91 01 02 +33 00 61 0c 12 40 01 00 61 02 00 00 01 82 01 02 +33 10 61 0c 12 40 02 00 61 00 00 00 01 92 01 02 +33 00 61 0c 12 40 01 00 61 02 00 00 01 83 01 02 +33 10 61 0c 12 40 02 00 61 00 00 00 01 93 01 02 +33 00 61 0c 12 20 01 00 41 00 00 00 01 87 01 04 +33 10 61 0c 12 40 00 00 41 00 00 00 01 97 01 04 +33 00 61 0c 12 20 01 00 41 00 00 00 01 8d 01 04 +33 10 61 0c 12 40 00 00 41 00 00 00 01 9d 01 04 +33 00 61 0c 12 20 01 00 41 00 00 00 01 81 01 04 +33 10 61 0c 12 40 00 00 41 00 00 00 01 91 01 04 +33 00 61 0c 12 20 01 00 41 00 00 00 01 82 01 04 +33 10 61 0c 12 40 00 00 41 00 00 00 01 92 01 04 +33 00 61 0c 12 20 01 00 41 00 00 00 01 83 01 04 +33 10 61 0c 12 40 00 00 41 00 00 00 01 93 01 04 diff --git a/src/intel/tools/tests/gen9/shl.asm b/src/intel/tools/tests/gen9/shl.asm new file mode 100644 index 00000000000..03484a216db --- /dev/null +++ b/src/intel/tools/tests/gen9/shl.asm @@ -0,0 +1,13 @@ +shl(16) g18<1>D g20<8,8,1>D 0x00000002UD { align1 1H }; +shl(8) g18<1>D g17<8,8,1>D 0x00000002UD { align1 1Q }; +shl(1) g8<1>UD g5<0,1,0>UD 0x00000008UD { align1 WE_all 1N }; +shl(8) g4<1>UD g6<8,8,1>UD g3<8,8,1>UD { align1 1Q }; +shl(1) a0<1>UD g43<0,1,0>UD 0x00000002UD { align1 WE_all 1N }; +shl(16) g116<1>D g1<0,1,0>D 0x00000005UD { align1 2H }; +shl(8) g26<1>UD g34<8,8,1>UW 0x00000002UD { align1 1Q }; +shl(8) g3<1>UD g23<8,8,1>UD g21<8,8,1>UD { align1 WE_all 1Q }; +shl(16) g10<1>UD g10<8,8,1>UD 0x00000010UD { align1 1H }; +shl(1) g14<1>UD g21<0,1,0>UD 0x00000008UD { align1 WE_all 3N }; +shl(8) g11<1>Q g5<4,4,1>Q g3<4,4,1>UD { align1 1Q }; +shl(1) a0<1>UD g13<0,1,0>D 0x00000002UD { align1 WE_all 1N }; +shl(8) g22<1>Q g8<4,4,1>Q g4<4,4,1>UD { align1 2Q }; diff --git a/src/intel/tools/tests/gen9/shl.expected b/src/intel/tools/tests/gen9/shl.expected new file mode 100644 index 00000000000..0b09a78762d --- /dev/null +++ b/src/intel/tools/tests/gen9/shl.expected @@ -0,0 +1,13 @@ +09 00 80 00 28 0a 40 22 80 02 8d 06 02 00 00 00 +09 00 60 00 28 0a 40 22 20 02 8d 06 02 00 00 00 +09 00 00 00 0c 02 00 21 a0 00 00 06 08 00 00 00 +09 00 60 00 08 02 80 20 c0 00 8d 02 60 00 8d 00 +09 00 00 00 04 02 00 22 60 05 00 06 02 00 00 00 +09 20 80 00 28 0a 80 2e 20 00 00 06 05 00 00 00 +09 00 60 00 08 12 40 23 40 04 8d 06 02 00 00 00 +09 00 60 00 0c 02 60 20 e0 02 8d 02 a0 02 8d 00 +09 00 80 00 08 02 40 21 40 01 8d 06 10 00 00 00 +09 10 00 00 0c 02 c0 21 a0 02 00 06 08 00 00 00 +09 00 60 00 28 4b 60 21 a0 00 69 02 60 00 69 00 +09 00 00 00 04 0a 00 22 a0 01 00 06 02 00 00 00 +09 10 60 00 28 4b c0 22 00 01 69 02 80 00 69 00 diff --git a/src/intel/tools/tests/gen9/shr.asm b/src/intel/tools/tests/gen9/shr.asm new file mode 100644 index 00000000000..f64c61767d2 --- /dev/null +++ b/src/intel/tools/tests/gen9/shr.asm @@ -0,0 +1,8 @@ +shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q }; +shr(16) g43<1>UD g41<8,8,1>UD 0x00000001UD { align1 1H }; +shr.z.f0.0(8) g3<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; +shr(16) g8<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; +shr.z.f0.0(8) null<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; +shr(8) g3<1>UW g1.28<1,8,0>UB 0x76543210V { align1 1Q }; +shr(8) g3<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q }; +shr(16) g20<2>UW g15<8,8,1>UD g13<8,8,1>UW { align1 1H }; diff --git a/src/intel/tools/tests/gen9/shr.expected b/src/intel/tools/tests/gen9/shr.expected new file mode 100644 index 00000000000..58830ed506a --- /dev/null +++ b/src/intel/tools/tests/gen9/shr.expected @@ -0,0 +1,8 @@ +08 00 60 00 08 02 80 22 60 02 8d 06 01 00 00 00 +08 00 80 00 08 02 60 25 20 05 8d 06 01 00 00 00 +08 00 60 01 08 02 60 20 20 00 8d 06 1b 00 00 00 +08 00 80 00 48 22 00 21 20 00 2c 36 00 00 44 44 +08 00 60 01 00 02 00 20 20 00 8d 06 1b 00 00 00 +08 00 60 00 48 22 60 20 3c 00 2c 36 10 32 54 76 +08 00 60 00 48 02 60 40 a0 00 8d 12 80 00 8d 00 +08 00 80 00 48 02 80 42 e0 01 8d 12 a0 01 8d 00 diff --git a/src/intel/tools/tests/gen9/wait.asm b/src/intel/tools/tests/gen9/wait.asm new file mode 100644 index 00000000000..8cb494e8f90 --- /dev/null +++ b/src/intel/tools/tests/gen9/wait.asm @@ -0,0 +1 @@ +wait(1) n0<0,1,0>UD { align1 WE_all 1N }; diff --git a/src/intel/tools/tests/gen9/wait.expected b/src/intel/tools/tests/gen9/wait.expected new file mode 100644 index 00000000000..81603b02af6 --- /dev/null +++ b/src/intel/tools/tests/gen9/wait.expected @@ -0,0 +1 @@ +30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00 diff --git a/src/intel/tools/tests/gen9/while.asm b/src/intel/tools/tests/gen9/while.asm new file mode 100644 index 00000000000..00bd8e1bff6 --- /dev/null +++ b/src/intel/tools/tests/gen9/while.asm @@ -0,0 +1,4 @@ +while(8) JIP: -160 { align1 1Q }; +while(16) JIP: -160 { align1 1H }; +(-f0.0) while(8) JIP: -384 { align1 1Q }; +(-f0.0) while(16) JIP: -384 { align1 1H }; diff --git a/src/intel/tools/tests/gen9/while.expected b/src/intel/tools/tests/gen9/while.expected new file mode 100644 index 00000000000..5b0fd8538ab --- /dev/null +++ b/src/intel/tools/tests/gen9/while.expected @@ -0,0 +1,4 @@ +27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff +27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff +27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff +27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff diff --git a/src/intel/tools/tests/gen9/xor.asm b/src/intel/tools/tests/gen9/xor.asm new file mode 100644 index 00000000000..bc4c05456ef --- /dev/null +++ b/src/intel/tools/tests/gen9/xor.asm @@ -0,0 +1,2 @@ +xor(16) g3<1>UD g1<0,1,0>UD g1.1<0,1,0>UD { align1 1H }; +xor(8) g4<1>UD g5.6<0,1,0>UD ~g5.7<0,1,0>D { align1 1Q }; diff --git a/src/intel/tools/tests/gen9/xor.expected b/src/intel/tools/tests/gen9/xor.expected new file mode 100644 index 00000000000..2e27e335dd8 --- /dev/null +++ b/src/intel/tools/tests/gen9/xor.expected @@ -0,0 +1,2 @@ +07 00 80 00 08 02 60 20 20 00 00 02 24 00 00 00 +07 00 60 00 08 02 80 20 b8 00 00 0a bc 40 00 00 |