diff options
Diffstat (limited to 'src/intel/tools/tests/gen8/sendc.asm')
| -rw-r--r-- | src/intel/tools/tests/gen8/sendc.asm | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen8/sendc.asm b/src/intel/tools/tests/gen8/sendc.asm new file mode 100644 index 00000000000..c5d0d6e590a --- /dev/null +++ b/src/intel/tools/tests/gen8/sendc.asm @@ -0,0 +1,100 @@ +sendc(8) null<1>UW g124<8,8,1>F 0x88031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g120<8,8,1>F 0x90031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g114<8,8,1>F 0x82031100 + render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; +(+f0.1) sendc(8) null<1>UW g124<8,8,1>F 0x88031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g13<8,8,1>F 0x0e0b0401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g121<8,8,1>F 0x8e0b1402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g7<8,8,1>F 0x180b0001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H }; +sendc(16) null<1>UW g116<8,8,1>F 0x980b1002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g123<8,8,1>F 0x8a031400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x94031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g119<8,8,1>F 0x92031000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g5<8,8,1>F 0x0c0b0400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<8,8,1>F 0x0c0b0401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<8,8,1>F 0x0c0b0402 + render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<8,8,1>F 0x0c0b0403 + render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g5<8,8,1>F 0x0c0b0404 + render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1405 + render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g5<8,8,1>F 0x140b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<8,8,1>F 0x140b0001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<8,8,1>F 0x140b0002 + render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<8,8,1>F 0x140b0003 + render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g5<8,8,1>F 0x140b0004 + render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1005 + render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1403 + render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1003 + render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g118<8,8,1>F 0x940b1200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW g3<8,8,1>F 0x140b1200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g118<8,8,1>F 0x940b1300 + render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT }; +sendc(8) null<1>UW g23<8,8,1>F 0x0c0b0405 + render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g29<8,8,1>F 0x0c0b0406 + render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1407 + render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g57<8,8,1>F 0x140b0005 + render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g17<8,8,1>F 0x140b0006 + render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1007 + render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g10<8,8,1>F 0x0e0b0400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q }; +sendc(8) null<1>UW g121<8,8,1>F 0x8e0b1401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g2<8,8,1>F 0x160b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H }; +sendc(16) null<1>UW g117<8,8,1>F 0x960b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1404 + render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1004 + render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW g122<8,8,1>F 0x8c0b1406 + render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW g118<8,8,1>F 0x940b1006 + render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g116<8,8,1>F 0x980b1001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW g11<8,8,1>F 0x180b0000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H }; |