diff options
Diffstat (limited to 'src/intel/tools/tests/gen6')
70 files changed, 2404 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen6/add.asm b/src/intel/tools/tests/gen6/add.asm new file mode 100644 index 00000000000..37b2e5dff75 --- /dev/null +++ b/src/intel/tools/tests/gen6/add.asm @@ -0,0 +1,79 @@ +add(16) g6<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; +add(16) g4<1>UW g1.4<2,4,0>UW 0x10101010V { align1 1H }; +add(8) g30<1>F g26<8,8,1>F -g4.4<0,1,0>F { align1 1Q }; +add(16) g18<1>F g8<8,8,1>F -g6.4<0,1,0>F { align1 1H }; +add(1) m22.4<1>D g39.4<0,1,0>D 1D { align1 WE_all 1N }; +add(8) m1<1>D g3.3<0,1,0>D g2<0,1,0>D { align1 1Q }; +add(16) m1<1>D g3.3<0,1,0>D g2<0,1,0>D { align1 1H }; +add(8) g11<1>.xyF g1<0>.xyyyF g2<0>.xF { align16 1Q }; +add(8) m6<1>F g4<8,8,1>F 0xbd4ccccdF /* -0.05F */ { align1 1Q }; +add(8) g2<1>F g4<8,8,1>F 0x3d4ccccdF /* 0.05F */ { align1 1Q }; +add(16) g2<1>F g11<8,8,1>F 0xbd4ccccdF /* -0.05F */ { align1 1H }; +add(8) g6<1>.xUD g6<4>.xUD 0x00000001UD { align16 1Q }; +add(8) g19<1>.xUD g6<4>.xUD 3D { align16 1Q }; +add(8) m3<1>F g2<4>F g1<0>F { align16 1Q }; +add(8) g67<1>.xD g38<4>.xD g40<4>.xD { align16 1Q }; +add(8) g21<1>.xD g19<4>.xD -1D { align16 1Q }; +add(8) a0<1>UW g3<16,8,2>UW 0x0040UW { align1 1Q }; +add(8) a0<1>UW g4<16,8,2>UW 0x0040UW { align1 2Q }; +add(8) m2<1>.xD g3.4<0>.xD 7D { align16 NoDDClr 1Q }; +add(8) g6<1>.xyF g1<4>.xyyyF 0x3f800000F /* 1F */ { align16 1Q }; +add(16) m3<1>F -g39<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +add(8) m4<1>F g10<8,8,1>F g2.7<0,1,0>F { align1 1Q }; +add(16) m7<1>F g35<8,8,1>F g2.7<0,1,0>F { align1 1H }; +add(8) m3<1>.xyF g10<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr 1Q }; +add(8) g26<1>UD g26<4>UD g28<4>UD { align16 1Q }; +add(8) m6<1>.xD g5<4>.zD g5<4>.xD { align16 1Q }; +add(8) g4<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 1Q }; +add(16) g4<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 1H }; +add(8) m2<1>.xyzD g3.4<0>.xyzzD g11<4>.xyzzD { align16 NoDDClr 1Q }; +add(8) g70<1>D g4<0,1,0>D 1D { align1 1Q }; +add(8) m2<1>F g4<8,8,1>D 1D { align1 1Q }; +add(16) g75<1>D g6<0,1,0>D 1D { align1 1H }; +add(16) m3<1>F g89<8,8,1>D 1D { align1 1H }; +add(8) g37<1>F g34<8,8,1>D 1D { align1 1Q }; +add(16) g68<1>F g62<8,8,1>D 1D { align1 1H }; +add(8) g11<1>F g10<4>.xF 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q }; +add(8) m4<1>.zD g1<0>.xD 2D { align16 NoDDClr,NoDDChk 1Q }; +add(8) g15<1>.yD g1<0>.xD 49D { align16 NoDDClr 1Q }; +add(8) g15<1>.zD g1<0>.xD 50D { align16 NoDDClr,NoDDChk 1Q }; +add(8) m5<1>.wD g1<0>.xD 7D { align16 NoDDChk 1Q }; +add(8) g15<1>.wD g1<0>.xD 51D { align16 NoDDChk 1Q }; +add(8) g3<1>.yF g5<4>.xF -g1<0>.xF { align16 NoDDClr 1Q }; +add(8) g3<1>.yF g13<4>.xF -g1<0>.xF { align16 NoDDClr,NoDDChk 1Q }; +add(8) g42<1>.wF g2<0>.xF 0x40400000F /* 3F */ { align16 NoDDClr 1Q }; +add(8) g43<1>.wF g2<0>.xF 0x40e00000F /* 7F */ { align16 NoDDChk 1Q }; +add(8) m5<1>.zF g1<0>.xF 0x40000000F /* 2F */ { align16 NoDDClr,NoDDChk 1Q }; +add(8) m14<1>.zF g1<0>.xF 0x42180000F /* 38F */ { align16 NoDDChk 1Q }; +add(8) m3<1>F g1<4>.xF 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q }; +add(8) g99<1>.xD g8<4>.xUD 32D { align16 1Q }; +add(8) m4<1>.xF g1<4>.xF 0x42c80000F /* 100F */ { align16 1Q }; +add(8) g3.1<2>UW g3.1<16,8,2>UW g13<16,8,2>UW { align1 1Q }; +add(16) g3.1<2>UW g3.1<16,8,2>UW g5<16,8,2>UW { align1 1H }; +add.sat(8) m4<1>F g2<4>.yzxwF -g2<4>F { align16 1Q }; +add(8) g15<1>.wF g2<0>.xF 0x40400000F /* 3F */ { align16 NoDDClr,NoDDChk 1Q }; +add(8) g2<1>UD g22<0,1,0>UD g12<1,4,0>UW { align1 1Q }; +add(8) g3<1>UD g22<0,1,0>UD g12.2<1,4,0>UW { align1 2Q }; +add(8) m3<1>.xyF g2<4>.xyyyF g1<0>.xyyyF { align16 NoDDChk 1Q }; +add.sat(8) m4<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1Q }; +add.sat(8) g3<1>F g2.3<0,1,0>F g2.4<0,1,0>F { align1 1Q }; +add.sat(16) m7<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; +add.sat(16) g3<1>F g2.3<0,1,0>F g2.4<0,1,0>F { align1 1H }; +add(8) m17<1>D g3<8,8,1>D 12D { align1 1Q }; +add(16) m17<1>D g3<8,8,1>D 12D { align1 1H }; +add(8) m3<1>.yF g1<4>.yF -g9<4>.xF { align16 NoDDClr,NoDDChk 1Q }; +add(8) m5<1>.xyD g6<4>.xyyyD g12<4>.xD { align16 NoDDClr,NoDDChk 1Q }; +add(8) m5<1>.xD g11<4>.xD 1D { align16 1Q }; +add.sat(8) m4<1>.xF -g15<4>.xF 0x3f800000F /* 1F */ { align16 NoDDClr 1Q }; +add(8) m10<1>UD g13<0,1,0>UD g10<1,4,0>UW { align1 1Q }; +add(8) m11<1>UD g13<0,1,0>UD g10.2<1,4,0>UW { align1 2Q }; +add(8) m17<1>UD g6<8,8,1>UD 0x00000110UD { align1 1Q }; +add(16) m17<1>UD g9<8,8,1>UD 0x00000110UD { align1 1H }; +add.sat(8) g22<1>.xUD g20<4>.xUD g10<4>.xUD { align16 1Q }; +add.l.f0.0(8) g14<1>.xD g12<4>.xD -g12<4>.yD { align16 1Q }; +add(8) g18<1>F -g16<4>.xyxyF g16<4>.zwzwF { align16 2Q }; +add.sat(8) m4<1>F g7<4>.xF 0xbf800000F /* -1F */ { align16 1Q }; +add.sat(8) m4<1>.yF -g1<0>.xF 0x3f000000F /* 0.5F */ { align16 NoDDClr,NoDDChk 1Q }; +add.sat(8) m4<1>.wF g3<4>.yF 0xc0000000F /* -2F */ { align16 NoDDChk 1Q }; +add(8) m5<1>.xF g25<4>.xF -g3<4>.yF { align16 NoDDClr 1Q }; +add(8) g18<1>.yF g21<4>.xF g27<4>.xF { align16 NoDDChk 1Q }; diff --git a/src/intel/tools/tests/gen6/add.expected b/src/intel/tools/tests/gen6/add.expected new file mode 100644 index 00000000000..7419dcac64d --- /dev/null +++ b/src/intel/tools/tests/gen6/add.expected @@ -0,0 +1,79 @@ +40 02 80 00 29 6d c0 20 28 00 28 00 10 10 00 11 +40 00 80 00 29 6d 80 20 28 00 48 00 10 10 10 10 +40 00 60 00 bd 77 c0 23 40 03 8d 00 90 40 00 00 +40 00 80 00 bd 77 40 22 00 01 8d 00 d0 40 00 00 +40 02 00 00 a6 1c d0 22 f0 04 00 00 01 00 00 00 +40 00 60 00 a6 14 20 20 6c 00 00 00 40 00 00 00 +40 00 80 00 a6 14 20 20 6c 00 00 00 40 00 00 00 +40 01 60 00 bd 77 63 21 24 00 05 00 40 00 00 00 +40 00 60 00 be 7f c0 20 80 00 8d 00 cd cc 4c bd +40 00 60 00 bd 7f 40 20 80 00 8d 00 cd cc 4c 3d +40 00 80 00 bd 7f 40 20 60 01 8d 00 cd cc 4c bd +40 01 60 00 21 0c c1 20 c0 00 60 00 01 00 00 00 +40 01 60 00 21 1c 61 22 c0 00 60 00 03 00 00 00 +40 01 60 00 be 77 6f 20 44 00 6e 00 24 00 0e 00 +40 01 60 00 a5 14 61 28 c0 04 60 00 00 05 60 00 +40 01 60 00 a5 1c a1 22 60 02 60 00 ff ff ff ff +40 00 60 00 28 2d 00 22 60 00 ae 00 40 00 40 00 +40 10 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00 +40 05 60 00 a6 1c 41 20 70 00 00 00 07 00 00 00 +40 01 60 00 bd 7f c3 20 24 00 65 00 00 00 80 3f +40 00 80 00 be 7f 60 20 e0 44 8d 00 00 00 80 3f +40 00 60 00 be 77 80 20 40 01 8d 00 5c 00 00 00 +40 00 80 00 be 77 e0 20 60 04 8d 00 5c 00 00 00 +40 05 60 00 be 7f 63 20 44 01 65 00 00 00 00 3f +40 01 60 00 21 04 4f 23 44 03 6e 00 84 03 6e 00 +40 01 60 00 a6 14 c1 20 aa 00 6a 00 a0 00 60 00 +40 00 60 00 a5 14 80 20 40 00 00 00 50 00 00 00 +40 00 80 00 a5 14 80 20 40 00 00 00 50 00 00 00 +40 05 60 00 a6 14 47 20 74 00 0a 00 64 01 6a 00 +40 00 60 00 a5 1c c0 28 80 00 00 00 01 00 00 00 +40 00 60 00 be 1c 40 20 80 00 8d 00 01 00 00 00 +40 00 80 00 a5 1c 60 29 c0 00 00 00 01 00 00 00 +40 00 80 00 be 1c 60 20 20 0b 8d 00 01 00 00 00 +40 00 60 00 bd 1c a0 24 40 04 8d 00 01 00 00 00 +40 00 80 00 bd 1c 80 28 c0 07 8d 00 01 00 00 00 +40 01 60 00 bd 5f 6f 21 40 01 60 00 00 30 40 48 +40 0d 60 00 a6 1c 84 20 20 00 00 00 02 00 00 00 +40 05 60 00 a5 1c e2 21 20 00 00 00 31 00 00 00 +40 0d 60 00 a5 1c e4 21 20 00 00 00 32 00 00 00 +40 09 60 00 a6 1c a8 20 20 00 00 00 07 00 00 00 +40 09 60 00 a5 1c e8 21 20 00 00 00 33 00 00 00 +40 05 60 00 bd 77 62 20 a0 00 60 00 20 40 00 00 +40 0d 60 00 bd 77 62 20 a0 01 60 00 20 40 00 00 +40 05 60 00 bd 7f 48 25 40 00 00 00 00 00 40 40 +40 09 60 00 bd 7f 68 25 40 00 00 00 00 00 e0 40 +40 0d 60 00 be 7f a4 20 20 00 00 00 00 00 00 40 +40 09 60 00 be 7f c4 21 20 00 00 00 00 00 18 42 +40 01 60 00 be 5f 6f 20 20 00 60 00 00 30 40 48 +40 01 60 00 25 1c 61 2c 00 01 60 00 20 00 00 00 +40 01 60 00 be 7f 81 20 20 00 60 00 00 00 c8 42 +40 00 60 00 29 25 62 40 62 00 ae 00 a0 01 ae 00 +40 00 80 00 29 25 62 40 62 00 ae 00 a0 00 ae 00 +40 01 60 80 be 77 8f 20 49 00 6c 00 44 40 6e 00 +40 0d 60 00 bd 7f e8 21 40 00 00 00 00 00 40 40 +40 00 60 00 21 24 40 20 c0 02 00 00 80 01 28 00 +40 10 60 00 21 24 60 20 c0 02 00 00 84 01 28 00 +40 09 60 00 be 77 63 20 44 00 65 00 24 00 05 00 +40 00 60 80 be 77 80 20 40 00 00 00 50 00 00 00 +40 00 60 80 bd 77 60 20 4c 00 00 00 50 00 00 00 +40 00 80 80 be 77 e0 20 40 00 00 00 50 00 00 00 +40 00 80 80 bd 77 60 20 4c 00 00 00 50 00 00 00 +40 00 60 00 a6 1c 20 22 60 00 8d 00 0c 00 00 00 +40 00 80 00 a6 1c 20 22 60 00 8d 00 0c 00 00 00 +40 0d 60 00 be 77 62 20 25 00 65 00 20 41 60 00 +40 0d 60 00 a6 14 a3 20 c4 00 65 00 80 01 60 00 +40 01 60 00 a6 1c a1 20 60 01 60 00 01 00 00 00 +40 05 60 80 be 7f 81 20 e0 41 60 00 00 00 80 3f +40 00 60 00 22 24 40 21 a0 01 00 00 40 01 28 00 +40 10 60 00 22 24 60 21 a0 01 00 00 44 01 28 00 +40 00 60 00 22 0c 20 22 c0 00 8d 00 10 01 00 00 +40 00 80 00 22 0c 20 22 20 01 8d 00 10 01 00 00 +40 01 60 80 21 04 c1 22 80 02 60 00 40 01 60 00 +40 01 60 05 a5 14 c1 21 80 01 60 00 85 41 65 00 +40 11 60 00 bd 77 4f 22 04 42 64 00 0e 02 6e 00 +40 01 60 80 be 7f 8f 20 e0 00 60 00 00 00 80 bf +40 0d 60 80 be 7f 82 20 20 40 00 00 00 00 00 3f +40 09 60 80 be 7f 88 20 65 00 65 00 00 00 00 c0 +40 05 60 00 be 77 a1 20 20 03 60 00 65 40 65 00 +40 09 60 00 bd 77 42 22 a0 02 60 00 60 03 60 00 diff --git a/src/intel/tools/tests/gen6/and.asm b/src/intel/tools/tests/gen6/and.asm new file mode 100644 index 00000000000..72f35e547b8 --- /dev/null +++ b/src/intel/tools/tests/gen6/and.asm @@ -0,0 +1,19 @@ +and(8) g22<1>UD g21<8,8,1>UD g20<8,8,1>UD { align1 1Q }; +and.nz.f0.0(8) null<1>UD g24<8,8,1>UD g25<8,8,1>UD { align1 1Q }; +and(16) g41<1>UD g39<8,8,1>UD g37<8,8,1>UD { align1 1H }; +and.nz.f0.0(16) null<1>UD g45<8,8,1>UD g47<8,8,1>UD { align1 1H }; +and(1) g28<1>UD g55<0,1,0>UD 0x0000ffffUD { align1 1N }; +and(8) g64<1>.xUD g27<4>.xUD 0x0000ffffUD { align16 1Q }; +and(8) g12<1>UD g11<8,8,1>UD 0x00000001UD { align1 1Q }; +and(16) g19<1>UD g17<8,8,1>UD 0x00000001UD { align1 1H }; +and(8) g16<1>.xUD g4<4>.yUD g3<4>.xUD { align16 1Q }; +and(8) g5<1>D g2.4<0,1,0>D -g2.4<0,1,0>D { align1 1Q }; +and(16) g6<1>D g2.4<0,1,0>D -g2.4<0,1,0>D { align1 1H }; +and(1) g22<1>UD g0<0,1,0>UD 0x000000c0UD { align1 WE_all 1N }; +and(8) g12<1>D g1.4<0>D -g1.4<0>D { align16 1Q }; +and.nz.f0.0(8) null<1>.xUD g90<4>.xUD g89<4>.xUD { align16 1Q }; +and.nz.f0.0(8) null<1>UD g4<0,1,0>UD 0x00000001UD { align1 1Q }; +and.nz.f0.0(16) null<1>UD g6<0,1,0>UD 0x00000001UD { align1 1H }; +and.z.f0.0(8) null<1>UD g20<8,8,1>UD 0x00000001UD { align1 1Q }; +and.z.f0.0(16) null<1>UD g33<8,8,1>UD 0x00000001UD { align1 1H }; +and.z.f0.0(8) null<1>.xUD g3<4>.xUD 0x00000001UD { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/and.expected b/src/intel/tools/tests/gen6/and.expected new file mode 100644 index 00000000000..c8926d09e09 --- /dev/null +++ b/src/intel/tools/tests/gen6/and.expected @@ -0,0 +1,19 @@ +05 00 60 00 21 04 c0 22 a0 02 8d 00 80 02 8d 00 +05 00 60 02 20 04 00 20 00 03 8d 00 20 03 8d 00 +05 00 80 00 21 04 20 25 e0 04 8d 00 a0 04 8d 00 +05 00 80 02 20 04 00 20 a0 05 8d 00 e0 05 8d 00 +05 00 00 00 21 0c 80 23 e0 06 00 00 ff ff 00 00 +05 01 60 00 21 0c 01 28 60 03 60 00 ff ff 00 00 +05 00 60 00 21 0c 80 21 60 01 8d 00 01 00 00 00 +05 00 80 00 21 0c 60 22 20 02 8d 00 01 00 00 00 +05 01 60 00 21 04 01 22 85 00 65 00 60 00 60 00 +05 00 60 00 a5 14 a0 20 50 00 00 00 50 40 00 00 +05 00 80 00 a5 14 c0 20 50 00 00 00 50 40 00 00 +05 02 00 00 21 0c c0 22 00 00 00 00 c0 00 00 00 +05 01 60 00 a5 14 8f 21 34 00 0e 00 34 40 0e 00 +05 01 60 02 20 04 01 20 40 0b 60 00 20 0b 60 00 +05 00 60 02 20 0c 00 20 80 00 00 00 01 00 00 00 +05 00 80 02 20 0c 00 20 c0 00 00 00 01 00 00 00 +05 00 60 01 20 0c 00 20 80 02 8d 00 01 00 00 00 +05 00 80 01 20 0c 00 20 20 04 8d 00 01 00 00 00 +05 01 60 01 20 0c 01 20 60 00 60 00 01 00 00 00 diff --git a/src/intel/tools/tests/gen6/asr.asm b/src/intel/tools/tests/gen6/asr.asm new file mode 100644 index 00000000000..65cb48eb352 --- /dev/null +++ b/src/intel/tools/tests/gen6/asr.asm @@ -0,0 +1,13 @@ +asr(8) g11<1>D g11<4>D 16D { align16 1Q }; +asr(8) g2<1>D g2<8,8,1>D 16D { align1 1Q }; +asr(16) g2<1>D g2<8,8,1>D 16D { align1 1H }; +asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q }; +asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H }; +asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q }; +asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H }; +asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q }; +asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H }; +asr(8) g26<1>D g25<4>D g20<4>UD { align16 1Q }; +asr(8) g16<1>D g15<4>D 0x00000017UD { align16 1Q }; +asr(8) g14<1>D g10<8,8,1>D g8<8,8,1>UD { align1 1Q }; +asr(16) g21<1>D g13<8,8,1>D g9<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen6/asr.expected b/src/intel/tools/tests/gen6/asr.expected new file mode 100644 index 00000000000..da7461db745 --- /dev/null +++ b/src/intel/tools/tests/gen6/asr.expected @@ -0,0 +1,13 @@ +0c 01 60 00 a5 1c 6f 21 64 01 6e 00 10 00 00 00 +0c 00 60 00 a5 1c 40 20 40 00 8d 00 10 00 00 00 +0c 00 80 00 a5 1c 40 20 40 00 8d 00 10 00 00 00 +0c 00 60 00 a5 0c c0 20 a0 00 8d 00 01 00 00 00 +0c 00 80 00 a5 0c 00 21 c0 00 8d 00 01 00 00 00 +0c 00 60 02 a4 1d 00 20 00 40 00 00 0f 00 00 00 +0c 00 80 02 a4 1d 00 20 00 40 00 00 0f 00 00 00 +0c 00 60 00 a5 1d 40 20 00 40 00 00 0f 00 00 00 +0c 00 80 00 a5 1d 40 20 00 40 00 00 0f 00 00 00 +0c 01 60 00 a5 04 4f 23 24 03 6e 00 84 02 6e 00 +0c 01 60 00 a5 0c 0f 22 e4 01 6e 00 17 00 00 00 +0c 00 60 00 a5 04 c0 21 40 01 8d 00 00 01 8d 00 +0c 00 80 00 a5 04 a0 22 a0 01 8d 00 20 01 8d 00 diff --git a/src/intel/tools/tests/gen6/break.asm b/src/intel/tools/tests/gen6/break.asm new file mode 100644 index 00000000000..4b8afa9d11c --- /dev/null +++ b/src/intel/tools/tests/gen6/break.asm @@ -0,0 +1,6 @@ +break(8) JIP: 2 UIP: 12 { align16 1Q }; +break(8) JIP: 2 UIP: 104 { align1 1Q }; +break(16) JIP: 2 UIP: 104 { align1 1H }; +(+f0.0) break(8) JIP: 4 UIP: 12 { align1 1Q }; +(+f0.0) break(16) JIP: 4 UIP: 12 { align1 1H }; +(+f0.0.x) break(8) JIP: 122 UIP: 124 { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/break.expected b/src/intel/tools/tests/gen6/break.expected new file mode 100644 index 00000000000..9ab35eca7f1 --- /dev/null +++ b/src/intel/tools/tests/gen6/break.expected @@ -0,0 +1,6 @@ +28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0c 00 +28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 68 00 +28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 68 00 +28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0c 00 +28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0c 00 +28 01 62 00 84 1c 0f 20 04 00 6e 00 7a 00 7c 00 diff --git a/src/intel/tools/tests/gen6/cmp.asm b/src/intel/tools/tests/gen6/cmp.asm new file mode 100644 index 00000000000..9ac10ddac49 --- /dev/null +++ b/src/intel/tools/tests/gen6/cmp.asm @@ -0,0 +1,135 @@ +cmp.ge.f0.0(8) g38<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q }; +cmp.l.f0.0(8) g39<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q }; +cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H }; +cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H }; +cmp.ge.f0.0(8) null<1>F g38<4>.xF g36<4>.xF { align16 1Q }; +cmp.g.f0.0(8) null<1>UD g17<4>.xUD 0x00000000UD { align16 1Q }; +cmp.ge.f0.0(8) null<1>UD g18<4>.xUD g17<4>.xUD { align16 1Q }; +cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.z.f0.0(8) null<1>UD g9<4>.xUD 0x00000000UD { align16 1Q }; +cmp.l.f0.0(8) null<1>UD g20<4>.xUD 0x00000004UD { align16 1Q }; +(+f0.0) cmp.nz.f0.0(8) null<1>UD g20<4>.xUD 0x00000000UD { align16 1Q }; +cmp.l.f0.0(8) null<1>D g4<0,1,0>D 1D { align1 1Q }; +cmp.z.f0.0(8) g20<1>F g3<8,8,1>F g4.3<0,1,0>F { align1 1Q }; +cmp.l.f0.0(16) null<1>D g6<0,1,0>D 1D { align1 1H }; +cmp.z.f0.0(16) g37<1>F g4<8,8,1>F g6.3<0,1,0>F { align1 1H }; +cmp.z.f0.0(8) null<1>F g66<4>F g3.4<0>F { align16 1Q }; +cmp.l.f0.0(8) g22<1>F g21<8,8,1>F g20<8,8,1>F { align1 1Q }; +cmp.ge.f0.0(8) g23<1>F g21<8,8,1>F g20<8,8,1>F { align1 1Q }; +cmp.l.f0.0(16) g25<1>F g23<8,8,1>F g2<8,8,1>F { align1 1H }; +cmp.ge.f0.0(16) g27<1>F g23<8,8,1>F g2<8,8,1>F { align1 1H }; +cmp.le.f0.0(8) null<1>.zF g7<4>.xF 0x0F /* 0F */ { align16 1Q }; +cmp.le.f0.0(8) null<1>UD g60<4>UD g29<4>UD { align16 1Q }; +cmp.l.f0.0(8) null<1>UD g60<4>UD g55<4>.xUD { align16 1Q }; +cmp.z.f0.0(8) null<1>D g4<0,1,0>D 1D { align1 1Q }; +cmp.z.f0.0(8) null<1>F g11<8,8,1>F g4.1<0,1,0>F { align1 1Q }; +cmp.z.f0.0(16) null<1>D g6<0,1,0>D 1D { align1 1H }; +cmp.z.f0.0(16) null<1>F g17<8,8,1>F g6.1<0,1,0>F { align1 1H }; +cmp.z.f0.0(8) g31<1>.yzwD g3<0>.xD g19<4>.yyzwD { align16 1Q }; +cmp.nz.f0.0(8) null<1>.xD g31<4>.yD 0D { align16 1Q }; +cmp.nz.f0.0(8) g8<1>D g5<8,8,1>D g3.1<0,1,0>D { align1 1Q }; +cmp.nz.f0.0(16) g12<1>D g6<8,8,1>D g3.1<0,1,0>D { align1 1H }; +cmp.nz.f0.0(8) null<1>D g4<0,1,0>D 0D { align1 1Q }; +cmp.nz.f0.0(16) null<1>D g6<0,1,0>D 0D { align1 1H }; +cmp.nz.f0.0(8) g72<1>F g74<8,8,1>F g71<8,8,1>F { align1 1Q }; +cmp.nz.f0.0(16) g77<1>F g75<8,8,1>F g71<8,8,1>F { align1 1H }; +cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 1Q }; +cmp.z.f0.0(8) g17<1>.xD g1<0>.xD 1D { align16 1Q }; +cmp.z.f0.0(8) null<1>D g2<4>.zD g17<4>.xD { align16 1Q }; +cmp.nz.f0.0(8) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.nz.f0.0(16) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.z.f0.0(8) null<1>D g4.4<0>.xD 0D { align16 1Q }; +cmp.z.f0.0(8) null<1>.xF (abs)g13<4>.xF 0x7f800000F /* infF */ { align16 1Q }; +cmp.nz.f0.0(8) null<1>.xF g13<4>.xF g13<4>.xF { align16 1Q }; +cmp.nz.f0.0(8) null<1>F g13<4>.xF 0x0F /* 0F */ { align16 1Q }; +cmp.l.f0.0(8) null<1>.xF g5<4>.xF g13<4>.xF { align16 1Q }; +cmp.l.f0.0(8) g10<1>UD g9<4>UD g1<0>UD { align16 1Q }; +cmp.nz.f0.0(8) null<1>D -g10<4>D g2<0>D { align16 1Q }; +cmp.g.f0.0(8) g34<1>F g33<8,8,1>F 0x3727c5acF /* 1e-05F */ { align1 1Q }; +cmp.le.f0.0(8) g35<1>F g33<8,8,1>F 0x3727c5acF /* 1e-05F */ { align1 1Q }; +cmp.g.f0.0(16) g8<1>F g6<8,8,1>F 0x3727c5acF /* 1e-05F */ { align1 1H }; +cmp.le.f0.0(16) g10<1>F g6<8,8,1>F 0x3727c5acF /* 1e-05F */ { align1 1H }; +cmp.z.f0.0(8) g11<1>F g9<4>.xF g2<4>F { align16 1Q }; +cmp.z.f0.0(8) g3<1>D g2.3<0,1,0>D 0D { align1 1Q }; +cmp.nz.f0.0(8) g4<1>D g2.3<0,1,0>D 0D { align1 1Q }; +cmp.z.f0.0(16) g3<1>D g2.3<0,1,0>D 0D { align1 1H }; +cmp.nz.f0.0(16) g5<1>D g2.3<0,1,0>D 0D { align1 1H }; +cmp.le.f0.0(8) g50<1>.xF g44<4>.xF 0x3727c5acF /* 1e-05F */ { align16 1Q }; +cmp.g.f0.0(8) null<1>.xF g49<4>.xF 0x3727c5acF /* 1e-05F */ { align16 1Q }; +cmp.l.f0.0(8) null<1>F g39<4>.xF 0x3189705fF /* 4e-09F */ { align16 1Q }; +cmp.nz.f0.0(8) null<1>F g4.4<0>F 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q }; +cmp.ge.f0.0(8) g5<1>D g2<0,1,0>D 1D { align1 1Q }; +cmp.ge.f0.0(16) g7<1>D g2<0,1,0>D 1D { align1 1H }; +cmp.z.f0.0(8) null<1>F (abs)g10<8,8,1>F 0x7f800000F /* infF */ { align1 1Q }; +cmp.nz.f0.0(8) null<1>F g10<8,8,1>F g10<8,8,1>F { align1 1Q }; +cmp.g.f0.0(8) null<1>F g10<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +cmp.z.f0.0(16) null<1>F (abs)g15<8,8,1>F 0x7f800000F /* infF */ { align1 1H }; +cmp.nz.f0.0(16) null<1>F g15<8,8,1>F g15<8,8,1>F { align1 1H }; +cmp.g.f0.0(16) null<1>F g15<8,8,1>F 0x0F /* 0F */ { align1 1H }; +cmp.z.f0.0(8) g3<1>F g2.1<0,1,0>F 0x40800000F /* 4F */ { align1 1Q }; +cmp.z.f0.0(16) g3<1>F g2.1<0,1,0>F 0x40800000F /* 4F */ { align1 1H }; +cmp.ge.f0.0(8) g77<1>.xD g2<0>.xD 16D { align16 1Q }; +cmp.l.f0.0(8) g76<1>.xyzF g8<0>.wF g75<4>.xF { align16 1Q }; +cmp.z.f0.0(8) g6<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1Q }; +cmp.z.f0.0(16) g9<1>D g7<8,8,1>D g2.5<0,1,0>D { align1 1H }; +cmp.le.f0.0(8) null<1>D g1<0>.xD 0D { align16 1Q }; +cmp.l.f0.0(8) g76<1>.xD g74<4>.xD 7D { align16 1Q }; +cmp.l.f0.0(8) null<1>.xD g74<4>.xD 3D { align16 1Q }; +cmp.le.f0.0(8) g4<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; +cmp.g.f0.0(8) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; +cmp.le.f0.0(16) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; +cmp.g.f0.0(16) g7<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; +cmp.le.f0.0(8) null<1>F g68<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +cmp.le.f0.0(16) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; +cmp.z.f0.0(8) null<1>F g3<0>.xyzzF 0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 1Q }; +cmp.ge.f0.0(8) g31<1>UD g30<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; +cmp.l.f0.0(8) g32<1>UD g30<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; +(+f0.1) cmp.z.f0.1(8) null<1>D g37<8,8,1>D 0D { align1 1Q }; +cmp.ge.f0.0(16) g49<1>UD g47<8,8,1>UD g7.7<0,1,0>UD { align1 1H }; +cmp.l.f0.0(16) g51<1>UD g47<8,8,1>UD g7.3<0,1,0>UD { align1 1H }; +(+f0.1) cmp.z.f0.1(16) null<1>D g80<8,8,1>D 0D { align1 1H }; +cmp.ge.f0.0(8) null<1>F g13<8,8,1>F 0x38d1b717F /* 0.0001F */ { align1 1Q }; +cmp.ge.f0.0(16) null<1>F g21<8,8,1>F 0x38d1b717F /* 0.0001F */ { align1 1H }; +cmp.g.f0.0(8) g6<1>F g2<4>F 0x3f000000F /* 0.5F */ { align16 1Q }; +cmp.nz.f0.0(8) g4<1>F g2.2<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.nz.f0.0(16) g5<1>F g2.2<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.ge.f0.0(8) null<1>D g6<8,8,1>D 4D { align1 1Q }; +cmp.nz.f0.0(8) null<1>D g8<8,8,1>D g6<8,8,1>D { align1 1Q }; +cmp.ge.f0.0(16) null<1>D g10<8,8,1>D 4D { align1 1H }; +cmp.nz.f0.0(16) null<1>D g14<8,8,1>D g10<8,8,1>D { align1 1H }; +cmp.ge.f0.0(8) g8<1>F g1<0>F g1.4<0>F { align16 1Q }; +cmp.l.f0.0(8) g54<1>D g5<0,1,0>D 1D { align1 1Q }; +cmp.l.f0.0(16) g52<1>D g7<0,1,0>D 1D { align1 1H }; +cmp.nz.f0.0(8) g13<1>.xyF g12<4>.xyyyF g12<4>.xyyyF { align16 1Q }; +cmp.ge.f0.0(8) null<1>F g3<4>.xF 0x41f00000F /* 30F */ { align16 1Q }; +cmp.g.f0.0(8) null<1>D g2.1<0,1,0>D 0D { align1 1Q }; +cmp.ge.f0.0(8) null<1>D g3<8,8,1>D g2.1<0,1,0>D { align1 1Q }; +cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 1H }; +cmp.ge.f0.0(16) null<1>D g3<8,8,1>D g2.1<0,1,0>D { align1 1H }; +cmp.ge.f0.0(8) g88<1>.xF g8<4>.xF 0x3727c5acF /* 1e-05F */ { align16 1Q }; +cmp.ge.f0.0(8) null<1>.xD g6<4>.xD g3<0>.yD { align16 1Q }; +cmp.g.f0.0(8) null<1>.xD g1<0>.xD 0D { align16 1Q }; +cmp.z.f0.0(8) null<1>D g4<8,8,1>D g2<0,1,0>D { align1 1Q }; +cmp.z.f0.0(16) null<1>D g5<8,8,1>D g2<0,1,0>D { align1 1H }; +cmp.ge.f0.0(8) null<1>F g2<8,8,1>F g8<8,8,1>F { align1 1Q }; +cmp.ge.f0.0(16) null<1>F g2<8,8,1>F g11<8,8,1>F { align1 1H }; +cmp.z.f0.0(8) g8<1>.xF g7<4>.xF 0x40533333F /* 3.3F */ { align16 1Q }; +cmp.nz.f0.0(8) g40<1>.xD g7<4>.xD g39<4>.xD { align16 1Q }; +(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1Q }; +(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1H }; +cmp.nz.f0.0(8) g20<1>.xD g19<4>.xD 0D { align16 1Q }; +cmp.nz.f0.0(8) g8<1>F g7<4>F 0x0F /* 0F */ { align16 1Q }; +cmp.le.f0.0(8) g3<1>D g2<0,1,0>D 0D { align1 1Q }; +cmp.le.f0.0(16) g3<1>D g2<0,1,0>D 0D { align1 1H }; +cmp.l.f0.0(8) g12<1>.xF g3<0>.zF 0x3f000000F /* 0.5F */ { align16 1Q }; +cmp.l.f0.0(8) null<1>.xD g9<4>.xD g5<4>.xD { align16 1Q }; +cmp.ge.f0.0(8) null<1>UD g4<8,8,1>UD g2.3<0,1,0>UD { align1 1Q }; +cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD g2.3<0,1,0>UD { align1 1H }; +cmp.l.f0.0(8) null<1>D g2.1<0,1,0>D g3<8,8,1>D { align1 1Q }; +cmp.l.f0.0(16) null<1>D g2.1<0,1,0>D g3<8,8,1>D { align1 1H }; +cmp.le.f0.0(8) g9<1>.xUD g1<0>.xUD 0x00000001UD { align16 1Q }; +cmp.l.f0.0(8) null<1>UD g2<8,8,1>UD g3<8,8,1>UD { align1 1Q }; +cmp.l.f0.0(16) null<1>UD g2<8,8,1>UD g4<8,8,1>UD { align1 1H }; +cmp.l.f0.0(8) null<1>F (abs)g7<8,8,1>F (abs)g16<8,8,1>F { align1 1Q }; +cmp.l.f0.0(16) null<1>F (abs)g31<8,8,1>F (abs)g33<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen6/cmp.expected b/src/intel/tools/tests/gen6/cmp.expected new file mode 100644 index 00000000000..3a4d09617c7 --- /dev/null +++ b/src/intel/tools/tests/gen6/cmp.expected @@ -0,0 +1,135 @@ +10 00 60 04 bd 7f c0 24 a0 04 8d 00 5f 70 89 31 +10 00 60 05 bd 7f e0 24 a0 04 8d 00 5f 70 89 31 +10 00 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31 +10 00 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31 +10 01 60 04 bc 77 0f 20 c0 04 60 00 80 04 60 00 +10 01 60 03 20 0c 0f 20 20 02 60 00 00 00 00 00 +10 01 60 04 20 04 0f 20 40 02 60 00 20 02 60 00 +10 00 60 05 bc 7f 00 20 90 00 00 00 00 00 00 00 +10 00 80 05 bc 7f 00 20 d0 00 00 00 00 00 00 00 +10 01 60 01 20 0c 0f 20 20 01 60 00 00 00 00 00 +10 01 60 05 20 0c 0f 20 80 02 60 00 04 00 00 00 +10 01 61 02 20 0c 0f 20 80 02 60 00 00 00 00 00 +10 00 60 05 a4 1c 00 20 80 00 00 00 01 00 00 00 +10 00 60 01 bd 77 80 22 60 00 8d 00 8c 00 00 00 +10 00 80 05 a4 1c 00 20 c0 00 00 00 01 00 00 00 +10 00 80 01 bd 77 a0 24 80 00 8d 00 cc 00 00 00 +10 01 60 01 bc 77 0f 20 44 08 6e 00 74 00 0e 00 +10 00 60 05 bd 77 c0 22 a0 02 8d 00 80 02 8d 00 +10 00 60 04 bd 77 e0 22 a0 02 8d 00 80 02 8d 00 +10 00 80 05 bd 77 20 23 e0 02 8d 00 40 00 8d 00 +10 00 80 04 bd 77 60 23 e0 02 8d 00 40 00 8d 00 +10 01 60 06 bc 7f 04 20 e0 00 60 00 00 00 00 00 +10 01 60 06 20 04 0f 20 84 07 6e 00 a4 03 6e 00 +10 01 60 05 20 04 0f 20 84 07 6e 00 e0 06 60 00 +10 00 60 01 a4 1c 00 20 80 00 00 00 01 00 00 00 +10 00 60 01 bc 77 00 20 60 01 8d 00 84 00 00 00 +10 00 80 01 a4 1c 00 20 c0 00 00 00 01 00 00 00 +10 00 80 01 bc 77 00 20 20 02 8d 00 c4 00 00 00 +10 01 60 01 a5 14 ee 23 60 00 00 00 65 02 6e 00 +10 01 60 02 a4 1c 01 20 e5 03 65 00 00 00 00 00 +10 00 60 02 a5 14 00 21 a0 00 8d 00 64 00 00 00 +10 00 80 02 a5 14 80 21 c0 00 8d 00 64 00 00 00 +10 00 60 02 a4 1c 00 20 80 00 00 00 00 00 00 00 +10 00 80 02 a4 1c 00 20 c0 00 00 00 00 00 00 00 +10 00 60 02 bd 77 00 29 40 09 8d 00 e0 08 8d 00 +10 00 80 02 bd 77 a0 29 60 09 8d 00 e0 08 8d 00 +10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00 +10 01 60 01 a5 1c 21 22 20 00 00 00 01 00 00 00 +10 01 60 01 a4 14 0f 20 4a 00 6a 00 20 02 60 00 +10 00 60 02 bc 7f 00 20 50 00 00 00 00 00 00 00 +10 00 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00 +10 01 60 01 a4 1c 0f 20 90 00 00 00 00 00 00 00 +10 01 60 01 bc 7f 01 20 a0 21 60 00 00 00 80 7f +10 01 60 02 bc 77 01 20 a0 01 60 00 a0 01 60 00 +10 01 60 02 bc 7f 0f 20 a0 01 60 00 00 00 00 00 +10 01 60 05 bc 77 01 20 a0 00 60 00 a0 01 60 00 +10 01 60 05 21 04 4f 21 24 01 6e 00 24 00 0e 00 +10 01 60 02 a4 14 0f 20 44 41 6e 00 44 00 0e 00 +10 00 60 03 bd 7f 40 24 20 04 8d 00 ac c5 27 37 +10 00 60 06 bd 7f 60 24 20 04 8d 00 ac c5 27 37 +10 00 80 03 bd 7f 00 21 c0 00 8d 00 ac c5 27 37 +10 00 80 06 bd 7f 40 21 c0 00 8d 00 ac c5 27 37 +10 01 60 01 bd 77 6f 21 20 01 60 00 44 00 6e 00 +10 00 60 01 a5 1c 60 20 4c 00 00 00 00 00 00 00 +10 00 60 02 a5 1c 80 20 4c 00 00 00 00 00 00 00 +10 00 80 01 a5 1c 60 20 4c 00 00 00 00 00 00 00 +10 00 80 02 a5 1c a0 20 4c 00 00 00 00 00 00 00 +10 01 60 06 bd 7f 41 26 80 05 60 00 ac c5 27 37 +10 01 60 03 bc 7f 01 20 20 06 60 00 ac c5 27 37 +10 01 60 05 bc 7f 0f 20 e0 04 60 00 5f 70 89 31 +10 01 60 02 bc 5f 0f 20 94 00 0e 00 00 30 40 48 +10 00 60 04 a5 1c a0 20 40 00 00 00 01 00 00 00 +10 00 80 04 a5 1c e0 20 40 00 00 00 01 00 00 00 +10 00 60 01 bc 7f 00 20 40 21 8d 00 00 00 80 7f +10 00 60 02 bc 77 00 20 40 01 8d 00 40 01 8d 00 +10 00 60 03 bc 7f 00 20 40 01 8d 00 00 00 00 00 +10 00 80 01 bc 7f 00 20 e0 21 8d 00 00 00 80 7f +10 00 80 02 bc 77 00 20 e0 01 8d 00 e0 01 8d 00 +10 00 80 03 bc 7f 00 20 e0 01 8d 00 00 00 00 00 +10 00 60 01 bd 7f 60 20 44 00 00 00 00 00 80 40 +10 00 80 01 bd 7f 60 20 44 00 00 00 00 00 80 40 +10 01 60 04 a5 1c a1 29 40 00 00 00 10 00 00 00 +10 01 60 05 bd 77 87 29 0f 01 0f 00 60 09 60 00 +10 00 60 01 a5 14 c0 20 a0 00 8d 00 54 00 00 00 +10 00 80 01 a5 14 20 21 e0 00 8d 00 54 00 00 00 +10 01 60 06 a4 1c 0f 20 20 00 00 00 00 00 00 00 +10 01 60 05 a5 1c 81 29 40 09 60 00 07 00 00 00 +10 01 60 05 a4 1c 01 20 40 09 60 00 03 00 00 00 +10 00 60 06 21 0c 80 20 40 00 00 00 01 00 00 00 +10 00 60 03 21 0c a0 20 40 00 00 00 01 00 00 00 +10 00 80 06 21 0c a0 20 40 00 00 00 01 00 00 00 +10 00 80 03 21 0c e0 20 40 00 00 00 01 00 00 00 +10 00 60 06 bc 7f 00 20 80 08 8d 00 00 00 00 3f +10 00 80 06 bc 7f 00 20 40 00 8d 00 00 00 00 3f +10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e +10 00 60 04 21 04 e0 23 c0 03 8d 00 bc 00 00 00 +10 00 60 05 21 04 00 24 c0 03 8d 00 ac 00 00 00 +10 00 61 01 a4 1c 00 20 a0 04 8d 02 00 00 00 00 +10 00 80 04 21 04 20 26 e0 05 8d 00 fc 00 00 00 +10 00 80 05 21 04 60 26 e0 05 8d 00 ec 00 00 00 +10 00 81 01 a4 1c 00 20 00 0a 8d 02 00 00 00 00 +10 00 60 04 bc 7f 00 20 a0 01 8d 00 17 b7 d1 38 +10 00 80 04 bc 7f 00 20 a0 02 8d 00 17 b7 d1 38 +10 01 60 03 bd 7f cf 20 44 00 6e 00 00 00 00 3f +10 00 60 02 bd 7f 80 20 48 00 00 00 00 00 00 00 +10 00 80 02 bd 7f a0 20 48 00 00 00 00 00 00 00 +10 00 60 04 a4 1c 00 20 c0 00 8d 00 04 00 00 00 +10 00 60 02 a4 14 00 20 00 01 8d 00 c0 00 8d 00 +10 00 80 04 a4 1c 00 20 40 01 8d 00 04 00 00 00 +10 00 80 02 a4 14 00 20 c0 01 8d 00 40 01 8d 00 +10 01 60 04 bd 77 0f 21 24 00 0e 00 34 00 0e 00 +10 00 60 05 a5 1c c0 26 a0 00 00 00 01 00 00 00 +10 00 80 05 a5 1c 80 26 e0 00 00 00 01 00 00 00 +10 01 60 02 bd 77 a3 21 84 01 65 00 84 01 65 00 +10 01 60 04 bc 7f 0f 20 60 00 60 00 00 00 f0 41 +10 00 60 03 a4 1c 00 20 44 00 00 00 00 00 00 00 +10 00 60 04 a4 14 00 20 60 00 8d 00 44 00 00 00 +10 00 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00 +10 00 80 04 a4 14 00 20 60 00 8d 00 44 00 00 00 +10 01 60 04 bd 7f 01 2b 00 01 60 00 ac c5 27 37 +10 01 60 04 a4 14 01 20 c0 00 60 00 65 00 05 00 +10 01 60 03 a4 1c 01 20 20 00 00 00 00 00 00 00 +10 00 60 01 a4 14 00 20 80 00 8d 00 40 00 00 00 +10 00 80 01 a4 14 00 20 a0 00 8d 00 40 00 00 00 +10 00 60 04 bc 77 00 20 40 00 8d 00 00 01 8d 00 +10 00 80 04 bc 77 00 20 40 00 8d 00 60 01 8d 00 +10 01 60 01 bd 7f 01 21 e0 00 60 00 33 33 53 40 +10 01 60 02 a5 14 01 25 e0 00 60 00 e0 04 60 00 +10 00 61 02 28 25 00 20 00 00 8d 02 00 00 8d 00 +10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00 +10 01 60 02 a5 1c 81 22 60 02 60 00 00 00 00 00 +10 01 60 02 bd 7f 0f 21 e4 00 6e 00 00 00 00 00 +10 00 60 06 a5 1c 60 20 40 00 00 00 00 00 00 00 +10 00 80 06 a5 1c 60 20 40 00 00 00 00 00 00 00 +10 01 60 05 bd 7f 81 21 6a 00 0a 00 00 00 00 3f +10 01 60 05 a4 14 01 20 20 01 60 00 a0 00 60 00 +10 00 60 04 20 04 00 20 80 00 8d 00 4c 00 00 00 +10 00 80 04 20 04 00 20 a0 00 8d 00 4c 00 00 00 +10 00 60 05 a4 14 00 20 44 00 00 00 60 00 8d 00 +10 00 80 05 a4 14 00 20 44 00 00 00 60 00 8d 00 +10 01 60 06 21 0c 21 21 20 00 00 00 01 00 00 00 +10 00 60 05 20 04 00 20 40 00 8d 00 60 00 8d 00 +10 00 80 05 20 04 00 20 40 00 8d 00 80 00 8d 00 +10 00 60 05 bc 77 00 20 e0 20 8d 00 00 22 8d 00 +10 00 80 05 bc 77 00 20 e0 23 8d 00 20 24 8d 00 diff --git a/src/intel/tools/tests/gen6/cont.asm b/src/intel/tools/tests/gen6/cont.asm new file mode 100644 index 00000000000..7f7a9c42196 --- /dev/null +++ b/src/intel/tools/tests/gen6/cont.asm @@ -0,0 +1,3 @@ +cont(8) JIP: 2 UIP: 8 { align1 1Q }; +cont(16) JIP: 2 UIP: 8 { align1 1H }; +cont(8) JIP: 2 UIP: 8 { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/cont.expected b/src/intel/tools/tests/gen6/cont.expected new file mode 100644 index 00000000000..a8376c2f2d5 --- /dev/null +++ b/src/intel/tools/tests/gen6/cont.expected @@ -0,0 +1,3 @@ +29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00 +29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00 +29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00 diff --git a/src/intel/tools/tests/gen6/dp2.asm b/src/intel/tools/tests/gen6/dp2.asm new file mode 100644 index 00000000000..dd2b52ca274 --- /dev/null +++ b/src/intel/tools/tests/gen6/dp2.asm @@ -0,0 +1,7 @@ +dp2(8) g91<1>F g88<4>.xyyyF g88<4>.xyyyF { align16 1Q }; +dp2(8) m4<1>.xF g1<0>.yF g1<0>.yF { align16 NoDDClr 1Q }; +dp2(8) m4<1>.yzF g1<0>.xF g1<0>.zwwwF { align16 NoDDClr,NoDDChk 1Q }; +dp2(8) m4<1>.wF g1<0>.ywwwF g1<0>.wyyyF { align16 NoDDChk 1Q }; +dp2(8) g4<1>.yF g1<0>.xyyyF g1.4<0>.xyyyF { align16 NoDDClr 1Q }; +dp2(8) g4<1>.zF g1<0>.xyyyF g1.4<0>.zwwwF { align16 NoDDClr,NoDDChk 1Q }; +dp2(8) g4<1>.wF g1<0>.xyyyF g2<0>.xyyyF { align16 NoDDChk 1Q }; diff --git a/src/intel/tools/tests/gen6/dp2.expected b/src/intel/tools/tests/gen6/dp2.expected new file mode 100644 index 00000000000..9aa792876ab --- /dev/null +++ b/src/intel/tools/tests/gen6/dp2.expected @@ -0,0 +1,7 @@ +57 01 60 00 bd 77 6f 2b 04 0b 65 00 04 0b 65 00 +57 05 60 00 be 77 81 20 25 00 05 00 25 00 05 00 +57 0d 60 00 be 77 86 20 20 00 00 00 2e 00 0f 00 +57 09 60 00 be 77 88 20 2d 00 0f 00 27 00 05 00 +57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00 +57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00 +57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00 diff --git a/src/intel/tools/tests/gen6/dp3.asm b/src/intel/tools/tests/gen6/dp3.asm new file mode 100644 index 00000000000..c51880a4e4b --- /dev/null +++ b/src/intel/tools/tests/gen6/dp3.asm @@ -0,0 +1,10 @@ +dp3(8) m4<1>.xF g3<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr 1Q }; +dp3(8) m4<1>.yF g3.4<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr,NoDDChk 1Q }; +dp3(8) g70<1>F g67<4>.xyzzF g67<4>.xyzzF { align16 1Q }; +dp3(8) m4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 1Q }; +dp3.le.f0.0(8) g42<1>.xF g33<4>.xyzzF g3.4<0>.xyzzF { align16 1Q }; +dp3(8) g21<1>.xF g20<4>.xyzzF g1<0>.xyzzF { align16 NoDDClr 1Q }; +dp3(8) g21<1>.yF g20<4>.xyzzF g1.4<0>.xyzzF { align16 NoDDClr,NoDDChk 1Q }; +dp3(8) g21<1>.zF g20<4>.xyzzF g2<0>.xyzzF { align16 NoDDChk 1Q }; +dp3.sat(8) g49<1>F g38<4>.xyzzF g43<4>.xyzzF { align16 1Q }; +dp3.sat(8) m4<1>F g2<4>.xyzzF g2<4>.xyzzF { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/dp3.expected b/src/intel/tools/tests/gen6/dp3.expected new file mode 100644 index 00000000000..2d71488b091 --- /dev/null +++ b/src/intel/tools/tests/gen6/dp3.expected @@ -0,0 +1,10 @@ +56 05 60 00 be 77 81 20 64 00 0a 00 c4 00 6a 00 +56 0d 60 00 be 77 82 20 74 00 0a 00 c4 00 6a 00 +56 01 60 00 bd 77 cf 28 64 08 6a 00 64 08 6a 00 +56 01 60 00 be 77 81 20 84 00 6a 00 a4 00 6a 00 +56 01 60 06 bd 77 41 25 24 04 6a 00 74 00 0a 00 +56 05 60 00 bd 77 a1 22 84 02 6a 00 24 00 0a 00 +56 0d 60 00 bd 77 a2 22 84 02 6a 00 34 00 0a 00 +56 09 60 00 bd 77 a4 22 84 02 6a 00 44 00 0a 00 +56 01 60 80 bd 77 2f 26 c4 04 6a 00 64 05 6a 00 +56 01 60 80 be 77 8f 20 44 00 6a 00 44 00 6a 00 diff --git a/src/intel/tools/tests/gen6/dp4.asm b/src/intel/tools/tests/gen6/dp4.asm new file mode 100644 index 00000000000..c873b54a9f1 --- /dev/null +++ b/src/intel/tools/tests/gen6/dp4.asm @@ -0,0 +1,9 @@ +dp4(8) m3<1>.xF g3<4>F g1<0>F { align16 NoDDClr 1Q }; +dp4(8) m3<1>.yF g3<4>F g1.4<0>F { align16 NoDDClr,NoDDChk 1Q }; +dp4(8) m3<1>.wF g3<4>F g2.4<0>F { align16 NoDDChk 1Q }; +dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 1Q }; +dp4(8) m3<1>.wF g4<4>F g2.4<0>F { align16 1Q }; +dp4(8) g26<1>.xF g24<4>F g5<0>F { align16 NoDDClr 1Q }; +dp4(8) g26<1>.yF g24<4>F g5.4<0>F { align16 NoDDChk 1Q }; +dp4.sat(8) m4<1>F g2<4>.xF g2<4>F { align16 1Q }; +dp4(8) g18<1>.xF g2.4<0>F 0x3f800000F /* 1F */ { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/dp4.expected b/src/intel/tools/tests/gen6/dp4.expected new file mode 100644 index 00000000000..4de79010c24 --- /dev/null +++ b/src/intel/tools/tests/gen6/dp4.expected @@ -0,0 +1,9 @@ +54 05 60 00 be 77 61 20 64 00 6e 00 24 00 0e 00 +54 0d 60 00 be 77 62 20 64 00 6e 00 34 00 0e 00 +54 09 60 00 be 77 68 20 64 00 6e 00 54 00 0e 00 +54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00 +54 01 60 00 be 77 68 20 84 00 6e 00 54 00 0e 00 +54 05 60 00 bd 77 41 23 04 03 6e 00 a4 00 0e 00 +54 09 60 00 bd 77 42 23 04 03 6e 00 b4 00 0e 00 +54 01 60 80 be 77 8f 20 40 00 60 00 44 00 6e 00 +54 01 60 00 bd 7f 41 22 54 00 0e 00 00 00 80 3f diff --git a/src/intel/tools/tests/gen6/dph.asm b/src/intel/tools/tests/gen6/dph.asm new file mode 100644 index 00000000000..e0fe6949fd6 --- /dev/null +++ b/src/intel/tools/tests/gen6/dph.asm @@ -0,0 +1,5 @@ +dph(8) m4<1>.xF g4<4>.xyzxF g5<4>F { align16 1Q }; +dph.sat(8) m4<1>F g1<0>.xyzxF g3<4>F { align16 1Q }; +dph(8) m3<1>.xF g5<4>.xyzxF g1<0>F { align16 NoDDClr 1Q }; +dph(8) m3<1>.yF g5<4>.xyzxF g1.4<0>F { align16 NoDDClr,NoDDChk 1Q }; +dph(8) m3<1>.wF g5<4>.xyzxF g2.4<0>F { align16 NoDDChk 1Q }; diff --git a/src/intel/tools/tests/gen6/dph.expected b/src/intel/tools/tests/gen6/dph.expected new file mode 100644 index 00000000000..2ef78a0a7cb --- /dev/null +++ b/src/intel/tools/tests/gen6/dph.expected @@ -0,0 +1,5 @@ +55 01 60 00 be 77 81 20 84 00 62 00 a4 00 6e 00 +55 01 60 80 be 77 8f 20 24 00 02 00 64 00 6e 00 +55 05 60 00 be 77 61 20 a4 00 62 00 24 00 0e 00 +55 0d 60 00 be 77 62 20 a4 00 62 00 34 00 0e 00 +55 09 60 00 be 77 68 20 a4 00 62 00 54 00 0e 00 diff --git a/src/intel/tools/tests/gen6/else.asm b/src/intel/tools/tests/gen6/else.asm new file mode 100644 index 00000000000..71a09a3996d --- /dev/null +++ b/src/intel/tools/tests/gen6/else.asm @@ -0,0 +1,3 @@ +else(8) JIP: 12 { align1 1Q }; +else(16) JIP: 12 { align1 1H }; +else(8) JIP: 18 { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/else.expected b/src/intel/tools/tests/gen6/else.expected new file mode 100644 index 00000000000..9e1b70e0ac3 --- /dev/null +++ b/src/intel/tools/tests/gen6/else.expected @@ -0,0 +1,3 @@ +24 00 60 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00 +24 00 80 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00 +24 01 60 00 8f 10 12 00 04 00 6e 00 04 00 6e 00 diff --git a/src/intel/tools/tests/gen6/endif.asm b/src/intel/tools/tests/gen6/endif.asm new file mode 100644 index 00000000000..b3a5066cb53 --- /dev/null +++ b/src/intel/tools/tests/gen6/endif.asm @@ -0,0 +1,3 @@ +endif(8) JIP: 2 { align16 1Q }; +endif(8) JIP: 2 { align1 1Q }; +endif(16) JIP: 2 { align1 1H }; diff --git a/src/intel/tools/tests/gen6/endif.expected b/src/intel/tools/tests/gen6/endif.expected new file mode 100644 index 00000000000..8bfc53eb0b0 --- /dev/null +++ b/src/intel/tools/tests/gen6/endif.expected @@ -0,0 +1,3 @@ +25 01 60 00 8f 10 02 00 04 00 6e 00 04 00 6e 00 +25 00 60 00 8f 10 02 00 00 00 8d 00 00 00 8d 00 +25 00 80 00 8f 10 02 00 00 00 8d 00 00 00 8d 00 diff --git a/src/intel/tools/tests/gen6/frc.asm b/src/intel/tools/tests/gen6/frc.asm new file mode 100644 index 00000000000..7639a63b3e4 --- /dev/null +++ b/src/intel/tools/tests/gen6/frc.asm @@ -0,0 +1,6 @@ +frc.sat(8) m4<1>F g3<4>F { align16 1Q }; +frc(8) g19<1>.xF (abs)g1<0>.xF { align16 1Q }; +frc(8) g12<1>F g6<8,8,1>F { align1 1Q }; +frc(16) g18<1>F g9<8,8,1>F { align1 1H }; +frc(8) m1<1>F g9<8,8,1>F { align1 1Q }; +frc(16) m1<1>F g11<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen6/frc.expected b/src/intel/tools/tests/gen6/frc.expected new file mode 100644 index 00000000000..c643a289788 --- /dev/null +++ b/src/intel/tools/tests/gen6/frc.expected @@ -0,0 +1,6 @@ +43 01 60 80 be 03 8f 20 64 00 6e 00 00 00 00 00 +43 01 60 00 bd 03 61 22 20 20 00 00 00 00 00 00 +43 00 60 00 bd 03 80 21 c0 00 8d 00 00 00 00 00 +43 00 80 00 bd 03 40 22 20 01 8d 00 00 00 00 00 +43 00 60 00 be 03 20 20 20 01 8d 00 00 00 00 00 +43 00 80 00 be 03 20 20 60 01 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/halt.asm b/src/intel/tools/tests/gen6/halt.asm new file mode 100644 index 00000000000..3674b30d6ba --- /dev/null +++ b/src/intel/tools/tests/gen6/halt.asm @@ -0,0 +1,4 @@ +(-f0.1.any4h) halt(8) JIP: 96 UIP: 98 { align1 1Q }; +halt(8) JIP: 2 UIP: 2 { align1 1Q }; +(-f0.1.any4h) halt(16) JIP: 100 UIP: 102 { align1 1H }; +halt(16) JIP: 2 UIP: 2 { align1 1H }; diff --git a/src/intel/tools/tests/gen6/halt.expected b/src/intel/tools/tests/gen6/halt.expected new file mode 100644 index 00000000000..b5b612af45d --- /dev/null +++ b/src/intel/tools/tests/gen6/halt.expected @@ -0,0 +1,4 @@ +2a 00 76 00 84 1c 00 20 00 00 8d 02 60 00 62 00 +2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00 +2a 00 96 00 84 1c 00 20 00 00 8d 02 64 00 66 00 +2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00 diff --git a/src/intel/tools/tests/gen6/if.asm b/src/intel/tools/tests/gen6/if.asm new file mode 100644 index 00000000000..532dbda784e --- /dev/null +++ b/src/intel/tools/tests/gen6/if.asm @@ -0,0 +1,6 @@ +(+f0.0) if(8) JIP: 84 { align16 1Q }; +(+f0.0) if(8) JIP: 32 { align1 1Q }; +(+f0.0) if(16) JIP: 32 { align1 1H }; +(+f0.0.x) if(8) JIP: 18 { align16 1Q }; +(-f0.0) if(8) JIP: 12 { align1 1Q }; +(-f0.0) if(16) JIP: 12 { align1 1H }; diff --git a/src/intel/tools/tests/gen6/if.expected b/src/intel/tools/tests/gen6/if.expected new file mode 100644 index 00000000000..e5a2666c0d6 --- /dev/null +++ b/src/intel/tools/tests/gen6/if.expected @@ -0,0 +1,6 @@ +22 01 61 00 8f 10 54 00 04 00 0e 00 04 00 0e 00 +22 00 61 00 8f 10 20 00 00 00 00 00 00 00 00 00 +22 00 81 00 8f 10 20 00 00 00 00 00 00 00 00 00 +22 01 62 00 8f 10 12 00 04 00 0e 00 04 00 0e 00 +22 00 71 00 8f 10 0c 00 00 00 00 00 00 00 00 00 +22 00 91 00 8f 10 0c 00 00 00 00 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/lrp.asm b/src/intel/tools/tests/gen6/lrp.asm new file mode 100644 index 00000000000..eaae1db07f6 --- /dev/null +++ b/src/intel/tools/tests/gen6/lrp.asm @@ -0,0 +1,8 @@ +lrp(8) g10<1>.xF g2.2<0,1,0>F g2.1<0,1,0>F g2.0<0,1,0>F { align16 1Q }; +lrp(8) m1<1>F g34<4,4,1>F g4<4,4,1>F g64<4,4,1>F { align16 1Q }; +lrp(8) m2<1>F g2<4,4,1>F g6<4,4,1>F g13<4,4,1>F { align16 2Q }; +lrp.sat(8) g7<1>F g12<4,4,1>F g15<4,4,1>F g18<4,4,1>F { align16 1Q }; +lrp.sat(8) g18<1>F g26<4,4,1>F g13<4,4,1>F g38<4,4,1>F { align16 2Q }; +lrp(8) g2<1>F g18<4,4,1>F g2<4,4,1>F g8<4,4,1>F { align16 2Q }; +lrp.sat(8) m1<1>F g6<4,4,1>F g13<4,4,1>F g4<4,4,1>F { align16 1Q }; +lrp.sat(8) m2<1>F g9<4,4,1>F g27<4,4,1>F g17<4,4,1>F { align16 2Q }; diff --git a/src/intel/tools/tests/gen6/lrp.expected b/src/intel/tools/tests/gen6/lrp.expected new file mode 100644 index 00000000000..deb5789bb41 --- /dev/null +++ b/src/intel/tools/tests/gen6/lrp.expected @@ -0,0 +1,8 @@ +5c 01 60 00 00 00 02 0a 01 24 20 40 04 04 80 00 +5c 01 60 00 01 00 1e 01 c8 21 02 39 08 20 07 10 +5c 11 60 00 01 00 1e 02 c8 21 00 39 0c 20 47 03 +5c 01 60 80 00 00 1e 07 c8 c1 00 39 1e 20 87 04 +5c 11 60 80 00 00 1e 12 c8 a1 01 39 1a 20 87 09 +5c 11 60 00 00 00 1e 02 c8 21 01 39 04 20 07 02 +5c 01 60 80 01 00 1e 01 c8 61 00 39 1a 20 07 01 +5c 11 60 80 01 00 1e 02 c8 91 00 39 36 20 47 04 diff --git a/src/intel/tools/tests/gen6/lzd.asm b/src/intel/tools/tests/gen6/lzd.asm new file mode 100644 index 00000000000..d9ba85681ba --- /dev/null +++ b/src/intel/tools/tests/gen6/lzd.asm @@ -0,0 +1,3 @@ +lzd(8) g16<1>UD g17<4>UD { align16 1Q }; +lzd(8) g4<1>UD g5<8,8,1>UD { align1 1Q }; +lzd(16) g4<1>UD g6<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen6/lzd.expected b/src/intel/tools/tests/gen6/lzd.expected new file mode 100644 index 00000000000..18c1fec06e5 --- /dev/null +++ b/src/intel/tools/tests/gen6/lzd.expected @@ -0,0 +1,3 @@ +4a 01 60 00 21 00 0f 22 24 02 6e 00 00 00 00 00 +4a 00 60 00 21 00 80 20 a0 00 8d 00 00 00 00 00 +4a 00 80 00 21 00 80 20 c0 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/mach.asm b/src/intel/tools/tests/gen6/mach.asm new file mode 100644 index 00000000000..45eb5a39eba --- /dev/null +++ b/src/intel/tools/tests/gen6/mach.asm @@ -0,0 +1,13 @@ +mach(8) g12<1>UD g10<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable }; +mach(8) g16<1>D g10<8,8,1>D 1431655766D { align1 1Q AccWrEnable }; +mach(16) g17<1>UD g14<8,8,1>UD 0xaaaaaaabUD { align1 1H AccWrEnable }; +mach(16) g25<1>D g14<8,8,1>D 1431655766D { align1 1H AccWrEnable }; +mach(8) g9<1>D g1<0>D g1.4<0>D { align16 1Q AccWrEnable }; +mach(8) null<1>D g1<4>.xD 741092396D { align16 1Q AccWrEnable }; +mach(8) g12<1>UD g4<8,8,1>UD g8<8,8,1>UD { align1 1Q AccWrEnable }; +mach(16) g20<1>UD g4<8,8,1>UD g12<8,8,1>UD { align1 1H AccWrEnable }; +mach(8) g13<1>D g5<8,8,1>D g9<8,8,1>D { align1 1Q AccWrEnable }; +mach(16) g21<1>D g5<8,8,1>D g13<8,8,1>D { align1 1H AccWrEnable }; +mach(8) null<1>D g9<4>D g11<4>D { align16 1Q AccWrEnable }; +mach(8) g24<1>.xUD g22<4>.xUD 0x80000001UD { align16 1Q AccWrEnable }; +mach(8) g12<1>UD g9<4>UD g11<4>UD { align16 1Q AccWrEnable }; diff --git a/src/intel/tools/tests/gen6/mach.expected b/src/intel/tools/tests/gen6/mach.expected new file mode 100644 index 00000000000..9799450164f --- /dev/null +++ b/src/intel/tools/tests/gen6/mach.expected @@ -0,0 +1,13 @@ +49 00 60 10 21 0c 80 21 40 01 8d 00 ab aa aa aa +49 00 60 10 a5 1c 00 22 40 01 8d 00 56 55 55 55 +49 00 80 10 21 0c 20 22 c0 01 8d 00 ab aa aa aa +49 00 80 10 a5 1c 20 23 c0 01 8d 00 56 55 55 55 +49 01 60 10 a5 14 2f 21 24 00 0e 00 34 00 0e 00 +49 01 60 10 a4 1c 0f 20 20 00 60 00 2c 2c 2c 2c +49 00 60 10 21 04 80 21 80 00 8d 00 00 01 8d 00 +49 00 80 10 21 04 80 22 80 00 8d 00 80 01 8d 00 +49 00 60 10 a5 14 a0 21 a0 00 8d 00 20 01 8d 00 +49 00 80 10 a5 14 a0 22 a0 00 8d 00 a0 01 8d 00 +49 01 60 10 a4 14 0f 20 24 01 6e 00 64 01 6e 00 +49 01 60 10 21 0c 01 23 c0 02 60 00 01 00 00 80 +49 01 60 10 21 04 8f 21 24 01 6e 00 64 01 6e 00 diff --git a/src/intel/tools/tests/gen6/mad.asm b/src/intel/tools/tests/gen6/mad.asm new file mode 100644 index 00000000000..164bfca6d8a --- /dev/null +++ b/src/intel/tools/tests/gen6/mad.asm @@ -0,0 +1,41 @@ +mad(8) g11<1>F g4.7<0,1,0>F g4.3<0,1,0>F g9<4,4,1>F { align16 1Q }; +mad(8) g17<1>F g6.7<0,1,0>F g6.3<0,1,0>F g13<4,4,1>F { align16 2Q }; +mad(8) m4<1>.xyzF g9<4,4,1>.xyzzF g6<4,4,1>.xyzzF g30<4,4,1>.xyzzF { align16 NoDDClr 1Q }; +mad(8) m3<1>F g20<4,4,1>F g5<4,4,1>.wF g22<4,4,1>F { align16 1Q }; +mad.le.f0.0(8) g5<1>F g3<4,4,1>F g4.2<0,1,0>F g21<4,4,1>F { align16 1Q }; +mad.le.f0.0(8) g4<1>F g2<4,4,1>F g6.2<0,1,0>F g24<4,4,1>F { align16 2Q }; +mad(8) m2<1>F g26<4,4,1>F g10<4,4,1>F g18<4,4,1>F { align16 2Q }; +mad(8) g5<1>F -g3.0<0,1,0>F g2.3<0,1,0>F g2.0<0,1,0>F { align16 1Q }; +mad(8) g5<1>F -g3.0<0,1,0>F g2.3<0,1,0>F g2.0<0,1,0>F { align16 2Q }; +mad.sat(8) m4<1>F g26<4,4,1>F g4.7<0,1,0>F g10<4,4,1>F { align16 1Q }; +mad.sat(8) m4<1>.xyzF g109<4,4,1>.xyzzF g100<4,4,1>.xyzzF g107<4,4,1>.zF { align16 NoDDClr 1Q }; +mad(8) g42<1>F g41<4,4,1>F g4.2<0,1,0>F -g64.0<0,1,0>F { align16 1Q }; +mad(8) g58<1>F -g57<4,4,1>F g53<4,4,1>F -g53<4,4,1>F { align16 1Q }; +mad(8) g76<1>F -g56<4,4,1>F -g64.1<0,1,0>F -g53<4,4,1>F { align16 1Q }; +mad.sat(8) g44<1>F g43<4,4,1>F g41<4,4,1>F g26<4,4,1>F { align16 1Q }; +mad(8) g4<1>F g2<4,4,1>F g6.2<0,1,0>F -g12.0<0,1,0>F { align16 2Q }; +mad(8) g2<1>F -g22<4,4,1>F g14<4,4,1>F -g14<4,4,1>F { align16 2Q }; +mad(8) g43<1>F -g20<4,4,1>F -g12.1<0,1,0>F -g14<4,4,1>F { align16 2Q }; +mad.sat(8) g12<1>F g4<4,4,1>F g68<4,4,1>F g14<4,4,1>F { align16 2Q }; +mad(8) m2<1>F g11<4,4,1>F g9<4,4,1>F -g18.1<0,1,0>F { align16 1Q }; +mad(8) m4<1>F g2<4,4,1>F g15<4,4,1>F -g64.1<0,1,0>F { align16 2Q }; +mad(8) m3<1>F -g11.1<0,1,0>F g2<4,4,1>F g9<4,4,1>F { align16 1Q }; +mad(8) m3<1>.xF g1<4,4,1>.xF g9<4,4,1>.xF g2<4,4,1>.xF { align16 NoDDChk 1Q }; +mad(8) g30<1>F g44.4<0,1,0>F -g44.5<0,1,0>F g27<4,4,1>F { align16 1Q }; +mad(8) g2<1>F g45.4<0,1,0>F -g45.5<0,1,0>F g5<4,4,1>F { align16 2Q }; +mad.sat(8) m4<1>.xyzF -g9<4,4,1>.xyzzF g8<4,4,1>.zxyyF g6<4,4,1>.yzxxF { align16 NoDDClr 1Q }; +mad(8) g3<1>.yF g17<4,4,1>.yF g6<4,4,1>.xF g19<4,4,1>.xF { align16 NoDDClr 1Q }; +mad(8) g2<1>F -g2<4,4,1>F (abs)g8<4,4,1>F g17.0<0,1,0>F { align16 1Q }; +mad(8) g13<1>F -g5<4,4,1>F (abs)g3<4,4,1>F g17.0<0,1,0>F { align16 2Q }; +mad(8) m2<1>F -g64.0<0,1,0>F g64.1<0,1,0>F g10<4,4,1>F { align16 2Q }; +mad(8) g5<1>F -g20.0<0,1,0>F g11<4,4,1>F (abs)g6<4,4,1>F { align16 1Q }; +mad(8) g13<1>F g20.1<0,1,0>F g5<4,4,1>F (abs)g6<4,4,1>F { align16 1Q }; +mad(8) g3<1>F -g25.0<0,1,0>F g6<4,4,1>F (abs)g10<4,4,1>F { align16 2Q }; +mad(8) g4<1>F g25.1<0,1,0>F g3<4,4,1>F (abs)g10<4,4,1>F { align16 2Q }; +mad(8) g7<1>.zF g79<4,4,1>.xF g36<4,4,1>.xF g1.3<0,1,0>F { align16 NoDDClr,NoDDChk 1Q }; +mad(8) g8<1>.wF g92<4,4,1>.xF g52<4,4,1>.xF g1.3<0,1,0>F { align16 NoDDChk 1Q }; +mad(8) g5<1>.xF -g16<4,4,1>.xF g2.2<0,1,0>F g1.5<0,1,0>F { align16 NoDDClr 1Q }; +mad(8) g6<1>.yF -g23<4,4,1>.xF g2.2<0,1,0>F g1.0<0,1,0>F { align16 NoDDClr,NoDDChk 1Q }; +mad(8) g5<1>.zF -g26<4,4,1>.xF g1.6<0,1,0>F g1.1<0,1,0>F { align16 NoDDChk 1Q }; +mad.nz.f0.0(8) g13<1>F -g23.0<0,1,0>F g9<4,4,1>F g12<4,4,1>F { align16 1Q }; +mad.nz.f0.0(8) g19<1>F -g30.0<0,1,0>F g10<4,4,1>F g17<4,4,1>F { align16 2Q }; diff --git a/src/intel/tools/tests/gen6/mad.expected b/src/intel/tools/tests/gen6/mad.expected new file mode 100644 index 00000000000..217141ecbcb --- /dev/null +++ b/src/intel/tools/tests/gen6/mad.expected @@ -0,0 +1,41 @@ +5b 01 60 00 00 00 1e 0b 01 4e 20 c0 08 20 47 02 +5b 11 60 00 00 00 1e 11 01 6e 20 c0 0c 20 47 03 +5b 05 60 00 01 00 0e 04 48 91 00 29 0c 20 85 07 +5b 01 60 00 01 00 1e 03 c8 41 c1 3f 0a 20 87 05 +5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 47 05 +5b 11 60 06 00 00 1e 04 c8 21 20 80 0c 20 07 06 +5b 11 60 00 01 00 1e 02 c8 a1 01 39 14 20 87 04 +5b 01 60 00 20 00 1e 05 01 30 20 c0 04 04 80 00 +5b 11 60 00 20 00 1e 05 01 30 20 c0 04 04 80 00 +5b 01 60 80 01 00 1e 04 c8 a1 21 c0 09 20 87 02 +5b 05 60 80 01 00 0e 04 48 d1 06 29 c8 50 c5 1a +5b 01 60 00 00 02 1e 2a c8 91 22 80 08 04 00 10 +5b 01 60 00 20 02 1e 3a c8 91 03 39 6a 20 47 0d +5b 01 60 00 a0 02 1e 4c c8 81 23 40 80 20 47 0d +5b 01 60 80 00 00 1e 2c c8 b1 02 39 52 20 87 06 +5b 11 60 00 00 02 1e 04 c8 21 20 80 0c 04 00 03 +5b 11 60 00 20 02 1e 02 c8 61 01 39 1c 20 87 03 +5b 11 60 00 a0 02 1e 2b c8 41 21 40 18 20 87 03 +5b 11 60 80 00 00 1e 0c c8 41 00 39 88 20 87 03 +5b 01 60 00 01 02 1e 02 c8 b1 00 39 12 04 88 04 +5b 11 60 00 01 02 1e 04 c8 21 00 39 1e 04 08 10 +5b 01 60 00 21 00 1e 03 01 b2 00 39 04 20 47 02 +5b 09 60 00 01 00 02 03 00 10 00 00 12 00 80 00 +5b 01 60 00 80 00 1e 1e 01 c8 22 40 59 20 c7 06 +5b 11 60 00 80 00 1e 02 01 d8 22 40 5b 20 47 01 +5b 05 60 80 21 00 0e 04 48 91 80 14 10 48 80 01 +5b 05 60 00 00 00 04 03 aa 10 01 00 0c 00 c0 04 +5b 01 60 00 60 00 1e 02 c8 21 00 39 10 04 40 04 +5b 11 60 00 60 00 1e 0d c8 51 00 39 06 04 40 04 +5b 11 60 00 21 00 1e 02 01 00 24 40 80 20 87 02 +5b 01 60 00 20 01 1e 05 01 40 01 39 16 20 87 01 +5b 01 60 00 00 01 1e 0d 01 42 01 39 0a 20 87 01 +5b 11 60 00 20 01 1e 03 01 90 01 39 0c 20 87 02 +5b 11 60 00 00 01 1e 04 01 92 01 39 06 20 87 02 +5b 0d 60 00 00 00 08 07 00 f0 04 00 48 04 58 00 +5b 09 60 00 00 00 10 08 00 c0 05 00 68 04 58 00 +5b 05 60 00 20 00 02 05 00 00 21 80 04 04 68 00 +5b 0d 60 00 20 00 04 06 00 70 21 80 04 04 40 00 +5b 09 60 00 20 00 08 05 00 a0 21 80 03 04 48 00 +5b 01 60 02 20 00 1e 0d 01 70 01 39 12 20 07 03 +5b 11 60 02 20 00 1e 13 01 e0 01 39 14 20 47 04 diff --git a/src/intel/tools/tests/gen6/math.asm b/src/intel/tools/tests/gen6/math.asm new file mode 100644 index 00000000000..e970850f022 --- /dev/null +++ b/src/intel/tools/tests/gen6/math.asm @@ -0,0 +1,26 @@ +math inv(8) g7<1>F g10<8,8,1>F null<8,8,1>F { align1 1Q }; +math inv(8) g13<1>F g18<8,8,1>F null<8,8,1>F { align1 2Q }; +math pow(8) g16<1>F g15<8,8,1>F g14<8,8,1>F { align1 1Q }; +math pow(8) g24<1>F g22<8,8,1>F g20<8,8,1>F { align1 2Q }; +math cos(8) g3<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; +math cos(8) g5<1>F g3<8,8,1>F null<8,8,1>F { align1 2Q }; +math sqrt(8) g16<1>F g15<8,8,1>F null<8,8,1>F { align1 1Q }; +math log(8) g21<1>F g20<8,8,1>F null<8,8,1>F { align1 1Q }; +math sqrt(8) g11<1>F g3<8,8,1>F null<8,8,1>F { align1 2Q }; +math log(8) g2<1>F g13<8,8,1>F null<8,8,1>F { align1 2Q }; +math sin(8) g23<1>F g22<4,4,1>F null<8,8,1>F { align1 1Q }; +math exp(8) g18<1>F g17<4,4,1>F null<8,8,1>F { align1 1Q }; +math exp(8) g19<1>F g8<8,8,1>F null<8,8,1>F { align1 2Q }; +math rsq(8) g71<1>F g70<4,4,1>F null<8,8,1>F { align1 1Q }; +math sin(8) g6<1>F g4<8,8,1>F null<8,8,1>F { align1 2Q }; +math rsq(8) g3<1>F g5<8,8,1>F null<8,8,1>F { align1 2Q }; +math.sat pow(8) g4<1>F g7<8,8,1>F g13<8,8,1>F { align1 1Q }; +math.sat pow(8) g2<1>F g8<8,8,1>F g14<8,8,1>F { align1 2Q }; +math.sat sqrt(8) g4<1>F g9<8,8,1>F null<8,8,1>F { align1 1Q }; +math.sat sqrt(8) g2<1>F g6<8,8,1>F null<8,8,1>F { align1 2Q }; +math.sat exp(8) g2<1>F g5<8,8,1>F null<8,8,1>F { align1 1Q }; +math.sat exp(8) g3<1>F g8<8,8,1>F null<8,8,1>F { align1 2Q }; +math intmod(8) g45<1>UD g44<8,8,1>UD g13<8,8,1>UD { align1 1Q }; +math intdiv(8) g52<1>D g51<8,8,1>D g12<8,8,1>D { align1 1Q }; +math intmod(8) g75<1>UD g73<8,8,1>UD g15<8,8,1>UD { align1 2Q }; +math intdiv(8) g87<1>D g85<8,8,1>D g13<8,8,1>D { align1 2Q }; diff --git a/src/intel/tools/tests/gen6/math.expected b/src/intel/tools/tests/gen6/math.expected new file mode 100644 index 00000000000..a4313089a2d --- /dev/null +++ b/src/intel/tools/tests/gen6/math.expected @@ -0,0 +1,26 @@ +38 00 60 01 bd 73 e0 20 40 01 8d 00 00 00 8d 00 +38 10 60 01 bd 73 a0 21 40 02 8d 00 00 00 8d 00 +38 00 60 0a bd 77 00 22 e0 01 8d 00 c0 01 8d 00 +38 10 60 0a bd 77 00 23 c0 02 8d 00 80 02 8d 00 +38 00 60 07 bd 73 60 20 40 00 8d 00 00 00 8d 00 +38 10 60 07 bd 73 a0 20 60 00 8d 00 00 00 8d 00 +38 00 60 04 bd 73 00 22 e0 01 8d 00 00 00 8d 00 +38 00 60 02 bd 73 a0 22 80 02 8d 00 00 00 8d 00 +38 10 60 04 bd 73 60 21 60 00 8d 00 00 00 8d 00 +38 10 60 02 bd 73 40 20 a0 01 8d 00 00 00 8d 00 +38 00 60 06 bd 73 e0 22 c0 02 69 00 00 00 8d 00 +38 00 60 03 bd 73 40 22 20 02 69 00 00 00 8d 00 +38 10 60 03 bd 73 60 22 00 01 8d 00 00 00 8d 00 +38 00 60 05 bd 73 e0 28 c0 08 69 00 00 00 8d 00 +38 10 60 06 bd 73 c0 20 80 00 8d 00 00 00 8d 00 +38 10 60 05 bd 73 60 20 a0 00 8d 00 00 00 8d 00 +38 00 60 8a bd 77 80 20 e0 00 8d 00 a0 01 8d 00 +38 10 60 8a bd 77 40 20 00 01 8d 00 c0 01 8d 00 +38 00 60 84 bd 73 80 20 20 01 8d 00 00 00 8d 00 +38 10 60 84 bd 73 40 20 c0 00 8d 00 00 00 8d 00 +38 00 60 83 bd 73 40 20 a0 00 8d 00 00 00 8d 00 +38 10 60 83 bd 73 60 20 00 01 8d 00 00 00 8d 00 +38 00 60 0d 21 04 a0 25 80 05 8d 00 a0 01 8d 00 +38 00 60 0c a5 14 80 26 60 06 8d 00 80 01 8d 00 +38 10 60 0d 21 04 60 29 20 09 8d 00 e0 01 8d 00 +38 10 60 0c a5 14 e0 2a a0 0a 8d 00 a0 01 8d 00 diff --git a/src/intel/tools/tests/gen6/mov.asm b/src/intel/tools/tests/gen6/mov.asm new file mode 100644 index 00000000000..797850033be --- /dev/null +++ b/src/intel/tools/tests/gen6/mov.asm @@ -0,0 +1,164 @@ +mov(8) g7<1>F g4<8,8,1>D { align1 1Q }; +mov(8) m1<1>F g7<8,8,1>F { align1 1Q }; +mov(16) g7<1>F g5<8,8,1>D { align1 1H }; +mov(16) m1<1>F g7<8,8,1>F { align1 1H }; +mov(8) m2<1>D 0D { align16 1Q }; +mov(8) m3<1>F 0x41880000F /* 17F */ { align16 1Q }; +mov(8) m1<1>UD g0<4>UD { align16 WE_all 1Q }; +mov.sat(8) m4<1>F g4<4>F { align16 1Q }; +mov(8) m2<1>.wF g5<4>.xF { align16 1Q }; +mov(4) m2<1>F g2.3<8,2,4>F { align1 WE_all 1N }; +mov(8) m2<1>D g3.3<0,1,0>D { align1 1Q }; +mov(8) m5<1>UD g4.7<0,1,0>D { align1 1Q }; +mov(8) g10<1>F g2<0,1,0>F { align1 1Q }; +mov(8) m2<1>F 0x0F /* 0F */ { align1 1Q }; +mov(16) m2<1>D g3.3<0,1,0>D { align1 1H }; +mov(16) m8<1>UD g4.7<0,1,0>D { align1 1H }; +mov(16) g17<1>F g2<0,1,0>F { align1 1H }; +mov(16) m3<1>F 0x0F /* 0F */ { align1 1H }; +mov(8) m5<1>UD 0D { align1 1Q }; +mov(8) g2<1>F g6<8,4,1>UW { align1 1Q }; +mov(8) g7<1>D g2<8,8,1>F { align1 1Q }; +mov(8) m2<1>D g11<8,8,1>F { align1 1Q }; +mov(16) m8<1>UD 0D { align1 1H }; +mov(16) g2<1>F g4<8,8,1>UW { align1 1H }; +mov(16) g8<1>D g2<8,8,1>F { align1 1H }; +mov(16) m2<1>D g16<8,8,1>F { align1 1H }; +mov(8) m1<1>F -g38<8,8,1>D { align1 1Q }; +mov(16) m1<1>F -g6<8,8,1>D { align1 1H }; +mov(1) m22<1>D 0D { align1 WE_all 1N }; +mov(8) m23<1>D g3<0>D { align16 1Q }; +mov(8) g28<1>.xD 1D { align16 1Q }; +mov(1) m22<1>D g39<0,1,0>D { align1 WE_all 1N }; +mov(8) m4<1>.xD 1059749626D { align16 NoDDClr 1Q }; +mov(8) m4<1>.yD 1143373824D { align16 NoDDClr,NoDDChk 1Q }; +mov(8) m5<1>.yD -1093874483D { align16 NoDDChk 1Q }; +mov(8) m5<1>.xzF 0x7e0020VF /* [0.5F, 0F, 30F, 0F]VF */ { align16 NoDDChk 1Q }; +mov(8) m1<1>F g0<8,8,1>F { align1 WE_all 1Q }; +mov(1) m1.2<1>UD 0x000003f2UD { align1 WE_all 1N }; +mov(8) m2<1>F g16<8,8,1>F { align1 2Q }; +mov(8) g5<1>F 0x30003000VF /* [0F, 1F, 0F, 1F]VF */ { align16 1Q }; +mov(8) m4<1>F 0x30003000VF /* [0F, 1F, 0F, 1F]VF */ { align16 1Q }; +mov(8) g21<1>F g11<8,8,1>F { align1 2Q }; +mov(1) g0.2<1>UD 0x00000000UD { align1 WE_all 1N }; +mov(8) g6<1>.xUD 0x00000000UD { align16 1Q }; +mov(8) g20<1>.xD 0x00000000UD { align16 1Q }; +mov(8) g21<1>UD 0x00000000UD { align16 WE_all 1Q }; +mov(8) m2<1>.xyzD g3.4<0>.xyzzD { align16 NoDDClr 1Q }; +mov(8) g22<1>.xD g6<4>.xUD { align16 1Q }; +mov(8) g27<1>UD 7D { align16 1Q }; +mov(1) m1.1<1>UD g9<0,1,0>UD { align1 WE_all 1N }; +mov(8) m2<1>F g30<4>F { align16 WE_all 1Q }; +mov(8) g13<1>D 0D { align1 1Q }; +mov(16) g9<1>D 0D { align1 1H }; +mov.sat(8) m1<1>F g2<0,1,0>F { align1 1Q }; +mov.sat(16) m1<1>F g2<0,1,0>F { align1 1H }; +mov(8) g16<1>UD g1.4<0>UD { align16 1Q }; +mov(8) m4<1>.wD g9<4>.wD { align16 NoDDChk 1Q }; +mov(8) g19<1>.xD g18<4>.xF { align16 1Q }; +mov(8) m4<1>F g[a0]<VxH,1,0>F { align1 1Q switch }; +mov(8) m8<1>F g[a0]<VxH,1,0>F { align1 2Q switch }; +mov(8) m2<1>UD 0x00000000UD { align1 1Q }; +mov(16) m2<1>UD 0x00000000UD { align1 1H }; +mov(8) m3<1>F g14<4>.xD { align16 1Q }; +mov.sat(8) m4<1>.xF 0x3f800000F /* 1F */ { align16 NoDDClr 1Q }; +mov.sat(8) m4<1>.yF 0x3f666666F /* 0.9F */ { align16 NoDDClr,NoDDChk 1Q }; +mov.sat(8) m4<1>.wF 0x3f333333F /* 0.7F */ { align16 NoDDChk 1Q }; +mov(1) g32<1>F 0x40000000F /* 2F */ { align1 WE_all 1N }; +mov(8) m17<1>UD g0<8,8,1>UD { align1 WE_all 1Q }; +mov(8) g12<1>F g11<4>D { align16 1Q }; +mov(8) g30<1>.xyD g3.4<0>.xyyyD { align16 NoDDClr 1Q }; +mov(8) g30<1>.wD 0D { align16 NoDDChk 1Q }; +mov(4) g28<1>F g23.1<4,4,1>F { align1 WE_all 1N }; +mov(8) g26<1>UD 0x403000VF /* [0F, 1F, 2F, 0F]VF */ { align16 WE_all 1Q }; +mov(4) m2<1>UD g101<4>UD { align16 1N }; +mov(8) g19<1>.yzwD 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q }; +mov(8) g11<1>UD g11<4>F { align16 1Q }; +mov(8) g12<1>F g11<4>UD { align16 1Q }; +mov(8) m1<1>UD g3<8,8,1>UD { align1 1Q }; +mov(16) m1<1>UD g3<8,8,1>UD { align1 1H }; +mov(16) g8<1>UD g0<8,8,1>UD { align1 WE_all 1H }; +mov(8) m1<1>F g4<8,8,1>UD { align1 1Q }; +mov(16) m1<1>F g4<8,8,1>UD { align1 1H }; +mov(8) m4<1>.xF g1<0>.xD { align16 NoDDClr 1Q }; +mov(8) m4<1>.yF g40<4>.xD { align16 NoDDClr,NoDDChk 1Q }; +mov(8) g15<1>.xF g87<4>.xD { align16 NoDDClr 1Q }; +mov(8) g15<1>.yF g88<4>.xD { align16 NoDDClr,NoDDChk 1Q }; +mov(8) m4<1>.wF g42<4>.xD { align16 NoDDChk 1Q }; +mov(8) g15<1>.wF g90<4>.xD { align16 NoDDChk 1Q }; +mov(8) g7<1>F g4<8,8,1>UD { align1 1Q }; +mov(16) g7<1>F g5<8,8,1>UD { align1 1H }; +mov(8) g3<1>D g11<4>D { align16 1Q }; +mov(8) g20<1>F g14<4>.xF { align16 1Q }; +mov(8) g5<1>.yF g21<4>.yF { align16 NoDDClr 1Q }; +mov(8) g5<1>.zF g23<4>.zF { align16 NoDDClr,NoDDChk 1Q }; +mov(8) g6<1>.xzwD g5<4>.wwywD { align16 NoDDChk 1Q }; +mov(8) m3<1>.zwF 0x30000000VF /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr 1Q }; +mov.nz.f0.0(8) g4<1>F -(abs)g2<0,1,0>F { align1 1Q }; +(+f0.0) mov(8) g4<1>F 0xbf800000F /* -1F */ { align1 1Q }; +mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 1H }; +(+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 1H }; +mov(8) g21<1>.xzwD 0D { align16 NoDDClr 1Q }; +mov(8) g3<1>.yzwF 0x30000000VF /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDChk 1Q }; +mov(8) g3<1>.xD g6<4>.xD { align16 NoDDClr,NoDDChk 1Q }; +mov(8) g3<1>.xF -g18<4>.xF { align16 NoDDChk 1Q }; +mov.sat(8) g12<1>.xF g1<0>.zF { align16 1Q }; +(+f0.0.any4h) mov(8) g4<1>.xD -1D { align16 1Q }; +mov(8) m2<1>.zD g2<4>.zD { align16 NoDDClr,NoDDChk 1Q }; +mov(8) g3<1>.xyzF g1.4<0>.xyzzUD { align16 NoDDClr 1Q }; +mov(8) g3<1>.wF g1<0>.xUD { align16 NoDDChk 1Q }; +mov(8) g3<1>D -g2<0,1,0>D { align1 1Q }; +mov(16) g3<1>D -g2<0,1,0>D { align1 1H }; +mov.nz.f0.0(8) null<1>.xD g1<0>.xD { align16 1Q }; +mov(8) g2<1>UD g2<8,8,1>F { align1 1Q }; +mov(16) g2<1>UD g2<8,8,1>F { align1 1H }; +mov.sat(8) g10<1>F g2.2<0,1,0>F { align1 1Q }; +mov.sat(16) g15<1>F g2.2<0,1,0>F { align1 1H }; +mov(8) m3<1>.zwF 0D { align16 NoDDChk 1Q }; +mov.nz.f0.0(8) null<1>D g2<8,8,1>D { align1 1Q }; +mov.nz.f0.0(16) null<1>D g87<8,8,1>D { align1 1H }; +mov(8) m2<1>D 0D { align1 1Q }; +mov(16) m2<1>D 0D { align1 1H }; +mov.sat(8) m4<1>.wF g20<4>.wF { align16 NoDDChk 1Q }; +mov(8) g55<1>.zD 1045220557D { align16 NoDDClr,NoDDChk 1Q }; +(+f0.0.all4h) mov(8) g60<1>.xD -1D { align16 1Q }; +mov(8) m7<1>F 0x0F /* 0F */ { align1 2Q }; +mov.sat(8) m4<1>F 0x3f800000F /* 1F */ { align16 1Q }; +mov(8) g33<1>.xF 0x3e8F /* 1.4013e-42F */ { align16 1Q }; +mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; +(-f0.0) mov(8) g4<1>F g2<8,8,1>F { align1 1Q }; +(-f0.0) mov(8) g8<1>F g4<8,8,1>F { align1 2Q }; +mov(8) m4<1>.xF g8<4>.xF { align16 NoDDClr 1Q }; +mov(8) m4<1>.yF g8<4>.xF { align16 NoDDChk 1Q }; +mov(1) g1<1>UD g0.1<0,1,0>UD { align1 WE_all 1N }; +mov(1) g7.14<1>UW f0.1<0,1,0>UW { align1 WE_all 1N }; +mov(8) g12<1>UW 0x32103210V { align1 WE_all 1Q }; +mov.sat(8) m4<1>F -g6<4>D { align16 1Q }; +mov(8) m5<1>.yF g4<4>.yF { align16 NoDDClr,NoDDChk 1Q }; +mov(8) g12<1>.xD acc0<4>D { align16 1Q }; +mov(8) m8<1>.xyzD 0x737271VF /* [17F, 18F, 19F, 0F]VF */ { align16 1Q }; +mov(8) m7<1>.zwD 0x706e0000VF /* [0F, 0F, 15F, 16F]VF */ { align16 NoDDChk 1Q }; +mov.sat(8) m4<1>.xyzF -g13<4>.xyzzD { align16 NoDDClr 1Q }; +mov(8) m2<1>UD 0x0F /* 0F */ { align1 1Q }; +mov(16) m2<1>UD 0x0F /* 0F */ { align1 1H }; +mov(8) m1<1>UD g4<8,8,1>UD { align1 WE_all 2Q }; +mov(8) m4<1>.yF 0x40a00000F /* 5F */ { align16 NoDDChk 1Q }; +mov(8) g6<1>UD 0D { align1 1Q }; +mov(16) g8<1>UD 0D { align1 1H }; +mov(8) m4<1>.yzF 0x484000VF /* [0F, 2F, 3F, 0F]VF */ { align16 NoDDClr,NoDDChk 1Q }; +mov(8) m4<1>F g10<4>UD { align16 1Q }; +mov(8) g20<1>.yzD 0x404800VF /* [0F, 3F, 2F, 0F]VF */ { align16 NoDDChk 1Q }; +mov.sat(8) m4<1>.yzF g1<0>.xxzzF { align16 NoDDClr,NoDDChk 1Q }; +mov.sat(8) m4<1>.xF -g1<0>.wF { align16 NoDDClr 1Q }; +mov.sat(8) m4<1>.yF -g11<4>.xD { align16 NoDDClr,NoDDChk 1Q }; +mov.sat(8) m4<1>.wF -g13<4>.xD { align16 NoDDChk 1Q }; +mov(8) m1<1>UD g9<8,8,1>F { align1 1Q }; +mov(16) m1<1>UD g11<8,8,1>F { align1 1H }; +mov(8) g84<1>UD g80.1<16,8,2>UW { align1 1Q }; +mov(16) g45<1>UD g37.1<16,8,2>UW { align1 1H }; +mov(8) g48<1>UD g44.3<32,8,4>UB { align1 1Q }; +mov(16) g99<1>UD g91.3<32,8,4>UB { align1 1H }; +mov.z.f0.0(8) null<1>D g22<8,8,1>F { align1 1Q }; +mov.z.f0.0(16) null<1>D g28<8,8,1>F { align1 1H }; +mov.nz.f0.0(8) g11<1>F -(abs)g1<0>F { align16 1Q }; +(+f0.0) mov(8) g11<1>F 0xbf800000F /* -1F */ { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/mov.expected b/src/intel/tools/tests/gen6/mov.expected new file mode 100644 index 00000000000..634f0d841f1 --- /dev/null +++ b/src/intel/tools/tests/gen6/mov.expected @@ -0,0 +1,164 @@ +01 00 60 00 bd 00 e0 20 80 00 8d 00 00 00 00 00 +01 00 60 00 be 03 20 20 e0 00 8d 00 00 00 00 00 +01 00 80 00 bd 00 e0 20 a0 00 8d 00 00 00 00 00 +01 00 80 00 be 03 20 20 e0 00 8d 00 00 00 00 00 +01 01 60 00 e6 10 4f 20 00 00 00 00 00 00 00 00 +01 01 60 00 fe 73 6f 20 00 00 00 00 00 00 88 41 +01 03 60 00 22 00 2f 20 04 00 6e 00 00 00 00 00 +01 01 60 80 be 03 8f 20 84 00 6e 00 00 00 00 00 +01 01 60 00 be 03 48 20 a0 00 60 00 00 00 00 00 +01 02 40 00 be 03 40 20 4c 00 87 00 00 00 00 00 +01 00 60 00 a6 00 40 20 6c 00 00 00 00 00 00 00 +01 00 60 00 a2 00 a0 20 9c 00 00 00 00 00 00 00 +01 00 60 00 bd 03 40 21 40 00 00 00 00 00 00 00 +01 00 60 00 fe 73 40 20 00 00 00 00 00 00 00 00 +01 00 80 00 a6 00 40 20 6c 00 00 00 00 00 00 00 +01 00 80 00 a2 00 00 21 9c 00 00 00 00 00 00 00 +01 00 80 00 bd 03 20 22 40 00 00 00 00 00 00 00 +01 00 80 00 fe 73 60 20 00 00 00 00 00 00 00 00 +01 00 60 00 e2 10 a0 20 00 00 00 00 00 00 00 00 +01 00 60 00 3d 01 40 20 c0 00 89 00 00 00 00 00 +01 00 60 00 a5 03 e0 20 40 00 8d 00 00 00 00 00 +01 00 60 00 a6 03 40 20 60 01 8d 00 00 00 00 00 +01 00 80 00 e2 10 00 21 00 00 00 00 00 00 00 00 +01 00 80 00 3d 01 40 20 80 00 8d 00 00 00 00 00 +01 00 80 00 a5 03 00 21 40 00 8d 00 00 00 00 00 +01 00 80 00 a6 03 40 20 00 02 8d 00 00 00 00 00 +01 00 60 00 be 00 20 20 c0 44 8d 00 00 00 00 00 +01 00 80 00 be 00 20 20 c0 40 8d 00 00 00 00 00 +01 02 00 00 e6 10 c0 22 00 00 00 00 00 00 00 00 +01 01 60 00 a6 00 ef 22 64 00 0e 00 00 00 00 00 +01 01 60 00 e5 10 81 23 00 00 00 00 01 00 00 00 +01 02 00 00 a6 00 c0 22 e0 04 00 00 00 00 00 00 +01 05 60 00 e6 10 81 20 00 00 00 00 fa 7e 2a 3f +01 0d 60 00 e6 10 82 20 00 00 00 00 00 80 26 44 +01 09 60 00 e6 10 a2 20 00 00 00 00 cd cc cc be +01 09 60 00 fe 52 a5 20 00 00 00 00 20 00 7e 00 +01 02 60 00 be 03 20 20 00 00 8d 00 00 00 00 00 +01 02 00 00 62 00 28 20 00 00 00 00 f2 03 00 00 +01 10 60 00 be 03 40 20 00 02 8d 00 00 00 00 00 +01 01 60 00 fd 52 af 20 00 00 00 00 00 30 00 30 +01 01 60 00 fe 52 8f 20 00 00 00 00 00 30 00 30 +01 10 60 00 bd 03 a0 22 60 01 8d 00 00 00 00 00 +01 02 00 00 61 00 08 20 00 00 00 00 00 00 00 00 +01 01 60 00 61 00 c1 20 00 00 00 00 00 00 00 00 +01 01 60 00 65 00 81 22 00 00 00 00 00 00 00 00 +01 03 60 00 61 00 af 22 00 00 00 00 00 00 00 00 +01 05 60 00 a6 00 47 20 74 00 0a 00 00 00 00 00 +01 01 60 00 25 00 c1 22 c0 00 60 00 00 00 00 00 +01 01 60 00 e1 10 6f 23 00 00 00 00 07 00 00 00 +01 02 00 00 22 00 24 20 20 01 00 00 00 00 00 00 +01 03 60 00 be 03 4f 20 c4 03 6e 00 00 00 00 00 +01 00 60 00 e5 10 a0 21 00 00 00 00 00 00 00 00 +01 00 80 00 e5 10 20 21 00 00 00 00 00 00 00 00 +01 00 60 80 be 03 20 20 40 00 00 00 00 00 00 00 +01 00 80 80 be 03 20 20 40 00 00 00 00 00 00 00 +01 01 60 00 21 00 0f 22 34 00 0e 00 00 00 00 00 +01 09 60 00 a6 00 88 20 2f 01 6f 00 00 00 00 00 +01 01 60 00 a5 03 61 22 40 02 60 00 00 00 00 00 +01 80 60 00 be 03 80 20 00 80 e0 01 00 00 00 00 +01 90 60 00 be 03 00 21 00 80 e0 01 00 00 00 00 +01 00 60 00 62 00 40 20 00 00 00 00 00 00 00 00 +01 00 80 00 62 00 40 20 00 00 00 00 00 00 00 00 +01 01 60 00 be 00 6f 20 c0 01 60 00 00 00 00 00 +01 05 60 80 fe 73 81 20 00 00 00 00 00 00 80 3f +01 0d 60 80 fe 73 82 20 00 00 00 00 66 66 66 3f +01 09 60 80 fe 73 88 20 00 00 00 00 33 33 33 3f +01 02 00 00 fd 73 00 24 00 00 00 00 00 00 00 40 +01 02 60 00 22 00 20 22 00 00 8d 00 00 00 00 00 +01 01 60 00 bd 00 8f 21 64 01 6e 00 00 00 00 00 +01 05 60 00 a5 00 c3 23 74 00 05 00 00 00 00 00 +01 09 60 00 e5 10 c8 23 00 00 00 00 00 00 00 00 +01 02 40 00 bd 03 80 23 e4 02 69 00 00 00 00 00 +01 03 60 00 e1 52 4f 23 00 00 00 00 00 30 40 00 +01 01 40 00 22 00 4f 20 a4 0c 6e 00 00 00 00 00 +01 01 60 00 e5 52 6e 22 00 00 00 00 00 30 40 48 +01 01 60 00 a1 03 6f 21 64 01 6e 00 00 00 00 00 +01 01 60 00 3d 00 8f 21 64 01 6e 00 00 00 00 00 +01 00 60 00 22 00 20 20 60 00 8d 00 00 00 00 00 +01 00 80 00 22 00 20 20 60 00 8d 00 00 00 00 00 +01 02 80 00 21 00 00 21 00 00 8d 00 00 00 00 00 +01 00 60 00 3e 00 20 20 80 00 8d 00 00 00 00 00 +01 00 80 00 3e 00 20 20 80 00 8d 00 00 00 00 00 +01 05 60 00 be 00 81 20 20 00 00 00 00 00 00 00 +01 0d 60 00 be 00 82 20 00 05 60 00 00 00 00 00 +01 05 60 00 bd 00 e1 21 e0 0a 60 00 00 00 00 00 +01 0d 60 00 bd 00 e2 21 00 0b 60 00 00 00 00 00 +01 09 60 00 be 00 88 20 40 05 60 00 00 00 00 00 +01 09 60 00 bd 00 e8 21 40 0b 60 00 00 00 00 00 +01 00 60 00 3d 00 e0 20 80 00 8d 00 00 00 00 00 +01 00 80 00 3d 00 e0 20 a0 00 8d 00 00 00 00 00 +01 01 60 00 a5 00 6f 20 64 01 6e 00 00 00 00 00 +01 01 60 00 bd 03 8f 22 c0 01 60 00 00 00 00 00 +01 05 60 00 bd 03 a2 20 a5 02 65 00 00 00 00 00 +01 0d 60 00 bd 03 a4 20 ea 02 6a 00 00 00 00 00 +01 09 60 00 a5 00 cd 20 af 00 6d 00 00 00 00 00 +01 05 60 00 fe 52 6c 20 00 00 00 00 00 00 00 30 +01 00 60 02 bd 03 80 20 40 60 00 00 00 00 00 00 +01 00 61 00 fd 73 80 20 00 00 00 00 00 00 80 bf +01 00 80 02 bd 03 80 20 40 60 00 00 00 00 00 00 +01 00 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf +01 05 60 00 e5 10 ad 22 00 00 00 00 00 00 00 00 +01 09 60 00 fd 52 6e 20 00 00 00 00 00 00 00 30 +01 0d 60 00 a5 00 61 20 c0 00 60 00 00 00 00 00 +01 09 60 00 bd 03 61 20 40 42 60 00 00 00 00 00 +01 01 60 80 bd 03 81 21 2a 00 0a 00 00 00 00 00 +01 01 66 00 e5 10 81 20 00 00 00 00 ff ff ff ff +01 0d 60 00 a6 00 44 20 4a 00 6a 00 00 00 00 00 +01 05 60 00 3d 00 67 20 34 00 0a 00 00 00 00 00 +01 09 60 00 3d 00 68 20 20 00 00 00 00 00 00 00 +01 00 60 00 a5 00 60 20 40 40 00 00 00 00 00 00 +01 00 80 00 a5 00 60 20 40 40 00 00 00 00 00 00 +01 01 60 02 a4 00 01 20 20 00 00 00 00 00 00 00 +01 00 60 00 a1 03 40 20 40 00 8d 00 00 00 00 00 +01 00 80 00 a1 03 40 20 40 00 8d 00 00 00 00 00 +01 00 60 80 bd 03 40 21 48 00 00 00 00 00 00 00 +01 00 80 80 bd 03 e0 21 48 00 00 00 00 00 00 00 +01 09 60 00 fe 10 6c 20 00 00 00 00 00 00 00 00 +01 00 60 02 a4 00 00 20 40 00 8d 00 00 00 00 00 +01 00 80 02 a4 00 00 20 e0 0a 8d 00 00 00 00 00 +01 00 60 00 e6 10 40 20 00 00 00 00 00 00 00 00 +01 00 80 00 e6 10 40 20 00 00 00 00 00 00 00 00 +01 09 60 80 be 03 88 20 8f 02 6f 00 00 00 00 00 +01 0d 60 00 e5 10 e4 26 00 00 00 00 cd cc 4c 3e +01 01 67 00 e5 10 81 27 00 00 00 00 ff ff ff ff +01 10 60 00 fe 73 e0 20 00 00 00 00 00 00 00 00 +01 01 60 80 fe 73 8f 20 00 00 00 00 00 00 80 3f +01 01 60 00 fd 73 21 24 00 00 00 00 e8 03 00 00 +01 02 00 00 28 01 00 26 3c 00 00 00 00 00 00 00 +01 00 71 00 bd 03 80 20 40 00 8d 00 00 00 00 00 +01 10 71 00 bd 03 00 21 80 00 8d 00 00 00 00 00 +01 05 60 00 be 03 81 20 00 01 60 00 00 00 00 00 +01 09 60 00 be 03 82 20 00 01 60 00 00 00 00 00 +01 02 00 00 21 00 20 20 04 00 00 00 00 00 00 00 +01 02 00 00 09 01 fc 20 02 06 00 00 00 00 00 00 +01 02 60 00 69 63 80 21 00 00 00 00 10 32 10 32 +01 01 60 80 be 00 8f 20 c4 40 6e 00 00 00 00 00 +01 0d 60 00 be 03 a2 20 85 00 65 00 00 00 00 00 +01 01 60 00 85 00 81 21 04 04 6e 00 00 00 00 00 +01 01 60 00 e6 52 07 21 00 00 00 00 71 72 73 00 +01 09 60 00 e6 52 ec 20 00 00 00 00 00 00 6e 70 +01 05 60 80 be 00 87 20 a4 41 6a 00 00 00 00 00 +01 00 60 00 e2 73 40 20 00 00 00 00 00 00 00 00 +01 00 80 00 e2 73 40 20 00 00 00 00 00 00 00 00 +01 12 60 00 22 00 20 20 80 00 8d 00 00 00 00 00 +01 09 60 00 fe 73 82 20 00 00 00 00 00 00 a0 40 +01 00 60 00 e1 10 c0 20 00 00 00 00 00 00 00 00 +01 00 80 00 e1 10 00 21 00 00 00 00 00 00 00 00 +01 0d 60 00 fe 52 86 20 00 00 00 00 00 40 48 00 +01 01 60 00 3e 00 8f 20 44 01 6e 00 00 00 00 00 +01 09 60 00 e5 52 86 22 00 00 00 00 00 48 40 00 +01 0d 60 80 be 03 86 20 20 00 0a 00 00 00 00 00 +01 05 60 80 be 03 81 20 2f 40 0f 00 00 00 00 00 +01 0d 60 80 be 00 82 20 60 41 60 00 00 00 00 00 +01 09 60 80 be 00 88 20 a0 41 60 00 00 00 00 00 +01 00 60 00 a2 03 20 20 20 01 8d 00 00 00 00 00 +01 00 80 00 a2 03 20 20 60 01 8d 00 00 00 00 00 +01 00 60 00 21 01 80 2a 02 0a ae 00 00 00 00 00 +01 00 80 00 21 01 a0 25 a2 04 ae 00 00 00 00 00 +01 00 60 00 21 02 00 26 83 05 cf 00 00 00 00 00 +01 00 80 00 21 02 60 2c 63 0b cf 00 00 00 00 00 +01 00 60 01 a4 03 00 20 c0 02 8d 00 00 00 00 00 +01 00 80 01 a4 03 00 20 80 03 8d 00 00 00 00 00 +01 01 60 02 bd 03 6f 21 24 60 0e 00 00 00 00 00 +01 01 61 00 fd 73 6f 21 00 00 00 00 00 00 80 bf diff --git a/src/intel/tools/tests/gen6/mul.asm b/src/intel/tools/tests/gen6/mul.asm new file mode 100644 index 00000000000..6fb1567088e --- /dev/null +++ b/src/intel/tools/tests/gen6/mul.asm @@ -0,0 +1,62 @@ +mul(8) m3<1>F g2<8,8,1>F g8<8,8,1>F { align1 1Q }; +mul(16) m5<1>F g2<8,8,1>F g14<8,8,1>F { align1 1H }; +mul(8) g7<1>F g44<8,8,1>F g4.1<0,1,0>F { align1 1Q }; +mul(16) g18<1>F g28<8,8,1>F g6.1<0,1,0>F { align1 1H }; +mul(8) g39<1>.xD g28<4>.xD g5<0>.xD { align16 1Q }; +mul(8) g39<1>.xD g39<4>.xD 2D { align16 1Q }; +mul(8) g38<1>.xF g2<0>.yF g2<0>.yF { align16 1Q }; +mul(8) m4<1>.xyF g6<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr 1Q }; +mul(8) g8<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 1Q }; +mul(8) g2<1>F g5<8,8,1>F 0x40490fdbF /* 3.14159F */ { align1 1Q }; +mul(16) g2<1>F g7<8,8,1>F 0x40490fdbF /* 3.14159F */ { align1 1H }; +mul(8) m4<1>F g12<4>F 0x3b808081F /* 0.00392157F */ { align16 1Q }; +mul(8) g61<1>UD g61<4>UD 0x00000003UD { align16 1Q }; +mul(8) m1<1>F g6<8,8,1>F 0x3c23d70aF /* 0.01F */ { align1 1Q }; +mul(16) m1<1>F g10<8,8,1>F 0x3c23d70aF /* 0.01F */ { align1 1H }; +mul(8) g41<1>F g40<4>.yF 0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q }; +mul(8) g3<1>.wF g23<4>.xF 0x3f000000F /* 0.5F */ { align16 NoDDClr 1Q }; +mul.sat(8) g10<1>F g9<8,8,1>F 0x40a00001F /* 5F */ { align1 1Q }; +mul.sat(16) g13<1>F g11<8,8,1>F 0x40a00001F /* 5F */ { align1 1H }; +mul(8) acc0<1>UD g10<8,8,1>UD 0xaaaaaaabUD { align1 1Q }; +mul(8) acc0<1>D g10<8,8,1>D 1431655766D { align1 1Q }; +mul(8) g14<1>D g14<8,8,1>D g13<8,8,1>D { align1 1Q }; +mul(16) acc0<1>UD g14<8,8,1>UD 0xaaaaaaabUD { align1 1H }; +mul(16) acc0<1>D g14<8,8,1>D 1431655766D { align1 1H }; +mul(16) g21<1>D g23<8,8,1>D g19<8,8,1>D { align1 1H }; +mul(8) m4<1>.yF g12<4>.xF 0x3b800000F /* 0.00390625F */ { align16 NoDDChk 1Q }; +mul(8) g3<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 1Q }; +mul(16) g3<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 1H }; +mul(8) acc0<1>D g1<0>D g1.4<0>D { align16 1Q }; +mul.l.f0.0(8) g20<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1Q }; +mul.l.f0.0(16) g14<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1H }; +mul(8) m3<1>.xF g15<4>.xF 0x40a66666F /* 5.2F */ { align16 NoDDClr,NoDDChk 1Q }; +mul.sat(8) m4<1>F g6<4>F 0x3b800000F /* 0.00390625F */ { align16 1Q }; +mul(8) acc0<1>D g1<4>.xD 741092396D { align16 1Q }; +mul(8) acc0<1>UD g4<8,8,1>UD g8<8,8,1>UD { align1 1Q }; +mul(16) acc0<1>UD g4<8,8,1>UD g12<8,8,1>UD { align1 1H }; +mul(8) m3<1>.xyzF g2<4>.xyzzF g11<4>.xF { align16 NoDDClr 1Q }; +mul.sat(8) m2<1>F g6<8,8,1>F g5<8,8,1>F { align1 1Q }; +mul.sat(16) m2<1>F g12<8,8,1>F g10<8,8,1>F { align1 1H }; +mul(8) acc0<1>D g5<8,8,1>D g9<8,8,1>D { align1 1Q }; +mul(16) acc0<1>D g5<8,8,1>D g13<8,8,1>D { align1 1H }; +mul.sat(8) m4<1>F g2<4>F g2<4>F { align16 1Q }; +mul(8) m3<1>F g2<4>F g3<4>F { align16 1Q }; +mul(8) g3<1>D g2<0,1,0>UW 1774483385D { align1 1Q }; +mul(16) g3<1>D g2<0,1,0>UW 1774483385D { align1 1H }; +mul(8) g15<1>.zF g61<4>.xF 0x3e800000F /* 0.25F */ { align16 NoDDClr,NoDDChk 1Q }; +mul(8) acc0<1>UD g22<4>.xUD 0x80000001UD { align16 1Q }; +mul.nz.f0.0(8) g6<1>F g12<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1Q }; +mul.nz.f0.0(16) g9<1>F g7<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1H }; +mul.sat(8) m4<1>.xyF g1<0>.wzzzF g3<4>.wzzzF { align16 NoDDClr 1Q }; +mul.sat(8) m4<1>.zwF g1<0>.yyyxF g3<4>.yyyxF { align16 NoDDChk 1Q }; +mul.sat(8) m4<1>F g4<4>F 0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 1Q }; +mul(8) g4<1>.xyzF g16<4>.zyxxF g20<4>.xF { align16 NoDDClr 1Q }; +mul(8) acc0<1>UD g9<4>UD g11<4>UD { align16 1Q }; +mul(8) m4<1>F g3<4>F 0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 1Q }; +mul(8) m4<1>.xyzF g3<4>.xyzzF 0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr 1Q }; +mul(8) g3<1>.wF g1<0>.zF g11<4>.xF { align16 NoDDClr,NoDDChk 1Q }; +mul(8) m4<1>.yF g15<4>.xF g11<4>.xF { align16 NoDDClr,NoDDChk 1Q }; +mul(8) m5<1>.yF g31<4>.xF g11<4>.xF { align16 NoDDChk 1Q }; +mul(8) m17<1>D g10<8,8,1>D g9<8,8,1>D { align1 1Q }; +mul(16) m17<1>D g16<8,8,1>D g14<8,8,1>D { align1 1H }; +mul.sat(8) m4<1>.xyzF g12<4>.xF 0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr 1Q }; diff --git a/src/intel/tools/tests/gen6/mul.expected b/src/intel/tools/tests/gen6/mul.expected new file mode 100644 index 00000000000..7b85bb5b5ac --- /dev/null +++ b/src/intel/tools/tests/gen6/mul.expected @@ -0,0 +1,62 @@ +41 00 60 00 be 77 60 20 40 00 8d 00 00 01 8d 00 +41 00 80 00 be 77 a0 20 40 00 8d 00 c0 01 8d 00 +41 00 60 00 bd 77 e0 20 80 05 8d 00 84 00 00 00 +41 00 80 00 bd 77 40 22 80 03 8d 00 c4 00 00 00 +41 01 60 00 a5 14 e1 24 80 03 60 00 a0 00 00 00 +41 01 60 00 a5 1c e1 24 e0 04 60 00 02 00 00 00 +41 01 60 00 bd 77 c1 24 45 00 05 00 45 00 05 00 +41 05 60 00 be 7f 83 20 c4 00 65 00 00 00 00 3f +41 01 60 00 bd 7f 0f 21 64 00 6e 00 00 00 80 37 +41 00 60 00 bd 7f 40 20 a0 00 8d 00 db 0f 49 40 +41 00 80 00 bd 7f 40 20 e0 00 8d 00 db 0f 49 40 +41 01 60 00 be 7f 8f 20 84 01 6e 00 81 80 80 3b +41 01 60 00 21 0c af 27 a4 07 6e 00 03 00 00 00 +41 00 60 00 be 7f 20 20 c0 00 8d 00 0a d7 23 3c +41 00 80 00 be 7f 20 20 40 01 8d 00 0a d7 23 3c +41 01 60 00 bd 5f 2f 25 05 05 65 00 00 30 00 00 +41 05 60 00 bd 7f 68 20 e0 02 60 00 00 00 00 3f +41 00 60 80 bd 7f 40 21 20 01 8d 00 01 00 a0 40 +41 00 80 80 bd 7f a0 21 60 01 8d 00 01 00 a0 40 +41 00 60 00 20 0c 00 24 40 01 8d 00 ab aa aa aa +41 00 60 00 a4 1c 00 24 40 01 8d 00 56 55 55 55 +41 00 60 00 a5 14 c0 21 c0 01 8d 00 a0 01 8d 00 +41 00 80 00 20 0c 00 24 c0 01 8d 00 ab aa aa aa +41 00 80 00 a4 1c 00 24 c0 01 8d 00 56 55 55 55 +41 00 80 00 a5 14 a0 22 e0 02 8d 00 60 02 8d 00 +41 09 60 00 be 7f 82 20 80 01 60 00 00 00 80 3b +41 00 60 00 25 15 60 20 40 00 00 00 48 00 00 00 +41 00 80 00 25 15 60 20 40 00 00 00 48 00 00 00 +41 01 60 00 a4 14 0f 24 24 00 0e 00 34 00 0e 00 +41 00 60 05 bd 7f 80 22 40 00 8d 00 00 00 70 42 +41 00 80 05 bd 7f c0 21 40 00 8d 00 00 00 70 42 +41 0d 60 00 be 7f 61 20 e0 01 60 00 66 66 a6 40 +41 01 60 80 be 7f 8f 20 c4 00 6e 00 00 00 80 3b +41 01 60 00 a4 1c 0f 24 20 00 60 00 2c 2c 2c 2c +41 00 60 00 20 04 00 24 80 00 8d 00 00 01 8d 00 +41 00 80 00 20 04 00 24 80 00 8d 00 80 01 8d 00 +41 05 60 00 be 77 67 20 44 00 6a 00 60 01 60 00 +41 00 60 80 be 77 40 20 c0 00 8d 00 a0 00 8d 00 +41 00 80 80 be 77 40 20 80 01 8d 00 40 01 8d 00 +41 00 60 00 a4 14 00 24 a0 00 8d 00 20 01 8d 00 +41 00 80 00 a4 14 00 24 a0 00 8d 00 a0 01 8d 00 +41 01 60 80 be 77 8f 20 44 00 6e 00 44 00 6e 00 +41 01 60 00 be 77 6f 20 44 00 6e 00 64 00 6e 00 +41 00 60 00 25 1d 60 20 40 00 00 00 b9 77 c4 69 +41 00 80 00 25 1d 60 20 40 00 00 00 b9 77 c4 69 +41 0d 60 00 bd 7f e4 21 a0 07 60 00 00 00 80 3e +41 01 60 00 20 0c 0f 24 c0 02 60 00 01 00 00 80 +41 00 60 02 bd 7f c0 20 80 01 8d 00 00 80 80 3f +41 00 80 02 bd 7f 20 21 e0 00 8d 00 00 80 80 3f +41 05 60 80 be 77 83 20 2b 00 0a 00 6b 00 6a 00 +41 09 60 80 be 77 8c 20 25 00 01 00 65 00 61 00 +41 01 60 80 be 5f 8f 20 84 00 6e 00 30 30 30 20 +41 05 60 00 bd 77 87 20 06 02 60 00 80 02 60 00 +41 01 60 00 20 04 0f 24 24 01 6e 00 64 01 6e 00 +41 01 60 00 be 5f 8f 20 64 00 6e 00 54 54 30 20 +41 05 60 00 be 5f 87 20 64 00 6a 00 20 20 30 30 +41 0d 60 00 bd 77 68 20 2a 00 0a 00 60 01 60 00 +41 0d 60 00 be 77 82 20 e0 01 60 00 60 01 60 00 +41 09 60 00 be 77 a2 20 e0 03 60 00 60 01 60 00 +41 00 60 00 a6 14 20 22 40 01 8d 00 20 01 8d 00 +41 00 80 00 a6 14 20 22 00 02 8d 00 c0 01 8d 00 +41 05 60 80 be 5f 87 20 80 01 60 00 30 30 00 00 diff --git a/src/intel/tools/tests/gen6/not.asm b/src/intel/tools/tests/gen6/not.asm new file mode 100644 index 00000000000..380433af6ac --- /dev/null +++ b/src/intel/tools/tests/gen6/not.asm @@ -0,0 +1,4 @@ +not(8) g29<1>.xD g26<4>.xD { align16 1Q }; +not.nz.f0.0(8) null<1>.xD g13<4>.xD { align16 1Q }; +not(8) g20<1>D g19<8,8,1>D { align1 1Q }; +not(16) g27<1>D g25<8,8,1>D { align1 1H }; diff --git a/src/intel/tools/tests/gen6/not.expected b/src/intel/tools/tests/gen6/not.expected new file mode 100644 index 00000000000..1d38da63129 --- /dev/null +++ b/src/intel/tools/tests/gen6/not.expected @@ -0,0 +1,4 @@ +04 01 60 00 a5 00 a1 23 40 03 60 00 00 00 00 00 +04 01 60 02 a4 00 01 20 a0 01 60 00 00 00 00 00 +04 00 60 00 a5 00 80 22 60 02 8d 00 00 00 00 00 +04 00 80 00 a5 00 60 23 20 03 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/or.asm b/src/intel/tools/tests/gen6/or.asm new file mode 100644 index 00000000000..aa3de469889 --- /dev/null +++ b/src/intel/tools/tests/gen6/or.asm @@ -0,0 +1,15 @@ +or(8) g29<1>UD g9<4>.xUD 0x00000014UD { align16 1Q }; +or(8) g43<1>UD g44<4>UD 1D { align16 1Q }; +or(1) g28<1>UD g28<0,1,0>UD g57<0,1,0>UD { align1 1N }; +or(8) g10<1>UD g9<8,8,1>UD g8<8,8,1>UD { align1 1Q }; +or(16) g16<1>UD g14<8,8,1>UD g12<8,8,1>UD { align1 1H }; +or(1) g9<1>UD g0<0,1,0>UD 0x00000800UD { align1 WE_all 1N }; +or.nz.f0.0(8) null<1>.xUD g17<4>.xUD g16<4>.xUD { align16 1Q }; +or.nz.f0.0(8) null<1>UD g16<8,8,1>UD g17<8,8,1>UD { align1 1Q }; +(+f0.0) or(8) g18<1>UD g18<8,8,1>UD 0x3f800000UD { align1 1Q }; +or.nz.f0.0(16) null<1>UD g28<8,8,1>UD g30<8,8,1>UD { align1 1H }; +(+f0.0) or(16) g31<1>UD g31<8,8,1>UD 0x3f800000UD { align1 1H }; +(+f0.0) or(8) g22<1>.xUD g22<4>.xUD 0x3f800000UD { align16 1Q }; +or.nz.f0.0(8) g8<1>UD g4<8,8,1>UD g7<8,8,1>UD { align1 1Q }; +or.nz.f0.0(16) g12<1>UD g5<8,8,1>UD g10<8,8,1>UD { align1 1H }; +or(8) g4<1>.xUD g57<4>.xUD g56<4>.xUD { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/or.expected b/src/intel/tools/tests/gen6/or.expected new file mode 100644 index 00000000000..ccaacac9467 --- /dev/null +++ b/src/intel/tools/tests/gen6/or.expected @@ -0,0 +1,15 @@ +06 01 60 00 21 0c af 23 20 01 60 00 14 00 00 00 +06 01 60 00 21 1c 6f 25 84 05 6e 00 01 00 00 00 +06 00 00 00 21 04 80 23 80 03 00 00 20 07 00 00 +06 00 60 00 21 04 40 21 20 01 8d 00 00 01 8d 00 +06 00 80 00 21 04 00 22 c0 01 8d 00 80 01 8d 00 +06 02 00 00 21 0c 20 21 00 00 00 00 00 08 00 00 +06 01 60 02 20 04 01 20 20 02 60 00 00 02 60 00 +06 00 60 02 20 04 00 20 00 02 8d 00 20 02 8d 00 +06 00 61 00 21 0c 40 22 40 02 8d 00 00 00 80 3f +06 00 80 02 20 04 00 20 80 03 8d 00 c0 03 8d 00 +06 00 81 00 21 0c e0 23 e0 03 8d 00 00 00 80 3f +06 01 61 00 21 0c c1 22 c0 02 60 00 00 00 80 3f +06 00 60 02 21 04 00 21 80 00 8d 00 e0 00 8d 00 +06 00 80 02 21 04 80 21 a0 00 8d 00 40 01 8d 00 +06 01 60 00 21 04 81 20 20 07 60 00 00 07 60 00 diff --git a/src/intel/tools/tests/gen6/pln.asm b/src/intel/tools/tests/gen6/pln.asm new file mode 100644 index 00000000000..179e2fa2e4b --- /dev/null +++ b/src/intel/tools/tests/gen6/pln.asm @@ -0,0 +1,12 @@ +pln(8) m1<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln(16) m1<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln(8) g41<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln(16) g22<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.sat(8) g8<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.sat(16) g7<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.g.f0.0(8) g7<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.g.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.l.f0.0(8) g8<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.l.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; +pln.nz.f0.0(8) g18<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; +pln.nz.f0.0(16) g14<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen6/pln.expected b/src/intel/tools/tests/gen6/pln.expected new file mode 100644 index 00000000000..f35a3ed85fc --- /dev/null +++ b/src/intel/tools/tests/gen6/pln.expected @@ -0,0 +1,12 @@ +5a 00 60 00 be 77 20 20 80 00 00 00 40 00 8d 00 +5a 00 80 00 be 77 20 20 c0 00 00 00 40 00 8d 00 +5a 00 60 00 bd 77 20 25 a0 00 00 00 40 00 8d 00 +5a 00 80 00 bd 77 c0 22 e0 00 00 00 40 00 8d 00 +5a 00 60 80 bd 77 00 21 80 00 00 00 40 00 8d 00 +5a 00 80 80 bd 77 e0 20 c0 00 00 00 40 00 8d 00 +5a 00 60 03 bd 77 e0 20 80 00 00 00 40 00 8d 00 +5a 00 80 03 bd 77 60 21 c0 00 00 00 40 00 8d 00 +5a 00 60 05 bd 77 00 21 80 00 00 00 40 00 8d 00 +5a 00 80 05 bd 77 60 21 c0 00 00 00 40 00 8d 00 +5a 00 60 02 bd 77 40 22 a0 00 00 00 40 00 8d 00 +5a 00 80 02 bd 77 c0 21 e0 00 00 00 40 00 8d 00 diff --git a/src/intel/tools/tests/gen6/rndd.asm b/src/intel/tools/tests/gen6/rndd.asm new file mode 100644 index 00000000000..0a0e25d53fb --- /dev/null +++ b/src/intel/tools/tests/gen6/rndd.asm @@ -0,0 +1,7 @@ +rndd(8) g18<1>.xF g1<0>.xF { align16 1Q }; +rndd(8) g3<1>F g5<8,8,1>F { align1 1Q }; +rndd(16) g8<1>F g6<8,8,1>F { align1 1H }; +rndd(8) g6<1>.zF g22<4>.xF { align16 NoDDClr 1Q }; +rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q }; +rndd.z.f0.0(16) null<1>F g28<8,8,1>F { align1 1H }; +rndd.sat(8) m4<1>F g6<4>F { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/rndd.expected b/src/intel/tools/tests/gen6/rndd.expected new file mode 100644 index 00000000000..778037a86fc --- /dev/null +++ b/src/intel/tools/tests/gen6/rndd.expected @@ -0,0 +1,7 @@ +45 01 60 00 bd 03 41 22 20 00 00 00 00 00 00 00 +45 00 60 00 bd 03 60 20 a0 00 8d 00 00 00 00 00 +45 00 80 00 bd 03 00 21 c0 00 8d 00 00 00 00 00 +45 05 60 00 bd 03 c4 20 c0 02 60 00 00 00 00 00 +45 00 60 01 bc 03 00 20 20 02 8d 00 00 00 00 00 +45 00 80 01 bc 03 00 20 80 03 8d 00 00 00 00 00 +45 01 60 80 be 03 8f 20 c4 00 6e 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/rnde.asm b/src/intel/tools/tests/gen6/rnde.asm new file mode 100644 index 00000000000..10d6924bc76 --- /dev/null +++ b/src/intel/tools/tests/gen6/rnde.asm @@ -0,0 +1,2 @@ +rnde(8) g6<1>F g3<8,8,1>F { align1 1Q }; +rnde(16) g8<1>F g4<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen6/rnde.expected b/src/intel/tools/tests/gen6/rnde.expected new file mode 100644 index 00000000000..374f68c6bb0 --- /dev/null +++ b/src/intel/tools/tests/gen6/rnde.expected @@ -0,0 +1,2 @@ +46 00 60 00 bd 03 c0 20 60 00 8d 00 00 00 00 00 +46 00 80 00 bd 03 00 21 80 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/rndz.asm b/src/intel/tools/tests/gen6/rndz.asm new file mode 100644 index 00000000000..975bac6030a --- /dev/null +++ b/src/intel/tools/tests/gen6/rndz.asm @@ -0,0 +1,3 @@ +rndz(8) g9<1>.xyzF g1<0>.xyzzF { align16 1Q }; +rndz(8) g6<1>F g5<8,8,1>F { align1 1Q }; +rndz(16) g8<1>F g6<8,8,1>F { align1 1H }; diff --git a/src/intel/tools/tests/gen6/rndz.expected b/src/intel/tools/tests/gen6/rndz.expected new file mode 100644 index 00000000000..56068d9a010 --- /dev/null +++ b/src/intel/tools/tests/gen6/rndz.expected @@ -0,0 +1,3 @@ +47 01 60 00 bd 03 27 21 24 00 0a 00 00 00 00 00 +47 00 60 00 bd 03 c0 20 a0 00 8d 00 00 00 00 00 +47 00 80 00 bd 03 00 21 c0 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen6/sel.asm b/src/intel/tools/tests/gen6/sel.asm new file mode 100644 index 00000000000..03a8fe5ff30 --- /dev/null +++ b/src/intel/tools/tests/gen6/sel.asm @@ -0,0 +1,58 @@ +(+f0.0) sel(8) g40<1>UD g5<4>UD g6<4>UD { align16 1Q }; +(-f0.0) sel(8) g6<1>UD g13<8,8,1>UD 0x00000000UD { align1 1Q }; +(-f0.0) sel(16) g7<1>UD g9<8,8,1>UD 0x00000000UD { align1 1H }; +(+f0.0) sel(8) g2<1>UD g31<8,8,1>UD g34<8,8,1>UD { align1 1Q }; +(+f0.0) sel(8) m1<1>UD g67<8,8,1>UD 0x3f800000UD { align1 1Q }; +(+f0.0) sel(16) g2<1>UD g35<8,8,1>UD g41<8,8,1>UD { align1 1H }; +(+f0.0) sel(16) m1<1>UD g31<8,8,1>UD 0x3f800000UD { align1 1H }; +(+f0.0.all4h) sel(8) g45<1>UD g23<4>UD g24<4>UD { align16 1Q }; +sel.ge(8) g64<1>F g5<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +sel.ge(16) g17<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 1H }; +sel.ge(8) g3<1>.yF g7<4>.xF 0x0F /* 0F */ { align16 1Q }; +sel.l(8) g11<1>.xF g7<4>.wF 0x43000000F /* 128F */ { align16 1Q }; +(-f0.0.z) sel(8) g3<1>.zUD g17<4>.xUD 0x00000000UD { align16 1Q }; +(+f0.0.x) sel(8) g32<1>.xUD g12<4>.yUD 0x41a80000UD { align16 1Q }; +(-f0.0.x) sel(8) g33<1>.xUD g32<4>.xUD 0x41b80000UD { align16 1Q }; +(+f0.0) sel(8) m1<1>UD g9<8,8,1>UD g12<8,8,1>UD { align1 1Q }; +(+f0.0) sel(16) m1<1>UD g15<8,8,1>UD g21<8,8,1>UD { align1 1H }; +sel.ge(8) g20<1>F g19<8,8,1>F g16<8,8,1>F { align1 1Q }; +sel.ge(16) g12<1>F g10<8,8,1>F g8<8,8,1>F { align1 1H }; +sel.sat.l(8) m4<1>F g2<4>F 0x3f000000F /* 0.5F */ { align16 1Q }; +(+f0.0.x) sel(8) g46<1>.xUD g72<4>.yUD g72<4>.xUD { align16 1Q }; +sel.l(8) g13<1>.xF g1<0>.wF g1<0>.zF { align16 1Q }; +sel.ge(8) g13<1>.xF g1<0>.wF g1<0>.zF { align16 1Q }; +(+f0.0.any4h) sel(8) g15<1>UD g14<4>UD g4<4>UD { align16 1Q }; +(-f0.0.any4h) sel(8) g67<1>.xUD g63<4>.xUD 0x00000000UD { align16 1Q }; +(-f0.0) sel(8) m1<1>UD g13<8,8,1>UD 0x3f800000UD { align1 1Q }; +(-f0.0) sel(16) m1<1>UD g22<8,8,1>UD 0x3f800000UD { align1 1H }; +sel.l(8) g10<1>F g2.3<0,1,0>F g2.2<0,1,0>F { align1 1Q }; +sel.l(16) g15<1>F g2.3<0,1,0>F g2.2<0,1,0>F { align1 1H }; +sel.ge(8) g18<1>.zD g18<4>.zD 1D { align16 1Q }; +(+f0.0) sel(8) g8<1>UD g4<8,8,1>UD 0x00000000UD { align1 1Q }; +(+f0.0) sel(16) g11<1>UD g5<8,8,1>UD 0x00000000UD { align1 1H }; +sel.ge(8) g4<1>D g3<0,1,0>D -252D { align1 1Q }; +sel.l(8) g5<1>D g4<8,8,1>D 254D { align1 1Q }; +sel.ge(16) g4<1>D g3<0,1,0>D -252D { align1 1H }; +sel.l(16) g6<1>D g4<8,8,1>D 254D { align1 1H }; +sel.sat.l(8) m4<1>F g1<0>F g3<4>F { align16 1Q }; +sel.l(8) g6<1>F g3<8,8,1>F 0x40400000F /* 3F */ { align1 1Q }; +sel.l(16) g20<1>F g14<8,8,1>F 0x40400000F /* 3F */ { align1 1H }; +(+f0.0) sel(8) g8<1>F (abs)g40<8,8,1>F g6<8,8,1>F { align1 1Q }; +(-f0.0) sel(8) g15<1>F (abs)g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; +(+f0.0) sel(16) g13<1>F (abs)g52<8,8,1>F g9<8,8,1>F { align1 1H }; +(-f0.0) sel(16) g27<1>F (abs)g25<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +(+f0.0) sel(8) g21<1>.xyzUD g19<4>.xyzzUD 0x00000000UD { align16 1Q }; +sel.l(8) m2<1>F g3<8,8,1>F g4<8,8,1>F { align1 1Q }; +sel.l(16) m3<1>F g3<8,8,1>F g5<8,8,1>F { align1 1H }; +(-f0.0.y) sel(8) g3<1>.yUD g10<4>.xUD 0x00000000UD { align16 1Q }; +(+f0.0.y) sel(8) g3<1>.yUD g1<0>.wUD g1<0>.zUD { align16 1Q }; +(-f0.0) sel(8) g28<1>UD g26<4>UD 0x00000000UD { align16 1Q }; +sel.ge(8) g22<1>.xD g3.4<0>.xD g5.4<0>.xD { align16 1Q }; +sel.l(8) m1<1>F g36<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; +sel.l(16) m1<1>F g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; +sel.sat.ge(8) m4<1>F g25<4>F 0xbf800000F /* -1F */ { align16 1Q }; +sel.ge(8) m2<1>F g5<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +sel.ge(16) m3<1>F g7<8,8,1>F 0x0F /* 0F */ { align1 1H }; +sel.l(8) g13<1>D g11<4>D 254D { align16 1Q }; +sel.sat.l(8) g47<1>F g46<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +sel.sat.l(16) g54<1>F g3<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; diff --git a/src/intel/tools/tests/gen6/sel.expected b/src/intel/tools/tests/gen6/sel.expected new file mode 100644 index 00000000000..246bc926597 --- /dev/null +++ b/src/intel/tools/tests/gen6/sel.expected @@ -0,0 +1,58 @@ +02 01 61 00 21 04 0f 25 a4 00 6e 00 c4 00 6e 00 +02 00 71 00 21 0c c0 20 a0 01 8d 00 00 00 00 00 +02 00 91 00 21 0c e0 20 20 01 8d 00 00 00 00 00 +02 00 61 00 21 04 40 20 e0 03 8d 00 40 04 8d 00 +02 00 61 00 22 0c 20 20 60 08 8d 00 00 00 80 3f +02 00 81 00 21 04 40 20 60 04 8d 00 20 05 8d 00 +02 00 81 00 22 0c 20 20 e0 03 8d 00 00 00 80 3f +02 01 67 00 21 04 af 25 e4 02 6e 00 04 03 6e 00 +02 00 60 04 bd 7f 00 28 a0 00 8d 00 00 00 00 00 +02 00 80 04 bd 7f 20 22 60 00 8d 00 00 00 00 00 +02 01 60 04 bd 7f 62 20 e0 00 60 00 00 00 00 00 +02 01 60 05 bd 7f 61 21 ef 00 6f 00 00 00 00 43 +02 01 74 00 21 0c 64 20 20 02 60 00 00 00 00 00 +02 01 62 00 21 0c 01 24 85 01 65 00 00 00 a8 41 +02 01 72 00 21 0c 21 24 00 04 60 00 00 00 b8 41 +02 00 61 00 22 04 20 20 20 01 8d 00 80 01 8d 00 +02 00 81 00 22 04 20 20 e0 01 8d 00 a0 02 8d 00 +02 00 60 04 bd 77 80 22 60 02 8d 00 00 02 8d 00 +02 00 80 04 bd 77 80 21 40 01 8d 00 00 01 8d 00 +02 01 60 85 be 7f 8f 20 44 00 6e 00 00 00 00 3f +02 01 62 00 21 04 c1 25 05 09 65 00 00 09 60 00 +02 01 60 05 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00 +02 01 60 04 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00 +02 01 66 00 21 04 ef 21 c4 01 6e 00 84 00 6e 00 +02 01 76 00 21 0c 61 28 e0 07 60 00 00 00 00 00 +02 00 71 00 22 0c 20 20 a0 01 8d 00 00 00 80 3f +02 00 91 00 22 0c 20 20 c0 02 8d 00 00 00 80 3f +02 00 60 05 bd 77 40 21 4c 00 00 00 48 00 00 00 +02 00 80 05 bd 77 e0 21 4c 00 00 00 48 00 00 00 +02 01 60 04 a5 1c 44 22 4a 02 6a 00 01 00 00 00 +02 00 61 00 21 0c 00 21 80 00 8d 00 00 00 00 00 +02 00 81 00 21 0c 60 21 a0 00 8d 00 00 00 00 00 +02 00 60 04 a5 1c 80 20 60 00 00 00 04 ff ff ff +02 00 60 05 a5 1c a0 20 80 00 8d 00 fe 00 00 00 +02 00 80 04 a5 1c 80 20 60 00 00 00 04 ff ff ff +02 00 80 05 a5 1c c0 20 80 00 8d 00 fe 00 00 00 +02 01 60 85 be 77 8f 20 24 00 0e 00 64 00 6e 00 +02 00 60 05 bd 7f c0 20 60 00 8d 00 00 00 40 40 +02 00 80 05 bd 7f 80 22 c0 01 8d 00 00 00 40 40 +02 00 61 00 bd 77 00 21 00 25 8d 00 c0 00 8d 00 +02 00 71 00 bd 7f e0 21 c0 21 8d 00 00 00 80 3f +02 00 81 00 bd 77 a0 21 80 26 8d 00 20 01 8d 00 +02 00 91 00 bd 7f 60 23 20 23 8d 00 00 00 80 3f +02 01 61 00 21 0c a7 22 64 02 6a 00 00 00 00 00 +02 00 60 05 be 77 40 20 60 00 8d 00 80 00 8d 00 +02 00 80 05 be 77 60 20 60 00 8d 00 a0 00 8d 00 +02 01 73 00 21 0c 62 20 40 01 60 00 00 00 00 00 +02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00 +02 01 71 00 21 0c 8f 23 44 03 6e 00 00 00 00 00 +02 01 60 04 a5 14 c1 22 70 00 00 00 b0 00 00 00 +02 00 60 05 be 7f 20 20 80 04 8d 00 00 00 80 3f +02 00 80 05 be 7f 20 20 c0 01 8d 00 00 00 80 3f +02 01 60 84 be 7f 8f 20 24 03 6e 00 00 00 80 bf +02 00 60 04 be 7f 40 20 a0 00 8d 00 00 00 00 00 +02 00 80 04 be 7f 60 20 e0 00 8d 00 00 00 00 00 +02 01 60 05 a5 1c af 21 64 01 6e 00 fe 00 00 00 +02 00 60 85 bd 7f e0 25 c0 05 8d 00 00 00 00 3f +02 00 80 85 bd 7f c0 26 60 00 8d 00 00 00 00 3f diff --git a/src/intel/tools/tests/gen6/send.asm b/src/intel/tools/tests/gen6/send.asm new file mode 100644 index 00000000000..fa9fe227ab5 --- /dev/null +++ b/src/intel/tools/tests/gen6/send.asm @@ -0,0 +1,516 @@ +send(8) null<1>F m1<4>F 0x8608c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 3 rlen 0 { align16 1Q EOT }; +send(8) null<1>F m1<4>F 0x8a08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 1Q EOT }; +send(8) g2<1>UW m2<8,8,1>F 0x08417001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x10827001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) g0<1>F m21<4>F 0x060920ff + render MsgDesc: OWORD dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 0 { align16 1Q }; +send(8) g41<1>F m22<4>F 0x041840ff + render MsgDesc: OWORD dual block read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x8e08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 1Q EOT }; +send(8) g2<1>UW m1<8,8,1>F 0x16494001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 11 rlen 4 { align1 1Q }; +send(8) g2<1>UW m1<8,8,1>F 0x0e494001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g3<1>UW m1<8,8,1>F 0x0e496001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g7<1>UW m1<8,8,1>F 0x0e496102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q }; +send(8) g14<1>D m2<4>F 0x04107040 + sampler MsgDesc: ld SIMD4x2 Surface = 64 Sampler = 0 mlen 2 rlen 1 { align16 1Q }; +send(8) g7<1>.xUD m1<4>UD 0x02182001 + urb MsgDesc: 0 ff_sync allocate mlen 1 rlen 1 { align16 1Q }; +send(8) g7<1>UD m1<4>F 0x0a18e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 5 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x82088400 + urb MsgDesc: 0 urb_write interleave complete mlen 1 rlen 0 { align16 1Q EOT }; +send(8) g8<1>UD m1<4>F 0x0618e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 3 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x1e084400 + urb MsgDesc: 0 urb_write interleave used mlen 15 rlen 0 { align16 1Q }; +send(8) null<1>F m1<4>F 0x8608c470 + urb MsgDesc: 7 urb_write interleave used complete mlen 3 rlen 0 { align16 1Q EOT }; +send(8) g7<1>UW m2<8,8,1>F 0x04410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g9<1>UW m2<8,8,1>F 0x08820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g7<1>UW m2<8,8,1>F 0x02410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(16) g9<1>UW m2<8,8,1>F 0x04820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(8) g24<1>UD m17<4>F 0x04184000 + dp_sampler MsgDesc: (0, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g8<1>UW m2<8,8,1>F 0x0241a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x06418002 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g11<1>UW m2<8,8,1>F 0x0482a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0c828002 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) g15<1>D m2<4>F 0x02107040 + sampler MsgDesc: ld SIMD4x2 Surface = 64 Sampler = 0 mlen 1 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x10414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q }; +send(8) g2<1>D m2<4>F 0x0210a000 + sampler MsgDesc: resinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q }; +send(8) g3<1>D m2<4>F 0x0210a101 + sampler MsgDesc: resinfo SIMD4x2 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align16 1Q }; +send(8) g5<1>D m2<4>F 0x0210a202 + sampler MsgDesc: resinfo SIMD4x2 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align16 1Q }; +send(8) g7<1>D m2<4>F 0x0210a303 + sampler MsgDesc: resinfo SIMD4x2 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align16 1Q }; +send(8) g9<1>D m2<4>F 0x0210a404 + sampler MsgDesc: resinfo SIMD4x2 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align16 1Q }; +send(8) g11<1>D m2<4>F 0x0210a505 + sampler MsgDesc: resinfo SIMD4x2 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align16 1Q }; +send(8) g13<1>D m2<4>F 0x0210a606 + sampler MsgDesc: resinfo SIMD4x2 Surface = 6 Sampler = 6 mlen 1 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x9208c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 1Q EOT }; +send(8) g2<1>UW m2<8,8,1>F 0x04419001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08829001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g13<1>UW m17<8,8,1>UD 0x02280301 + const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g11<1>D m2<4>F 0x04188001 + sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a000 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 0 mlen 1 rlen 0 { align16 1Q }; +send(8) g63<1>UD m2<4>UD 0x021ba000 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 0 mlen 1 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x0a412001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x14822001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x02419001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x04829001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x0c416001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) null<1>F m1<4>F 0x1e084470 + urb MsgDesc: 7 urb_write interleave used mlen 15 rlen 0 { align16 1Q }; +send(8) null<1>F m1<4>F 0x8e08c4e0 + urb MsgDesc: 14 urb_write interleave used complete mlen 7 rlen 0 { align16 1Q EOT }; +send(8) g2<1>UW m2<8,8,1>F 0x0a413001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x14823001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x06410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x0c820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x04418002 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08828002 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g8<1>F m2<4>F 0x02107000 + sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x9e08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 15 rlen 0 { align16 1Q EOT }; +send(8) g2<1>UW m16<8,8,1>F 0x04497001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m16<8,8,1>F 0x068a7001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H }; +send(8) g2<1>UW m1<8,8,1>F 0x08498002 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x0e8a8002 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H }; +send(8) g2<1>UW m1<8,8,1>F 0x0c491001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x168a1001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(8) g18<1>D m2<4>F 0x0210a040 + sampler MsgDesc: resinfo SIMD4x2 Surface = 64 Sampler = 0 mlen 1 rlen 1 { align16 1Q }; +send(8) g9<1>UW m2<8,8,1>F 0x0241a102 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; +send(8) g9<1>UW m2<8,8,1>F 0x0c416102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q }; +send(16) g7<1>UW m2<8,8,1>F 0x0482a102 + sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H }; +send(8) g9<1>UD m1<4>F 0x1618e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 11 rlen 1 { align16 1Q }; +send(8) g19<1>F m17<4>F 0x04184040 + dp_sampler MsgDesc: (64, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g3<1>UW m1<8,8,1>F 0x0c493001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g7<1>UW m1<8,8,1>F 0x0c493102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q }; +send(16) g4<1>UW m1<8,8,1>F 0x168a3001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(16) g12<1>UW m1<8,8,1>F 0x168a3102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 11 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x08418002 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x10828002 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x0a411001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x14821001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x0c415001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g6<1>UW m2<8,8,1>F 0x0c415102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q }; +send(8) g19<1>F m17<4>F 0x04184001 + dp_sampler MsgDesc: (1, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g2<1>UW m1<8,8,1>F 0x06498002 + sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x0a8a8002 + sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 5 rlen 8 { align1 1H }; +send(8) null<1>F m1<4>F 0x9608c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 1Q EOT }; +send(8) g7<1>UD m2<4>F 0x04107000 + sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q }; +send(8) g12<1>UD m1<4>F 0x1a18e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 13 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x0a417001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x14827001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x04410304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08820304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H }; +send(8) g11<1>UD m1<4>F 0x0e18e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 7 rlen 1 { align16 1Q }; +send(8) g26<1>UD m2<4>UD 0x021ba001 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x0c414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x06419001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x0c829001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; +send(8) null<1>F m2<4>UD 0x0209a001 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a002 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 2 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a003 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 3 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a004 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 4 mlen 1 rlen 0 { align16 1Q }; +send(8) g43<1>UD m2<4>UD 0x021ba005 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 5 mlen 1 rlen 1 { align16 1Q }; +send(8) g2<1>UW m1<8,8,1>F 0x12494001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q }; +send(16) g3<1>UW m17<8,8,1>UD 0x02280302 + const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g7<1>UW m2<8,8,1>F 0x0a413102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; +send(16) g12<1>UW m2<8,8,1>F 0x14823102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H }; +send(8) g2<1>UW m1<8,8,1>F 0x06490001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x0a8a0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x04410203 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(8) g9<1>UW m2<8,8,1>F 0x04410102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08820203 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H }; +send(16) g13<1>UW m2<8,8,1>F 0x08820102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a203 + sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a304 + sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a405 + sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a506 + sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a607 + sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a708 + sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a809 + sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241a90a + sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241aa0b + sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241ab0c + sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; +send(8) g3<1>UW m2<8,8,1>F 0x0241ac0d + sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a203 + sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a304 + sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a405 + sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a506 + sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a607 + sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a708 + sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a809 + sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482a90a + sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482aa0b + sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482ab0c + sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0482ac0d + sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x14414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q }; +send(8) g17<1>F m2<4>F 0x04102000 + sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410405 + sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410506 + sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410607 + sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410708 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410809 + sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x0441090a + sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410a0b + sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410b0c + sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410c0d + sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410d0e + sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410e0f + sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410f10 + sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08820405 + sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820506 + sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820607 + sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820708 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820809 + sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x0882090a + sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820a0b + sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820b0c + sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820c0d + sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820d0e + sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820e0f + sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H }; +send(16) g2<1>UW m2<8,8,1>F 0x08820f10 + sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H }; +send(8) g6<1>UW m2<8,8,1>F 0x02410102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; +send(16) g10<1>UW m2<8,8,1>F 0x04820102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H }; +send(8) g2<1>UW m1<8,8,1>F 0x0c492001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x168a2001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; +send(8) g3<1>UW m1<8,8,1>F 0x0e495001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; +send(8) g7<1>UW m1<8,8,1>F 0x0e495102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q }; +send(8) g2<1>UW m1<8,8,1>F 0x04490001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x068a0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x04410003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x08820003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x08417008 + sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(8) g6<1>UW m2<8,8,1>F 0x08417109 + sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; +send(8) g7<1>UW m2<8,8,1>F 0x0841720a + sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; +send(8) g8<1>UW m2<8,8,1>F 0x0841730b + sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 3 mlen 4 rlen 4 { align1 1Q }; +send(8) g9<1>UW m2<8,8,1>F 0x0841740c + sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; +send(8) g10<1>UW m2<8,8,1>F 0x0841750d + sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 5 mlen 4 rlen 4 { align1 1Q }; +send(8) g11<1>UW m2<8,8,1>F 0x0841760e + sampler MsgDesc: ld SIMD8 Surface = 14 Sampler = 6 mlen 4 rlen 4 { align1 1Q }; +send(8) g12<1>UW m2<8,8,1>F 0x0841770f + sampler MsgDesc: ld SIMD8 Surface = 15 Sampler = 7 mlen 4 rlen 4 { align1 1Q }; +send(16) g4<1>UW m2<8,8,1>F 0x10827008 + sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(16) g12<1>UW m2<8,8,1>F 0x10827109 + sampler MsgDesc: ld SIMD16 Surface = 9 Sampler = 1 mlen 8 rlen 8 { align1 1H }; +send(16) g12<1>UW m2<8,8,1>F 0x1082720a + sampler MsgDesc: ld SIMD16 Surface = 10 Sampler = 2 mlen 8 rlen 8 { align1 1H }; +send(16) g13<1>UW m2<8,8,1>F 0x1082730b + sampler MsgDesc: ld SIMD16 Surface = 11 Sampler = 3 mlen 8 rlen 8 { align1 1H }; +send(16) g14<1>UW m2<8,8,1>F 0x1082740c + sampler MsgDesc: ld SIMD16 Surface = 12 Sampler = 4 mlen 8 rlen 8 { align1 1H }; +send(16) g15<1>UW m2<8,8,1>F 0x1082750d + sampler MsgDesc: ld SIMD16 Surface = 13 Sampler = 5 mlen 8 rlen 8 { align1 1H }; +send(16) g16<1>UW m2<8,8,1>F 0x1082760e + sampler MsgDesc: ld SIMD16 Surface = 14 Sampler = 6 mlen 8 rlen 8 { align1 1H }; +send(16) g17<1>UW m2<8,8,1>F 0x1082770f + sampler MsgDesc: ld SIMD16 Surface = 15 Sampler = 7 mlen 8 rlen 8 { align1 1H }; +send(8) g30<1>UD m2<4>UD 0x021ba002 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 2 mlen 1 rlen 1 { align16 1Q }; +send(8) g5<1>F m2<4>F 0x04102505 + sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 1Q }; +send(8) g11<1>UW m16<8,8,1>F 0x04497002 + sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(16) g19<1>UW m16<8,8,1>F 0x068a7002 + sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 3 rlen 8 { align1 1H }; +send(8) g6<1>UW m2<8,8,1>F 0x06410102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; +send(16) g10<1>UW m2<8,8,1>F 0x0c820102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; +send(8) null<1>F m1<4>F 0x8a08c470 + urb MsgDesc: 7 urb_write interleave used complete mlen 5 rlen 0 { align16 1Q EOT }; +send(8) g6<1>UD m1<4>F 0x1218e400 + urb MsgDesc: 0 urb_write interleave allocate used complete mlen 9 rlen 1 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a005 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 5 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a006 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 6 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a007 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 7 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a008 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 8 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a009 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 9 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a00a + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 10 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a00b + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 11 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a00c + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 12 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a00d + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 13 mlen 1 rlen 0 { align16 1Q }; +send(8) null<1>F m2<4>UD 0x0209a00e + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 14 mlen 1 rlen 0 { align16 1Q }; +send(8) g18<1>UD m2<4>UD 0x021ba00f + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 15 mlen 1 rlen 1 { align16 1Q }; +send(8) g9<1>UD m1<4>F 0x1a18e470 + urb MsgDesc: 7 urb_write interleave allocate used complete mlen 13 rlen 1 { align16 1Q }; +send(8) null<1>F m1<4>F 0x9a08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 1Q EOT }; +send(16) g2<1>UW m17<8,8,1>UD 0x02280304 + const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g2<1>UW m17<8,8,1>UD 0x02280303 + const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g2<1>UW m17<8,8,1>UD 0x02280306 + const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(16) g2<1>UW m17<8,8,1>UD 0x02280305 + const MsgDesc: (5, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g34<1>UD m2<4>UD 0x021ba003 + render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 3 mlen 1 rlen 1 { align16 1Q }; +send(8) g15<1>D m2<4>F 0x0210a707 + sampler MsgDesc: resinfo SIMD4x2 Surface = 7 Sampler = 7 mlen 1 rlen 1 { align16 1Q }; +send(8) g17<1>D m2<4>F 0x0210a808 + sampler MsgDesc: resinfo SIMD4x2 Surface = 8 Sampler = 8 mlen 1 rlen 1 { align16 1Q }; +send(8) g19<1>D m2<4>F 0x0210a909 + sampler MsgDesc: resinfo SIMD4x2 Surface = 9 Sampler = 9 mlen 1 rlen 1 { align16 1Q }; +send(8) g21<1>D m2<4>F 0x0210aa0a + sampler MsgDesc: resinfo SIMD4x2 Surface = 10 Sampler = 10 mlen 1 rlen 1 { align16 1Q }; +send(8) g23<1>D m2<4>F 0x0210ab0b + sampler MsgDesc: resinfo SIMD4x2 Surface = 11 Sampler = 11 mlen 1 rlen 1 { align16 1Q }; +send(8) g25<1>D m2<4>F 0x0210ac0c + sampler MsgDesc: resinfo SIMD4x2 Surface = 12 Sampler = 12 mlen 1 rlen 1 { align16 1Q }; +send(8) null<1>UW m22<8,8,1>UD 0x040902ff + render MsgDesc: OWORD block write MsgCtrl = 0x2 Surface = 255 mlen 2 rlen 0 { align1 1Q }; +send(8) g69<1>UW m22<8,8,1>UD 0x021802ff + render MsgDesc: OWORD block read MsgCtrl = 0x2 Surface = 255 mlen 1 rlen 1 { align1 WE_all 1Q }; +send(8) g9<1>UD m1<4>F 0x0e18e4e0 + urb MsgDesc: 14 urb_write interleave allocate used complete mlen 7 rlen 1 { align16 1Q }; +send(8) g2<1>UW m1<8,8,1>F 0x08490001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW m1<8,8,1>F 0x0e8a0001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; +send(8) g2<1>UW m2<8,8,1>F 0x08410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; +send(16) g2<1>UW m2<8,8,1>F 0x10820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; +send(8) null<1>F m1<4>F 0x9a08c470 + urb MsgDesc: 7 urb_write interleave used complete mlen 13 rlen 0 { align16 1Q EOT }; +send(8) g15<1>F m17<4>F 0x04184043 + dp_sampler MsgDesc: (67, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g21<1>F m17<4>F 0x04184042 + dp_sampler MsgDesc: (66, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g23<1>F m17<4>F 0x04184041 + dp_sampler MsgDesc: (65, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g4<1>F m17<4>F 0x04184003 + dp_sampler MsgDesc: (3, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g13<1>F m17<4>F 0x04184002 + dp_sampler MsgDesc: (2, 0, 2, 0) mlen 2 rlen 1 { align16 1Q }; +send(8) g14<1>UW m2<8,8,1>F 0x0a417102 + sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; +send(16) g24<1>UW m2<8,8,1>F 0x14827102 + sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H }; +send(16) g2<1>UW m17<8,8,1>UD 0x02280307 + const MsgDesc: (7, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; +send(8) g6<1>UW m2<8,8,1>F 0x0a413203 + sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; +send(16) g13<1>UW m2<8,8,1>F 0x14823203 + sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 10 rlen 8 { align1 1H }; +send(8) g5<1>F m2<4>F 0x04102303 + sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 1Q }; +send(8) g2<1>UW m2<8,8,1>F 0x04410002 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g20<1>UW m2<8,8,1>F 0x04410008 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; +send(8) g24<1>UW m2<8,8,1>F 0x04410109 + sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; +send(8) g28<1>UW m2<8,8,1>F 0x0441020a + sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; +send(8) g32<1>UW m2<8,8,1>F 0x0441030b + sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; +send(8) g36<1>UW m2<8,8,1>F 0x0441040c + sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; +send(8) g40<1>UW m2<8,8,1>F 0x0441050d + sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; +send(8) g44<1>UW m2<8,8,1>F 0x0441060e + sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; +send(8) g48<1>UW m2<8,8,1>F 0x0441070f + sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; +send(16) g22<1>UW m2<8,8,1>F 0x08820008 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H }; +send(16) g30<1>UW m2<8,8,1>F 0x08820109 + sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H }; +send(16) g22<1>UW m2<8,8,1>F 0x0882020a + sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H }; +send(16) g38<1>UW m2<8,8,1>F 0x0882030b + sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H }; +send(16) g30<1>UW m2<8,8,1>F 0x0882040c + sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H }; +send(16) g46<1>UW m2<8,8,1>F 0x0882050d + sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H }; +send(16) g22<1>UW m2<8,8,1>F 0x0882060e + sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H }; +send(16) g54<1>UW m2<8,8,1>F 0x0882070f + sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; +send(8) g5<1>F m2<4>F 0x04102101 + sampler MsgDesc: sample_l SIMD4x2 Surface = 1 Sampler = 1 mlen 2 rlen 1 { align16 1Q }; +send(8) g6<1>F m2<4>F 0x04102202 + sampler MsgDesc: sample_l SIMD4x2 Surface = 2 Sampler = 2 mlen 2 rlen 1 { align16 1Q }; +send(8) g8<1>F m2<4>F 0x04102404 + sampler MsgDesc: sample_l SIMD4x2 Surface = 4 Sampler = 4 mlen 2 rlen 1 { align16 1Q }; +send(8) g10<1>F m2<4>F 0x04102606 + sampler MsgDesc: sample_l SIMD4x2 Surface = 6 Sampler = 6 mlen 2 rlen 1 { align16 1Q }; +send(8) g11<1>F m2<4>F 0x04102707 + sampler MsgDesc: sample_l SIMD4x2 Surface = 7 Sampler = 7 mlen 2 rlen 1 { align16 1Q }; +send(8) g9<1>UD m1<4>F 0x0a18e470 + urb MsgDesc: 7 urb_write interleave allocate used complete mlen 5 rlen 1 { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/send.expected b/src/intel/tools/tests/gen6/send.expected new file mode 100644 index 00000000000..b89db52d964 --- /dev/null +++ b/src/intel/tools/tests/gen6/send.expected @@ -0,0 +1,258 @@ +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 86 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 8a +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 70 41 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 70 82 10 +31 01 60 05 dd 0f 0f 20 a4 02 6e 00 ff 20 09 06 +31 01 60 05 dd 0f 2f 25 c4 02 6e 00 ff 40 18 04 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 8e +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 40 49 16 +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 40 49 0e +31 00 60 02 c9 0f 60 20 20 00 8d 00 01 60 49 0e +31 00 60 02 c9 0f e0 20 20 00 8d 00 02 61 49 0e +31 01 60 02 c5 0f cf 21 44 00 6e 00 40 70 10 04 +31 01 60 06 41 0c e1 20 24 00 6e 00 01 20 18 02 +31 01 60 06 c1 0f ef 20 24 00 6e 00 00 e4 18 0a +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 84 08 82 +31 01 60 06 c1 0f 0f 21 24 00 6e 00 00 e4 18 06 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 44 08 1e +31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 c4 08 86 +31 00 60 02 c9 0f e0 20 40 00 8d 00 01 00 41 04 +31 00 80 02 c9 0f 20 21 40 00 8d 00 01 00 82 08 +31 00 60 02 c9 0f e0 20 40 00 8d 00 01 00 41 02 +31 00 80 02 c9 0f 20 21 40 00 8d 00 01 00 82 04 +31 01 60 04 c1 0f 0f 23 24 02 6e 00 00 40 18 04 +31 00 60 02 c9 0f 00 21 40 00 8d 00 01 a0 41 02 +31 00 60 02 c9 0f 40 20 40 00 8d 00 02 80 41 06 +31 00 80 02 c9 0f 60 21 40 00 8d 00 01 a0 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 02 80 82 0c +31 01 60 02 c5 0f ef 21 44 00 6e 00 40 70 10 02 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 40 41 10 +31 01 60 02 c5 0f 4f 20 44 00 6e 00 00 a0 10 02 +31 01 60 02 c5 0f 6f 20 44 00 6e 00 01 a1 10 02 +31 01 60 02 c5 0f af 20 44 00 6e 00 02 a2 10 02 +31 01 60 02 c5 0f ef 20 44 00 6e 00 03 a3 10 02 +31 01 60 02 c5 0f 2f 21 44 00 6e 00 04 a4 10 02 +31 01 60 02 c5 0f 6f 21 44 00 6e 00 05 a5 10 02 +31 01 60 02 c5 0f af 21 44 00 6e 00 06 a6 10 02 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 92 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 90 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 90 82 08 +31 02 80 09 49 0c a0 21 20 02 8d 00 01 03 28 02 +31 01 60 02 c5 0f 6f 21 44 00 6e 00 01 80 18 04 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 00 a0 09 02 +31 01 60 05 41 0c ef 27 44 00 6e 00 00 a0 1b 02 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 20 41 0a +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 20 82 14 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 90 41 02 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 90 82 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 60 41 0c +31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 44 08 1e +31 01 60 06 dc 0f 0f 20 24 00 6e 00 e0 c4 08 8e +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 30 41 0a +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 30 82 14 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 00 41 06 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 00 82 0c +31 00 60 02 c9 0f 40 20 40 00 8d 00 02 80 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 02 80 82 08 +31 01 60 02 dd 0f 0f 21 44 00 6e 00 00 70 10 02 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 9e +31 00 60 02 c9 0f 40 20 00 02 8d 00 01 70 49 04 +31 00 80 02 c9 0f 40 20 00 02 8d 00 01 70 8a 06 +31 00 60 02 c9 0f 40 20 20 00 8d 00 02 80 49 08 +31 00 80 02 c9 0f 40 20 20 00 8d 00 02 80 8a 0e +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 10 49 0c +31 00 80 02 c9 0f 40 20 20 00 8d 00 01 10 8a 16 +31 01 60 02 c5 0f 4f 22 44 00 6e 00 40 a0 10 02 +31 00 60 02 c9 0f 20 21 40 00 8d 00 02 a1 41 02 +31 00 60 02 c9 0f 20 21 40 00 8d 00 02 61 41 0c +31 00 80 02 c9 0f e0 20 40 00 8d 00 02 a1 82 04 +31 01 60 06 c1 0f 2f 21 24 00 6e 00 00 e4 18 16 +31 01 60 04 dd 0f 6f 22 24 02 6e 00 40 40 18 04 +31 00 60 02 c9 0f 60 20 20 00 8d 00 01 30 49 0c +31 00 60 02 c9 0f e0 20 20 00 8d 00 02 31 49 0c +31 00 80 02 c9 0f 80 20 20 00 8d 00 01 30 8a 16 +31 00 80 02 c9 0f 80 21 20 00 8d 00 02 31 8a 16 +31 00 60 02 c9 0f 40 20 40 00 8d 00 02 80 41 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 02 80 82 10 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 10 41 0a +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 10 82 14 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 50 41 0c +31 00 60 02 c9 0f c0 20 40 00 8d 00 02 51 41 0c +31 01 60 04 dd 0f 6f 22 24 02 6e 00 01 40 18 04 +31 00 60 02 c9 0f 40 20 20 00 8d 00 02 80 49 06 +31 00 80 02 c9 0f 40 20 20 00 8d 00 02 80 8a 0a +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 96 +31 01 60 02 c1 0f ef 20 44 00 6e 00 00 70 10 04 +31 01 60 06 c1 0f 8f 21 24 00 6e 00 00 e4 18 1a +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 70 41 0a +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 70 82 14 +31 00 60 02 c9 0f 40 20 40 00 8d 00 04 03 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 04 03 82 08 +31 01 60 06 c1 0f 6f 21 24 00 6e 00 00 e4 18 0e +31 01 60 05 41 0c 4f 23 44 00 6e 00 01 a0 1b 02 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 40 41 0c +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 90 41 06 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 90 82 0c +31 01 60 05 5c 0c 0f 20 44 00 6e 00 01 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 02 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 03 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 04 a0 09 02 +31 01 60 05 41 0c 6f 25 44 00 6e 00 05 a0 1b 02 +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 40 49 12 +31 02 80 09 49 0c 60 20 20 02 8d 00 02 03 28 02 +31 00 60 02 c9 0f e0 20 40 00 8d 00 02 31 41 0a +31 00 80 02 c9 0f 80 21 40 00 8d 00 02 31 82 14 +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 00 49 06 +31 00 80 02 c9 0f 40 20 20 00 8d 00 01 00 8a 0a +31 00 60 02 c9 0f 40 20 40 00 8d 00 03 02 41 04 +31 00 60 02 c9 0f 20 21 40 00 8d 00 02 01 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 03 02 82 08 +31 00 80 02 c9 0f a0 21 40 00 8d 00 02 01 82 08 +31 00 60 02 c9 0f 60 20 40 00 8d 00 03 a2 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 04 a3 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 05 a4 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 06 a5 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 07 a6 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 08 a7 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 09 a8 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 0a a9 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 0b aa 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 0c ab 41 02 +31 00 60 02 c9 0f 60 20 40 00 8d 00 0d ac 41 02 +31 00 80 02 c9 0f 40 20 40 00 8d 00 03 a2 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 04 a3 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 05 a4 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 06 a5 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 07 a6 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 08 a7 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 09 a8 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0a a9 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0b aa 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0c ab 82 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0d ac 82 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 40 41 14 +31 01 60 02 dd 0f 2f 22 44 00 6e 00 00 20 10 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 05 04 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 06 05 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 07 06 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 08 07 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 09 08 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0a 09 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0b 0a 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0c 0b 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0d 0c 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0e 0d 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 0f 0e 41 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 10 0f 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 05 04 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 06 05 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 07 06 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 08 07 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 09 08 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0a 09 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0b 0a 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0c 0b 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0d 0c 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0e 0d 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 0f 0e 82 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 10 0f 82 08 +31 00 60 02 c9 0f c0 20 40 00 8d 00 02 01 41 02 +31 00 80 02 c9 0f 40 21 40 00 8d 00 02 01 82 04 +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 20 49 0c +31 00 80 02 c9 0f 40 20 20 00 8d 00 01 20 8a 16 +31 00 60 02 c9 0f 60 20 20 00 8d 00 01 50 49 0e +31 00 60 02 c9 0f e0 20 20 00 8d 00 02 51 49 0e +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 00 49 04 +31 00 80 02 c9 0f 40 20 20 00 8d 00 01 00 8a 06 +31 00 60 02 c9 0f 40 20 40 00 8d 00 03 00 41 04 +31 00 80 02 c9 0f 40 20 40 00 8d 00 03 00 82 08 +31 00 60 02 c9 0f 40 20 40 00 8d 00 08 70 41 08 +31 00 60 02 c9 0f c0 20 40 00 8d 00 09 71 41 08 +31 00 60 02 c9 0f e0 20 40 00 8d 00 0a 72 41 08 +31 00 60 02 c9 0f 00 21 40 00 8d 00 0b 73 41 08 +31 00 60 02 c9 0f 20 21 40 00 8d 00 0c 74 41 08 +31 00 60 02 c9 0f 40 21 40 00 8d 00 0d 75 41 08 +31 00 60 02 c9 0f 60 21 40 00 8d 00 0e 76 41 08 +31 00 60 02 c9 0f 80 21 40 00 8d 00 0f 77 41 08 +31 00 80 02 c9 0f 80 20 40 00 8d 00 08 70 82 10 +31 00 80 02 c9 0f 80 21 40 00 8d 00 09 71 82 10 +31 00 80 02 c9 0f 80 21 40 00 8d 00 0a 72 82 10 +31 00 80 02 c9 0f a0 21 40 00 8d 00 0b 73 82 10 +31 00 80 02 c9 0f c0 21 40 00 8d 00 0c 74 82 10 +31 00 80 02 c9 0f e0 21 40 00 8d 00 0d 75 82 10 +31 00 80 02 c9 0f 00 22 40 00 8d 00 0e 76 82 10 +31 00 80 02 c9 0f 20 22 40 00 8d 00 0f 77 82 10 +31 01 60 05 41 0c cf 23 44 00 6e 00 02 a0 1b 02 +31 01 60 02 dd 0f af 20 44 00 6e 00 05 25 10 04 +31 00 60 02 c9 0f 60 21 00 02 8d 00 02 70 49 04 +31 00 80 02 c9 0f 60 22 00 02 8d 00 02 70 8a 06 +31 00 60 02 c9 0f c0 20 40 00 8d 00 02 01 41 06 +31 00 80 02 c9 0f 40 21 40 00 8d 00 02 01 82 0c +31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 c4 08 8a +31 01 60 06 c1 0f cf 20 24 00 6e 00 00 e4 18 12 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 05 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 06 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 07 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 08 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 09 a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 0a a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 0b a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 0c a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 0d a0 09 02 +31 01 60 05 5c 0c 0f 20 44 00 6e 00 0e a0 09 02 +31 01 60 05 41 0c 4f 22 44 00 6e 00 0f a0 1b 02 +31 01 60 06 c1 0f 2f 21 24 00 6e 00 70 e4 18 1a +31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 9a +31 02 80 09 49 0c 40 20 20 02 8d 00 04 03 28 02 +31 02 80 09 49 0c 40 20 20 02 8d 00 03 03 28 02 +31 02 80 09 49 0c 40 20 20 02 8d 00 06 03 28 02 +31 02 80 09 49 0c 40 20 20 02 8d 00 05 03 28 02 +31 01 60 05 41 0c 4f 24 44 00 6e 00 03 a0 1b 02 +31 01 60 02 c5 0f ef 21 44 00 6e 00 07 a7 10 02 +31 01 60 02 c5 0f 2f 22 44 00 6e 00 08 a8 10 02 +31 01 60 02 c5 0f 6f 22 44 00 6e 00 09 a9 10 02 +31 01 60 02 c5 0f af 22 44 00 6e 00 0a aa 10 02 +31 01 60 02 c5 0f ef 22 44 00 6e 00 0b ab 10 02 +31 01 60 02 c5 0f 2f 23 44 00 6e 00 0c ac 10 02 +31 00 60 05 48 0c 00 20 c0 02 8d 00 ff 02 09 04 +31 02 60 05 49 0c a0 28 c0 02 8d 00 ff 02 18 02 +31 01 60 06 c1 0f 2f 21 24 00 6e 00 e0 e4 18 0e +31 00 60 02 c9 0f 40 20 20 00 8d 00 01 00 49 08 +31 00 80 02 c9 0f 40 20 20 00 8d 00 01 00 8a 0e +31 00 60 02 c9 0f 40 20 40 00 8d 00 01 00 41 08 +31 00 80 02 c9 0f 40 20 40 00 8d 00 01 00 82 10 +31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 c4 08 9a +31 01 60 04 dd 0f ef 21 24 02 6e 00 43 40 18 04 +31 01 60 04 dd 0f af 22 24 02 6e 00 42 40 18 04 +31 01 60 04 dd 0f ef 22 24 02 6e 00 41 40 18 04 +31 01 60 04 dd 0f 8f 20 24 02 6e 00 03 40 18 04 +31 01 60 04 dd 0f af 21 24 02 6e 00 02 40 18 04 +31 00 60 02 c9 0f c0 21 40 00 8d 00 02 71 41 0a +31 00 80 02 c9 0f 00 23 40 00 8d 00 02 71 82 14 +31 02 80 09 49 0c 40 20 20 02 8d 00 07 03 28 02 +31 00 60 02 c9 0f c0 20 40 00 8d 00 03 32 41 0a +31 00 80 02 c9 0f a0 21 40 00 8d 00 03 32 82 14 +31 01 60 02 dd 0f af 20 44 00 6e 00 03 23 10 04 +31 00 60 02 c9 0f 40 20 40 00 8d 00 02 00 41 04 +31 00 60 02 c9 0f 80 22 40 00 8d 00 08 00 41 04 +31 00 60 02 c9 0f 00 23 40 00 8d 00 09 01 41 04 +31 00 60 02 c9 0f 80 23 40 00 8d 00 0a 02 41 04 +31 00 60 02 c9 0f 00 24 40 00 8d 00 0b 03 41 04 +31 00 60 02 c9 0f 80 24 40 00 8d 00 0c 04 41 04 +31 00 60 02 c9 0f 00 25 40 00 8d 00 0d 05 41 04 +31 00 60 02 c9 0f 80 25 40 00 8d 00 0e 06 41 04 +31 00 60 02 c9 0f 00 26 40 00 8d 00 0f 07 41 04 +31 00 80 02 c9 0f c0 22 40 00 8d 00 08 00 82 08 +31 00 80 02 c9 0f c0 23 40 00 8d 00 09 01 82 08 +31 00 80 02 c9 0f c0 22 40 00 8d 00 0a 02 82 08 +31 00 80 02 c9 0f c0 24 40 00 8d 00 0b 03 82 08 +31 00 80 02 c9 0f c0 23 40 00 8d 00 0c 04 82 08 +31 00 80 02 c9 0f c0 25 40 00 8d 00 0d 05 82 08 +31 00 80 02 c9 0f c0 22 40 00 8d 00 0e 06 82 08 +31 00 80 02 c9 0f c0 26 40 00 8d 00 0f 07 82 08 +31 01 60 02 dd 0f af 20 44 00 6e 00 01 21 10 04 +31 01 60 02 dd 0f cf 20 44 00 6e 00 02 22 10 04 +31 01 60 02 dd 0f 0f 21 44 00 6e 00 04 24 10 04 +31 01 60 02 dd 0f 4f 21 44 00 6e 00 06 26 10 04 +31 01 60 02 dd 0f 6f 21 44 00 6e 00 07 27 10 04 +31 01 60 06 c1 0f 2f 21 24 00 6e 00 70 e4 18 0a diff --git a/src/intel/tools/tests/gen6/sendc.asm b/src/intel/tools/tests/gen6/sendc.asm new file mode 100644 index 00000000000..6526e54d48a --- /dev/null +++ b/src/intel/tools/tests/gen6/sendc.asm @@ -0,0 +1,76 @@ +sendc(8) null<1>UW m1<8,8,1>F 0x88019400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x90019000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; +sendc(16) null<1>UW m2<8,8,1>F 0x82019100 + render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x8c099401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x94099001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x0e098401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x8e099402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x18098001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x98099002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098401 + render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098402 + render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098403 + render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098404 + render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x8c099405 + render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098000 + render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098001 + render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098002 + render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098003 + render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098004 + render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x94099005 + render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x8c099400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x94099000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x8a019400 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x94099200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x14099200 + render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x94099300 + render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x8c099402 + render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x94099002 + render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098405 + render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x0c098406 + render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q }; +sendc(8) null<1>UW m1<8,8,1>F 0x8c099407 + render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098005 + render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x14098006 + render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H }; +sendc(16) null<1>UW m1<8,8,1>F 0x94099007 + render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x8e099401 + render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT }; +sendc(16) null<1>UW m1<8,8,1>F 0x98099001 + render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT }; +sendc(8) null<1>UW m1<8,8,1>F 0x0e098400 + render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q }; diff --git a/src/intel/tools/tests/gen6/sendc.expected b/src/intel/tools/tests/gen6/sendc.expected new file mode 100644 index 00000000000..ff1644f7f69 --- /dev/null +++ b/src/intel/tools/tests/gen6/sendc.expected @@ -0,0 +1,38 @@ +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 01 88 +32 00 80 05 c8 0f 00 20 20 00 8d 00 00 90 01 90 +32 00 80 05 c8 0f 00 20 40 00 8d 00 00 91 01 82 +32 00 60 05 c8 0f 00 20 20 00 8d 00 01 94 09 8c +32 00 80 05 c8 0f 00 20 20 00 8d 00 01 90 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 01 84 09 0e +32 00 60 05 c8 0f 00 20 20 00 8d 00 02 94 09 8e +32 00 80 05 c8 0f 00 20 20 00 8d 00 01 80 09 18 +32 00 80 05 c8 0f 00 20 20 00 8d 00 02 90 09 98 +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 01 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 02 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 03 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 04 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 05 94 09 8c +32 00 80 05 c8 0f 00 20 20 00 8d 00 00 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 01 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 02 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 03 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 04 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 05 90 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 09 8c +32 00 80 05 c8 0f 00 20 20 00 8d 00 00 90 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 01 8a +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 92 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 92 09 14 +32 10 60 05 c8 0f 00 20 20 00 8d 00 00 93 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 02 94 09 8c +32 00 80 05 c8 0f 00 20 20 00 8d 00 02 90 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 05 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 06 84 09 0c +32 00 60 05 c8 0f 00 20 20 00 8d 00 07 94 09 8c +32 00 80 05 c8 0f 00 20 20 00 8d 00 05 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 06 80 09 14 +32 00 80 05 c8 0f 00 20 20 00 8d 00 07 90 09 94 +32 00 60 05 c8 0f 00 20 20 00 8d 00 01 94 09 8e +32 00 80 05 c8 0f 00 20 20 00 8d 00 01 90 09 98 +32 00 60 05 c8 0f 00 20 20 00 8d 00 00 84 09 0e diff --git a/src/intel/tools/tests/gen6/shl.asm b/src/intel/tools/tests/gen6/shl.asm new file mode 100644 index 00000000000..a8fce90e111 --- /dev/null +++ b/src/intel/tools/tests/gen6/shl.asm @@ -0,0 +1,13 @@ +shl(8) g25<1>.xD g21<4>.xD 0x00000004UD { align16 1Q }; +shl(8) g3<1>D g2.4<0,1,0>D 0x00000004UD { align1 1Q }; +shl(16) g3<1>D g2.4<0,1,0>D 0x00000004UD { align1 1H }; +shl(8) g11<1>D g11<4>D 16D { align16 1Q }; +shl(1) g28<1>UD g28<0,1,0>UD 0x00000010UD { align1 1N }; +shl(8) g64<1>.xUD g64<4>.xUD 0x00000010UD { align16 1Q }; +shl(8) m17<1>D g2<0,1,0>D 0x00000004UD { align1 1Q }; +shl(16) m17<1>D g2<0,1,0>D 0x00000004UD { align1 1H }; +shl(8) g2<1>D g2<8,8,1>D 16D { align1 1Q }; +shl(16) g2<1>D g2<8,8,1>D 16D { align1 1H }; +shl(8) g25<1>D g2<0>D g24<4>UD { align16 1Q }; +shl(8) g10<1>D g2.5<0,1,0>D g9<8,8,1>UD { align1 1Q }; +shl(16) g13<1>D g2.5<0,1,0>D g11<8,8,1>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen6/shl.expected b/src/intel/tools/tests/gen6/shl.expected new file mode 100644 index 00000000000..d07c862e6d5 --- /dev/null +++ b/src/intel/tools/tests/gen6/shl.expected @@ -0,0 +1,13 @@ +09 01 60 00 a5 0c 21 23 a0 02 60 00 04 00 00 00 +09 00 60 00 a5 0c 60 20 50 00 00 00 04 00 00 00 +09 00 80 00 a5 0c 60 20 50 00 00 00 04 00 00 00 +09 01 60 00 a5 1c 6f 21 64 01 6e 00 10 00 00 00 +09 00 00 00 21 0c 80 23 80 03 00 00 10 00 00 00 +09 01 60 00 21 0c 01 28 00 08 60 00 10 00 00 00 +09 00 60 00 a6 0c 20 22 40 00 00 00 04 00 00 00 +09 00 80 00 a6 0c 20 22 40 00 00 00 04 00 00 00 +09 00 60 00 a5 1c 40 20 40 00 8d 00 10 00 00 00 +09 00 80 00 a5 1c 40 20 40 00 8d 00 10 00 00 00 +09 01 60 00 a5 04 2f 23 44 00 0e 00 04 03 6e 00 +09 00 60 00 a5 04 40 21 54 00 00 00 20 01 8d 00 +09 00 80 00 a5 04 a0 21 54 00 00 00 60 01 8d 00 diff --git a/src/intel/tools/tests/gen6/shr.asm b/src/intel/tools/tests/gen6/shr.asm new file mode 100644 index 00000000000..3d4d99c78f1 --- /dev/null +++ b/src/intel/tools/tests/gen6/shr.asm @@ -0,0 +1,8 @@ +shr(8) m18<1>D g25<4>.xUD 4D { align16 1Q }; +shr(8) g13<1>UD g12<8,8,1>UD 0x00000001UD { align1 1Q }; +shr(16) g19<1>UD g17<8,8,1>UD 0x00000001UD { align1 1H }; +shr(1) g22<1>UD g22<0,1,0>UD 5D { align1 WE_all 1N }; +shr(8) g34<1>UD g3<0>UD g1<0>.yUD { align16 1Q }; +shr(8) g3<1>.xUD g3<4>.xUD 0x00000001UD { align16 1Q }; +shr(8) g28<1>UD g3.5<0,1,0>UD g4.1<0,1,0>UD { align1 1Q }; +shr(16) g48<1>UD g3.5<0,1,0>UD g4.1<0,1,0>UD { align1 1H }; diff --git a/src/intel/tools/tests/gen6/shr.expected b/src/intel/tools/tests/gen6/shr.expected new file mode 100644 index 00000000000..0e218041b16 --- /dev/null +++ b/src/intel/tools/tests/gen6/shr.expected @@ -0,0 +1,8 @@ +08 01 60 00 26 1c 4f 22 20 03 60 00 04 00 00 00 +08 00 60 00 21 0c a0 21 80 01 8d 00 01 00 00 00 +08 00 80 00 21 0c 60 22 20 02 8d 00 01 00 00 00 +08 02 00 00 21 1c c0 22 c0 02 00 00 05 00 00 00 +08 01 60 00 21 04 4f 24 64 00 0e 00 25 00 05 00 +08 01 60 00 21 0c 61 20 60 00 60 00 01 00 00 00 +08 00 60 00 21 04 80 23 74 00 00 00 84 00 00 00 +08 00 80 00 21 04 00 26 74 00 00 00 84 00 00 00 diff --git a/src/intel/tools/tests/gen6/while.asm b/src/intel/tools/tests/gen6/while.asm new file mode 100644 index 00000000000..0df3ed79922 --- /dev/null +++ b/src/intel/tools/tests/gen6/while.asm @@ -0,0 +1,6 @@ +while(8) JIP: -76 { align16 1Q }; +while(8) JIP: -108 { align1 1Q }; +while(16) JIP: -108 { align1 1H }; +(-f0.0) while(8) JIP: -48 { align1 1Q }; +(-f0.0) while(16) JIP: -48 { align1 1H }; +(-f0.0.x) while(8) JIP: -48 { align16 1Q }; diff --git a/src/intel/tools/tests/gen6/while.expected b/src/intel/tools/tests/gen6/while.expected new file mode 100644 index 00000000000..4ea711e07b8 --- /dev/null +++ b/src/intel/tools/tests/gen6/while.expected @@ -0,0 +1,6 @@ +27 01 60 00 8f 10 b4 ff 04 00 6e 00 04 00 6e 00 +27 00 60 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00 +27 00 80 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00 +27 00 71 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00 +27 00 91 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00 +27 01 72 00 8f 10 d0 ff 04 00 6e 00 04 00 6e 00 diff --git a/src/intel/tools/tests/gen6/xor.asm b/src/intel/tools/tests/gen6/xor.asm new file mode 100644 index 00000000000..8df3d4716ea --- /dev/null +++ b/src/intel/tools/tests/gen6/xor.asm @@ -0,0 +1,5 @@ +xor(8) g17<1>D g17<4>D g2<0>D { align16 1Q }; +xor(8) g7<1>D g7<8,8,1>D g2.5<0,1,0>D { align1 1Q }; +xor(16) g8<1>D g8<8,8,1>D g2.5<0,1,0>D { align1 1H }; +xor(8) g9<1>UD g5<8,8,1>UD 0x000003ffUD { align1 1Q }; +xor(16) g4<1>UD g7<8,8,1>UD 0x000003ffUD { align1 1H }; diff --git a/src/intel/tools/tests/gen6/xor.expected b/src/intel/tools/tests/gen6/xor.expected new file mode 100644 index 00000000000..48cf314acb6 --- /dev/null +++ b/src/intel/tools/tests/gen6/xor.expected @@ -0,0 +1,5 @@ +07 01 60 00 a5 14 2f 22 24 02 6e 00 44 00 0e 00 +07 00 60 00 a5 14 e0 20 e0 00 8d 00 54 00 00 00 +07 00 80 00 a5 14 00 21 00 01 8d 00 54 00 00 00 +07 00 60 00 21 0c 20 21 a0 00 8d 00 ff 03 00 00 +07 00 80 00 21 0c 80 20 e0 00 8d 00 ff 03 00 00 |