diff options
Diffstat (limited to 'src/intel/tools/tests/gen5')
54 files changed, 1286 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen5/add.asm b/src/intel/tools/tests/gen5/add.asm new file mode 100644 index 00000000000..eff22ad88a7 --- /dev/null +++ b/src/intel/tools/tests/gen5/add.asm @@ -0,0 +1,49 @@ +add(8) g2<1>UW g1.4<2,4,0>UW 0x10101010V { align1 }; +add(8) g8<1>F g2<8,8,1>UW -g1<0,1,0>F { align1 }; +add(16) g10<1>UW g1.4<2,4,0>UW 0x10101010V { align1 }; +add(8) g8<1>F g10.8<8,8,1>UW -g1<0,1,0>F { align1 sechalf }; +add(8) g2<1>F g2<8,8,1>F g6.7<0,1,0>F { align1 }; +add(16) g4<1>F g10<8,8,1>F g6.7<0,1,0>F { align1 compr }; +add(8) g5<1>.xD g2<4>.xD 64D { align16 }; +add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 }; +add(8) g3<1>F g3<4>F g5<4>F { align16 }; +add(8) g14<1>F g6<8,8,1>F 0x3f800000F /* 1F */ { align1 }; +add(8) g12<1>D g12<8,8,1>D 1D { align1 }; +add(16) g24<1>F g20<8,8,1>F 0x3f800000F /* 1F */ { align1 compr }; +add(16) g14<1>D g14<8,8,1>D 1D { align1 compr }; +add(8) m3<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 }; +add(16) m3<1>F g6<8,8,1>F g2.1<0,1,0>F { align1 compr4 }; +add(8) m5<1>.xyzF g10<4>.xyzzF g8<4>.xyzzF { align16 NoDDClr }; +add.le.f0.0(8) g3<1>F g3<8,8,1>F g4<8,8,1>F { align1 }; +add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr }; +add(8) g3<1>.xyF g2<4>.xyyyF 0x3f800000F /* 1F */ { align16 }; +add(8) m4<1>F -g2<8,8,1>F 0x3f800000F /* 1F */ { align1 }; +add(16) m4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr4 }; +add.sat(8) g3<1>F g3<8,8,1>F g2.1<0,1,0>F { align1 }; +add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr }; +add(8) g2<1>D g2<8,8,1>D -g9.3<0,1,0>D { align1 }; +add(16) g12<1>D g4<8,8,1>D -g9.3<0,1,0>D { align1 compr }; +add(8) m5<1>.xF g3<4>.xF 0x3f000000F /* 0.5F */ { align16 }; +add(8) g31<1>.xyzF g28<4>.xyzzF 0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 }; +add.sat(8) m5<1>.xyzF g25<4>.xyzzF g26<4>.xyzzF { align16 NoDDClr }; +add(8) g3.1<2>UW g3.1<16,8,2>UW g4<16,8,2>UW { align1 }; +add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr }; +add(8) g4<1>.xyF g4<4>.xyyyF 0xbf800000F /* -1F */ { align16 NoDDClr }; +add.sat(8) m5<1>F g3<4>.yzxwF -g3<4>F { align16 }; +add(8) m5<1>.zwF g8<4>.xxxyF g9<4>.xxxyF { align16 NoDDChk }; +add(8) m8<1>.xyF g8<4>.xyyyF g9<4>.xyyyF { align16 }; +add(1) m15.4<1>D g5.4<0,1,0>D 16D { align1 nomask }; +add.sat(8) m3<1>F g6<8,8,1>F g12<8,8,1>F { align1 }; +add.sat(16) m3<1>F g16<8,8,1>F g12<8,8,1>F { align1 compr4 }; +add.sat(8) m5<1>.xF -g8<4>.xF 0x3f800000F /* 1F */ { align16 }; +add(16) g4<1>F -g8<4>.xyxyF g8<4>.zwzwF { align16 compr }; +add(8) m14<1>D g3<8,8,1>D 12D { align1 }; +add(16) m14<1>D g4<8,8,1>D 12D { align1 compr }; +add.sat(8) m5<1>.yF g6<4>.xF g7<4>.xF { align16 NoDDClr,NoDDChk }; +add.sat(8) m5<1>.wF g6<4>.xF g7<4>.xF { align16 NoDDChk }; +add.ge.f0.0(8) g8<1>F g8<8,8,1>F g9<8,8,1>F { align1 }; +add.ge.f0.0(16) g16<1>F g18<8,8,1>F g10<8,8,1>F { align1 compr }; +add(8) g5<1>.zF g4<4>.xF 0xbf800000F /* -1F */ { align16 NoDDClr,NoDDChk }; +add(8) m5<1>.xyF g12<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr }; +add(8) g5<1>.xUD g7<4>.xUD 0x00000080UD { align16 }; +add(8) m5<1>.yF -g5<4>.xF 0x3f800000F /* 1F */ { align16 NoDDClr,NoDDChk }; diff --git a/src/intel/tools/tests/gen5/add.expected b/src/intel/tools/tests/gen5/add.expected new file mode 100644 index 00000000000..7b4013159fb --- /dev/null +++ b/src/intel/tools/tests/gen5/add.expected @@ -0,0 +1,49 @@ +40 00 60 00 29 6d 40 20 28 00 48 00 10 10 10 10 +40 00 60 00 3d 75 00 21 40 00 8d 00 20 40 00 00 +40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10 +40 10 60 00 3d 75 00 21 50 01 8d 00 20 40 00 00 +40 00 60 00 bd 77 40 20 40 00 8d 00 dc 00 00 00 +40 20 80 00 bd 77 80 20 40 01 8d 00 dc 00 00 00 +40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00 +40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00 +40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00 +40 00 60 00 bd 7f c0 21 c0 00 8d 00 00 00 80 3f +40 00 60 00 a5 1c 80 21 80 01 8d 00 01 00 00 00 +40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f +40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00 +40 00 60 00 be 77 60 20 80 00 8d 00 44 00 00 00 +40 20 80 00 be 77 60 30 c0 00 8d 00 44 00 00 00 +40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00 +40 00 60 06 bd 77 60 20 60 00 8d 00 80 00 8d 00 +40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00 +40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f +40 00 60 00 be 7f 80 20 40 40 8d 00 00 00 80 3f +40 20 80 00 be 7f 80 30 c0 40 8d 00 00 00 80 3f +40 00 60 80 bd 77 60 20 60 00 8d 00 44 00 00 00 +40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00 +40 00 60 00 a5 14 40 20 40 00 8d 00 2c 41 00 00 +40 20 80 00 a5 14 80 21 80 00 8d 00 2c 41 00 00 +40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f +40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30 +40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00 +40 00 60 00 29 25 62 40 62 00 ae 00 80 00 ae 00 +40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00 +40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf +40 01 60 80 be 77 af 20 69 00 6c 00 64 40 6e 00 +40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00 +40 01 60 00 be 77 03 21 04 01 65 00 24 01 65 00 +40 02 00 00 a6 1c f0 21 b0 00 00 00 10 00 00 00 +40 00 60 80 be 77 60 20 c0 00 8d 00 80 01 8d 00 +40 20 80 80 be 77 60 30 00 02 8d 00 80 01 8d 00 +40 01 60 80 be 7f a1 20 00 41 60 00 00 00 80 3f +40 21 80 00 bd 77 8f 20 04 41 64 00 0e 01 6e 00 +40 00 60 00 a6 1c c0 21 60 00 8d 00 0c 00 00 00 +40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00 +40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00 +40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00 +40 00 60 04 bd 77 00 21 00 01 8d 00 20 01 8d 00 +40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00 +40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf +40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f +40 01 60 00 21 0c a1 20 e0 00 60 00 80 00 00 00 +40 0d 60 00 be 7f a2 20 a0 40 60 00 00 00 80 3f diff --git a/src/intel/tools/tests/gen5/and.asm b/src/intel/tools/tests/gen5/and.asm new file mode 100644 index 00000000000..cc2f7608a12 --- /dev/null +++ b/src/intel/tools/tests/gen5/and.asm @@ -0,0 +1,20 @@ +and(8) g9<1>.wUD g9<4>.wUD 524032D { align16 }; +and(8) g5<1>.xD g5<4>.xD 1D { align16 }; +and(8) g5<1>D g6<8,8,1>D 1D { align1 }; +and(16) g14<1>D g12<8,8,1>D 1D { align1 compr }; +and(8) g2<1>D g2<8,8,1>UD 1D { align1 }; +and.nz.f0.0(8) null<1>.xD g9<4>.xUD 1D { align16 }; +and.nz.f0.0(8) null<1>D g8<8,8,1>UD 1D { align1 }; +and(8) g8<1>UD g2.4<0,1,0>UD 0x80000000UD { align1 }; +and.nz.f0.0(16) null<1>D g12<8,8,1>UD 1D { align1 compr }; +and(16) g12<1>UD g2.4<0,1,0>UD 0x80000000UD { align1 compr }; +and(16) g6<1>D g4<8,8,1>UD 1D { align1 compr }; +and(8) g2<1>UD g4<8,8,1>UD g3<8,8,1>UD { align1 }; +and(16) g6<1>UD g8<8,8,1>UD g4<8,8,1>UD { align1 compr }; +and(8) g17<1>.xUD g1<0>.xUD 0x80000000UD { align16 }; +and(8) g47<1>.xUD g48<4>.xUD g47<4>.xUD { align16 }; +and(1) g8<1>UD f0<0,1,0>UW 0x0000000fUD { align1 nomask }; +and.nz.f0.0(8) g7<1>D g7<8,8,1>D 1D { align1 }; +and.nz.f0.0(16) g14<1>D g8<8,8,1>D 1D { align1 compr }; +and(8) g3<1>.xD g3<4>.xUD 1D { align16 }; +and.nz.f0.0(1) null<1>UD g1.6<0,1,0>UD 0x04000000UD { align1 }; diff --git a/src/intel/tools/tests/gen5/and.expected b/src/intel/tools/tests/gen5/and.expected new file mode 100644 index 00000000000..7d12dd55a7a --- /dev/null +++ b/src/intel/tools/tests/gen5/and.expected @@ -0,0 +1,20 @@ +05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00 +05 01 60 00 a5 1c a1 20 a0 00 60 00 01 00 00 00 +05 00 60 00 a5 1c a0 20 c0 00 8d 00 01 00 00 00 +05 20 80 00 a5 1c c0 21 80 01 8d 00 01 00 00 00 +05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00 +05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00 +05 00 60 02 24 1c 00 20 00 01 8d 00 01 00 00 00 +05 00 60 00 21 0c 00 21 50 00 00 00 00 00 00 80 +05 20 80 02 24 1c 00 20 80 01 8d 00 01 00 00 00 +05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80 +05 20 80 00 25 1c c0 20 80 00 8d 00 01 00 00 00 +05 00 60 00 21 04 40 20 80 00 8d 00 60 00 8d 00 +05 20 80 00 21 04 c0 20 00 01 8d 00 80 00 8d 00 +05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80 +05 01 60 00 21 04 e1 25 00 06 60 00 e0 05 60 00 +05 02 00 00 01 0d 00 21 00 06 00 00 0f 00 00 00 +05 00 60 02 a5 1c e0 20 e0 00 8d 00 01 00 00 00 +05 20 80 02 a5 1c c0 21 00 01 8d 00 01 00 00 00 +05 01 60 00 25 1c 61 20 60 00 60 00 01 00 00 00 +05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04 diff --git a/src/intel/tools/tests/gen5/asr.asm b/src/intel/tools/tests/gen5/asr.asm new file mode 100644 index 00000000000..4374a805e85 --- /dev/null +++ b/src/intel/tools/tests/gen5/asr.asm @@ -0,0 +1,6 @@ +asr.nz.f0.0(8) null<1>D -g1.6<0,1,0>D 31D { align1 }; +asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr }; +asr(8) g4<1>D g5<4>D g4<4>UD { align16 }; +asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 }; +asr(8) g5<1>D g3<8,8,1>D 0x00000002UD { align1 }; +asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr }; diff --git a/src/intel/tools/tests/gen5/asr.expected b/src/intel/tools/tests/gen5/asr.expected new file mode 100644 index 00000000000..8da3c86b04a --- /dev/null +++ b/src/intel/tools/tests/gen5/asr.expected @@ -0,0 +1,6 @@ +0c 00 60 02 a4 1c 00 20 38 40 00 00 1f 00 00 00 +0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00 +0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00 +0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00 +0c 00 60 00 a5 0c a0 20 60 00 8d 00 02 00 00 00 +0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00 diff --git a/src/intel/tools/tests/gen5/break.asm b/src/intel/tools/tests/gen5/break.asm new file mode 100644 index 00000000000..26ab8819c18 --- /dev/null +++ b/src/intel/tools/tests/gen5/break.asm @@ -0,0 +1,4 @@ +(+f0.0) break(8) Jump: 282 Pop: 0 { align1 }; +(+f0.0) break(16) Jump: 282 Pop: 0 { align1 }; +(+f0.0.x) break(8) Jump: 32 Pop: 0 { align16 }; +break(8) Jump: 12 Pop: 2 { align16 }; diff --git a/src/intel/tools/tests/gen5/break.expected b/src/intel/tools/tests/gen5/break.expected new file mode 100644 index 00000000000..1ccb9111760 --- /dev/null +++ b/src/intel/tools/tests/gen5/break.expected @@ -0,0 +1,4 @@ +28 00 61 00 00 1c 00 34 00 14 60 00 1a 01 00 00 +28 00 81 00 00 1c 00 34 00 14 60 00 1a 01 00 00 +28 01 62 00 00 1c 0f 34 04 14 6e 00 20 00 00 00 +28 01 60 00 00 1c 0f 34 04 14 6e 00 0c 00 02 00 diff --git a/src/intel/tools/tests/gen5/cmp.asm b/src/intel/tools/tests/gen5/cmp.asm new file mode 100644 index 00000000000..d2cbcf031b2 --- /dev/null +++ b/src/intel/tools/tests/gen5/cmp.asm @@ -0,0 +1,91 @@ +cmp.ge.f0.0(8) null<1>D g12<8,8,1>D 16D { align1 }; +cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr }; +cmp.ge.f0.0(8) null<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 }; +cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr }; +cmp.ge.f0.0(8) null<1>F g5<4>.xF 0x0F /* 0F */ { align16 }; +cmp.l.f0.0(8) null<1>F g5<4>.wF 0x43000000F /* 128F */ { align16 }; +cmp.le.f0.0(8) g5<1>.xF g5<4>.xF 0x0F /* 0F */ { align16 }; +cmp.nz.f0.0(8) null<1>.zD -g5<4>.xD 0D { align16 }; +cmp.ge.f0.0(8) g6<1>F g4<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 }; +cmp.ge.f0.0(16) g12<1>F g8<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 compr }; +cmp.ge.f0.0(8) null<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 }; +cmp.ge.f0.0(16) null<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr }; +cmp.z.f0.0(8) null<1>D g3<8,8,1>D 1D { align1 }; +cmp.z.f0.0(16) null<1>D g8<8,8,1>D 1D { align1 compr }; +cmp.nz.f0.0(8) g5<1>F g5<8,8,1>F g38<8,8,1>F { align1 }; +cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 }; +cmp.z.f0.0(8) g9<1>.xD g4<4>.xD g1<0>.xD { align16 }; +cmp.z.f0.0(8) g10<1>.xD g1<0>.xD 1D { align16 }; +cmp.nz.f0.0(8) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 }; +cmp.nz.f0.0(16) g20<1>F g6<8,8,1>F -g14<8,8,1>F { align1 compr }; +cmp.nz.f0.0(16) null<1>F g2.4<0,1,0>F 0x0F /* 0F */ { align1 compr }; +cmp.z.f0.0(8) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 }; +cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr }; +cmp.l.f0.0(8) g31<1>.xyzF g8<0>.wF g30<4>.xF { align16 }; +cmp.z.f0.0(8) g3<1>D g3<8,8,1>D g2.5<0,1,0>D { align1 }; +cmp.z.f0.0(16) g4<1>D g8<8,8,1>D g2.5<0,1,0>D { align1 compr }; +cmp.nz.f0.0(8) null<1>F g1<0>.xF 0x0F /* 0F */ { align16 }; +cmp.nz.f0.0(8) g17<1>.xF g17<4>.xF g1<0>.zF { align16 }; +cmp.le.f0.0(8) g5<1>.xD g1<0>.xD 0D { align16 }; +cmp.le.f0.0(8) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 }; +cmp.le.f0.0(8) g10<1>F g2<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 }; +cmp.ge.f0.0(8) g9<1>F -g3<8,8,1>F g9<8,8,1>F { align1 }; +cmp.nz.f0.0(8) null<1>D g20<8,8,1>D 0D { align1 }; +cmp.nz.f0.0(8) g24<1>D g20<8,8,1>D 2D { align1 }; +cmp.z.f0.0(8) g25<1>D g20<8,8,1>D 2D { align1 }; +cmp.le.f0.0(16) null<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 compr }; +cmp.le.f0.0(16) g20<1>F g4<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 compr }; +cmp.ge.f0.0(16) g24<1>F -g6<8,8,1>F g12<8,8,1>F { align1 compr }; +cmp.nz.f0.0(16) null<1>D g40<8,8,1>D 0D { align1 compr }; +cmp.nz.f0.0(16) g48<1>D g40<8,8,1>D 2D { align1 compr }; +cmp.z.f0.0(16) g52<1>D g40<8,8,1>D 2D { align1 compr }; +cmp.g.f0.0(8) g4<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 }; +cmp.l.f0.0(8) null<1>F g1<0>F g3<4>F { align16 }; +cmp.z.f0.0(8) null<1>.xD g1<0>.xD 1D { align16 }; +cmp.ge.f0.0(8) g3<1>F g1<0>F g1.4<0>F { align16 }; +cmp.g.f0.0(8) g3<1>F (abs)g2<8,8,1>F 0x3a83126fF /* 0.001F */ { align1 }; +cmp.g.f0.0(16) g6<1>F (abs)g4<8,8,1>F 0x3a83126fF /* 0.001F */ { align1 compr }; +cmp.le.f0.0(8) null<1>.xF g8<4>.xF 0x3f000000F /* 0.5F */ { align16 }; +cmp.ge.f0.0(8) g48<1>.xF g8<4>.xF 0x3727c5acF /* 1e-05F */ { align16 }; +cmp.ge.f0.0(8) null<1>.xF g22<4>.xF g10<4>.xF { align16 }; +cmp.l.f0.0(8) null<1>F g2<0,1,0>F 0x3eb33333F /* 0.35F */ { align1 }; +cmp.l.f0.0(8) null<1>F g3<8,8,1>F g4<8,8,1>F { align1 }; +cmp.l.f0.0(16) null<1>F g2<0,1,0>F 0x3eb33333F /* 0.35F */ { align1 compr }; +cmp.l.f0.0(16) null<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr }; +cmp.l.f0.0(8) g2<1>F g2<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 }; +cmp.l.f0.0(16) g4<1>F g6<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 compr }; +cmp.z.f0.0(8) null<1>D g3<8,8,1>D g2<0,1,0>D { align1 }; +cmp.nz.f0.0(8) g4<1>D g3<8,8,1>D g2.1<0,1,0>D { align1 }; +cmp.z.f0.0(16) null<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr }; +cmp.nz.f0.0(16) g4<1>D g6<8,8,1>D g2.1<0,1,0>D { align1 compr }; +cmp.nz.f0.0(8) g3<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 }; +(+f0.1) cmp.z.f0.1(8) null<1>D g3<8,8,1>D 0D { align1 }; +cmp.nz.f0.0(16) g8<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr }; +(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D 0D { align1 compr }; +cmp.ge.f0.0(8) null<1>D g4<8,8,1>D g2<0,1,0>D { align1 }; +cmp.ge.f0.0(16) null<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr }; +cmp.nz.f0.0(8) null<1>F g4<4>.xyyyF g3<4>.xyyyF { align16 }; +cmp.z.f0.0(8) g3<1>F g3<4>F 0x0F /* 0F */ { align16 }; +cmp.nz.f0.0(8) g11<1>.xD g4<4>.xD 10D { align16 }; +cmp.nz.f0.0(8) null<1>.xD g6<4>.xD g3<4>.xD { align16 }; +cmp.z.f0.0(8) g3<1>F g3<8,8,1>F g2.2<0,1,0>F { align1 }; +cmp.z.f0.0(16) g8<1>F g6<8,8,1>F g2.2<0,1,0>F { align1 compr }; +cmp.nz.f0.0(8) g3<1>F g3<4>F 0x0F /* 0F */ { align16 }; +cmp.l.f0.0(8) g5<1>F g2<0,1,0>F g7<8,8,1>F { align1 }; +cmp.l.f0.0(16) g4<1>F g2<0,1,0>F g16<8,8,1>F { align1 compr }; +cmp.le.f0.0(8) g3<1>D g2<0,1,0>D 0D { align1 }; +cmp.le.f0.0(16) g4<1>D g2<0,1,0>D 0D { align1 compr }; +cmp.l.f0.0(8) g5<1>.xF g3<0>.zF 0x3f000000F /* 0.5F */ { align16 }; +cmp.ge.f0.0(8) null<1>.xD g5<4>.xD g1<0>.xD { align16 }; +cmp.l.f0.0(8) null<1>.xD g6<4>.xD g5<4>.xD { align16 }; +cmp.ge.f0.0(8) g10<1>.xD g5<4>.xD 2D { align16 }; +cmp.z.f0.0(8) g3<1>F g3<8,8,1>F 0x40a00000F /* 5F */ { align1 }; +cmp.z.f0.0(16) g8<1>F g4<8,8,1>F 0x40a00000F /* 5F */ { align1 compr }; +cmp.g.f0.0(8) null<1>.xF g2<4>.zF 0x3f400000F /* 0.75F */ { align16 }; +cmp.le.f0.0(8) g3<1>.xUD g1<0>.xUD 0x00000001UD { align16 }; +cmp.z.f0.0(8) null<1>F g8<4>.xyzzF g3<0>.yzwwF { align16 }; +cmp.z.f0.0(8) g8<1>.xF g8<4>.xF g3<0>.yF { align16 }; +cmp.g.f0.0(8) null<1>.xD g1<0>.xD 0D { align16 }; +cmp.g.f0.0(8) g8<1>.xD g1<0>.xD 2D { align16 }; +cmp.nz.f0.0(8) null<1>F g27<8,8,1>F g2.6<0,1,0>F { align1 }; +cmp.nz.f0.0(16) null<1>F g16<8,8,1>F g2.6<0,1,0>F { align1 compr }; diff --git a/src/intel/tools/tests/gen5/cmp.expected b/src/intel/tools/tests/gen5/cmp.expected new file mode 100644 index 00000000000..c8ba62906ec --- /dev/null +++ b/src/intel/tools/tests/gen5/cmp.expected @@ -0,0 +1,91 @@ +10 00 60 04 a4 1c 00 20 80 01 8d 00 10 00 00 00 +10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00 +10 00 60 04 bc 7f 00 20 60 00 8d 00 00 00 00 00 +10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00 +10 01 60 04 bc 7f 0f 20 a0 00 60 00 00 00 00 00 +10 01 60 05 bc 7f 0f 20 af 00 6f 00 00 00 00 43 +10 01 60 06 bd 7f a1 20 a0 00 60 00 00 00 00 00 +10 01 60 02 a4 1c 04 20 a0 40 60 00 00 00 00 00 +10 00 60 04 bd 7f c0 20 80 00 8d 00 7d 1d 90 26 +10 20 80 04 bd 7f 80 21 00 01 8d 00 7d 1d 90 26 +10 00 60 04 bc 77 00 20 80 20 8d 00 60 20 8d 00 +10 20 80 04 bc 77 00 20 00 22 8d 00 00 21 8d 00 +10 00 60 01 a4 1c 00 20 60 00 8d 00 01 00 00 00 +10 20 80 01 a4 1c 00 20 00 01 8d 00 01 00 00 00 +10 00 60 02 bd 77 a0 20 a0 00 8d 00 c0 04 8d 00 +10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00 +10 01 60 01 a5 14 21 21 80 00 60 00 20 00 00 00 +10 01 60 01 a5 1c 41 21 20 00 00 00 01 00 00 00 +10 00 60 02 bc 7f 00 20 50 00 00 00 00 00 00 00 +10 20 80 02 bd 77 80 22 c0 00 8d 00 c0 41 8d 00 +10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00 +10 00 60 01 bc 7f 00 20 84 00 00 00 00 00 80 3f +10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f +10 01 60 05 bd 77 e7 23 0f 01 0f 00 c0 03 60 00 +10 00 60 01 a5 14 60 20 60 00 8d 00 54 00 00 00 +10 20 80 01 a5 14 80 20 00 01 8d 00 54 00 00 00 +10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00 +10 01 60 02 bd 77 21 22 20 02 60 00 2a 00 0a 00 +10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00 +10 00 60 06 bc 7f 00 20 40 00 8d 00 00 00 00 3f +10 00 60 06 bd 7f 40 21 40 00 8d 00 9a 3f 1c 46 +10 00 60 04 bd 77 20 21 60 40 8d 00 20 01 8d 00 +10 00 60 02 a4 1c 00 20 80 02 8d 00 00 00 00 00 +10 00 60 02 a5 1c 00 23 80 02 8d 00 02 00 00 00 +10 00 60 01 a5 1c 20 23 80 02 8d 00 02 00 00 00 +10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f +10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46 +10 20 80 04 bd 77 00 23 c0 40 8d 00 80 01 8d 00 +10 20 80 02 a4 1c 00 20 00 05 8d 00 00 00 00 00 +10 20 80 02 a5 1c 00 26 00 05 8d 00 02 00 00 00 +10 20 80 01 a5 1c 80 26 00 05 8d 00 02 00 00 00 +10 01 60 03 bd 7f 8f 20 64 00 6e 00 00 00 00 3f +10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00 +10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00 +10 01 60 04 bd 77 6f 20 24 00 0e 00 34 00 0e 00 +10 00 60 03 bd 7f 60 20 40 20 8d 00 6f 12 83 3a +10 20 80 03 bd 7f c0 20 80 20 8d 00 6f 12 83 3a +10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f +10 01 60 04 bd 7f 01 26 00 01 60 00 ac c5 27 37 +10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00 +10 00 60 05 bc 7f 00 20 40 00 00 00 33 33 b3 3e +10 00 60 05 bc 77 00 20 60 00 8d 00 80 00 8d 00 +10 20 80 05 bc 7f 00 20 40 00 00 00 33 33 b3 3e +10 20 80 05 bc 77 00 20 80 00 8d 00 c0 00 8d 00 +10 00 60 05 bd 7f 40 20 40 00 8d 00 00 00 80 3b +10 20 80 05 bd 7f 80 20 c0 00 8d 00 00 00 80 3b +10 00 60 01 a4 14 00 20 60 00 8d 00 40 00 00 00 +10 00 60 02 a5 14 80 20 60 00 8d 00 44 00 00 00 +10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00 +10 20 80 02 a5 14 80 20 c0 00 8d 00 44 00 00 00 +10 00 60 02 bd 7f 60 20 60 00 8d 00 00 00 00 00 +10 00 61 01 a4 1c 00 20 60 00 8d 02 00 00 00 00 +10 20 80 02 bd 7f 00 21 c0 00 8d 00 00 00 00 00 +10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00 +10 00 60 04 a4 14 00 20 80 00 8d 00 40 00 00 00 +10 20 80 04 a4 14 00 20 c0 00 8d 00 40 00 00 00 +10 01 60 02 bc 77 0f 20 84 00 65 00 64 00 65 00 +10 01 60 01 bd 7f 6f 20 64 00 6e 00 00 00 00 00 +10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00 +10 01 60 02 a4 14 01 20 c0 00 60 00 60 00 60 00 +10 00 60 01 bd 77 60 20 60 00 8d 00 48 00 00 00 +10 20 80 01 bd 77 00 21 c0 00 8d 00 48 00 00 00 +10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00 +10 00 60 05 bd 77 a0 20 40 00 00 00 e0 00 8d 00 +10 20 80 05 bd 77 80 20 40 00 00 00 00 02 8d 00 +10 00 60 06 a5 1c 60 20 40 00 00 00 00 00 00 00 +10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00 +10 01 60 05 bd 7f a1 20 6a 00 0a 00 00 00 00 3f +10 01 60 04 a4 14 01 20 a0 00 60 00 20 00 00 00 +10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00 +10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00 +10 00 60 01 bd 7f 60 20 60 00 8d 00 00 00 a0 40 +10 20 80 01 bd 7f 00 21 80 00 8d 00 00 00 a0 40 +10 01 60 03 bc 7f 01 20 4a 00 6a 00 00 00 40 3f +10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00 +10 01 60 01 bc 77 0f 20 04 01 6a 00 69 00 0f 00 +10 01 60 01 bd 77 01 21 00 01 60 00 65 00 05 00 +10 01 60 03 a4 1c 01 20 20 00 00 00 00 00 00 00 +10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00 +10 00 60 02 bc 77 00 20 60 03 8d 00 58 00 00 00 +10 20 80 02 bc 77 00 20 00 02 8d 00 58 00 00 00 diff --git a/src/intel/tools/tests/gen5/do.asm b/src/intel/tools/tests/gen5/do.asm new file mode 100644 index 00000000000..945fdc1c7e6 --- /dev/null +++ b/src/intel/tools/tests/gen5/do.asm @@ -0,0 +1,3 @@ +do(8) { align1 }; +do(16) { align1 }; +do(8) { align16 }; diff --git a/src/intel/tools/tests/gen5/do.expected b/src/intel/tools/tests/gen5/do.expected new file mode 100644 index 00000000000..7dac5f7f435 --- /dev/null +++ b/src/intel/tools/tests/gen5/do.expected @@ -0,0 +1,3 @@ +26 00 60 00 9c 73 00 20 00 00 8d 00 00 00 8d 00 +26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00 +26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00 diff --git a/src/intel/tools/tests/gen5/dp3.asm b/src/intel/tools/tests/gen5/dp3.asm new file mode 100644 index 00000000000..4af3bc91ae1 --- /dev/null +++ b/src/intel/tools/tests/gen5/dp3.asm @@ -0,0 +1,10 @@ +dp3(8) m5<1>.xF g3<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr }; +dp3(8) m5<1>.yF g3.4<0>.xyzzF g6<4>.xyzzF { align16 NoDDClr,NoDDChk }; +dp3(8) g25<1>.xF g17<4>.xyzzF g3<0>.xyzzF { align16 }; +dp3(8) g19<1>.xF g3<0>.xyzzF g3.4<0>.xyzzF { align16 NoDDClr }; +dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk }; +dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk }; +dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 }; +dp3.le.f0.0(8) g18<1>.xF g17<4>.xyzzF g3.4<0>.xyzzF { align16 }; +dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 }; +dp3.sat(8) m5<1>F g3<4>.xyzzF g3<4>.xyzzF { align16 }; diff --git a/src/intel/tools/tests/gen5/dp3.expected b/src/intel/tools/tests/gen5/dp3.expected new file mode 100644 index 00000000000..01365ea8889 --- /dev/null +++ b/src/intel/tools/tests/gen5/dp3.expected @@ -0,0 +1,10 @@ +56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00 +56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00 +56 01 60 00 bd 77 21 23 24 02 6a 00 64 00 0a 00 +56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00 +56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00 +56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00 +56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00 +56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00 +56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00 +56 01 60 80 be 77 af 20 64 00 6a 00 64 00 6a 00 diff --git a/src/intel/tools/tests/gen5/dp4.asm b/src/intel/tools/tests/gen5/dp4.asm new file mode 100644 index 00000000000..3ea82da7ffd --- /dev/null +++ b/src/intel/tools/tests/gen5/dp4.asm @@ -0,0 +1,6 @@ +dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 }; +dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr }; +dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk }; +dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk }; +dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 }; +dp4.sat(8) m5<1>F g3<4>.xF g3<4>F { align16 }; diff --git a/src/intel/tools/tests/gen5/dp4.expected b/src/intel/tools/tests/gen5/dp4.expected new file mode 100644 index 00000000000..cae5f7689ea --- /dev/null +++ b/src/intel/tools/tests/gen5/dp4.expected @@ -0,0 +1,6 @@ +54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00 +54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00 +54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00 +54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00 +54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00 +54 01 60 80 be 77 af 20 60 00 60 00 64 00 6e 00 diff --git a/src/intel/tools/tests/gen5/dph.asm b/src/intel/tools/tests/gen5/dph.asm new file mode 100644 index 00000000000..2992b2802ba --- /dev/null +++ b/src/intel/tools/tests/gen5/dph.asm @@ -0,0 +1,4 @@ +dph(8) m5<1>.xF g4<4>.xyzxF g5<4>F { align16 }; +dph.sat(8) m5<1>F g1<0>.xyzxF g3<4>F { align16 }; +dph(8) g5<1>.xF g4<4>.xyzxF g1<0>F { align16 NoDDClr }; +dph(8) g5<1>.yF g4<4>.xyzxF g1.4<0>F { align16 NoDDClr,NoDDChk }; diff --git a/src/intel/tools/tests/gen5/dph.expected b/src/intel/tools/tests/gen5/dph.expected new file mode 100644 index 00000000000..c54009202f9 --- /dev/null +++ b/src/intel/tools/tests/gen5/dph.expected @@ -0,0 +1,4 @@ +55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00 +55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00 +55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00 +55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00 diff --git a/src/intel/tools/tests/gen5/else.asm b/src/intel/tools/tests/gen5/else.asm new file mode 100644 index 00000000000..114c607ef53 --- /dev/null +++ b/src/intel/tools/tests/gen5/else.asm @@ -0,0 +1,3 @@ +else(8) Jump: 86 Pop: 1 { align1 switch }; +else(16) Jump: 86 Pop: 1 { align1 switch }; +else(8) Jump: 14 Pop: 1 { align16 switch }; diff --git a/src/intel/tools/tests/gen5/else.expected b/src/intel/tools/tests/gen5/else.expected new file mode 100644 index 00000000000..1ef88bcbeb8 --- /dev/null +++ b/src/intel/tools/tests/gen5/else.expected @@ -0,0 +1,3 @@ +24 80 60 00 00 1c 00 34 00 14 60 00 56 00 01 00 +24 80 80 00 00 1c 00 34 00 14 60 00 56 00 01 00 +24 81 60 00 00 1c 0f 34 04 14 6e 00 0e 00 01 00 diff --git a/src/intel/tools/tests/gen5/endif.asm b/src/intel/tools/tests/gen5/endif.asm new file mode 100644 index 00000000000..48994f75772 --- /dev/null +++ b/src/intel/tools/tests/gen5/endif.asm @@ -0,0 +1,3 @@ +endif(8) Pop: 1 { align16 switch }; +endif(8) Pop: 1 { align1 switch }; +endif(16) Pop: 1 { align1 switch }; diff --git a/src/intel/tools/tests/gen5/endif.expected b/src/intel/tools/tests/gen5/endif.expected new file mode 100644 index 00000000000..67335a7e387 --- /dev/null +++ b/src/intel/tools/tests/gen5/endif.expected @@ -0,0 +1,3 @@ +25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00 +25 80 60 00 84 1c 00 20 00 00 8d 00 00 00 01 00 +25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00 diff --git a/src/intel/tools/tests/gen5/frc.asm b/src/intel/tools/tests/gen5/frc.asm new file mode 100644 index 00000000000..102fba1959d --- /dev/null +++ b/src/intel/tools/tests/gen5/frc.asm @@ -0,0 +1,4 @@ +frc.sat(8) m5<1>F g3<4>F { align16 }; +frc(8) g7<1>.xF (abs)g1<0>.xF { align16 }; +frc(8) g4<1>F g3<8,8,1>F { align1 }; +frc(16) g4<1>F g6<8,8,1>F { align1 compr }; diff --git a/src/intel/tools/tests/gen5/frc.expected b/src/intel/tools/tests/gen5/frc.expected new file mode 100644 index 00000000000..4bd4f50ee3c --- /dev/null +++ b/src/intel/tools/tests/gen5/frc.expected @@ -0,0 +1,4 @@ +43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00 +43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00 +43 00 60 00 bd 03 80 20 60 00 8d 00 00 00 00 00 +43 20 80 00 bd 03 80 20 c0 00 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen5/if.asm b/src/intel/tools/tests/gen5/if.asm new file mode 100644 index 00000000000..e6f832ec474 --- /dev/null +++ b/src/intel/tools/tests/gen5/if.asm @@ -0,0 +1,3 @@ +(+f0.0) if(8) Jump: 10 { align1 switch }; +(+f0.0) if(16) Jump: 10 { align1 switch }; +(+f0.0.x) if(8) Jump: 26 { align16 switch }; diff --git a/src/intel/tools/tests/gen5/if.expected b/src/intel/tools/tests/gen5/if.expected new file mode 100644 index 00000000000..d6199765627 --- /dev/null +++ b/src/intel/tools/tests/gen5/if.expected @@ -0,0 +1,3 @@ +22 80 61 00 00 1c 00 34 00 14 60 00 0a 00 00 00 +22 80 81 00 00 1c 00 34 00 14 60 00 0a 00 00 00 +22 81 62 00 00 1c 0f 34 04 14 6e 00 1a 00 00 00 diff --git a/src/intel/tools/tests/gen5/iff.asm b/src/intel/tools/tests/gen5/iff.asm new file mode 100644 index 00000000000..6ccc9c49c46 --- /dev/null +++ b/src/intel/tools/tests/gen5/iff.asm @@ -0,0 +1,3 @@ +(+f0.0.x) iff(8) Jump: 22 { align16 switch }; +(+f0.0) iff(8) Jump: 44 { align1 switch }; +(+f0.0) iff(16) Jump: 44 { align1 switch }; diff --git a/src/intel/tools/tests/gen5/iff.expected b/src/intel/tools/tests/gen5/iff.expected new file mode 100644 index 00000000000..75a81c3788e --- /dev/null +++ b/src/intel/tools/tests/gen5/iff.expected @@ -0,0 +1,3 @@ +23 81 62 00 00 1c 0f 34 04 14 6e 00 16 00 00 00 +23 80 61 00 00 1c 00 34 00 14 60 00 2c 00 00 00 +23 80 81 00 00 1c 00 34 00 14 60 00 2c 00 00 00 diff --git a/src/intel/tools/tests/gen5/jmpi.asm b/src/intel/tools/tests/gen5/jmpi.asm new file mode 100644 index 00000000000..e3dc60543d9 --- /dev/null +++ b/src/intel/tools/tests/gen5/jmpi.asm @@ -0,0 +1 @@ +(+f0.0) jmpi(1) 0x00000004UD { align1 nomask }; diff --git a/src/intel/tools/tests/gen5/jmpi.expected b/src/intel/tools/tests/gen5/jmpi.expected new file mode 100644 index 00000000000..9c2dfcfcf5a --- /dev/null +++ b/src/intel/tools/tests/gen5/jmpi.expected @@ -0,0 +1 @@ +20 02 01 00 00 0c 00 34 00 14 00 00 04 00 00 00 diff --git a/src/intel/tools/tests/gen5/mach.asm b/src/intel/tools/tests/gen5/mach.asm new file mode 100644 index 00000000000..4854911925b --- /dev/null +++ b/src/intel/tools/tests/gen5/mach.asm @@ -0,0 +1,4 @@ +mach(8) g3<1>UD g2<8,8,1>UD 0xaaaaaaabUD { align1 }; +mach(8) g2<1>D g2<8,8,1>D 1431655766D { align1 }; +mach(16) g4<1>UD g12<8,8,1>UD 0xaaaaaaabUD { align1 compr }; +mach(16) g4<1>D g12<8,8,1>D 1431655766D { align1 compr }; diff --git a/src/intel/tools/tests/gen5/mach.expected b/src/intel/tools/tests/gen5/mach.expected new file mode 100644 index 00000000000..472d8b03ba0 --- /dev/null +++ b/src/intel/tools/tests/gen5/mach.expected @@ -0,0 +1,4 @@ +49 00 60 00 21 0c 60 20 40 00 8d 00 ab aa aa aa +49 00 60 00 a5 1c 40 20 40 00 8d 00 56 55 55 55 +49 20 80 00 21 0c 80 20 80 01 8d 00 ab aa aa aa +49 20 80 00 a5 1c 80 20 80 01 8d 00 56 55 55 55 diff --git a/src/intel/tools/tests/gen5/mov.asm b/src/intel/tools/tests/gen5/mov.asm new file mode 100644 index 00000000000..d441898a286 --- /dev/null +++ b/src/intel/tools/tests/gen5/mov.asm @@ -0,0 +1,103 @@ +mov(8) m2<1>UD g1<8,8,1>UD { align1 nomask }; +mov(8) g9<1>.xyzUD 0x00000000UD { align16 }; +mov.sat(8) m5<1>F g4<4>F { align16 }; +mov(8) m4<1>F g6<4>F { align16 }; +mov(8) m2<1>UD g9<4>UD { align16 }; +mov(8) m3<1>F g4.3<0,1,0>F { align1 }; +mov(16) m3<1>F g4.3<0,1,0>F { align1 compr4 }; +mov(8) g2<1>F g2<8,8,1>UW { align1 }; +mov(8) g2<1>D g2<8,8,1>F { align1 }; +mov(8) g2<1>F g2<8,8,1>D { align1 }; +mov(16) g12<1>F g4<8,8,1>UW { align1 compr }; +mov(16) g4<1>D g12<8,8,1>F { align1 compr }; +mov(16) g12<1>F g4<8,8,1>D { align1 compr }; +mov(8) m2<1>UD 0x00000000UD { align16 }; +mov(8) m4<1>F 0x0F /* 0F */ { align1 }; +mov(16) m3<1>F 0x0F /* 0F */ { align1 compr4 }; +mov(8) g2<1>.xD 224D { align16 }; +mov(8) m15<1>D g2<4>.xUD { align16 }; +mov(8) g12<1>D 0D { align1 }; +mov(8) m2<1>UD 0x00000000UD { align1 }; +mov(16) g14<1>D 0D { align1 compr }; +mov(16) m2<1>UD 0x00000000UD { align1 compr }; +mov(8) g5<1>.xyF 0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 }; +mov(8) g4<1>.xyD g2<4>.xyyyD { align16 }; +mov(8) m4<1>D g9.3<0,1,0>D { align1 }; +mov(8) m5<1>UD 0D { align1 }; +mov(8) m2<1>D g2<8,8,1>F { align1 }; +mov(16) m6<1>D g9.3<0,1,0>D { align1 compr }; +mov(16) m8<1>UD 0D { align1 compr }; +mov(16) m2<1>D g4<8,8,1>F { align1 compr }; +mov.sat(8) m3<1>F g2<0,1,0>F { align1 }; +mov.sat(16) m3<1>F g2<0,1,0>F { align1 compr4 }; +mov(8) m5<1>.wD 0D { align16 NoDDChk }; +mov(8) m3<1>F 0x42fc6666F /* 126.2F */ { align1 sechalf }; +mov(8) m5<1>.wD g8<4>.wD { align16 NoDDChk }; +mov(8) g6<1>.xD g6<4>.xF { align16 }; +mov(8) m3<1>UD g2<8,8,1>UD { align1 }; +mov(16) m3<1>UD g4<8,8,1>UD { align1 compr4 }; +mov(8) m5<1>F 0x28000030VF /* [1F, 0F, 0F, 0.75F]VF */ { align16 }; +mov(8) m6<1>.xF 0x0F /* 0F */ { align16 }; +mov(8) m3<1>F g2<8,8,1>D { align1 }; +mov(8) m5<1>.xF g1<0>.xD { align16 NoDDClr }; +mov(8) m5<1>.yF g3<4>.xD { align16 NoDDClr,NoDDChk }; +mov(8) m5<1>.wF g3<4>.xD { align16 NoDDChk }; +mov(8) g3<1>.xF g3<4>.xD { align16 NoDDClr }; +mov(8) g3<1>.yF g4<4>.xD { align16 NoDDClr,NoDDChk }; +mov(8) g3<1>.wF g4<4>.xD { align16 NoDDChk }; +mov(8) g8<1>UD g2<4>UD { align16 }; +mov(8) g7<1>.xF g3<0>.xD { align16 }; +mov(8) g6<1>.xF -g5<4>.yF { align16 NoDDClr }; +mov(8) g6<1>.yD g5<4>.xD { align16 NoDDChk }; +mov(8) m2<1>D g3<0>.xD { align16 }; +mov.nz.f0.0(8) g4<1>F -(abs)g2<0,1,0>F { align1 }; +(+f0.0) mov(8) g4<1>F 0xbf800000F /* -1F */ { align1 }; +mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 compr }; +(+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 compr }; +mov(8) g3<1>.xyzF 0x0F /* 0F */ { align16 }; +mov(8) g3<1>.xyD g2<4>.xyyyD { align16 NoDDClr }; +mov.sat(8) m5<1>.wF g20<4>.wF { align16 NoDDChk }; +mov(8) g26<1>.xyzUD 0x00000000UD { align16 NoDDClr }; +mov(8) g21<1>.xD 1065353216D { align16 NoDDClr }; +mov(8) g5<1>.zwD 0D { align16 NoDDChk }; +mov(16) m4<1>F g4<8,8,1>D { align1 compr4 }; +mov(8) g3<1>D g2<8,8,1>D { align1 }; +mov(16) g6<1>D g4<8,8,1>D { align1 compr }; +mov(8) m3<1>F g4<8,8,1>F { align1 nomask }; +mov(8) m15<1>F g6<8,8,1>F { align1 sechalf }; +mov.sat(8) m5<1>.zF 0x3eaaaaabF /* 0.333333F */ { align16 }; +mov.sat(8) m5<1>.wF 0x3dcccccdF /* 0.1F */ { align16 NoDDClr }; +mov(8) m5<1>.xyF 0x2030VF /* [1F, 0.5F, 0F, 0F]VF */ { align16 NoDDChk }; +mov.sat(8) m5<1>F g4<4>D { align16 }; +mov(8) g10<1>F g10<8,8,1>F { align1 }; +mov(8) g11<1>F g4<8,8,1>F { align1 sechalf }; +mov.sat(8) m5<1>.zF 0x3f666660F /* 0.9F */ { align16 NoDDClr,NoDDChk }; +mov.sat(8) m5<1>.wF 0x3e4cccc0F /* 0.2F */ { align16 NoDDChk }; +mov(16) g10<1>F g2<0,1,0>F { align1 compr }; +mov(8) g5<1>F 0x3f800000F /* 1F */ { align1 }; +mov(16) g10<1>F 0x3f800000F /* 1F */ { align1 compr }; +mov(8) g3<1>.zD g1<0>.xD { align16 NoDDClr,NoDDChk }; +mov(1) m14<1>D 96D { align1 nomask }; +mov(1) m15<1>D g5<0,1,0>D { align1 nomask }; +mov(8) g33<1>.zD 1053609165D { align16 NoDDClr,NoDDChk }; +mov(8) g2<1>.xyzF g2<4>.wF { align16 }; +mov.nz.f0.0(8) null<1>D g2<8,8,1>D { align1 }; +mov.nz.f0.0(16) null<1>D g4<8,8,1>D { align1 compr }; +mov(8) m2<1>.zwF 0D { align16 }; +mov(8) m5<1>.xD 1036831949D { align16 }; +mov(8) m5<1>.yD 1045220557D { align16 NoDDClr }; +mov(8) m5<1>.zD 1050253722D { align16 NoDDClr,NoDDChk }; +mov(1) f0.1<1>UW g0<0,1,0>UW { align1 nomask }; +mov(1) g0<1>UW f0.1<0,1,0>UW { align1 nomask }; +(+f0.0.any4h) mov(8) g3<1>.xD -1D { align16 }; +mov.sat(8) m5<1>.yzF g1<0>.xxzzF { align16 NoDDClr }; +mov(8) m5<1>F g3<4>D { align16 }; +mov.sat(8) m5<1>.xF g5<4>.xD { align16 NoDDClr }; +mov.sat(8) m5<1>.yF g5<4>.xD { align16 NoDDClr,NoDDChk }; +mov.sat(8) m5<1>.wF g5<4>.xD { align16 NoDDChk }; +mov(8) g4<1>D 0x7e767676VF /* [22F, 22F, 22F, 30F]VF */ { align16 }; +mov(8) g5<1>F g3<4>UD { align16 }; +mov(8) m5<1>.xyzF 0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 NoDDClr }; +mov.nz.f0.0(8) null<1>.xD g8<4>.xD { align16 }; +mov.nz.f0.0(8) g8<1>F -(abs)g1<0>F { align16 }; +(+f0.0) mov(8) g8<1>F 0xbf800000F /* -1F */ { align16 }; diff --git a/src/intel/tools/tests/gen5/mov.expected b/src/intel/tools/tests/gen5/mov.expected new file mode 100644 index 00000000000..ab3947c1600 --- /dev/null +++ b/src/intel/tools/tests/gen5/mov.expected @@ -0,0 +1,103 @@ +01 02 60 00 22 00 40 20 20 00 8d 00 00 00 00 00 +01 01 60 00 61 00 27 21 00 00 00 00 00 00 00 00 +01 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00 +01 01 60 00 be 03 8f 20 c4 00 6e 00 00 00 00 00 +01 01 60 00 22 00 4f 20 24 01 6e 00 00 00 00 00 +01 00 60 00 be 03 60 20 8c 00 00 00 00 00 00 00 +01 20 80 00 be 03 60 30 8c 00 00 00 00 00 00 00 +01 00 60 00 3d 01 40 20 40 00 8d 00 00 00 00 00 +01 00 60 00 a5 03 40 20 40 00 8d 00 00 00 00 00 +01 00 60 00 bd 00 40 20 40 00 8d 00 00 00 00 00 +01 20 80 00 3d 01 80 21 80 00 8d 00 00 00 00 00 +01 20 80 00 a5 03 80 20 80 01 8d 00 00 00 00 00 +01 20 80 00 bd 00 80 21 80 00 8d 00 00 00 00 00 +01 01 60 00 62 00 4f 20 00 00 00 00 00 00 00 00 +01 00 60 00 fe 73 80 20 00 00 00 00 00 00 00 00 +01 20 80 00 fe 73 60 30 00 00 00 00 00 00 00 00 +01 01 60 00 e5 10 41 20 00 00 00 00 e0 00 00 00 +01 01 60 00 26 00 ef 21 40 00 60 00 00 00 00 00 +01 00 60 00 e5 10 80 21 00 00 00 00 00 00 00 00 +01 00 60 00 62 00 40 20 00 00 00 00 00 00 00 00 +01 20 80 00 e5 10 c0 21 00 00 00 00 00 00 00 00 +01 20 80 00 62 00 40 20 00 00 00 00 00 00 00 00 +01 01 60 00 fd 52 a3 20 00 00 00 00 00 30 00 00 +01 01 60 00 a5 00 83 20 44 00 65 00 00 00 00 00 +01 00 60 00 a6 00 80 20 2c 01 00 00 00 00 00 00 +01 00 60 00 e2 10 a0 20 00 00 00 00 00 00 00 00 +01 00 60 00 a6 03 40 20 40 00 8d 00 00 00 00 00 +01 20 80 00 a6 00 c0 20 2c 01 00 00 00 00 00 00 +01 20 80 00 e2 10 00 21 00 00 00 00 00 00 00 00 +01 20 80 00 a6 03 40 20 80 00 8d 00 00 00 00 00 +01 00 60 80 be 03 60 20 40 00 00 00 00 00 00 00 +01 20 80 80 be 03 60 30 40 00 00 00 00 00 00 00 +01 09 60 00 e6 10 a8 20 00 00 00 00 00 00 00 00 +01 10 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42 +01 09 60 00 a6 00 a8 20 0f 01 6f 00 00 00 00 00 +01 01 60 00 a5 03 c1 20 c0 00 60 00 00 00 00 00 +01 00 60 00 22 00 60 20 40 00 8d 00 00 00 00 00 +01 20 80 00 22 00 60 30 80 00 8d 00 00 00 00 00 +01 01 60 00 fe 52 af 20 00 00 00 00 30 00 00 28 +01 01 60 00 fe 73 c1 20 00 00 00 00 00 00 00 00 +01 00 60 00 be 00 60 20 40 00 8d 00 00 00 00 00 +01 05 60 00 be 00 a1 20 20 00 00 00 00 00 00 00 +01 0d 60 00 be 00 a2 20 60 00 60 00 00 00 00 00 +01 09 60 00 be 00 a8 20 60 00 60 00 00 00 00 00 +01 05 60 00 bd 00 61 20 60 00 60 00 00 00 00 00 +01 0d 60 00 bd 00 62 20 80 00 60 00 00 00 00 00 +01 09 60 00 bd 00 68 20 80 00 60 00 00 00 00 00 +01 01 60 00 21 00 0f 21 44 00 6e 00 00 00 00 00 +01 01 60 00 bd 00 e1 20 60 00 00 00 00 00 00 00 +01 05 60 00 bd 03 c1 20 a5 40 65 00 00 00 00 00 +01 09 60 00 a5 00 c2 20 a0 00 60 00 00 00 00 00 +01 01 60 00 a6 00 4f 20 60 00 00 00 00 00 00 00 +01 00 60 02 bd 03 80 20 40 60 00 00 00 00 00 00 +01 00 61 00 fd 73 80 20 00 00 00 00 00 00 80 bf +01 20 80 02 bd 03 80 20 40 60 00 00 00 00 00 00 +01 20 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf +01 01 60 00 fd 73 67 20 00 00 00 00 00 00 00 00 +01 05 60 00 a5 00 63 20 44 00 65 00 00 00 00 00 +01 09 60 80 be 03 a8 20 8f 02 6f 00 00 00 00 00 +01 05 60 00 61 00 47 23 00 00 00 00 00 00 00 00 +01 05 60 00 e5 10 a1 22 00 00 00 00 00 00 80 3f +01 09 60 00 e5 10 ac 20 00 00 00 00 00 00 00 00 +01 20 80 00 be 00 80 30 80 00 8d 00 00 00 00 00 +01 00 60 00 a5 00 60 20 40 00 8d 00 00 00 00 00 +01 20 80 00 a5 00 c0 20 80 00 8d 00 00 00 00 00 +01 02 60 00 be 03 60 20 80 00 8d 00 00 00 00 00 +01 10 60 00 be 03 e0 21 c0 00 8d 00 00 00 00 00 +01 01 60 80 fe 73 a4 20 00 00 00 00 ab aa aa 3e +01 05 60 80 fe 73 a8 20 00 00 00 00 cd cc cc 3d +01 09 60 00 fe 52 a3 20 00 00 00 00 30 20 00 00 +01 01 60 80 be 00 af 20 84 00 6e 00 00 00 00 00 +01 00 60 00 bd 03 40 21 40 01 8d 00 00 00 00 00 +01 10 60 00 bd 03 60 21 80 00 8d 00 00 00 00 00 +01 0d 60 80 fe 73 a4 20 00 00 00 00 60 66 66 3f +01 09 60 80 fe 73 a8 20 00 00 00 00 c0 cc 4c 3e +01 20 80 00 bd 03 40 21 40 00 00 00 00 00 00 00 +01 00 60 00 fd 73 a0 20 00 00 00 00 00 00 80 3f +01 20 80 00 fd 73 40 21 00 00 00 00 00 00 80 3f +01 0d 60 00 a5 00 64 20 20 00 00 00 00 00 00 00 +01 02 00 00 e6 10 c0 21 00 00 00 00 60 00 00 00 +01 02 00 00 a6 00 e0 21 a0 00 00 00 00 00 00 00 +01 0d 60 00 e5 10 24 24 00 00 00 00 cd cc cc 3e +01 01 60 00 bd 03 47 20 4f 00 6f 00 00 00 00 00 +01 00 60 02 a4 00 00 20 40 00 8d 00 00 00 00 00 +01 20 80 02 a4 00 00 20 80 00 8d 00 00 00 00 00 +01 01 60 00 fe 10 4c 20 00 00 00 00 00 00 00 00 +01 01 60 00 e6 10 a1 20 00 00 00 00 cd cc cc 3d +01 05 60 00 e6 10 a2 20 00 00 00 00 cd cc 4c 3e +01 0d 60 00 e6 10 a4 20 00 00 00 00 9a 99 99 3e +01 02 00 00 28 01 02 26 00 00 00 00 00 00 00 00 +01 02 00 00 09 01 00 20 02 06 00 00 00 00 00 00 +01 01 66 00 e5 10 61 20 00 00 00 00 ff ff ff ff +01 05 60 80 be 03 a6 20 20 00 0a 00 00 00 00 00 +01 01 60 00 be 00 af 20 64 00 6e 00 00 00 00 00 +01 05 60 80 be 00 a1 20 a0 00 60 00 00 00 00 00 +01 0d 60 80 be 00 a2 20 a0 00 60 00 00 00 00 00 +01 09 60 80 be 00 a8 20 a0 00 60 00 00 00 00 00 +01 01 60 00 e5 52 8f 20 00 00 00 00 76 76 76 7e +01 01 60 00 3d 00 af 20 64 00 6e 00 00 00 00 00 +01 05 60 00 fe 52 a7 20 00 00 00 00 00 30 00 00 +01 01 60 02 a4 00 01 20 00 01 60 00 00 00 00 00 +01 01 60 02 bd 03 0f 21 24 60 0e 00 00 00 00 00 +01 01 61 00 fd 73 0f 21 00 00 00 00 00 00 80 bf diff --git a/src/intel/tools/tests/gen5/mul.asm b/src/intel/tools/tests/gen5/mul.asm new file mode 100644 index 00000000000..06998c2f310 --- /dev/null +++ b/src/intel/tools/tests/gen5/mul.asm @@ -0,0 +1,35 @@ +mul(8) m3<1>F g3<8,8,1>F g2<8,8,1>F { align1 }; +mul(16) m3<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr4 }; +mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 }; +mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 }; +mul(8) g2<1>F g2<8,8,1>F g6.3<0,1,0>F { align1 }; +mul(16) g10<1>F g12<8,8,1>F g6.3<0,1,0>F { align1 compr }; +mul(8) g2<1>.xD g2<4>.xD g1<0>.xD { align16 }; +mul(8) g5<1>F g3<8,8,1>F 0x41800000F /* 16F */ { align1 }; +mul(8) m3<1>F g8<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 }; +mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr }; +mul(16) m3<1>F g6<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 compr4 }; +mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr }; +mul(8) g5<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 }; +mul.sat(8) m2<1>F g6<8,8,1>F g2<8,8,1>F { align1 }; +mul.sat(16) m2<1>F g14<8,8,1>F g6<8,8,1>F { align1 compr }; +mul.sat(8) g8<1>F g7<8,8,1>F g3<8,8,1>F { align1 }; +mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr }; +mul(8) acc0<1>UD g2<8,8,1>UD 0xaaaaaaabUD { align1 }; +mul(8) g3<1>D g4<8,8,1>D g3<8,8,1>D { align1 }; +mul(8) acc0<1>D g2<8,8,1>D 1431655766D { align1 }; +mul(16) acc0<1>UD g12<8,8,1>UD 0xaaaaaaabUD { align1 compr }; +mul(16) g4<1>D g16<8,8,1>D g8<8,8,1>D { align1 compr }; +mul(16) acc0<1>D g12<8,8,1>D 1431655766D { align1 compr }; +mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk }; +mul(8) g2<1>.xyzF g2<4>.wF 0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 }; +mul(8) g3<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 }; +mul(16) g4<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 compr }; +mul(8) m5<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 }; +mul.sat(8) m5<1>F g6<4>F 0x3b800000F /* 0.00390625F */ { align16 }; +mul(8) g5<1>.xD g5<4>.xD 32D { align16 }; +mul.sat(8) m5<1>F g3<4>F g3<4>F { align16 }; +mul.sat(8) m6<1>.xyzF g32<4>.xF g30<4>.xyzzF { align16 NoDDClr }; +mul.sat(8) m5<1>F g4<4>F 0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 }; +mul(8) m6<1>.xyzF g12<4>.xyzzF g13<4>.xF { align16 NoDDClr }; +mul.sat(8) m5<1>.xyzF g7<4>.xF 0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr }; diff --git a/src/intel/tools/tests/gen5/mul.expected b/src/intel/tools/tests/gen5/mul.expected new file mode 100644 index 00000000000..d2a3e29b69b --- /dev/null +++ b/src/intel/tools/tests/gen5/mul.expected @@ -0,0 +1,35 @@ +41 00 60 00 be 77 60 20 60 00 8d 00 40 00 8d 00 +41 20 80 00 be 77 60 30 40 01 8d 00 80 01 8d 00 +41 01 60 00 bd 77 07 21 c4 00 6a 00 0f 01 6f 00 +41 01 60 00 a1 7f 28 21 ef 00 6f 00 00 00 00 45 +41 00 60 00 bd 77 40 20 40 00 8d 00 cc 00 00 00 +41 20 80 00 bd 77 40 21 80 01 8d 00 cc 00 00 00 +41 01 60 00 a5 14 41 20 40 00 60 00 20 00 00 00 +41 00 60 00 bd 7f a0 20 60 00 8d 00 00 00 80 41 +41 00 60 00 be 7f 60 20 00 01 8d 00 00 00 80 3b +41 20 80 00 bd 7f c0 22 00 02 8d 00 00 00 80 41 +41 20 80 00 be 7f 60 30 c0 00 8d 00 00 00 80 3b +41 05 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f +41 01 60 00 bd 7f af 20 64 00 6e 00 00 00 80 37 +41 00 60 80 be 77 40 20 c0 00 8d 00 40 00 8d 00 +41 20 80 80 be 77 40 20 c0 01 8d 00 c0 00 8d 00 +41 00 60 80 bd 77 00 21 e0 00 8d 00 60 00 8d 00 +41 20 80 80 bd 77 40 22 00 02 8d 00 c0 01 8d 00 +41 00 60 00 20 0c 00 24 40 00 8d 00 ab aa aa aa +41 00 60 00 a5 14 60 20 80 00 8d 00 60 00 8d 00 +41 00 60 00 a4 1c 00 24 40 00 8d 00 56 55 55 55 +41 20 80 00 20 0c 00 24 80 01 8d 00 ab aa aa aa +41 20 80 00 a5 14 80 20 00 02 8d 00 00 01 8d 00 +41 20 80 00 a4 1c 00 24 80 01 8d 00 56 55 55 55 +41 09 60 00 a1 7f 48 23 af 03 6f 00 00 00 00 45 +41 01 60 00 bd 5f 47 20 4f 00 6f 00 30 48 40 40 +41 00 60 00 25 15 60 20 40 00 00 00 48 00 00 00 +41 20 80 00 25 15 80 20 40 00 00 00 48 00 00 00 +41 01 60 00 be 7f af 20 64 00 6e 00 00 00 00 3f +41 01 60 80 be 7f af 20 c4 00 6e 00 00 00 80 3b +41 01 60 00 a5 1c a1 20 a0 00 60 00 20 00 00 00 +41 01 60 80 be 77 af 20 64 00 6e 00 64 00 6e 00 +41 05 60 80 be 77 c7 20 00 04 60 00 c4 03 6a 00 +41 01 60 80 be 5f af 20 84 00 6e 00 30 30 30 20 +41 05 60 00 be 77 c7 20 84 01 6a 00 a0 01 60 00 +41 05 60 80 be 5f a7 20 e0 00 60 00 30 30 00 00 diff --git a/src/intel/tools/tests/gen5/not.asm b/src/intel/tools/tests/gen5/not.asm new file mode 100644 index 00000000000..699da8b1273 --- /dev/null +++ b/src/intel/tools/tests/gen5/not.asm @@ -0,0 +1,2 @@ +not(8) g2<1>D -g2<8,8,1>D { align1 }; +not(16) g4<1>D -g6<8,8,1>D { align1 compr }; diff --git a/src/intel/tools/tests/gen5/not.expected b/src/intel/tools/tests/gen5/not.expected new file mode 100644 index 00000000000..dae14234b34 --- /dev/null +++ b/src/intel/tools/tests/gen5/not.expected @@ -0,0 +1,2 @@ +04 00 60 00 a5 00 40 20 40 40 8d 00 00 00 00 00 +04 20 80 00 a5 00 80 20 c0 40 8d 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen5/or.asm b/src/intel/tools/tests/gen5/or.asm new file mode 100644 index 00000000000..aa482dc1c63 --- /dev/null +++ b/src/intel/tools/tests/gen5/or.asm @@ -0,0 +1,7 @@ +or(8) g3<1>UD g3<8,8,1>UD g5<8,8,1>UD { align1 }; +or(8) g9<1>.xUD g10<4>.xUD g9<4>.xUD { align16 }; +(+f0.0) or(8) g8<1>UD g8<8,8,1>UD 0x3f800000UD { align1 }; +or(16) g12<1>UD g14<8,8,1>UD g20<8,8,1>UD { align1 compr }; +(+f0.0) or(16) g12<1>UD g12<8,8,1>UD 0x3f800000UD { align1 compr }; +(+f0.0) or(8) g17<1>.xUD g17<4>.xUD 0x3f800000UD { align16 }; +or(8) m2<1>.wUD g8<4>.xUD g11<4>.xUD { align16 }; diff --git a/src/intel/tools/tests/gen5/or.expected b/src/intel/tools/tests/gen5/or.expected new file mode 100644 index 00000000000..4d56bda1b0f --- /dev/null +++ b/src/intel/tools/tests/gen5/or.expected @@ -0,0 +1,7 @@ +06 00 60 00 21 04 60 20 60 00 8d 00 a0 00 8d 00 +06 01 60 00 21 04 21 21 40 01 60 00 20 01 60 00 +06 00 61 00 21 0c 00 21 00 01 8d 00 00 00 80 3f +06 20 80 00 21 04 80 21 c0 01 8d 00 80 02 8d 00 +06 20 81 00 21 0c 80 21 80 01 8d 00 00 00 80 3f +06 01 61 00 21 0c 21 22 20 02 60 00 00 00 80 3f +06 01 60 00 22 04 48 20 00 01 60 00 60 01 60 00 diff --git a/src/intel/tools/tests/gen5/pln.asm b/src/intel/tools/tests/gen5/pln.asm new file mode 100644 index 00000000000..e730b2dd1fc --- /dev/null +++ b/src/intel/tools/tests/gen5/pln.asm @@ -0,0 +1,4 @@ +pln(8) g2<1>F g3.4<0,1,0>F g8<8,8,1>F { align1 }; +pln(16) g10<1>F g3.4<0,1,0>F g6<8,8,1>F { align1 compr }; +pln(8) m4<1>F g5.4<0,1,0>F g6<8,8,1>F { align1 }; +pln(16) m4<1>F g5.4<0,1,0>F g6<8,8,1>F { align1 compr4 }; diff --git a/src/intel/tools/tests/gen5/pln.expected b/src/intel/tools/tests/gen5/pln.expected new file mode 100644 index 00000000000..7f4987ff9b6 --- /dev/null +++ b/src/intel/tools/tests/gen5/pln.expected @@ -0,0 +1,4 @@ +5a 00 60 00 bd 77 40 20 70 00 00 00 00 01 8d 00 +5a 20 80 00 bd 77 40 21 70 00 00 00 c0 00 8d 00 +5a 00 60 00 be 77 80 20 b0 00 00 00 c0 00 8d 00 +5a 20 80 00 be 77 80 30 b0 00 00 00 c0 00 8d 00 diff --git a/src/intel/tools/tests/gen5/rndd.asm b/src/intel/tools/tests/gen5/rndd.asm new file mode 100644 index 00000000000..4dff9546499 --- /dev/null +++ b/src/intel/tools/tests/gen5/rndd.asm @@ -0,0 +1,6 @@ +rndd(8) g3<1>F g5<8,8,1>F { align1 }; +rndd(16) g16<1>F g24<8,8,1>F { align1 compr }; +rndd(8) g6<1>.xF g1<0>.xF { align16 }; +rndd(8) g6<1>.xF (abs)g1<0>.xF { align16 NoDDClr }; +rndd(8) g6<1>.yF g7<4>.xF { align16 NoDDClr,NoDDChk }; +rndd.sat(8) m5<1>F g4<4>F { align16 }; diff --git a/src/intel/tools/tests/gen5/rndd.expected b/src/intel/tools/tests/gen5/rndd.expected new file mode 100644 index 00000000000..ad3844874f2 --- /dev/null +++ b/src/intel/tools/tests/gen5/rndd.expected @@ -0,0 +1,6 @@ +45 00 60 00 bd 03 60 20 a0 00 8d 00 00 00 00 00 +45 20 80 00 bd 03 00 22 00 03 8d 00 00 00 00 00 +45 01 60 00 bd 03 c1 20 20 00 00 00 00 00 00 00 +45 05 60 00 bd 03 c1 20 20 20 00 00 00 00 00 00 +45 0d 60 00 bd 03 c2 20 e0 00 60 00 00 00 00 00 +45 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00 diff --git a/src/intel/tools/tests/gen5/sel.asm b/src/intel/tools/tests/gen5/sel.asm new file mode 100644 index 00000000000..a97923f0ba8 --- /dev/null +++ b/src/intel/tools/tests/gen5/sel.asm @@ -0,0 +1,34 @@ +(+f0.0) sel(8) g6<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 }; +(-f0.0) sel(8) g2<1>UD g2<8,8,1>UD 0x00000000UD { align1 }; +(+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr }; +(-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr }; +(+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 }; +(-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 }; +(+f0.0) sel(8) g2<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 }; +(+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr }; +(+f0.0) sel(8) g2<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 }; +(+f0.0) sel(8) m3<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 }; +(+f0.0) sel(16) g4<1>UD g12<8,8,1>UD g14<8,8,1>UD { align1 compr }; +(+f0.0) sel(16) m3<1>UD g10<8,8,1>UD g4<8,8,1>UD { align1 compr4 }; +(+f0.0) sel.sat(8) m5<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 }; +(+f0.0) sel(8) m7<1>UD g2<8,8,1>UD 0x3f000000UD { align1 }; +(+f0.0) sel(16) m11<1>UD g4<8,8,1>UD 0x3f000000UD { align1 compr }; +(+f0.0) sel(8) g15<1>UD g16<4>UD g15<4>UD { align16 }; +(+f0.0) sel.sat(8) m5<1>F g1<0>F g3<4>F { align16 }; +(-f0.0.x) sel(8) g17<1>.xUD g17<4>.xUD 0x00000000UD { align16 }; +(+f0.0) sel(8) m4<1>F g3<8,8,1>F g4<8,8,1>F { align1 }; +(+f0.0) sel(16) m4<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr4 }; +(-f0.0) sel(8) m5<1>UD g2<8,8,1>UD 0x00000000UD { align1 }; +(-f0.0) sel(16) m5<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr4 }; +(+f0.0.any4h) sel(8) g4<1>UD g4<4>UD g5<4>UD { align16 }; +(+f0.0) sel(8) g3<1>.xyUD g3<4>.xyyyUD 0x3e4ccccdUD { align16 }; +(+f0.0.x) sel(8) g4<1>.xD -g4<4>.xD 0D { align16 }; +(+f0.0) sel(8) g2<1>D -g2<8,8,1>D -1D { align1 }; +(+f0.0) sel(16) g4<1>D -g6<8,8,1>D -1D { align1 compr }; +(+f0.0) sel(8) m3<1>F g2<8,8,1>F 0x3f800000F /* 1F */ { align1 }; +(+f0.0) sel(16) m3<1>F g4<8,8,1>F 0x3f800000F /* 1F */ { align1 compr4 }; +(+f0.0.x) sel(8) g3<1>.xUD g3<4>.xUD 0x3e4ccccdUD { align16 }; +(+f0.0) sel(8) g3<1>UD g2.1<0,1,0>UD 0x40800000UD { align1 }; +(+f0.0) sel(16) g4<1>UD g2.1<0,1,0>UD 0x40800000UD { align1 compr }; +(+f0.0.all4h) sel(8) g6<1>UD g6<4>UD g7<4>UD { align16 }; +(+f0.0.x) sel(8) g8<1>.xUD g3<0>.wUD g3<0>.zUD { align16 }; diff --git a/src/intel/tools/tests/gen5/sel.expected b/src/intel/tools/tests/gen5/sel.expected new file mode 100644 index 00000000000..8d4449a4ec4 --- /dev/null +++ b/src/intel/tools/tests/gen5/sel.expected @@ -0,0 +1,34 @@ +02 00 61 00 bd 7f c0 20 60 00 8d 00 00 00 00 00 +02 00 71 00 21 0c 40 20 40 00 8d 00 00 00 00 00 +02 20 81 00 bd 7f 40 21 c0 00 8d 00 00 00 00 00 +02 20 91 00 21 0c 80 20 c0 00 8d 00 00 00 00 00 +02 01 61 00 bd 7f 82 20 a0 00 60 00 00 00 00 00 +02 01 74 00 21 0c 84 20 c0 00 60 00 00 00 00 00 +02 00 61 00 bd 77 40 20 80 20 8d 00 60 20 8d 00 +02 20 81 00 bd 77 80 20 00 22 8d 00 00 21 8d 00 +02 00 61 00 21 04 40 20 a0 00 8d 00 c0 00 8d 00 +02 00 61 00 22 04 60 20 80 00 8d 00 40 00 8d 00 +02 20 81 00 21 04 80 20 80 01 8d 00 c0 01 8d 00 +02 20 81 00 22 04 60 30 40 01 8d 00 80 00 8d 00 +02 01 61 80 be 7f af 20 64 00 6e 00 00 00 00 3f +02 00 61 00 22 0c e0 20 40 00 8d 00 00 00 00 3f +02 20 81 00 22 0c 60 21 80 00 8d 00 00 00 00 3f +02 01 61 00 21 04 ef 21 04 02 6e 00 e4 01 6e 00 +02 01 61 80 be 77 af 20 24 00 0e 00 64 00 6e 00 +02 01 72 00 21 0c 21 22 20 02 60 00 00 00 00 00 +02 00 61 00 be 77 80 20 60 00 8d 00 80 00 8d 00 +02 20 81 00 be 77 80 30 80 00 8d 00 c0 00 8d 00 +02 00 71 00 22 0c a0 20 40 00 8d 00 00 00 00 00 +02 20 91 00 22 0c a0 30 c0 00 8d 00 00 00 00 00 +02 01 66 00 21 04 8f 20 84 00 6e 00 a4 00 6e 00 +02 01 61 00 21 0c 63 20 64 00 65 00 cd cc 4c 3e +02 01 62 00 a5 1c 81 20 80 40 60 00 00 00 00 00 +02 00 61 00 a5 1c 40 20 40 40 8d 00 ff ff ff ff +02 20 81 00 a5 1c 80 20 c0 40 8d 00 ff ff ff ff +02 00 61 00 be 7f 60 20 40 00 8d 00 00 00 80 3f +02 20 81 00 be 7f 60 30 80 00 8d 00 00 00 80 3f +02 01 62 00 21 0c 61 20 60 00 60 00 cd cc 4c 3e +02 00 61 00 21 0c 60 20 44 00 00 00 00 00 80 40 +02 20 81 00 21 0c 80 20 44 00 00 00 00 00 80 40 +02 01 67 00 21 04 cf 20 c4 00 6e 00 e4 00 6e 00 +02 01 62 00 21 04 01 21 6f 00 0f 00 6a 00 0a 00 diff --git a/src/intel/tools/tests/gen5/send.asm b/src/intel/tools/tests/gen5/send.asm new file mode 100644 index 00000000000..4500f06ae26 --- /dev/null +++ b/src/intel/tools/tests/gen5/send.asm @@ -0,0 +1,300 @@ +send(8) 2 g2<1>F g2<8,8,1>F 0x02100001 + math MsgDesc: inv mlen 1 rlen 1 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c00 + write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT }; +send(16) 2 g12<1>F g10<8,8,1>F 0x02100001 + math MsgDesc: inv mlen 1 rlen 1 { align1 compr }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084800 + write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT }; +send(8) 1 null<1>F g0<4>F 0x8a08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT }; +send(8) 2 g2<1>UW null<8,8,1>F 0x06410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x0c820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x04410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x08820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 }; +send(8) 14 g3<1>UD g0<4>F 0x04181000 + read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 }; +send(8) 1 null<1>F g0<4>F 0x8808c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT }; +send(8) 2 g13<1>UW null<8,8,1>F 0x0241a001 + sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 }; +send(16) 2 g26<1>UW null<8,8,1>F 0x0482a001 + sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x08417001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x10827001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 }; +send(8) 1 null<1>F g0<4>F 0x8c08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 6 rlen 0 { align16 EOT }; +send(8) 2 g2<1>F g2<8,8,1>F 0x0410000a + math MsgDesc: pow mlen 2 rlen 1 { align1 }; +send(8) 2 g12<1>UW null<8,8,1>F 0x02410001 + sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 }; +send(16) 2 g16<1>UW null<8,8,1>F 0x04820001 + sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 }; +send(8) 2 g2<1>F g2<8,8,1>F 0x02100007 + math MsgDesc: cos mlen 1 rlen 1 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0a411001 + sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x14821001 + sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x90084c00 + write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 8 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x9c084800 + write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT }; +send(8) 1 null<1>F g0<4>F 0x1a084400 + urb MsgDesc: 0 urb_write interleave used mlen 13 rlen 0 { align16 }; +send(8) 1 null<1>F g0<4>F 0x9008c460 + urb MsgDesc: 6 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT }; +send(8) 1 g5<1>.yF g6<4>.xF 0x02100006 + math MsgDesc: sin mlen 1 rlen 1 { align16 }; +send(8) 1 g7<1>.xD g1<0>.zD 0x0410001c + math MsgDesc: intdiv signed mlen 2 rlen 1 { align16 }; +send(8) 2 g3<1>F g2.3<0,1,0>F 0x02100081 + math MsgDesc: inv scalar mlen 1 rlen 1 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8e084c00 + write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 7 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x98084800 + write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT }; +send(8) 1 g30<1>.xF (abs)g30<4>.xF 0x02100005 + math MsgDesc: rsq mlen 1 rlen 1 { align16 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0a412001 + sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x14822001 + sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 }; +send(8) 2 g2<1>F g2<8,8,1>F 0x02100004 + math MsgDesc: sqrt mlen 1 rlen 1 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x92084c00 + write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 9 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x9e084800 + write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT }; +send(8) 2 g2<1>UW null<8,8,1>F 0x04410304 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x08820304 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0a413001 + sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x14823001 + sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 }; +send(8) 1 null<1>F g0<4>F 0x9008c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT }; +send(8) 1 null<1>F g0<4>F 0x9608c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 EOT }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084400 + write MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084401 + write MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084402 + write MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c03 + write MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084000 + write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084001 + write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084002 + write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084803 + write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT }; +send(8) 2 g2<1>F g2<8,8,1>F 0x02100002 + math MsgDesc: log mlen 1 rlen 1 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0c416001 + sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 }; +send(8) 2 g3<1>F g2<0,1,0>F 0x041000ca + math MsgDesc: pow sat scalar mlen 2 rlen 1 { align1 }; +send(8) 2 g7<1>UW null<8,8,1>F 0x0a413102 + sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 }; +send(16) 2 g14<1>UW null<8,8,1>F 0x14823102 + sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c01 + write MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084801 + write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c02 + write MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084802 + write MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 EOT }; +send(8) 2 g9<1>UW null<8,8,1>F 0x04410102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 }; +send(16) 2 g20<1>UW null<8,8,1>F 0x08820102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 }; +send(8) 1 null<1>F g0<4>F 0x8e08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 EOT }; +send(8) 13 g0<1>F g0<4>F 0x061890ff + write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 }; +send(8) 14 g6<1>F g0<4>F 0x041850ff + read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 }; +send(8) 2 g17<1>UW null<8,8,1>F 0x0241a102 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 }; +send(8) 2 g30<1>UW null<8,8,1>F 0x0241a203 + sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 }; +send(8) 2 g30<1>UW null<8,8,1>F 0x04410203 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 }; +send(8) 2 g13<1>UW null<8,8,1>F 0x0241a304 + sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 }; +send(8) 2 g34<1>UW null<8,8,1>F 0x0241a405 + sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 }; +send(8) 2 g34<1>UW null<8,8,1>F 0x04410405 + sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 }; +send(8) 2 g38<1>UW null<8,8,1>F 0x0241a506 + sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 }; +send(8) 2 g9<1>UW null<8,8,1>F 0x04410506 + sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 }; +send(8) 2 g38<1>UW null<8,8,1>F 0x0241a607 + sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 }; +send(8) 2 g38<1>UW null<8,8,1>F 0x04410607 + sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 }; +send(8) 2 g42<1>UW null<8,8,1>F 0x0241a708 + sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 }; +send(8) 2 g42<1>UW null<8,8,1>F 0x04410708 + sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 }; +send(16) 2 g14<1>UW null<8,8,1>F 0x0482a102 + sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 }; +send(16) 2 g26<1>UW null<8,8,1>F 0x0482a203 + sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 }; +send(16) 2 g26<1>UW null<8,8,1>F 0x08820203 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 }; +send(16) 2 g34<1>UW null<8,8,1>F 0x0482a304 + sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 }; +send(16) 2 g42<1>UW null<8,8,1>F 0x0482a405 + sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 }; +send(16) 2 g42<1>UW null<8,8,1>F 0x08820405 + sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 }; +send(16) 2 g50<1>UW null<8,8,1>F 0x0482a506 + sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 }; +send(16) 2 g50<1>UW null<8,8,1>F 0x08820506 + sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 }; +send(16) 2 g58<1>UW null<8,8,1>F 0x0482a607 + sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 }; +send(16) 2 g58<1>UW null<8,8,1>F 0x08820607 + sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 }; +send(16) 2 g66<1>UW null<8,8,1>F 0x0482a708 + sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 }; +send(16) 2 g66<1>UW null<8,8,1>F 0x08820708 + sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 }; +send(8) 1 null<1>F g0<4>F 0x9a08c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 EOT }; +send(8) 1 null<1>F g0<4>F 0x9808c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 12 rlen 0 { align16 EOT }; +send(8) 2 g8<1>UW null<8,8,1>F 0x0c416102 + sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x96084800 + write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 11 rlen 0 { align1 EOT }; +send(8) 2 g3<1>F null<4>UD 0x04102505 + sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 }; +send(8) 2 g3<1>F g2<0,1,0>F 0x021000c4 + math MsgDesc: sqrt sat scalar mlen 1 rlen 1 { align1 }; +send(8) 2 g3<1>F g2<0,1,0>F 0x021000c3 + math MsgDesc: exp sat scalar mlen 1 rlen 1 { align1 }; +send(8) 2 g3<1>F null<4>UD 0x04102000 + sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 }; +send(8) 1 g3<1>F g1<0>F 0x02100044 + math MsgDesc: sqrt sat mlen 1 rlen 1 { align16 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084403 + write MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c04 + write MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084003 + write MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084804 + write MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 EOT }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084404 + write MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c05 + write MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084004 + write MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084805 + write MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 EOT }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084405 + write MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c06 + write MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084005 + write MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084806 + write MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 EOT }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x0c084406 + write MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 }; +send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c07 + write MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 EOT }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x14084006 + write MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 }; +send(16) 1 null<1>UW g0<8,8,1>UW 0x94084807 + write MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 EOT }; +send(8) 2 g2<1>UW null<8,8,1>F 0x10414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 }; +send(8) 2 g6<1>UW null<8,8,1>F 0x06410102 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 }; +send(16) 2 g12<1>UW null<8,8,1>F 0x0c820102 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 }; +send(8) 13 g11<1>UW g0<8,8,1>F 0x04497001 + sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(16) 13 g4<1>UW g0<8,8,1>F 0x068a7001 + sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 }; +send(8) 1 null<1>F g0<4>F 0x9408c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 10 rlen 0 { align16 EOT }; +send(8) 1 null<1>F g0<4>F 0x8408c460 + urb MsgDesc: 6 urb_write interleave used complete mlen 2 rlen 0 { align16 EOT }; +send(8) 2 g4<1>F g2<0,1,0>F 0x02100084 + math MsgDesc: sqrt scalar mlen 1 rlen 1 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0c414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 }; +send(8) 1 g3<1>F g1<0>F 0x02100043 + math MsgDesc: exp sat mlen 1 rlen 1 { align16 }; +send(8) 1 null<1>F g0<4>F 0x9208c400 + urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 EOT }; +send(8) 2 g2<1>UW null<8,8,1>F 0x0c415001 + sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 }; +send(8) 2 g5<1>F g2<0,1,0>F 0x02100087 + math MsgDesc: cos scalar mlen 1 rlen 1 { align1 }; +send(8) 1 g4<1>.xF g3<4>.xF 0x02100003 + math MsgDesc: exp mlen 1 rlen 1 { align16 }; +send(8) 2 g7<1>UW null<8,8,1>F 0x0c415102 + sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x14414001 + sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 }; +send(8) 2 g3<1>F g2<0,1,0>F 0x02100083 + math MsgDesc: exp scalar mlen 1 rlen 1 { align1 }; +send(8) 2 g6<1>UW null<8,8,1>F 0x04410003 + sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(8) 2 g10<1>UW null<8,8,1>F 0x04410004 + sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(16) 2 g14<1>UW null<8,8,1>F 0x08820003 + sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 }; +send(16) 2 g22<1>UW null<8,8,1>F 0x08820004 + sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x04419001 + sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x08829001 + sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x04410f10 + sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x08820f10 + sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 }; +send(8) 2 g3<1>F null<4>UD 0x04102303 + sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 }; +send(8) 1 g3<1>F g1<0>F 0x0410004a + math MsgDesc: pow sat mlen 2 rlen 1 { align16 }; +send(8) 2 g4<1>UW null<8,8,1>F 0x0241a004 + sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 }; +send(16) 2 g10<1>UW null<8,8,1>F 0x0482a004 + sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 0 mlen 2 rlen 8 { align1 }; +send(8) 2 g4<1>UW null<8,8,1>F 0x0241a003 + sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 }; +send(16) 2 g10<1>UW null<8,8,1>F 0x0482a003 + sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 0 mlen 2 rlen 8 { align1 }; +send(8) 2 g4<1>UW null<8,8,1>F 0x0241a002 + sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 }; +send(8) 2 g2<1>UW null<8,8,1>F 0x04410002 + sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 }; +send(16) 2 g10<1>UW null<8,8,1>F 0x0482a002 + sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 }; +send(16) 2 g4<1>UW null<8,8,1>F 0x08820002 + sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 }; +send(8) 2 g5<1>F g2<0,1,0>F 0x02100086 + math MsgDesc: sin scalar mlen 1 rlen 1 { align1 }; diff --git a/src/intel/tools/tests/gen5/send.expected b/src/intel/tools/tests/gen5/send.expected new file mode 100644 index 00000000000..30aa14788ef --- /dev/null +++ b/src/intel/tools/tests/gen5/send.expected @@ -0,0 +1,150 @@ +31 00 60 02 bd 0f 40 20 40 00 8d 10 01 00 10 02 +31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 8c +31 20 80 02 bd 0f 80 21 40 01 8d 10 01 00 10 02 +31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 94 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8a +31 00 60 02 89 0f 40 20 00 00 8d 20 01 00 41 06 +31 00 80 02 89 0f 80 20 00 00 8d 20 01 00 82 0c +31 00 60 02 89 0f 40 20 00 00 8d 20 01 00 41 04 +31 00 80 02 89 0f 80 20 00 00 8d 20 01 00 82 08 +31 01 60 0e a1 0f 6f 20 04 00 6e 40 00 10 18 04 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 88 +31 00 60 02 89 0f a0 21 00 00 8d 20 01 a0 41 02 +31 00 80 02 89 0f 40 23 00 00 8d 20 01 a0 82 04 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 70 41 08 +31 00 80 02 89 0f 80 20 00 00 8d 20 01 70 82 10 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8c +31 00 60 02 bd 0f 40 20 40 00 8d 10 0a 00 10 04 +31 00 60 02 89 0f 80 21 00 00 8d 20 01 00 41 02 +31 00 80 02 89 0f 00 22 00 00 8d 20 01 00 82 04 +31 00 60 02 bd 0f 40 20 40 00 8d 10 07 00 10 02 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 10 41 0a +31 00 80 02 89 0f 80 20 00 00 8d 20 01 10 82 14 +31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 90 +31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 9c +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 44 08 1a +31 01 60 01 bc 0f 0f 20 04 00 6e 60 60 c4 08 90 +31 01 60 01 bd 0f a2 20 c0 00 60 10 06 00 10 02 +31 01 60 01 a5 0c e1 20 2a 00 0a 10 1c 00 10 04 +31 00 60 02 bd 0f 60 20 4c 00 00 10 81 00 10 02 +31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 8e +31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 98 +31 01 60 01 bd 0f c1 23 c0 23 60 10 05 00 10 02 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 20 41 0a +31 00 80 02 89 0f 80 20 00 00 8d 20 01 20 82 14 +31 00 60 02 bd 0f 40 20 40 00 8d 10 04 00 10 02 +31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 92 +31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 9e +31 00 60 02 89 0f 40 20 00 00 8d 20 04 03 41 04 +31 00 80 02 89 0f 80 20 00 00 8d 20 04 03 82 08 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 30 41 0a +31 00 80 02 89 0f 80 20 00 00 8d 20 01 30 82 14 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 90 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 96 +31 00 60 01 28 0d 00 20 00 00 8d 50 00 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 01 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 02 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 03 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 00 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 01 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 02 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 03 48 08 94 +31 00 60 02 bd 0f 40 20 40 00 8d 10 02 00 10 02 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 60 41 0c +31 00 60 02 bd 0f 60 20 40 00 00 10 ca 00 10 04 +31 00 60 02 89 0f e0 20 00 00 8d 20 02 31 41 0a +31 00 80 02 89 0f c0 21 00 00 8d 20 02 31 82 14 +31 00 60 01 28 0d 00 20 00 00 8d 50 01 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 01 48 08 94 +31 00 60 01 28 0d 00 20 00 00 8d 50 02 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 02 48 08 94 +31 00 60 02 89 0f 20 21 00 00 8d 20 02 01 41 04 +31 00 80 02 89 0f 80 22 00 00 8d 20 02 01 82 08 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8e +31 01 60 0d bd 0f 0f 20 04 00 6e 50 ff 90 18 06 +31 01 60 0e bd 0f cf 20 04 00 6e 40 ff 50 18 04 +31 00 60 02 89 0f 20 22 00 00 8d 20 02 a1 41 02 +31 00 60 02 89 0f c0 23 00 00 8d 20 03 a2 41 02 +31 00 60 02 89 0f c0 23 00 00 8d 20 03 02 41 04 +31 00 60 02 89 0f a0 21 00 00 8d 20 04 a3 41 02 +31 00 60 02 89 0f 40 24 00 00 8d 20 05 a4 41 02 +31 00 60 02 89 0f 40 24 00 00 8d 20 05 04 41 04 +31 00 60 02 89 0f c0 24 00 00 8d 20 06 a5 41 02 +31 00 60 02 89 0f 20 21 00 00 8d 20 06 05 41 04 +31 00 60 02 89 0f c0 24 00 00 8d 20 07 a6 41 02 +31 00 60 02 89 0f c0 24 00 00 8d 20 07 06 41 04 +31 00 60 02 89 0f 40 25 00 00 8d 20 08 a7 41 02 +31 00 60 02 89 0f 40 25 00 00 8d 20 08 07 41 04 +31 00 80 02 89 0f c0 21 00 00 8d 20 02 a1 82 04 +31 00 80 02 89 0f 40 23 00 00 8d 20 03 a2 82 04 +31 00 80 02 89 0f 40 23 00 00 8d 20 03 02 82 08 +31 00 80 02 89 0f 40 24 00 00 8d 20 04 a3 82 04 +31 00 80 02 89 0f 40 25 00 00 8d 20 05 a4 82 04 +31 00 80 02 89 0f 40 25 00 00 8d 20 05 04 82 08 +31 00 80 02 89 0f 40 26 00 00 8d 20 06 a5 82 04 +31 00 80 02 89 0f 40 26 00 00 8d 20 06 05 82 08 +31 00 80 02 89 0f 40 27 00 00 8d 20 07 a6 82 04 +31 00 80 02 89 0f 40 27 00 00 8d 20 07 06 82 08 +31 00 80 02 89 0f 40 28 00 00 8d 20 08 a7 82 04 +31 00 80 02 89 0f 40 28 00 00 8d 20 08 07 82 08 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 9a +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 98 +31 00 60 02 89 0f 00 21 00 00 8d 20 02 61 41 0c +31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 96 +31 01 60 02 1d 0c 6f 20 04 00 6e 20 05 25 10 04 +31 00 60 02 bd 0f 60 20 40 00 00 10 c4 00 10 02 +31 00 60 02 bd 0f 60 20 40 00 00 10 c3 00 10 02 +31 01 60 02 1d 0c 6f 20 04 00 6e 20 00 20 10 04 +31 01 60 01 bd 0f 6f 20 24 00 0e 10 44 00 10 02 +31 00 60 01 28 0d 00 20 00 00 8d 50 03 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 04 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 03 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 04 48 08 94 +31 00 60 01 28 0d 00 20 00 00 8d 50 04 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 05 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 04 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 05 48 08 94 +31 00 60 01 28 0d 00 20 00 00 8d 50 05 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 06 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 05 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 06 48 08 94 +31 00 60 01 28 0d 00 20 00 00 8d 50 06 44 08 0c +31 00 60 01 28 0d 00 20 00 00 8d 50 07 4c 08 8c +31 00 80 01 28 0d 00 20 00 00 8d 50 06 40 08 14 +31 00 80 01 28 0d 00 20 00 00 8d 50 07 48 08 94 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 10 +31 00 60 02 89 0f c0 20 00 00 8d 20 02 01 41 06 +31 00 80 02 89 0f 80 21 00 00 8d 20 02 01 82 0c +31 00 60 0d a9 0f 60 21 00 00 8d 20 01 70 49 04 +31 00 80 0d a9 0f 80 20 00 00 8d 20 01 70 8a 06 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 94 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 60 c4 08 84 +31 00 60 02 bd 0f 80 20 40 00 00 10 84 00 10 02 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 0c +31 01 60 01 bd 0f 6f 20 24 00 0e 10 43 00 10 02 +31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 92 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 50 41 0c +31 00 60 02 bd 0f a0 20 40 00 00 10 87 00 10 02 +31 01 60 01 bd 0f 81 20 60 00 60 10 03 00 10 02 +31 00 60 02 89 0f e0 20 00 00 8d 20 02 51 41 0c +31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 14 +31 00 60 02 bd 0f 60 20 40 00 00 10 83 00 10 02 +31 00 60 02 89 0f c0 20 00 00 8d 20 03 00 41 04 +31 00 60 02 89 0f 40 21 00 00 8d 20 04 00 41 04 +31 00 80 02 89 0f c0 21 00 00 8d 20 03 00 82 08 +31 00 80 02 89 0f c0 22 00 00 8d 20 04 00 82 08 +31 00 60 02 89 0f 40 20 00 00 8d 20 01 90 41 04 +31 00 80 02 89 0f 80 20 00 00 8d 20 01 90 82 08 +31 00 60 02 89 0f 40 20 00 00 8d 20 10 0f 41 04 +31 00 80 02 89 0f 80 20 00 00 8d 20 10 0f 82 08 +31 01 60 02 1d 0c 6f 20 04 00 6e 20 03 23 10 04 +31 01 60 01 bd 0f 6f 20 24 00 0e 10 4a 00 10 04 +31 00 60 02 89 0f 80 20 00 00 8d 20 04 a0 41 02 +31 00 80 02 89 0f 40 21 00 00 8d 20 04 a0 82 04 +31 00 60 02 89 0f 80 20 00 00 8d 20 03 a0 41 02 +31 00 80 02 89 0f 40 21 00 00 8d 20 03 a0 82 04 +31 00 60 02 89 0f 80 20 00 00 8d 20 02 a0 41 02 +31 00 60 02 89 0f 40 20 00 00 8d 20 02 00 41 04 +31 00 80 02 89 0f 40 21 00 00 8d 20 02 a0 82 04 +31 00 80 02 89 0f 80 20 00 00 8d 20 02 00 82 08 +31 00 60 02 bd 0f a0 20 40 00 00 10 86 00 10 02 diff --git a/src/intel/tools/tests/gen5/shl.asm b/src/intel/tools/tests/gen5/shl.asm new file mode 100644 index 00000000000..a02bfff871f --- /dev/null +++ b/src/intel/tools/tests/gen5/shl.asm @@ -0,0 +1,7 @@ +shl(8) g4<1>.xD g1<0>.yD 0x00000004UD { align16 }; +shl(8) g4<1>D g3<8,8,1>D 0x00000001UD { align1 }; +shl(16) g6<1>D g4<8,8,1>D 0x00000001UD { align1 compr }; +shl(8) g11<1>.xUD g11<4>.xUD 4D { align16 }; +shl(8) m14<1>D g4<0,1,0>D 0x00000004UD { align1 }; +shl(16) m14<1>D g4<0,1,0>D 0x00000004UD { align1 compr }; +shl(8) g5<1>D g3<4>D g4<4>UD { align16 }; diff --git a/src/intel/tools/tests/gen5/shl.expected b/src/intel/tools/tests/gen5/shl.expected new file mode 100644 index 00000000000..f9c9cef2e3f --- /dev/null +++ b/src/intel/tools/tests/gen5/shl.expected @@ -0,0 +1,7 @@ +09 01 60 00 a5 0c 81 20 25 00 05 00 04 00 00 00 +09 00 60 00 a5 0c 80 20 60 00 8d 00 01 00 00 00 +09 20 80 00 a5 0c c0 20 80 00 8d 00 01 00 00 00 +09 01 60 00 21 1c 61 21 60 01 60 00 04 00 00 00 +09 00 60 00 a6 0c c0 21 80 00 00 00 04 00 00 00 +09 20 80 00 a6 0c c0 21 80 00 00 00 04 00 00 00 +09 01 60 00 a5 04 af 20 64 00 6e 00 84 00 6e 00 diff --git a/src/intel/tools/tests/gen5/shr.asm b/src/intel/tools/tests/gen5/shr.asm new file mode 100644 index 00000000000..51db89dd17d --- /dev/null +++ b/src/intel/tools/tests/gen5/shr.asm @@ -0,0 +1,3 @@ +shr(8) g3<1>UD g3<8,8,1>UD 0x00000001UD { align1 }; +shr(16) g8<1>UD g4<8,8,1>UD 0x00000001UD { align1 compr }; +shr(1) g8.4<1>UD g8.4<0,1,0>UD 0x00000004UD { align1 nomask }; diff --git a/src/intel/tools/tests/gen5/shr.expected b/src/intel/tools/tests/gen5/shr.expected new file mode 100644 index 00000000000..fe61e45da45 --- /dev/null +++ b/src/intel/tools/tests/gen5/shr.expected @@ -0,0 +1,3 @@ +08 00 60 00 21 0c 60 20 60 00 8d 00 01 00 00 00 +08 20 80 00 21 0c 00 21 80 00 8d 00 01 00 00 00 +08 02 00 00 21 0c 10 21 10 01 00 00 04 00 00 00 diff --git a/src/intel/tools/tests/gen5/while.asm b/src/intel/tools/tests/gen5/while.asm new file mode 100644 index 00000000000..a5985d985d8 --- /dev/null +++ b/src/intel/tools/tests/gen5/while.asm @@ -0,0 +1,3 @@ +while(8) Jump: -282 { align1 }; +while(16) Jump: -282 { align1 }; +while(8) Jump: -32 { align16 }; diff --git a/src/intel/tools/tests/gen5/while.expected b/src/intel/tools/tests/gen5/while.expected new file mode 100644 index 00000000000..290e75f50e5 --- /dev/null +++ b/src/intel/tools/tests/gen5/while.expected @@ -0,0 +1,3 @@ +27 00 60 00 00 1c 00 34 00 14 60 00 e6 fe 00 00 +27 00 80 00 00 1c 00 34 00 14 60 00 e6 fe 00 00 +27 01 60 00 00 1c 0f 34 04 14 6e 00 e0 ff 00 00 |