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-rw-r--r--src/intel/isl/isl_surface_state.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index b7354781cf0..c7b220b73fb 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -453,6 +453,38 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
+ if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
+ /* From the Sky Lake PRM Vol. 2d,
+ * RENDER_SURFACE_STATE::Shader Channel Select Red
+ *
+ * "For Render Target, Red, Green and Blue Shader Channel Selects
+ * MUST be such that only valid components can be swapped i.e. only
+ * change the order of components in the pixel. Any other values for
+ * these Shader Channel Select fields are not valid for Render
+ * Targets. This also means that there MUST not be multiple shader
+ * channels mapped to the same RT channel."
+ */
+ assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
+ info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
+ info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
+ assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
+ info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
+ info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
+ assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
+ info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
+ info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
+ assert(info->view->swizzle.r != info->view->swizzle.g);
+ assert(info->view->swizzle.r != info->view->swizzle.b);
+ assert(info->view->swizzle.g != info->view->swizzle.b);
+
+ /* From the Sky Lake PRM Vol. 2d,
+ * RENDER_SURFACE_STATE::Shader Channel Select Alpha
+ *
+ * "For Render Target, this field MUST be programmed to
+ * value = SCS_ALPHA."
+ */
+ assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
+ }
s.ShaderChannelSelectRed = info->view->swizzle.r;
s.ShaderChannelSelectGreen = info->view->swizzle.g;
s.ShaderChannelSelectBlue = info->view->swizzle.b;