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-rw-r--r--src/intel/compiler/brw_nir.c24
-rw-r--r--src/intel/compiler/brw_nir_analyze_ubo_ranges.c2
-rw-r--r--src/intel/compiler/brw_nir_lower_cs_intrinsics.c2
-rw-r--r--src/intel/compiler/brw_nir_tcs_workarounds.c2
-rw-r--r--src/intel/compiler/brw_shader.cpp2
-rw-r--r--src/intel/compiler/brw_vec4_generator.cpp10
6 files changed, 21 insertions, 21 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index a04f4af7b08..327216eaaa7 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -165,7 +165,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
- gl_shader_stage stage = b->shader->stage;
+ gl_shader_stage stage = b->shader->info.stage;
if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
(stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
@@ -526,11 +526,11 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
bool is_scalar)
{
nir_variable_mode indirect_mask = 0;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectInput)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectInput)
indirect_mask |= nir_var_shader_in;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectOutput)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectOutput)
indirect_mask |= nir_var_shader_out;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectTemp)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectTemp)
indirect_mask |= nir_var_local;
bool progress;
@@ -601,9 +601,9 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
const struct gen_device_info *devinfo = compiler->devinfo;
UNUSED bool progress; /* Written by OPT */
- const bool is_scalar = compiler->scalar_stage[nir->stage];
+ const bool is_scalar = compiler->scalar_stage[nir->info.stage];
- if (nir->stage == MESA_SHADER_GEOMETRY)
+ if (nir->info.stage == MESA_SHADER_GEOMETRY)
OPT(nir_lower_gs_intrinsics);
/* See also brw_nir_trig_workarounds.py */
@@ -638,11 +638,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
OPT(nir_lower_clip_cull_distance_arrays);
nir_variable_mode indirect_mask = 0;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectInput)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectInput)
indirect_mask |= nir_var_shader_in;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectOutput)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectOutput)
indirect_mask |= nir_var_shader_out;
- if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectTemp)
+ if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectTemp)
indirect_mask |= nir_var_local;
nir_lower_indirect_derefs(nir, indirect_mask);
@@ -672,7 +672,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
{
const struct gen_device_info *devinfo = compiler->devinfo;
bool debug_enabled =
- (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
+ (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->info.stage));
UNUSED bool progress; /* Written by OPT */
@@ -706,7 +706,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
}
fprintf(stderr, "NIR (SSA form) for %s shader:\n",
- _mesa_shader_stage_to_string(nir->stage));
+ _mesa_shader_stage_to_string(nir->info.stage));
nir_print_shader(nir, stderr);
}
@@ -729,7 +729,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (unlikely(debug_enabled)) {
fprintf(stderr, "NIR (final form) for %s shader:\n",
- _mesa_shader_stage_to_string(nir->stage));
+ _mesa_shader_stage_to_string(nir->info.stage));
nir_print_shader(nir, stderr);
}
diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
index 097aa8e62d6..32fbf8fccd9 100644
--- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
+++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
@@ -172,7 +172,7 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
const struct gen_device_info *devinfo = compiler->devinfo;
if ((devinfo->gen <= 7 && !devinfo->is_haswell) ||
- !compiler->scalar_stage[nir->stage]) {
+ !compiler->scalar_stage[nir->info.stage]) {
memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
return;
}
diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
index 9b4a0fdf2eb..f9322654e7c 100644
--- a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
+++ b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
@@ -159,7 +159,7 @@ bool
brw_nir_lower_cs_intrinsics(nir_shader *nir,
struct brw_cs_prog_data *prog_data)
{
- assert(nir->stage == MESA_SHADER_COMPUTE);
+ assert(nir->info.stage == MESA_SHADER_COMPUTE);
bool progress = false;
struct lower_intrinsics_state state;
diff --git a/src/intel/compiler/brw_nir_tcs_workarounds.c b/src/intel/compiler/brw_nir_tcs_workarounds.c
index a85f493c704..af7b7180431 100644
--- a/src/intel/compiler/brw_nir_tcs_workarounds.c
+++ b/src/intel/compiler/brw_nir_tcs_workarounds.c
@@ -123,7 +123,7 @@ emit_quads_workaround(nir_builder *b, nir_block *block)
void
brw_nir_apply_tcs_quads_workaround(nir_shader *nir)
{
- assert(nir->stage == MESA_SHADER_TESS_CTRL);
+ assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 4eb602b000a..7d62479fc63 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -670,7 +670,7 @@ backend_shader::backend_shader(const struct brw_compiler *compiler,
stage_prog_data(stage_prog_data),
mem_ctx(mem_ctx),
cfg(NULL),
- stage(shader->stage)
+ stage(shader->info.stage)
{
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
stage_name = _mesa_shader_stage_to_string(stage);
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 6a3a0a080c3..bde4110e549 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1497,9 +1497,9 @@ generate_code(struct brw_codegen *p,
const struct cfg_t *cfg)
{
const struct gen_device_info *devinfo = p->devinfo;
- const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
+ const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
bool debug_flag = INTEL_DEBUG &
- intel_debug_flag_for_shader_stage(nir->stage);
+ intel_debug_flag_for_shader_stage(nir->info.stage);
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
int spill_count = 0, fill_count = 0;
@@ -1770,7 +1770,7 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
- generate_tex(p, prog_data, nir->stage,
+ generate_tex(p, prog_data, nir->info.stage,
inst, dst, src[0], src[1], src[2]);
break;
@@ -1910,7 +1910,7 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
const struct brw_reg mask =
- brw_stage_has_packed_dispatch(devinfo, nir->stage,
+ brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
&prog_data->base) ? brw_imm_ud(~0u) :
brw_dmask_reg();
brw_find_live_channel(p, dst, mask);
@@ -2195,7 +2195,7 @@ generate_code(struct brw_codegen *p,
if (unlikely(debug_flag)) {
fprintf(stderr, "Native code for %s %s shader %s:\n",
nir->info.label ? nir->info.label : "unnamed",
- _mesa_shader_stage_to_string(nir->stage), nir->info.name);
+ _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
"spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 01:06:21 +0000