diff options
Diffstat (limited to 'src/intel/compiler/brw_vec4_tcs.cpp')
| -rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index d4a647d029f..c362a0a5f14 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -95,9 +95,9 @@ vec4_tcs_visitor::emit_prolog() * HS instance dispatched will only have its bottom half doing real * work, and so we need to disable the upper half: */ - if (nir->info->tess.tcs_vertices_out % 2) { + if (nir->info.tess.tcs_vertices_out % 2) { emit(CMP(dst_null_d(), invocation_id, - brw_imm_ud(nir->info->tess.tcs_vertices_out), + brw_imm_ud(nir->info.tess.tcs_vertices_out), BRW_CONDITIONAL_L)); /* Matching ENDIF is in emit_thread_end() */ @@ -112,7 +112,7 @@ vec4_tcs_visitor::emit_thread_end() vec4_instruction *inst; current_annotation = "thread end"; - if (nir->info->tess.tcs_vertices_out % 2) { + if (nir->info.tess.tcs_vertices_out % 2) { emit(BRW_OPCODE_ENDIF); } @@ -402,15 +402,15 @@ brw_compile_tcs(const struct brw_compiler *compiler, const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL]; nir_shader *nir = nir_shader_clone(mem_ctx, src_shader); - nir->info->outputs_written = key->outputs_written; - nir->info->patch_outputs_written = key->patch_outputs_written; + nir->info.outputs_written = key->outputs_written; + nir->info.patch_outputs_written = key->patch_outputs_written; struct brw_vue_map input_vue_map; - brw_compute_vue_map(devinfo, &input_vue_map, nir->info->inputs_read, - nir->info->separate_shader); + brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read, + nir->info.separate_shader); brw_compute_tess_vue_map(&vue_prog_data->vue_map, - nir->info->outputs_written, - nir->info->patch_outputs_written); + nir->info.outputs_written, + nir->info.patch_outputs_written); nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar); brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map); @@ -422,9 +422,9 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir = brw_postprocess_nir(nir, compiler, is_scalar); if (is_scalar) - prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 8); + prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 8); else - prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 2); + prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 2); /* Compute URB entry size. The maximum allowed URB entry size is 32k. * That divides up as follows: @@ -443,7 +443,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, unsigned output_size_bytes = 0; /* Note that the patch header is counted in num_per_patch_slots. */ output_size_bytes += num_per_patch_slots * 16; - output_size_bytes += nir->info->tess.tcs_vertices_out * + output_size_bytes += nir->info.tess.tcs_vertices_out * num_per_vertex_slots * 16; assert(output_size_bytes >= 1); @@ -485,9 +485,9 @@ brw_compile_tcs(const struct brw_compiler *compiler, if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { g.enable_debug(ralloc_asprintf(mem_ctx, "%s tessellation control shader %s", - nir->info->label ? nir->info->label + nir->info.label ? nir->info.label : "unnamed", - nir->info->name)); + nir->info.name)); } g.generate_code(v.cfg, 8); |