diff options
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 35 |
1 files changed, 11 insertions, 24 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index ef569b5588c..bc1ccfba3d2 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -641,17 +641,17 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) } switch (instr->op) { - case nir_op_i2f: - case nir_op_u2f: + case nir_op_i2f32: + case nir_op_u2f32: if (optimize_extract_to_float(instr, result)) return; inst = bld.MOV(result, op[0]); inst->saturate = instr->dest.saturate; break; - case nir_op_f2d: - case nir_op_i2d: - case nir_op_u2d: + case nir_op_f2f64: + case nir_op_i2f64: + case nir_op_u2f64: /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions: * * "When source or destination is 64b (...), regioning in Align1 @@ -676,25 +676,15 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } /* fallthrough */ - case nir_op_i642d: - case nir_op_u642d: + case nir_op_f2f32: + case nir_op_f2i32: + case nir_op_f2u32: case nir_op_f2i64: case nir_op_f2u64: - case nir_op_i2i64: - case nir_op_i2u64: - case nir_op_u2i64: - case nir_op_u2u64: - case nir_op_d2f: - case nir_op_d2i: - case nir_op_d2u: - case nir_op_i642f: - case nir_op_u642f: - case nir_op_u2i32: case nir_op_i2i32: + case nir_op_i2i64: case nir_op_u2u32: - case nir_op_i2u32: - case nir_op_f2i: - case nir_op_f2u: + case nir_op_u2u64: inst = bld.MOV(result, op[0]); inst->saturate = instr->dest.saturate; break; @@ -1077,7 +1067,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_b2i64: case nir_op_b2i: case nir_op_b2f: bld.MOV(result, negate(op[0])); @@ -1085,14 +1074,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_i2b: case nir_op_f2b: - case nir_op_i642b: - case nir_op_d2b: if (nir_src_bit_size(instr->src[0].src) == 64) { /* two-argument instructions can't take 64-bit immediates */ fs_reg zero; fs_reg tmp; - if (instr->op == nir_op_d2b) { + if (instr->op == nir_op_f2b) { zero = vgrf(glsl_type::double_type); tmp = vgrf(glsl_type::double_type); } else { |