diff options
Diffstat (limited to 'src/intel/compiler/brw_fs.cpp')
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 4ab50aad11f..b16ed3be424 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -8264,15 +8264,33 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, min_dispatch_width = MAX2(8, min_dispatch_width); min_dispatch_width = util_next_power_of_two(min_dispatch_width); assert(min_dispatch_width <= 32); + unsigned max_dispatch_width = 32; fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL; cfg_t *cfg = NULL; const char *fail_msg = NULL; unsigned promoted_constants = 0; + if ((int)key->base.subgroup_size_type >= (int)BRW_SUBGROUP_SIZE_REQUIRE_8) { + /* These enum values are expressly chosen to be equal to the subgroup + * size that they require. + */ + const unsigned required_dispatch_width = + (unsigned)key->base.subgroup_size_type; + assert(required_dispatch_width == 8 || + required_dispatch_width == 16 || + required_dispatch_width == 32); + if (required_dispatch_width < min_dispatch_width || + required_dispatch_width > max_dispatch_width) { + fail_msg = "Cannot satisfy explicit subgroup size"; + } else { + min_dispatch_width = max_dispatch_width = required_dispatch_width; + } + } + /* Now the main event: Visit the shader IR and generate our CS IR for it. */ - if (min_dispatch_width <= 8) { + if (!fail_msg && min_dispatch_width <= 8 && max_dispatch_width >= 8) { nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key, src_shader, 8); v8 = new fs_visitor(compiler, log_data, mem_ctx, &key->base, @@ -8293,7 +8311,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, } if (likely(!(INTEL_DEBUG & DEBUG_NO16)) && - !fail_msg && min_dispatch_width <= 16) { + !fail_msg && min_dispatch_width <= 16 && max_dispatch_width >= 16) { /* Try a SIMD16 compile */ nir_shader *nir16 = compile_cs_to_nir(compiler, mem_ctx, key, src_shader, 16); @@ -8327,7 +8345,8 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, /* We should always be able to do SIMD32 for compute shaders */ assert(!v16 || v16->max_dispatch_width >= 32); - if (!fail_msg && (min_dispatch_width > 16 || (INTEL_DEBUG & DEBUG_DO32))) { + if (!fail_msg && (min_dispatch_width > 16 || (INTEL_DEBUG & DEBUG_DO32)) && + max_dispatch_width >= 32) { /* Try a SIMD32 compile */ nir_shader *nir32 = compile_cs_to_nir(compiler, mem_ctx, key, src_shader, 32); |