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-rw-r--r--src/intel/compiler/brw_eu_emit.c32
1 files changed, 18 insertions, 14 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index fae74cf80ab..39f82913651 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -141,22 +141,26 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
/* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
* or 16 (SIMD16), as that's normally correct. However, when dealing with
- * small registers, we automatically reduce it to match the register size.
- *
- * In platforms that support fp64 we can emit instructions with a width of
- * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In these
- * cases we need to make sure that these instructions have their exec sizes
- * set properly when they are emitted and we can't rely on this code to fix
- * it.
+ * small registers, it can be useful for us to automatically reduce it to
+ * match the register size.
*/
- bool fix_exec_size;
- if (devinfo->gen >= 6)
- fix_exec_size = dest.width < BRW_EXECUTE_4;
- else
- fix_exec_size = dest.width < BRW_EXECUTE_8;
+ if (p->automatic_exec_sizes) {
+ /*
+ * In platforms that support fp64 we can emit instructions with a width
+ * of 4 that need two SIMD8 registers and an exec_size of 8 or 16. In
+ * these cases we need to make sure that these instructions have their
+ * exec sizes set properly when they are emitted and we can't rely on
+ * this code to fix it.
+ */
+ bool fix_exec_size;
+ if (devinfo->gen >= 6)
+ fix_exec_size = dest.width < BRW_EXECUTE_4;
+ else
+ fix_exec_size = dest.width < BRW_EXECUTE_8;
- if (fix_exec_size)
- brw_inst_set_exec_size(devinfo, inst, dest.width);
+ if (fix_exec_size)
+ brw_inst_set_exec_size(devinfo, inst, dest.width);
+ }
}
void