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-rw-r--r--src/intel/compiler/brw_compiler.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index 626ff4bb16a..6a41cd20270 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -99,6 +99,9 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
+ compiler->use_tcs_8_patch =
+ devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH);
+
if (devinfo->gen >= 10) {
/* We don't support vec4 mode on Cannonlake. */
for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)