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-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp1
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 7cf0166cbbd..4c92a1efb51 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3307,6 +3307,7 @@ bool
PostRaLoadPropagation::visit(Instruction *i)
{
switch (i->op) {
+ case OP_FMA:
case OP_MAD:
if (prog->getTarget()->getChipset() < 0xc0)
handleMADforNV50(i);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index d36c8531a27..193628cfbda 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -1471,7 +1471,7 @@ GCRA::allocateRegisters(ArrayList& insns)
if (lval->inFile(FILE_GPR) && lval->getInsn() != NULL &&
prog->getTarget()->getChipset() < 0xc0) {
Instruction *insn = lval->getInsn();
- if (insn->op == OP_MAD || insn->op == OP_SAD)
+ if (insn->op == OP_MAD || insn->op == OP_FMA || insn->op == OP_SAD)
// Short encoding only possible if they're all GPRs, no need to
// affect them otherwise.
if (insn->flagsDef < 0 &&