diff options
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 10 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 26 |
2 files changed, 27 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index adbb716fead..3e771b297be 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3084,10 +3084,12 @@ void si_init_config(struct r600_context *rctx) si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); - si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, - S_028AA8_SWITCH_ON_EOP(1) | - S_028AA8_PARTIAL_VS_WAVE_ON(1) | - S_028AA8_PRIMGROUP_SIZE(63)); + if (rctx->b.chip_class == SI) { + si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, + S_028AA8_SWITCH_ON_EOP(1) | + S_028AA8_PARTIAL_VS_WAVE_ON(1) | + S_028AA8_PRIMGROUP_SIZE(63)); + } si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); if (rctx->b.chip_class < CIK) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 021352307c2..626ba9533f4 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -302,7 +302,8 @@ static unsigned r600_conv_prim_to_gs_out(unsigned mode) } static bool si_update_draw_info_state(struct r600_context *rctx, - const struct pipe_draw_info *info) + const struct pipe_draw_info *info, + const struct pipe_index_buffer *ib) { struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); struct si_shader *vs = &rctx->vs_shader->current->shader; @@ -318,12 +319,27 @@ static bool si_update_draw_info_state(struct r600_context *rctx, return false; } - if (rctx->b.chip_class >= CIK) + if (rctx->b.chip_class >= CIK) { + bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON || + prim == V_008958_DI_PT_LINELOOP || + prim == V_008958_DI_PT_TRIFAN || + prim == V_008958_DI_PT_TRISTRIP_ADJ || + info->primitive_restart; + + si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, + S_028AA8_SWITCH_ON_EOP(1) | + S_028AA8_PARTIAL_VS_WAVE_ON(1) | + S_028AA8_PRIMGROUP_SIZE(63) | + S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop)); + si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX, + ib->index_size == 4 ? 0xFC000000 : 0xFC00); + si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim); - else { + } else { si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); - si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); } + + si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, @@ -721,7 +737,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) } } - if (!si_update_draw_info_state(rctx, info)) + if (!si_update_draw_info_state(rctx, info, &ib)) return; si_state_draw(rctx, info, &ib); |