summaryrefslogtreecommitdiffstats
path: root/src/gallium
diff options
context:
space:
mode:
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_info.c6
-rw-r--r--src/gallium/docs/source/tgsi.rst30
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp10
-rw-r--r--src/gallium/drivers/r600/r600_shader.c18
-rw-r--r--src/gallium/include/pipe/p_shader_tokens.h5
5 files changed, 13 insertions, 56 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 38c4a81d03e..396e1900178 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -201,9 +201,9 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, 0, COMP, "ISSG", TGSI_OPCODE_ISSG },
{ 1, 2, 0, 0, 0, 0, 0, OTHR, "LOAD", TGSI_OPCODE_LOAD },
{ 1, 2, 0, 1, 0, 0, 0, OTHR, "STORE", TGSI_OPCODE_STORE },
- { 1, 0, 0, 0, 0, 0, 0, OTHR, "MFENCE", TGSI_OPCODE_MFENCE },
- { 1, 0, 0, 0, 0, 0, 0, OTHR, "LFENCE", TGSI_OPCODE_LFENCE },
- { 1, 0, 0, 0, 0, 0, 0, OTHR, "SFENCE", TGSI_OPCODE_SFENCE },
+ { 1, 0, 0, 0, 0, 0, 0, OTHR, "", 163 }, /* removed */
+ { 1, 0, 0, 0, 0, 0, 0, OTHR, "", 164 }, /* removed */
+ { 1, 0, 0, 0, 0, 0, 0, OTHR, "", 165 }, /* removed */
{ 0, 0, 0, 0, 0, 0, 0, OTHR, "BARRIER", TGSI_OPCODE_BARRIER },
{ 1, 3, 0, 1, 0, 0, 0, OTHR, "ATOMUADD", TGSI_OPCODE_ATOMUADD },
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 83ef7853949..be1f411b91a 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -2635,36 +2635,6 @@ These opcodes are intended for communication between threads running
within the same compute grid. For now they're only valid in compute
programs.
-.. opcode:: MFENCE - Memory fence
-
- Syntax: ``MFENCE resource``
-
- Example: ``MFENCE RES[0]``
-
- This opcode forces strong ordering between any memory access
- operations that affect the specified resource. This means that
- previous loads and stores (and only those) will be performed and
- visible to other threads before the program execution continues.
-
-
-.. opcode:: LFENCE - Load memory fence
-
- Syntax: ``LFENCE resource``
-
- Example: ``LFENCE RES[0]``
-
- Similar to MFENCE, but it only affects the ordering of memory loads.
-
-
-.. opcode:: SFENCE - Store memory fence
-
- Syntax: ``SFENCE resource``
-
- Example: ``SFENCE RES[0]``
-
- Similar to MFENCE, but it only affects the ordering of memory stores.
-
-
.. opcode:: BARRIER - Thread group barrier
``BARRIER``
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 0b1f5503348..23c7d106e39 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -994,9 +994,6 @@ static nv50_ir::operation translateOpcode(uint opcode)
static uint16_t opcodeToSubOp(uint opcode)
{
switch (opcode) {
- case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
- case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
- case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
@@ -3783,13 +3780,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
geni->fixed = 1;
geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
break;
- case TGSI_OPCODE_MFENCE:
- case TGSI_OPCODE_LFENCE:
- case TGSI_OPCODE_SFENCE:
- geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
- geni->fixed = 1;
- geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
- break;
case TGSI_OPCODE_MEMBAR:
{
uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 74f5add1191..d4eece3e724 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -9231,9 +9231,9 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
[TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
[TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
+ [163] = { ALU_OP0_NOP, tgsi_unsupported},
+ [164] = { ALU_OP0_NOP, tgsi_unsupported},
+ [165] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9429,9 +9429,9 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
[TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
+ [163] = { ALU_OP0_NOP, tgsi_unsupported},
+ [164] = { ALU_OP0_NOP, tgsi_unsupported},
+ [165] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
[TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9652,9 +9652,9 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
[TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
+ [163] = { ALU_OP0_NOP, tgsi_unsupported},
+ [164] = { ALU_OP0_NOP, tgsi_unsupported},
+ [165] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
[TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h
index 502446dc858..2254d3fdb7a 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -506,10 +506,7 @@ struct tgsi_property_data {
#define TGSI_OPCODE_LOAD 161
#define TGSI_OPCODE_STORE 162
-
-#define TGSI_OPCODE_MFENCE 163
-#define TGSI_OPCODE_LFENCE 164
-#define TGSI_OPCODE_SFENCE 165
+/* gap */
#define TGSI_OPCODE_BARRIER 166
#define TGSI_OPCODE_ATOMUADD 167
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 09:35:22 +0000