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-rw-r--r--src/gallium/drivers/vc4/vc4_qpu_schedule.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/gallium/drivers/vc4/vc4_qpu_schedule.c b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
index 8aa83741ff5..2b0a6326b8c 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
@@ -439,24 +439,24 @@ get_instruction_priority(uint64_t inst)
uint32_t baseline_score;
uint32_t next_score = 0;
- /* Schedule texture read setup early to hide their latency better. */
- if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
+ /* Schedule TLB operations as late as possible, to get more
+ * parallelism between shaders.
+ */
+ if (qpu_inst_is_tlb(inst))
return next_score;
next_score++;
- /* Default score for things that aren't otherwise special. */
- baseline_score = next_score;
- next_score++;
-
/* Schedule texture read results collection late to hide latency. */
if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
return next_score;
next_score++;
- /* Schedule TLB operations as late as possible, to get more
- * parallelism between shaders.
- */
- if (qpu_inst_is_tlb(inst))
+ /* Default score for things that aren't otherwise special. */
+ baseline_score = next_score;
+ next_score++;
+
+ /* Schedule texture read setup early to hide their latency better. */
+ if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
return next_score;
next_score++;