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-rw-r--r--src/gallium/drivers/nvc0/nve4_compute.c58
-rw-r--r--src/gallium/drivers/nvc0/nve4_compute.h4
-rw-r--r--src/gallium/drivers/nvc0/nve4_compute.xml.h116
3 files changed, 129 insertions, 49 deletions
diff --git a/src/gallium/drivers/nvc0/nve4_compute.c b/src/gallium/drivers/nvc0/nve4_compute.c
index 89da7d568cb..d7aa61ec81d 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nvc0/nve4_compute.c
@@ -129,14 +129,14 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
/* MS sample coordinate offsets: these do not work with _ALT modes ! */
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 64);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
PUSH_DATA (push, 0); /* 0 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 1); /* 1 */
@@ -155,14 +155,14 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
PUSH_DATA (push, 1);
#ifdef DEBUG
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 28);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, 1);
PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
PUSH_DATA (push, screen->tls->offset);
@@ -199,14 +199,14 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
* NVE4's surface load/store instructions receive all the information
* directly instead of via binding points, so we have to supply them.
*/
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 64);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
@@ -279,14 +279,14 @@ nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, n * 4);
PUSH_DATA (push, 0x1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
@@ -365,24 +365,24 @@ nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
struct nvc0_program *cp = nvc0->compprog;
if (cp->parm_size) {
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->parm->offset);
PUSH_DATA (push, screen->parm->offset);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, cp->parm_size);
PUSH_DATA (push, 0x1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
PUSH_DATAp(push, input, cp->parm_size / 4);
}
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 7 * 4);
PUSH_DATA (push, 0x1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
PUSH_DATAp(push, block_layout, 3);
PUSH_DATAp(push, grid_layout, 3);
PUSH_DATA (push, 0);
@@ -488,14 +488,14 @@ nve4_launch_grid(struct pipe_context *pipe,
/* upload descriptor and flush */
#if 0
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, desc_gpuaddr);
PUSH_DATA (push, desc_gpuaddr);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 256);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DESC);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
@@ -542,14 +542,14 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
PUSH_SPACE(push, 16);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, txc->offset + (tic->id * 32));
PUSH_DATA (push, txc->offset + (tic->id * 32));
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 32);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
PUSH_DATAp(push, &tic->tic[0], 8);
commands[0][n[0]++] = (tic->id << 4) | 1;
diff --git a/src/gallium/drivers/nvc0/nve4_compute.h b/src/gallium/drivers/nvc0/nve4_compute.h
index 91d64fff695..4939790e530 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.h
+++ b/src/gallium/drivers/nvc0/nve4_compute.h
@@ -68,10 +68,6 @@ struct nve4_cp_launch_desc
u32 unk48[16];
};
-#define NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA 0x41
-#define NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DESC 0x11
-#define NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL 0x1
-
static INLINE void
nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
{
diff --git a/src/gallium/drivers/nvc0/nve4_compute.xml.h b/src/gallium/drivers/nvc0/nve4_compute.xml.h
index 9a774668239..96527cc7a23 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.xml.h
+++ b/src/gallium/drivers/nvc0/nve4_compute.xml.h
@@ -8,12 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- nve4_compute.xml ( 11117 bytes, from 2013-03-27 19:22:20)
+- nve4_compute.xml ( 10168 bytes, from 2013-03-31 20:05:20)
- copyright.xml ( 6452 bytes, from 2011-08-11 18:25:12)
- nvchipsets.xml ( 3954 bytes, from 2013-03-26 01:26:43)
-- nv_object.xml ( 13792 bytes, from 2013-03-26 01:26:43)
+- nv_object.xml ( 14395 bytes, from 2013-03-31 20:05:20)
- nv_defs.xml ( 4437 bytes, from 2011-08-11 18:25:12)
-- nv50_defs.xml ( 7783 bytes, from 2013-03-08 12:42:29)
+- nv50_defs.xml ( 9613 bytes, from 2013-03-28 11:02:04)
+- nve4_p2mf.xml ( 2373 bytes, from 2013-03-31 20:05:20)
Copyright (C) 2006-2013 by the following authors:
- Artur Huillet <[email protected]> (ahuillet)
@@ -75,32 +76,91 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-#define NVE4_COMPUTE_UPLOAD_SIZE 0x00000180
-#define NVE4_COMPUTE_UPLOAD_UNK0184 0x00000184
+#define NVE4_COMPUTE_UNK0144 0x00000144
-#define NVE4_COMPUTE_UPLOAD_ADDRESS_HIGH 0x00000188
+#define NVE4_COMPUTE_UPLOAD 0x00000000
-#define NVE4_COMPUTE_UPLOAD_ADDRESS_LOW 0x0000018c
+#define NVE4_COMPUTE_UPLOAD_LINE_LENGTH_IN 0x00000180
-#define NVE4_COMPUTE_UNK01A0 0x000001a0
+#define NVE4_COMPUTE_UPLOAD_LINE_COUNT 0x00000184
-#define NVE4_COMPUTE_UNK01A4 0x000001a4
+#define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_HIGH 0x00000188
-#define NVE4_COMPUTE_UNK01A8 0x000001a8
+#define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_LOW 0x0000018c
-#define NVE4_COMPUTE_UNK01AC 0x000001ac
+#define NVE4_COMPUTE_UPLOAD_DST_PITCH 0x00000190
+
+#define NVE4_COMPUTE_UPLOAD_DST_TILE_MODE 0x00000194
+
+#define NVE4_COMPUTE_UPLOAD_DST_WIDTH 0x00000198
+
+#define NVE4_COMPUTE_UPLOAD_DST_HEIGHT 0x0000019c
+
+#define NVE4_COMPUTE_UPLOAD_DST_DEPTH 0x000001a0
+
+#define NVE4_COMPUTE_UPLOAD_DST_Z 0x000001a4
+
+#define NVE4_COMPUTE_UPLOAD_DST_X 0x000001a8
+
+#define NVE4_COMPUTE_UPLOAD_DST_Y 0x000001ac
#define NVE4_COMPUTE_UPLOAD_EXEC 0x000001b0
+#define NVE4_COMPUTE_UPLOAD_EXEC_LINEAR 0x00000001
+#define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__MASK 0x0000007e
+#define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__SHIFT 1
+#define NVE4_COMPUTE_UPLOAD_EXEC_BUF_NOTIFY 0x00000300
+#define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__MASK 0x0000f000
+#define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__SHIFT 12
#define NVE4_COMPUTE_UPLOAD_DATA 0x000001b4
+#define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_HIGH 0x000001dc
+
+#define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_LOW 0x000001e0
+
+#define NVE4_COMPUTE_UPLOAD_QUERY_SEQUENCE 0x000001e4
+
+#define NVE4_COMPUTE_UPLOAD_UNK01F0 0x000001f0
+
+#define NVE4_COMPUTE_UPLOAD_UNK01F4 0x000001f4
+
+#define NVE4_COMPUTE_UPLOAD_UNK01F8 0x000001f8
+
+#define NVE4_COMPUTE_UPLOAD_UNK01FC 0x000001fc
+
#define NVE4_COMPUTE_SHARED_BASE 0x00000214
#define NVE4_COMPUTE_MEM_BARRIER 0x0000021c
+#define NVE4_COMPUTE_MEM_BARRIER_UNK0__MASK 0x00000007
+#define NVE4_COMPUTE_MEM_BARRIER_UNK0__SHIFT 0
+#define NVE4_COMPUTE_MEM_BARRIER_UNK4 0x00000010
+#define NVE4_COMPUTE_MEM_BARRIER_UNK12 0x00001000
+
+#define NVE4_COMPUTE_UNK0240 0x00000240
+
+#define NVE4_COMPUTE_UNK244_TIC_FLUSH 0x00000244
+
+#define NVE4_COMPUTE_UNK0248 0x00000248
+#define NVE4_COMPUTE_UNK0248_UNK0__MASK 0x0000003f
+#define NVE4_COMPUTE_UNK0248_UNK0__SHIFT 0
+#define NVE4_COMPUTE_UNK0248_UNK8__MASK 0x00ffff00
+#define NVE4_COMPUTE_UNK0248_UNK8__SHIFT 8
+
+#define NVE4_COMPUTE_UNK0274 0x00000274
+
+#define NVE4_COMPUTE_UNK0278 0x00000278
+
+#define NVE4_COMPUTE_UNK027C 0x0000027c
#define NVE4_COMPUTE_UNK0280 0x00000280
+#define NVE4_COMPUTE_UNK0284 0x00000284
+
+#define NVE4_COMPUTE_UNK0288 0x00000288
+
+#define NVE4_COMPUTE_UNK0290 0x00000290
+
#define NVE4_COMPUTE_UNK02B0 0x000002b0
#define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS 0x000002b4
@@ -122,15 +182,29 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVE4_COMPUTE_UNK0310 0x00000310
+#define NVE4_COMPUTE_FIRMWARE(i0) (0x00000500 + 0x4*(i0))
+#define NVE4_COMPUTE_FIRMWARE__ESIZE 0x00000004
+#define NVE4_COMPUTE_FIRMWARE__LEN 0x00000020
+
#define NVE4_COMPUTE_LOCAL_BASE 0x0000077c
#define NVE4_COMPUTE_TEMP_ADDRESS_HIGH 0x00000790
#define NVE4_COMPUTE_TEMP_ADDRESS_LOW 0x00000794
+#define NVE4_COMPUTE_UNK0D94 0x00000d94
+
#define NVE4_COMPUTE_WATCHDOG_TIMER 0x00000de4
-#define NVE4_COMPUTE_LINKED_TSC 0x00001234
+#define NVE4_COMPUTE_UNK0F44(i0) (0x00000f44 + 0x4*(i0))
+#define NVE4_COMPUTE_UNK0F44__ESIZE 0x00000004
+#define NVE4_COMPUTE_UNK0F44__LEN 0x00000004
+
+#define NVE4_COMPUTE_UNK1040(i0) (0x00001040 + 0x4*(i0))
+#define NVE4_COMPUTE_UNK1040__ESIZE 0x00000004
+#define NVE4_COMPUTE_UNK1040__LEN 0x0000000c
+
+#define NVE4_COMPUTE_UNK1288_TIC_FLUSH 0x00001288
#define NVE4_COMPUTE_TSC_FLUSH 0x00001330
#define NVE4_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001
@@ -143,11 +217,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVE4_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4
#define NVE4_COMPUTE_TEX_CACHE_CTL 0x00001338
-#define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0__MASK 0x00000007
-#define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0__SHIFT 0
+#define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0 0x00000001
#define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0
#define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT 4
+#define NVE4_COMPUTE_UNK1424_TSC_FLUSH 0x00001424
+
#define NVE4_COMPUTE_COND_ADDRESS_HIGH 0x00001550
#define NVE4_COMPUTE_COND_ADDRESS_LOW 0x00001554
@@ -175,12 +250,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVE4_COMPUTE_CODE_ADDRESS_LOW 0x0000160c
+#define NVE4_COMPUTE_UNK1690 0x00001690
+
#define NVE4_COMPUTE_FLUSH 0x00001698
#define NVE4_COMPUTE_FLUSH_CODE 0x00000001
#define NVE4_COMPUTE_FLUSH_GLOBAL 0x00000010
-#define NVE4_COMPUTE_FLUSH_UNK8 0x00000100
#define NVE4_COMPUTE_FLUSH_CB 0x00001000
+#define NVE4_COMPUTE_UNK1944 0x00001944
+
+#define NVE4_COMPUTE_DELAY 0x00001a24
+
+#define NVE4_COMPUTE_UNK1A2C(i0) (0x00001a2c + 0x4*(i0))
+#define NVE4_COMPUTE_UNK1A2C__ESIZE 0x00000004
+#define NVE4_COMPUTE_UNK1A2C__LEN 0x00000005
+
#define NVE4_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00
#define NVE4_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04
@@ -197,7 +281,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVE4_COMPUTE_TEX_CB_INDEX 0x00002608
-#define NVE4_COMPUTE_UNK260c 0x0000260c
+#define NVE4_COMPUTE_UNK260C 0x0000260c
#define NVE4_COMPUTE_MP_PM_SET(i0) (0x0000335c + 0x4*(i0))
#define NVE4_COMPUTE_MP_PM_SET__ESIZE 0x00000004
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 14:23:55 +0000