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-rw-r--r--src/gallium/drivers/radeonsi/si_compute.c4
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c1
2 files changed, 2 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e95e79c7b46..e20bae0afc4 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -331,9 +331,7 @@ static void si_initialize_compute(struct si_context *sctx)
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
} else {
- if (sctx->screen->info.drm_major == 3 ||
- (sctx->screen->info.drm_major == 2 &&
- sctx->screen->info.drm_minor >= 48)) {
+ if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
bc_va >> 8);
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 21579fd9563..6040134c2da 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -532,6 +532,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
+ ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;