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-rw-r--r--src/gallium/drivers/radeonsi/si_build_pm4.h8
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c12
2 files changed, 15 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 796adda0963..4e8890a5f97 100644
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -100,12 +100,18 @@ static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg
}
static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
+ struct si_screen *screen,
unsigned reg, unsigned idx,
unsigned value)
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->current.cdw + 3 <= cs->current.max_dw);
- radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
+ assert(idx != 0);
+ unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
+ if (screen->info.chip_class < GFX9 ||
+ (screen->info.chip_class == GFX9 && screen->info.me_fw_version < 26))
+ opcode = PKT3_SET_UCONFIG_REG;
+ radeon_emit(cs, PKT3(opcode, 1, 0));
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, value);
}
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 254f9edeb75..d011adb2cad 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -618,7 +618,9 @@ static void si_emit_draw_registers(struct si_context *sctx,
/* Draw state. */
if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
if (sctx->chip_class >= GFX9)
- radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
+ radeon_set_uconfig_reg_idx(cs, sctx->screen,
+ R_030960_IA_MULTI_VGT_PARAM, 4,
+ ia_multi_vgt_param);
else if (sctx->chip_class >= CIK)
radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
else
@@ -628,7 +630,8 @@ static void si_emit_draw_registers(struct si_context *sctx,
}
if (prim != sctx->last_prim) {
if (sctx->chip_class >= CIK)
- radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
+ radeon_set_uconfig_reg_idx(cs, sctx->screen,
+ R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
else
radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
@@ -716,8 +719,9 @@ static void si_emit_draw_packets(struct si_context *sctx,
}
if (sctx->chip_class >= GFX9) {
- radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
- 2, index_type);
+ radeon_set_uconfig_reg_idx(cs, sctx->screen,
+ R_03090C_VGT_INDEX_TYPE, 2,
+ index_type);
} else {
radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cs, index_type);