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-rw-r--r--src/gallium/drivers/radeonsi/si_state.c182
1 files changed, 71 insertions, 111 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 2b574f3cc52..46112f7656f 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1496,6 +1496,64 @@ boolean si_is_format_supported(struct pipe_screen *screen,
return retval == usage;
}
+static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level)
+{
+ if (util_format_is_depth_or_stencil(rtex->real_format)) {
+ if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
+ return 4;
+ } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
+ switch (rtex->real_format) {
+ case PIPE_FORMAT_Z16_UNORM:
+ return 5;
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_Z32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ return 6;
+ default:
+ return 7;
+ }
+ }
+ }
+
+ switch (rtex->surface.level[level].mode) {
+ default:
+ assert(!"Invalid surface mode");
+ /* Fall through */
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ return 8;
+ case RADEON_SURF_MODE_1D:
+ return 9;
+ case RADEON_SURF_MODE_2D:
+ if (rtex->surface.flags & RADEON_SURF_SCANOUT) {
+ switch (util_format_get_blocksize(rtex->real_format)) {
+ case 1:
+ return 10;
+ case 2:
+ return 11;
+ default:
+ assert(!"Invalid block size");
+ /* Fall through */
+ case 4:
+ return 12;
+ }
+ } else {
+ switch (util_format_get_blocksize(rtex->real_format)) {
+ case 1:
+ return 14;
+ case 2:
+ return 15;
+ case 4:
+ return 16;
+ case 8:
+ return 17;
+ default:
+ return 13;
+ }
+ }
+ }
+}
+
/*
* framebuffer handling
*/
@@ -1507,10 +1565,10 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
struct r600_surface *surf;
unsigned level = state->cbufs[cb]->u.tex.level;
unsigned pitch, slice;
- unsigned color_info, color_attrib;
+ unsigned color_info;
+ unsigned tile_mode_index;
unsigned format, swap, ntype, endian;
uint64_t offset;
- unsigned blocksize;
const struct util_format_description *desc;
int i;
unsigned blend_clamp = 0, blend_bypass = 0;
@@ -1518,7 +1576,6 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
- blocksize = util_format_get_blocksize(rtex->real_format);
if (rtex->depth)
rctx->have_depth_fb = TRUE;
@@ -1539,46 +1596,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
slice = slice - 1;
}
- color_attrib = S_028C74_TILE_MODE_INDEX(8);
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- color_attrib = S_028C74_TILE_MODE_INDEX(8);
- break;
- case RADEON_SURF_MODE_1D:
- color_attrib = S_028C74_TILE_MODE_INDEX(9);
- break;
- case RADEON_SURF_MODE_2D:
- if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
- switch (blocksize) {
- case 1:
- color_attrib = S_028C74_TILE_MODE_INDEX(10);
- break;
- case 2:
- color_attrib = S_028C74_TILE_MODE_INDEX(11);
- break;
- case 4:
- color_attrib = S_028C74_TILE_MODE_INDEX(12);
- break;
- }
- break;
- } else switch (blocksize) {
- case 1:
- color_attrib = S_028C74_TILE_MODE_INDEX(14);
- break;
- case 2:
- color_attrib = S_028C74_TILE_MODE_INDEX(15);
- break;
- case 4:
- color_attrib = S_028C74_TILE_MODE_INDEX(16);
- break;
- case 8:
- color_attrib = S_028C74_TILE_MODE_INDEX(17);
- break;
- default:
- color_attrib = S_028C74_TILE_MODE_INDEX(13);
- }
- break;
- }
+ tile_mode_index = si_tile_mode_index(rtex, level);
desc = util_format_description(surf->base.format);
for (i = 0; i < 4; i++) {
@@ -1656,7 +1674,8 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
}
si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
- si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
+ si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
+ S_028C74_TILE_MODE_INDEX(tile_mode_index));
/* Determine pixel shader export format */
max_comp_size = si_colorformat_max_comp_size(format);
@@ -1675,7 +1694,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, pitch, slice, format;
+ unsigned level, pitch, slice, format, tile_mode_index;
uint32_t z_info, s_info;
uint64_t z_offs, s_offs;
@@ -1715,33 +1734,16 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
else
s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
- if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
- z_info |= S_028040_TILE_MODE_INDEX(4);
- s_info |= S_028044_TILE_MODE_INDEX(4);
-
- } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
- switch (format) {
- case V_028040_Z_16:
- z_info |= S_028040_TILE_MODE_INDEX(5);
- s_info |= S_028044_TILE_MODE_INDEX(5);
- break;
- case V_028040_Z_24:
- case V_028040_Z_32_FLOAT:
- z_info |= S_028040_TILE_MODE_INDEX(6);
- s_info |= S_028044_TILE_MODE_INDEX(6);
- break;
- default:
- z_info |= S_028040_TILE_MODE_INDEX(7);
- s_info |= S_028044_TILE_MODE_INDEX(7);
- }
-
- } else {
+ tile_mode_index = si_tile_mode_index(rtex, level);
+ if (tile_mode_index < 4 || tile_mode_index > 7) {
R600_ERR("Invalid DB tiling mode %d!\n",
- rtex->surface.level[level].mode);
+ rtex->surface.level[level].mode);
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
return;
}
+ z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
+ s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
@@ -2039,8 +2041,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
const struct util_format_description *desc = util_format_description(state->format);
- unsigned blocksize = util_format_get_blocksize(tmp->real_format);
- unsigned format, num_format, /*endian,*/ tiling_index;
+ unsigned format, num_format;
uint32_t pitch = 0;
unsigned char state_swizzle[4], swizzle[4];
unsigned height, depth, width;
@@ -2105,47 +2106,6 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
depth = texture->array_size;
}
- tiling_index = 8;
- switch (tmp->surface.level[0].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- tiling_index = 8;
- break;
- case RADEON_SURF_MODE_1D:
- tiling_index = 9;
- break;
- case RADEON_SURF_MODE_2D:
- if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
- switch (blocksize) {
- case 1:
- tiling_index = 10;
- break;
- case 2:
- tiling_index = 11;
- break;
- case 4:
- tiling_index = 12;
- break;
- }
- break;
- } else switch (blocksize) {
- case 1:
- tiling_index = 14;
- break;
- case 2:
- tiling_index = 15;
- break;
- case 4:
- tiling_index = 16;
- break;
- case 8:
- tiling_index = 17;
- break;
- default:
- tiling_index = 13;
- }
- break;
- }
-
va = r600_resource_va(ctx->screen, texture);
va += tmp->surface.level[0].offset;
view->state[0] = va >> 8;
@@ -2160,7 +2120,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
- S_008F1C_TILING_INDEX(tiling_index) |
+ S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) |
S_008F1C_POW2_PAD(texture->last_level > 0) |
S_008F1C_TYPE(si_tex_dim(texture->target)));
view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 13:00:57 +0000