diff options
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/vc5/Makefile.sources | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/v3dx_context.h | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/v3dx_simulator.c | 18 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_bufmgr.c | 16 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_context.h | 8 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_drm.h | 191 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_job.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_screen.c | 13 | ||||
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_simulator.c | 20 |
9 files changed, 39 insertions, 234 deletions
diff --git a/src/gallium/drivers/vc5/Makefile.sources b/src/gallium/drivers/vc5/Makefile.sources index c1e4e0b0236..486857c1f03 100644 --- a/src/gallium/drivers/vc5/Makefile.sources +++ b/src/gallium/drivers/vc5/Makefile.sources @@ -6,7 +6,6 @@ C_SOURCES := \ vc5_cl.h \ vc5_context.c \ vc5_context.h \ - vc5_drm.h \ vc5_fence.c \ vc5_formats.c \ vc5_format_table.h \ diff --git a/src/gallium/drivers/vc5/v3dx_context.h b/src/gallium/drivers/vc5/v3dx_context.h index f9edd1c636d..538aed68be0 100644 --- a/src/gallium/drivers/vc5/v3dx_context.h +++ b/src/gallium/drivers/vc5/v3dx_context.h @@ -38,8 +38,8 @@ void v3dX(bcl_epilogue)(struct vc5_context *vc5, struct vc5_job *job); void v3dX(simulator_init_regs)(struct v3d_hw *v3d); int v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d, - struct drm_vc5_get_param *args); -void v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit, + struct drm_v3d_get_param *args); +void v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_v3d_submit_cl *submit, uint32_t gmp_ofs); const struct vc5_format *v3dX(get_format_desc)(enum pipe_format f); void v3dX(get_internal_type_bpp_for_output_format)(uint32_t format, diff --git a/src/gallium/drivers/vc5/v3dx_simulator.c b/src/gallium/drivers/vc5/v3dx_simulator.c index 90fafaee1e2..e1589d44b22 100644 --- a/src/gallium/drivers/vc5/v3dx_simulator.c +++ b/src/gallium/drivers/vc5/v3dx_simulator.c @@ -100,16 +100,16 @@ vc5_flush_caches(struct v3d_hw *v3d) int v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d, - struct drm_vc5_get_param *args) + struct drm_v3d_get_param *args) { static const uint32_t reg_map[] = { - [DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG, - [DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1, - [DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2, - [DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3, - [DRM_VC5_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0, - [DRM_VC5_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1, - [DRM_VC5_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2, + [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG, + [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1, + [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2, + [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3, + [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0, + [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1, + [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2, }; if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) { @@ -139,7 +139,7 @@ v3dX(simulator_init_regs)(struct v3d_hw *v3d) } void -v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit, +v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_v3d_submit_cl *submit, uint32_t gmp_ofs) { /* Completely reset the GMP. */ diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c b/src/gallium/drivers/vc5/vc5_bufmgr.c index ef6995e4def..28a7b008f9e 100644 --- a/src/gallium/drivers/vc5/vc5_bufmgr.c +++ b/src/gallium/drivers/vc5/vc5_bufmgr.c @@ -152,11 +152,11 @@ vc5_bo_alloc(struct vc5_screen *screen, uint32_t size, const char *name) ; bool cleared_and_retried = false; - struct drm_vc5_create_bo create = { + struct drm_v3d_create_bo create = { .size = size }; - ret = vc5_ioctl(screen->fd, DRM_IOCTL_VC5_CREATE_BO, &create); + ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_CREATE_BO, &create); bo->handle = create.handle; bo->offset = create.offset; @@ -354,10 +354,10 @@ vc5_bo_open_handle(struct vc5_screen *screen, bo->map = malloc(bo->size); #endif - struct drm_vc5_get_bo_offset get = { + struct drm_v3d_get_bo_offset get = { .handle = handle, }; - int ret = vc5_ioctl(screen->fd, DRM_IOCTL_VC5_GET_BO_OFFSET, &get); + int ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_GET_BO_OFFSET, &get); if (ret) { fprintf(stderr, "Failed to get BO offset: %s\n", strerror(errno)); @@ -455,11 +455,11 @@ vc5_bo_flink(struct vc5_bo *bo, uint32_t *name) static int vc5_wait_bo_ioctl(int fd, uint32_t handle, uint64_t timeout_ns) { - struct drm_vc5_wait_bo wait = { + struct drm_v3d_wait_bo wait = { .handle = handle, .timeout_ns = timeout_ns, }; - int ret = vc5_ioctl(fd, DRM_IOCTL_VC5_WAIT_BO, &wait); + int ret = vc5_ioctl(fd, DRM_IOCTL_V3D_WAIT_BO, &wait); if (ret == -1) return -errno; else @@ -501,10 +501,10 @@ vc5_bo_map_unsynchronized(struct vc5_bo *bo) if (bo->map) return bo->map; - struct drm_vc5_mmap_bo map; + struct drm_v3d_mmap_bo map; memset(&map, 0, sizeof(map)); map.handle = bo->handle; - ret = vc5_ioctl(bo->screen->fd, DRM_IOCTL_VC5_MMAP_BO, &map); + ret = vc5_ioctl(bo->screen->fd, DRM_IOCTL_V3D_MMAP_BO, &map); offset = map.offset; if (ret != 0) { fprintf(stderr, "map ioctl failure\n"); diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h index 9e55f80f947..ad52ea61290 100644 --- a/src/gallium/drivers/vc5/vc5_context.h +++ b/src/gallium/drivers/vc5/vc5_context.h @@ -36,15 +36,13 @@ #include "util/bitset.h" #include "util/slab.h" #include "xf86drm.h" -#include "vc5_drm.h" +#include "v3d_drm.h" #include "vc5_screen.h" struct vc5_job; struct vc5_bo; void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo); -#define __user -#include "vc5_drm.h" #include "vc5_bufmgr.h" #include "vc5_resource.h" #include "vc5_cl.h" @@ -225,7 +223,7 @@ struct vc5_job { struct vc5_bo *tile_state; uint32_t shader_rec_count; - struct drm_vc5_submit_cl submit; + struct drm_v3d_submit_cl submit; /** * Set of all BOs referenced by the job. This will be used for making @@ -492,7 +490,7 @@ void vc5_query_init(struct pipe_context *pctx); void vc5_simulator_init(struct vc5_screen *screen); void vc5_simulator_destroy(struct vc5_screen *screen); int vc5_simulator_flush(struct vc5_context *vc5, - struct drm_vc5_submit_cl *args, + struct drm_v3d_submit_cl *args, struct vc5_job *job); int vc5_simulator_ioctl(int fd, unsigned long request, void *arg); void vc5_simulator_open_from_handle(int fd, uint32_t winsys_stride, diff --git a/src/gallium/drivers/vc5/vc5_drm.h b/src/gallium/drivers/vc5/vc5_drm.h deleted file mode 100644 index 184863d206a..00000000000 --- a/src/gallium/drivers/vc5/vc5_drm.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright © 2014-2017 Broadcom - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _VC5_DRM_H_ -#define _VC5_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_VC5_SUBMIT_CL 0x00 -#define DRM_VC5_WAIT_BO 0x01 -#define DRM_VC5_CREATE_BO 0x02 -#define DRM_VC5_MMAP_BO 0x03 -#define DRM_VC5_GET_PARAM 0x04 -#define DRM_VC5_GET_BO_OFFSET 0x05 - -#define DRM_IOCTL_VC5_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_SUBMIT_CL, struct drm_vc5_submit_cl) -#define DRM_IOCTL_VC5_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_WAIT_BO, struct drm_vc5_wait_bo) -#define DRM_IOCTL_VC5_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_CREATE_BO, struct drm_vc5_create_bo) -#define DRM_IOCTL_VC5_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_MMAP_BO, struct drm_vc5_mmap_bo) -#define DRM_IOCTL_VC5_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_GET_PARAM, struct drm_vc5_get_param) -#define DRM_IOCTL_VC5_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_GET_BO_OFFSET, struct drm_vc5_get_bo_offset) - -/** - * struct drm_vc5_submit_cl - ioctl argument for submitting commands to the 3D - * engine. - * - * This asks the kernel to have the GPU execute an optional binner - * command list, and a render command list. - */ -struct drm_vc5_submit_cl { - /* Pointer to the binner command list. - * - * This is the first set of commands executed, which runs the - * coordinate shader to determine where primitives land on the screen, - * then writes out the state updates and draw calls necessary per tile - * to the tile allocation BO. - */ - __u32 bcl_start; - - /** End address of the BCL (first byte after the BCL) */ - __u32 bcl_end; - - /* Offset of the render command list. - * - * This is the second set of commands executed, which will either - * execute the tiles that have been set up by the BCL, or a fixed set - * of tiles (in the case of RCL-only blits). - */ - __u32 rcl_start; - - /** End address of the RCL (first byte after the RCL) */ - __u32 rcl_end; - - /** An optional sync object to wait on before starting the BCL. */ - __u32 in_sync_bcl; - /** An optional sync object to wait on before starting the RCL. */ - __u32 in_sync_rcl; - /** An optional sync object to place the completion fence in. */ - __u32 out_sync; - - /* Offset of the tile alloc memory - * - * This is optional on V3D 3.3 (where the CL can set the value) but - * required on V3D 4.1. - */ - __u32 qma; - - /** Size of the tile alloc memory. */ - __u32 qms; - - /** Offset of the tile state data array. */ - __u32 qts; - - /* Pointer to a u32 array of the BOs that are referenced by the job. - */ - __u64 bo_handles; - - /* Number of BO handles passed in (size is that times 4). */ - __u32 bo_handle_count; -}; - -/** - * struct drm_vc5_wait_bo - ioctl argument for waiting for - * completion of the last DRM_VC5_SUBMIT_CL on a BO. - * - * This is useful for cases where multiple processes might be - * rendering to a BO and you want to wait for all rendering to be - * completed. - */ -struct drm_vc5_wait_bo { - __u32 handle; - __u32 pad; - __u64 timeout_ns; -}; - -/** - * struct drm_vc5_create_bo - ioctl argument for creating VC5 BOs. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc5_create_bo { - __u32 size; - __u32 flags; - /** Returned GEM handle for the BO. */ - __u32 handle; - /** - * Returned offset for the BO in the V3D address space. This offset - * is private to the DRM fd and is valid for the lifetime of the GEM - * handle. - * - * This offset value will always be nonzero, since various HW - * units treat 0 specially. - */ - __u32 offset; -}; - -/** - * struct drm_vc5_mmap_bo - ioctl argument for mapping VC5 BOs. - * - * This doesn't actually perform an mmap. Instead, it returns the - * offset you need to use in an mmap on the DRM device node. This - * means that tools like valgrind end up knowing about the mapped - * memory. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc5_mmap_bo { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 flags; - /** offset into the drm node to use for subsequent mmap call. */ - __u64 offset; -}; - -enum drm_vc5_param { - DRM_VC5_PARAM_V3D_UIFCFG, - DRM_VC5_PARAM_V3D_HUB_IDENT1, - DRM_VC5_PARAM_V3D_HUB_IDENT2, - DRM_VC5_PARAM_V3D_HUB_IDENT3, - DRM_VC5_PARAM_V3D_CORE0_IDENT0, - DRM_VC5_PARAM_V3D_CORE0_IDENT1, - DRM_VC5_PARAM_V3D_CORE0_IDENT2, -}; - -struct drm_vc5_get_param { - __u32 param; - __u32 pad; - __u64 value; -}; - -/** - * Returns the offset for the BO in the V3D address space for this DRM fd. - * This is the same value returned by drm_vc5_create_bo, if that was called - * from this DRM fd. - */ -struct drm_vc5_get_bo_offset { - __u32 handle; - __u32 offset; -}; - -#if defined(__cplusplus) -} -#endif - -#endif /* _VC5_DRM_H_ */ diff --git a/src/gallium/drivers/vc5/vc5_job.c b/src/gallium/drivers/vc5/vc5_job.c index 9947fb47ff0..3da6ba82f47 100644 --- a/src/gallium/drivers/vc5/vc5_job.c +++ b/src/gallium/drivers/vc5/vc5_job.c @@ -411,7 +411,7 @@ vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job) int ret; #ifndef USE_VC5_SIMULATOR - ret = drmIoctl(vc5->fd, DRM_IOCTL_VC5_SUBMIT_CL, &job->submit); + ret = drmIoctl(vc5->fd, DRM_IOCTL_V3D_SUBMIT_CL, &job->submit); #else ret = vc5_simulator_flush(vc5, &job->submit, job); #endif diff --git a/src/gallium/drivers/vc5/vc5_screen.c b/src/gallium/drivers/vc5/vc5_screen.c index a287a5e0ebd..c36495f646b 100644 --- a/src/gallium/drivers/vc5/vc5_screen.c +++ b/src/gallium/drivers/vc5/vc5_screen.c @@ -34,7 +34,6 @@ #include "util/ralloc.h" #include <xf86drm.h> -#include "vc5_drm.h" #include "vc5_screen.h" #include "vc5_context.h" #include "vc5_resource.h" @@ -550,21 +549,21 @@ static int handle_compare(void *key1, void *key2) static bool vc5_get_device_info(struct vc5_screen *screen) { - struct drm_vc5_get_param ident0 = { - .param = DRM_VC5_PARAM_V3D_CORE0_IDENT0, + struct drm_v3d_get_param ident0 = { + .param = DRM_V3D_PARAM_V3D_CORE0_IDENT0, }; - struct drm_vc5_get_param ident1 = { - .param = DRM_VC5_PARAM_V3D_CORE0_IDENT1, + struct drm_v3d_get_param ident1 = { + .param = DRM_V3D_PARAM_V3D_CORE0_IDENT1, }; int ret; - ret = vc5_ioctl(screen->fd, DRM_IOCTL_VC5_GET_PARAM, &ident0); + ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_GET_PARAM, &ident0); if (ret != 0) { fprintf(stderr, "Couldn't get V3D core IDENT0: %s\n", strerror(errno)); return false; } - ret = vc5_ioctl(screen->fd, DRM_IOCTL_VC5_GET_PARAM, &ident1); + ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_GET_PARAM, &ident1); if (ret != 0) { fprintf(stderr, "Couldn't get V3D core IDENT1: %s\n", strerror(errno)); diff --git a/src/gallium/drivers/vc5/vc5_simulator.c b/src/gallium/drivers/vc5/vc5_simulator.c index 5fbcad346ad..7c6f1ce0a4b 100644 --- a/src/gallium/drivers/vc5/vc5_simulator.c +++ b/src/gallium/drivers/vc5/vc5_simulator.c @@ -360,7 +360,7 @@ vc5_dump_to_file(struct vc5_exec_info *exec) int vc5_simulator_flush(struct vc5_context *vc5, - struct drm_vc5_submit_cl *submit, struct vc5_job *job) + struct drm_v3d_submit_cl *submit, struct vc5_job *job) { struct vc5_screen *screen = vc5->screen; int fd = screen->fd; @@ -469,7 +469,7 @@ void vc5_simulator_open_from_handle(int fd, uint32_t winsys_stride, * Making a VC5 BO is just a matter of making a corresponding BO on the host. */ static int -vc5_simulator_create_bo_ioctl(int fd, struct drm_vc5_create_bo *args) +vc5_simulator_create_bo_ioctl(int fd, struct drm_v3d_create_bo *args) { int ret; struct drm_mode_create_dumb create = { @@ -497,7 +497,7 @@ vc5_simulator_create_bo_ioctl(int fd, struct drm_vc5_create_bo *args) * We just pass this straight through to dumb mmap. */ static int -vc5_simulator_mmap_bo_ioctl(int fd, struct drm_vc5_mmap_bo *args) +vc5_simulator_mmap_bo_ioctl(int fd, struct drm_v3d_mmap_bo *args) { int ret; struct drm_mode_map_dumb map = { @@ -511,7 +511,7 @@ vc5_simulator_mmap_bo_ioctl(int fd, struct drm_vc5_mmap_bo *args) } static int -vc5_simulator_get_bo_offset_ioctl(int fd, struct drm_vc5_get_bo_offset *args) +vc5_simulator_get_bo_offset_ioctl(int fd, struct drm_v3d_get_bo_offset *args) { struct vc5_simulator_file *file = vc5_get_simulator_file_for_fd(fd); struct vc5_simulator_bo *sim_bo = vc5_get_simulator_bo(file, @@ -537,7 +537,7 @@ vc5_simulator_gem_close_ioctl(int fd, struct drm_gem_close *args) } static int -vc5_simulator_get_param_ioctl(int fd, struct drm_vc5_get_param *args) +vc5_simulator_get_param_ioctl(int fd, struct drm_v3d_get_param *args) { if (sim_state.ver >= 41) return v3d41_simulator_get_param_ioctl(sim_state.v3d, args); @@ -549,14 +549,14 @@ int vc5_simulator_ioctl(int fd, unsigned long request, void *args) { switch (request) { - case DRM_IOCTL_VC5_CREATE_BO: + case DRM_IOCTL_V3D_CREATE_BO: return vc5_simulator_create_bo_ioctl(fd, args); - case DRM_IOCTL_VC5_MMAP_BO: + case DRM_IOCTL_V3D_MMAP_BO: return vc5_simulator_mmap_bo_ioctl(fd, args); - case DRM_IOCTL_VC5_GET_BO_OFFSET: + case DRM_IOCTL_V3D_GET_BO_OFFSET: return vc5_simulator_get_bo_offset_ioctl(fd, args); - case DRM_IOCTL_VC5_WAIT_BO: + case DRM_IOCTL_V3D_WAIT_BO: /* We do all of the vc5 rendering synchronously, so we just * return immediately on the wait ioctls. This ignores any * native rendering to the host BO, so it does mean we race on @@ -564,7 +564,7 @@ vc5_simulator_ioctl(int fd, unsigned long request, void *args) */ return 0; - case DRM_IOCTL_VC5_GET_PARAM: + case DRM_IOCTL_V3D_GET_PARAM: return vc5_simulator_get_param_ioctl(fd, args); case DRM_IOCTL_GEM_CLOSE: |