4 files changed, 26 insertions, 10 deletions

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index fdec3f20b0d..cfcb807de31 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -46,6 +46,7 @@
 
 #include "compiler/glsl/standalone.h"
 #include "compiler/glsl/glsl_to_nir.h"
+#include "compiler/nir_types.h"
 
 static void dump_info(struct ir3_shader_variant *so, const char *str)
 {
@@ -57,8 +58,6 @@ static void dump_info(struct ir3_shader_variant *so, const char *str)
 	free(bin);
 }
 
-int st_glsl_type_size(const struct glsl_type *type);
-
 static void
 insert_sorted(struct exec_list *var_list, nir_variable *new_var)
 {
@@ -131,7 +130,7 @@ load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
 	case MESA_SHADER_VERTEX:
 		nir_assign_var_locations(&nir->inputs,
 				&nir->num_inputs,
-				st_glsl_type_size);
+				ir3_glsl_type_size);
 
 		/* Re-lower global vars, to deal with any dead VS inputs. */
 		NIR_PASS_V(nir, nir_lower_global_vars_to_local);
@@ -139,18 +138,18 @@ load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
 		sort_varyings(&nir->outputs);
 		nir_assign_var_locations(&nir->outputs,
 				&nir->num_outputs,
-				st_glsl_type_size);
+				ir3_glsl_type_size);
 		fixup_varying_slots(&nir->outputs);
 		break;
 	case MESA_SHADER_FRAGMENT:
 		sort_varyings(&nir->inputs);
 		nir_assign_var_locations(&nir->inputs,
 				&nir->num_inputs,
-				st_glsl_type_size);
+				ir3_glsl_type_size);
 		fixup_varying_slots(&nir->inputs);
 		nir_assign_var_locations(&nir->outputs,
 				&nir->num_outputs,
-				st_glsl_type_size);
+				ir3_glsl_type_size);
 		break;
 	default:
 		errx(1, "unhandled shader stage: %d", stage);
@@ -158,10 +157,10 @@ load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
 
 	nir_assign_var_locations(&nir->uniforms,
 			&nir->num_uniforms,
-			st_glsl_type_size);
+			ir3_glsl_type_size);
 
 	NIR_PASS_V(nir, nir_lower_system_values);
-	NIR_PASS_V(nir, nir_lower_io, nir_var_all, st_glsl_type_size, 0);
+	NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
 	NIR_PASS_V(nir, nir_lower_samplers, prog);
 
 	return nir;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index a176f16e722..636111b1036 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -41,6 +41,12 @@
 #include "ir3_compiler.h"
 #include "ir3_nir.h"
 
+int
+ir3_glsl_type_size(const struct glsl_type *type)
+{
+	return glsl_count_attribute_slots(type, false);
+}
+
 static void
 delete_variant(struct ir3_shader_variant *v)
 {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 6c2af6d3664..9984809ea24 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -36,6 +36,8 @@
 #include "ir3.h"
 #include "disasm.h"
 
+struct glsl_type;
+
 /* driver param indices: */
 enum ir3_driver_param {
 	/* compute shader driver params: */
@@ -339,6 +341,9 @@ void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer
 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 		struct fd_context *ctx, const struct pipe_grid_info *info);
 
+int
+ir3_glsl_type_size(const struct glsl_type *type);
+
 static inline const char *
 ir3_shader_stage(struct ir3_shader *shader)
 {
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index 60eb68e847b..3beac61f313 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -33,17 +33,23 @@
 #include "tgsi/tgsi_parse.h"
 #include "compiler/nir/nir.h"
 #include "compiler/nir/nir_builder.h"
+#include "compiler/nir_types.h"
 #include "nir/tgsi_to_nir.h"
 #include "vc4_context.h"
 #include "vc4_qpu.h"
 #include "vc4_qir.h"
-#include "mesa/state_tracker/st_glsl_types.h"
 
 static struct qreg
 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
 static void
 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
 
+static int
+type_size(const struct glsl_type *type)
+{
+   return glsl_count_attribute_slots(type, false);
+}
+
 static void
 resize_qreg_array(struct vc4_compile *c,
                   struct qreg **regs,
@@ -1653,7 +1659,7 @@ static void
 ntq_setup_uniforms(struct vc4_compile *c)
 {
         nir_foreach_variable(var, &c->s->uniforms) {
-                uint32_t vec4_count = st_glsl_type_size(var->type);
+                uint32_t vec4_count = type_size(var->type);
                 unsigned vec4_size = 4 * sizeof(float);
 
                 declare_uniform_range(c, var->data.driver_location * vec4_size,