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-rw-r--r--src/gallium/drivers/r600/evergreen_state.c4
-rw-r--r--src/gallium/drivers/r600/r600_state.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index f0fdd2b9770..15727986ea8 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1533,7 +1533,7 @@ static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rsta
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
first_layer = surf->base.u.tex.first_layer;
- format = r600_translate_dbformat(rtex->real_format);
+ format = r600_translate_dbformat(surf->base.format);
offset = r600_resource_va(rctx->context.screen, surf->base.texture);
/* XXX remove this once tiling is properly supported */
@@ -2546,7 +2546,7 @@ void evergreen_polygon_offset_update(struct r600_context *rctx)
float offset_units = rctx->rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
- switch (rctx->framebuffer.zsbuf->texture->format) {
+ switch (rctx->framebuffer.zsbuf->format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index bb72bf80359..3fd77daae7d 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -637,7 +637,7 @@ void r600_polygon_offset_update(struct r600_context *rctx)
float offset_units = rctx->rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
- switch (rctx->framebuffer.zsbuf->texture->format) {
+ switch (rctx->framebuffer.zsbuf->format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
@@ -1611,7 +1611,7 @@ static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
}
}
- format = r600_translate_dbformat(state->zsbuf->texture->format);
+ format = r600_translate_dbformat(state->zsbuf->format);
r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);