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-rw-r--r--src/gallium/drivers/radeon/R600InstrInfo.cpp1
-rw-r--r--src/gallium/drivers/radeon/R600Instructions.td120
2 files changed, 28 insertions, 93 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 14b42044436..e990dd9370b 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -113,7 +113,6 @@ bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
switch (Opcode) {
default: return false;
case AMDGPU::RETURN:
- case AMDGPU::LAST:
case AMDGPU::MASK_WRITE:
case AMDGPU::RESERVE_REG:
return true;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 00c57e62315..519f384cdeb 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -179,10 +179,10 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
bits<1> MARK;
bits<1> BARRIER;
- /* CF_ALLOC_EXPORT_WORD0_RAT */
+ // CF_ALLOC_EXPORT_WORD0_RAT
let Inst{3-0} = rat_id;
let Inst{9-4} = rat_inst;
- let Inst{10} = 0; /* Reserved */
+ let Inst{10} = 0; // Reserved
let Inst{12-11} = RIM;
let Inst{14-13} = TYPE;
let Inst{21-15} = RW_GPR;
@@ -190,7 +190,7 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
let Inst{29-23} = INDEX_GPR;
let Inst{31-30} = ELEM_SIZE;
- /* CF_ALLOC_EXPORT_WORD1_BUF */
+ // CF_ALLOC_EXPORT_WORD1_BUF
let Inst{43-32} = ARRAY_SIZE;
let Inst{47-44} = COMP_MASK;
let Inst{51-48} = BURST_COUNT;
@@ -201,21 +201,6 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
let Inst{63} = BARRIER;
}
-/*
-def store_global : PatFrag<(ops node:$value, node:$ptr),
- (store node:$value, node:$ptr),
- [{
- const Value *Src;
- const PointerType *Type;
- if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
- PT = dyn_cast<PointerType>(Src->getType()))) {
- return PT->getAddressSpace() == 1;
- }
- return false;
- }]>;
-
-*/
-
def load_param : PatFrag<(ops node:$ptr),
(load node:$ptr),
[{
@@ -227,36 +212,6 @@ def load_param : PatFrag<(ops node:$ptr),
return false;
}]>;
-//class EG_CF <bits<32> inst, string asm> :
-// InstR600 <inst, (outs), (ins), asm, []>;
-
-/* XXX: We will use this when we emit the real ISA.
- bits<24> ADDR = 0;
- bits<3> JTS = 0;
-
- bits<3> PC = 0;
- bits<5> CF_CONS = 0;
- bits<2> COND = 0;
- bits<6> COUNT = 0;
- bits<1> VPM = 0;
- bits<1> EOP = 0;
- bits<8> CF_INST = 0;
- bits<1> WQM = 0;
- bits<1> B = 0;
-
- let Inst{23-0} = ADDR;
- let Inst{26-24} = JTS;
- let Inst{34-32} = PC;
- let Inst{39-35} = CF_CONST;
- let Inst{41-40} = COND;
- let Inst{47-42} = COUNT;
- let Inst{52} = VPM;
- let Inst{53} = EOP;
- let Inst{61-54} = CF_INST;
- let Inst{62} = WQM;
- let Inst{63} = B;
-//}
-*/
def isR600 : Predicate<"Subtarget.device()"
"->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
def isR700 : Predicate<"Subtarget.device()"
@@ -279,9 +234,10 @@ def isR600toCayman : Predicate<
let Predicates = [isR600toCayman] in {
-/* ------------------------------------------- */
-/* Common Instructions R600, R700, Evergreen, Cayman */
-/* ------------------------------------------- */
+//===----------------------------------------------------------------------===//
+// Common Instructions R600, R700, Evergreen, Cayman
+//===----------------------------------------------------------------------===//
+
def ADD : R600_2OP <
0x0, "ADD",
[(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
@@ -308,10 +264,9 @@ def MIN : R600_2OP <
[(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
>;
-/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
- * so some of the instruction names don't match the asm string.
- * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
- */
+// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
+// so some of the instruction names don't match the asm string.
+// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
def SETE : R600_2OP <
0x08, "SETE",
@@ -492,8 +447,9 @@ def CNDE_INT : R600_3OP <
(select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
>;
-/* Texture instructions */
-
+//===----------------------------------------------------------------------===//
+// Texture instructions
+//===----------------------------------------------------------------------===//
def TEX_LD : R600_TEX <
0x03, "TEX_LD",
@@ -568,7 +524,9 @@ def TEX_SAMPLE_C_G : R600_TEX <
[]
>;
-/* Helper classes for common instructions */
+//===----------------------------------------------------------------------===//
+// Helper classes for common instructions
+//===----------------------------------------------------------------------===//
class MUL_LIT_Common <bits<32> inst> : R600_3OP <
inst, "MUL_LIT",
@@ -738,8 +696,9 @@ class COS_Common <bits<32> inst> : R600_1OP <
let Trig = 1;
}
-/* Helper patterns for complex intrinsics */
-/* -------------------------------------- */
+//===----------------------------------------------------------------------===//
+// Helper patterns for complex intrinsics
+//===----------------------------------------------------------------------===//
class DIV_Common <InstR600 recip_ieee> : Pat<
(int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
@@ -756,9 +715,9 @@ class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ie
(exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
>;
-/* ---------------------- */
-/* R600 / R700 Only Instructions */
-/* ---------------------- */
+//===----------------------------------------------------------------------===//
+// R600 / R700 Instructions
+//===----------------------------------------------------------------------===//
let Predicates = [isR600] in {
@@ -835,9 +794,9 @@ def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
} // End Predicates = [isEG]
-/* ------------------------------- */
-/* Evergreen / Cayman Instructions */
-/* ------------------------------- */
+//===----------------------------------------------------------------------===//
+// Evergreen / Cayman Instructions
+//===----------------------------------------------------------------------===//
let Predicates = [isEGorCayman] in {
@@ -926,7 +885,7 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
[]>
{
let RIM = 0;
- /* XXX: Have a separate instruction for non-indexed writes. */
+ // XXX: Have a separate instruction for non-indexed writes.
let TYPE = 1;
let RW_REL = 0;
let ELEM_SIZE = 0;
@@ -940,6 +899,7 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
}
} // End usesCustomInserter = 1
+
// i32 global_store
def : Pat <
(global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
@@ -1128,31 +1088,7 @@ def : Pat <
} // End isCayman
-/* Other Instructions */
-
let isCodeGenOnly = 1 in {
-/*
- def SWIZZLE : AMDGPUShaderInst <
- (outs GPRV4F32:$dst),
- (ins GPRV4F32:$src0, i32imm:$src1),
- "SWIZZLE $dst, $src0, $src1",
- [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
- >;
-*/
-
- def LAST : AMDGPUShaderInst <
- (outs),
- (ins),
- "LAST",
- []
- >;
-
- def GET_CHAN : AMDGPUShaderInst <
- (outs R600_Reg32:$dst),
- (ins R600_Reg128:$src0, i32imm:$src1),
- "GET_CHAN $dst, $src0, $src1",
- []
- >;
def MULLIT : AMDGPUShaderInst <
(outs R600_Reg128:$dst),
@@ -1218,7 +1154,7 @@ def MASK_WRITE : AMDGPUShaderInst <
} // End usesCustomInserter = 1
//===---------------------------------------------------------------------===//
-// return instruction
+// Return instruction
//===---------------------------------------------------------------------===//
let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
def RETURN : ILFormat<(outs), (ins variable_ops),
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 07:17:57 +0000