diff options
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 9 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 5 |
2 files changed, 6 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 64fcd50f3a1..1f7cab6b2f3 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -315,6 +315,8 @@ static int si_init_surface(struct si_screen *sscreen, flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE; if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; + if (sscreen->debug_flags & DBG(NO_FMASK)) + flags |= RADEON_SURF_NO_FMASK; if (sscreen->info.chip_class >= GFX10 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) { @@ -1369,9 +1371,7 @@ si_texture_create_object(struct pipe_screen *screen, si_texture_allocate_htile(sscreen, tex); } } else { - if (base->nr_samples > 1 && - !buf && - !(sscreen->debug_flags & DBG(NO_FMASK))) { + if (tex->surface.fmask_size) { /* Allocate FMASK. */ tex->fmask_offset = align64(tex->size, tex->surface.fmask_alignment); @@ -1382,9 +1382,6 @@ si_texture_create_object(struct pipe_screen *screen, tex->size = tex->cmask_offset + tex->surface.cmask_size; tex->cb_color_info |= S_028C70_FAST_CLEAR(1); tex->cmask_buffer = &tex->buffer; - - if (!tex->surface.fmask_size || !tex->surface.cmask_size) - goto error; } /* Shared textures must always set up DCC here. diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index d33c4c7132d..e09805784e0 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -307,7 +307,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws, /* Compute FMASK. */ if (ws->gen == DRV_SI && tex->nr_samples >= 2 && - !(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))) { + !(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK | RADEON_SURF_NO_FMASK))) { /* FMASK is allocated like an ordinary texture. */ struct pipe_resource templ = *tex; struct radeon_surf fmask = {}; @@ -351,7 +351,8 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws, surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; } - if (ws->gen == DRV_SI) { + if (ws->gen == DRV_SI && + (tex->nr_samples <= 1 || surf_ws->fmask_size)) { struct ac_surf_config config; /* Only these fields need to be set for the CMASK computation. */ |