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-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_3d_top.h48
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_3d.h99
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c5
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_3d_top.c832
-rw-r--r--src/gallium/drivers/ilo/ilo_render_dynamic.c16
-rw-r--r--src/gallium/drivers/ilo/ilo_render_surface.c64
-rw-r--r--src/gallium/drivers/ilo/ilo_screen.c2
-rw-r--r--src/gallium/drivers/ilo/ilo_state.c139
-rw-r--r--src/gallium/drivers/ilo/ilo_state.h35
9 files changed, 205 insertions, 1035 deletions
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
index cfa0e441855..cec1043b204 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
+++ b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
@@ -1627,8 +1627,7 @@ gen6_BINDING_TABLE_STATE(struct ilo_builder *builder,
static inline uint32_t
gen6_SURFACE_STATE(struct ilo_builder *builder,
- const struct ilo_view_surface *surf,
- bool for_render)
+ const struct ilo_state_surface *surf)
{
int state_align, state_len;
uint32_t state_offset, *dw;
@@ -1641,7 +1640,7 @@ gen6_SURFACE_STATE(struct ilo_builder *builder,
state_offset = ilo_builder_surface_pointer(builder,
ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->payload, state_len << 2);
+ memcpy(dw, surf->surface, state_len << 2);
if (surf->bo) {
const uint32_t mocs = (surf->scanout) ?
@@ -1650,7 +1649,7 @@ gen6_SURFACE_STATE(struct ilo_builder *builder,
dw[1] |= mocs << GEN8_SURFACE_DW1_MOCS__SHIFT;
ilo_builder_surface_reloc64(builder, state_offset, 8, surf->bo,
- surf->payload[8], (for_render) ? INTEL_RELOC_WRITE : 0);
+ surf->surface[8], (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
}
} else {
state_align = 32;
@@ -1658,7 +1657,7 @@ gen6_SURFACE_STATE(struct ilo_builder *builder,
state_offset = ilo_builder_surface_pointer(builder,
ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->payload, state_len << 2);
+ memcpy(dw, surf->surface, state_len << 2);
if (surf->bo) {
/*
@@ -1668,7 +1667,7 @@ gen6_SURFACE_STATE(struct ilo_builder *builder,
dw[5] |= builder->mocs << GEN6_SURFACE_DW5_MOCS__SHIFT;
ilo_builder_surface_reloc(builder, state_offset, 1, surf->bo,
- surf->payload[1], (for_render) ? INTEL_RELOC_WRITE : 0);
+ surf->surface[1], (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
}
}
@@ -1682,38 +1681,49 @@ gen6_so_SURFACE_STATE(struct ilo_builder *builder,
int so_index)
{
struct ilo_buffer *buf = ilo_buffer(so->buffer);
- unsigned bo_offset, struct_size;
- enum pipe_format elem_format;
- struct ilo_view_surface surf;
+ struct ilo_state_surface_buffer_info info;
+ struct ilo_state_surface surf;
ILO_DEV_ASSERT(builder->dev, 6, 6);
- bo_offset = so->buffer_offset + so_info->output[so_index].dst_offset * 4;
- struct_size = so_info->stride[so_info->output[so_index].output_buffer] * 4;
+ memset(&info, 0, sizeof(info));
+ info.buf = buf;
+ info.access = ILO_STATE_SURFACE_ACCESS_DP_SVB;
switch (so_info->output[so_index].num_components) {
case 1:
- elem_format = PIPE_FORMAT_R32_FLOAT;
+ info.format = GEN6_FORMAT_R32_FLOAT;
+ info.format_size = 4;
break;
case 2:
- elem_format = PIPE_FORMAT_R32G32_FLOAT;
+ info.format = GEN6_FORMAT_R32G32_FLOAT;
+ info.format_size = 8;
break;
case 3:
- elem_format = PIPE_FORMAT_R32G32B32_FLOAT;
+ info.format = GEN6_FORMAT_R32G32B32_FLOAT;
+ info.format_size = 12;
break;
case 4:
- elem_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
+ info.format = GEN6_FORMAT_R32G32B32A32_FLOAT;
+ info.format_size = 16;
break;
default:
assert(!"unexpected SO components length");
- elem_format = PIPE_FORMAT_R32_FLOAT;
+ info.format = GEN6_FORMAT_R32_FLOAT;
+ info.format_size = 4;
break;
}
- ilo_gpe_init_view_surface_for_buffer(builder->dev, buf, bo_offset,
- so->buffer_size, struct_size, elem_format, false, &surf);
+ info.struct_size =
+ so_info->stride[so_info->output[so_index].output_buffer] * 4;
+ info.offset = so->buffer_offset + so_info->output[so_index].dst_offset * 4;
+ info.size = so->buffer_size - so_info->output[so_index].dst_offset * 4;
- return gen6_SURFACE_STATE(builder, &surf, false);
+ memset(&surf, 0, sizeof(surf));
+ ilo_state_surface_init_for_buffer(&surf, builder->dev, &info);
+ surf.bo = info.buf->bo;
+
+ return gen6_SURFACE_STATE(builder, &surf);
}
static inline uint32_t
diff --git a/src/gallium/drivers/ilo/core/ilo_state_3d.h b/src/gallium/drivers/ilo/core/ilo_state_3d.h
index 3c7c50de702..6518c442249 100644
--- a/src/gallium/drivers/ilo/core/ilo_state_3d.h
+++ b/src/gallium/drivers/ilo/core/ilo_state_3d.h
@@ -33,6 +33,7 @@
#include "ilo_core.h"
#include "ilo_dev.h"
+#include "ilo_state_surface.h"
#include "ilo_state_zs.h"
/**
@@ -214,53 +215,12 @@ struct ilo_sampler_state {
const struct ilo_sampler_cso *cso[ILO_MAX_SAMPLERS];
};
-struct ilo_view_surface {
- /* SURFACE_STATE */
- uint32_t payload[13];
- struct intel_bo *bo;
-
- uint32_t scanout;
-};
-
-struct ilo_view_cso {
- struct pipe_sampler_view base;
-
- struct ilo_view_surface surface;
-};
-
-struct ilo_view_state {
- struct pipe_sampler_view *states[ILO_MAX_SAMPLER_VIEWS];
- unsigned count;
-};
-
-struct ilo_cbuf_cso {
- struct pipe_resource *resource;
- struct ilo_view_surface surface;
-
- /*
- * this CSO is not so constant because user buffer needs to be uploaded in
- * finalize_constant_buffers()
- */
- const void *user_buffer;
- unsigned user_buffer_size;
-};
-
-struct ilo_cbuf_state {
- struct ilo_cbuf_cso cso[ILO_MAX_CONST_BUFFERS];
- uint32_t enabled_mask;
-};
-
-struct ilo_resource_state {
- struct pipe_surface *states[PIPE_MAX_SHADER_RESOURCES];
- unsigned count;
-};
-
struct ilo_surface_cso {
struct pipe_surface base;
bool is_rt;
union {
- struct ilo_view_surface rt;
+ struct ilo_state_surface rt;
struct ilo_state_zs zs;
} u;
};
@@ -268,7 +228,7 @@ struct ilo_surface_cso {
struct ilo_fb_state {
struct pipe_framebuffer_state state;
- struct ilo_view_surface null_rt;
+ struct ilo_state_surface null_rt;
struct ilo_state_zs null_zs;
struct ilo_fb_blend_caps {
@@ -285,33 +245,6 @@ struct ilo_shader_cso {
uint32_t payload[5];
};
-/**
- * Translate a pipe texture target to the matching hardware surface type.
- */
-static inline int
-ilo_gpe_gen6_translate_texture(enum pipe_texture_target target)
-{
- switch (target) {
- case PIPE_BUFFER:
- return GEN6_SURFTYPE_BUFFER;
- case PIPE_TEXTURE_1D:
- case PIPE_TEXTURE_1D_ARRAY:
- return GEN6_SURFTYPE_1D;
- case PIPE_TEXTURE_2D:
- case PIPE_TEXTURE_RECT:
- case PIPE_TEXTURE_2D_ARRAY:
- return GEN6_SURFTYPE_2D;
- case PIPE_TEXTURE_3D:
- return GEN6_SURFTYPE_3D;
- case PIPE_TEXTURE_CUBE:
- case PIPE_TEXTURE_CUBE_ARRAY:
- return GEN6_SURFTYPE_CUBE;
- default:
- assert(!"unknown texture target");
- return GEN6_SURFTYPE_BUFFER;
- }
-}
-
void
ilo_gpe_init_ve(const struct ilo_dev *dev,
unsigned num_states,
@@ -363,32 +296,6 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev *dev,
struct ilo_sampler_cso *sampler);
void
-ilo_gpe_init_view_surface_null(const struct ilo_dev *dev,
- unsigned width, unsigned height,
- unsigned depth, unsigned level,
- struct ilo_view_surface *surf);
-
-void
-ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev *dev,
- const struct ilo_buffer *buf,
- unsigned offset, unsigned size,
- unsigned struct_size,
- enum pipe_format elem_format,
- bool is_rt,
- struct ilo_view_surface *surf);
-
-void
-ilo_gpe_init_view_surface_for_image(const struct ilo_dev *dev,
- const struct ilo_image *img,
- enum pipe_format format,
- unsigned first_level,
- unsigned num_levels,
- unsigned first_layer,
- unsigned num_layers,
- bool is_rt,
- struct ilo_view_surface *surf);
-
-void
ilo_gpe_init_vs_cso(const struct ilo_dev *dev,
const struct ilo_shader_state *vs,
struct ilo_shader_cso *cso);
diff --git a/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c b/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
index 0ca5106ca55..31d9a203c5a 100644
--- a/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
+++ b/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
@@ -1799,11 +1799,6 @@ ilo_gpe_set_fb(const struct ilo_dev *dev,
util_copy_framebuffer_state(&fb->state, state);
- ilo_gpe_init_view_surface_null(dev,
- (state->width) ? state->width : 1,
- (state->height) ? state->height : 1,
- 1, 0, &fb->null_rt);
-
for (i = 0; i < state->nr_cbufs; i++) {
if (state->cbufs[i]) {
fb_set_blend_caps(dev, state->cbufs[i]->format, &fb->blend_caps[i]);
diff --git a/src/gallium/drivers/ilo/core/ilo_state_3d_top.c b/src/gallium/drivers/ilo/core/ilo_state_3d_top.c
index 4c06c91da90..8f3133e1345 100644
--- a/src/gallium/drivers/ilo/core/ilo_state_3d_top.c
+++ b/src/gallium/drivers/ilo/core/ilo_state_3d_top.c
@@ -410,838 +410,6 @@ ilo_gpe_init_gs_cso(const struct ilo_dev *dev,
}
static void
-view_init_null_gen6(const struct ilo_dev *dev,
- unsigned width, unsigned height,
- unsigned depth, unsigned level,
- struct ilo_view_surface *surf)
-{
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- assert(width >= 1 && height >= 1 && depth >= 1);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 71:
- *
- * "A null surface will be used in instances where an actual surface is
- * not bound. When a write message is generated to a null surface, no
- * actual surface is written to. When a read message (including any
- * sampling engine message) is generated to a null surface, the result
- * is all zeros. Note that a null surface type is allowed to be used
- * with all messages, even if it is not specificially indicated as
- * supported. All of the remaining fields in surface state are ignored
- * for null surfaces, with the following exceptions:
- *
- * * [DevSNB+]: Width, Height, Depth, and LOD fields must match the
- * depth buffer's corresponding state for all render target
- * surfaces, including null.
- * * Surface Format must be R8G8B8A8_UNORM."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 82:
- *
- * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
- * true"
- */
-
- STATIC_ASSERT(Elements(surf->payload) >= 6);
- dw = surf->payload;
-
- dw[0] = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_B8G8R8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT;
-
- dw[1] = 0;
-
- dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- (width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT |
- level << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
-
- dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- GEN6_TILING_X;
-
- dw[4] = 0;
- dw[5] = 0;
-}
-
-static void
-view_init_for_buffer_gen6(const struct ilo_dev *dev,
- const struct ilo_buffer *buf,
- unsigned offset, unsigned size,
- unsigned struct_size,
- enum pipe_format elem_format,
- bool is_rt, struct ilo_view_surface *surf)
-{
- const int elem_size = util_format_get_blocksize(elem_format);
- int width, height, depth, pitch;
- int surface_format, num_entries;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /*
- * For SURFTYPE_BUFFER, a SURFACE_STATE specifies an element of a
- * structure in a buffer.
- */
-
- surface_format = ilo_format_translate_color(dev, elem_format);
-
- num_entries = size / struct_size;
- /* see if there is enough space to fit another element */
- if (size % struct_size >= elem_size)
- num_entries++;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 76:
- *
- * "For SURFTYPE_BUFFER render targets, this field (Surface Base
- * Address) specifies the base address of first element of the
- * surface. The surface is interpreted as a simple array of that
- * single element type. The address must be naturally-aligned to the
- * element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
- * must be 16-byte aligned).
- *
- * For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
- * the base address of the first element of the surface, computed in
- * software by adding the surface base address to the byte offset of
- * the element in the buffer."
- */
- if (is_rt)
- assert(offset % elem_size == 0);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 77:
- *
- * "For buffer surfaces, the number of entries in the buffer ranges
- * from 1 to 2^27."
- */
- assert(num_entries >= 1 && num_entries <= 1 << 27);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "For surfaces of type SURFTYPE_BUFFER, this field (Surface Pitch)
- * indicates the size of the structure."
- */
- pitch = struct_size;
-
- pitch--;
- num_entries--;
- /* bits [6:0] */
- width = (num_entries & 0x0000007f);
- /* bits [19:7] */
- height = (num_entries & 0x000fff80) >> 7;
- /* bits [26:20] */
- depth = (num_entries & 0x07f00000) >> 20;
-
- STATIC_ASSERT(Elements(surf->payload) >= 6);
- dw = surf->payload;
-
- dw[0] = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
- surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
-
- dw[1] = offset;
-
- dw[2] = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN6_SURFACE_DW2_WIDTH__SHIFT;
-
- dw[3] = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- pitch << GEN6_SURFACE_DW3_PITCH__SHIFT;
-
- dw[4] = 0;
- dw[5] = 0;
-}
-
-static void
-view_init_for_image_gen6(const struct ilo_dev *dev,
- const struct ilo_image *img,
- enum pipe_format format,
- unsigned first_level,
- unsigned num_levels,
- unsigned first_layer,
- unsigned num_layers,
- bool is_rt,
- struct ilo_view_surface *surf)
-{
- int surface_type, surface_format;
- int width, height, depth, pitch, lod;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- surface_type = ilo_gpe_gen6_translate_texture(img->target);
- assert(surface_type != GEN6_SURFTYPE_BUFFER);
-
- if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && img->separate_stencil)
- format = PIPE_FORMAT_Z32_FLOAT;
-
- if (is_rt)
- surface_format = ilo_format_translate_render(dev, format);
- else
- surface_format = ilo_format_translate_texture(dev, format);
- assert(surface_format >= 0);
-
- width = img->width0;
- height = img->height0;
- depth = (img->target == PIPE_TEXTURE_3D) ? img->depth0 : num_layers;
- pitch = img->bo_stride;
-
- if (surface_type == GEN6_SURFTYPE_CUBE) {
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "For SURFTYPE_CUBE: [DevSNB+]: for Sampling Engine Surfaces, the
- * range of this field (Depth) is [0,84], indicating the number of
- * cube array elements (equal to the number of underlying 2D array
- * elements divided by 6). For other surfaces, this field must be
- * zero."
- *
- * When is_rt is true, we treat the texture as a 2D one to avoid the
- * restriction.
- */
- if (is_rt) {
- surface_type = GEN6_SURFTYPE_2D;
- }
- else {
- assert(num_layers % 6 == 0);
- depth = num_layers / 6;
- }
- }
-
- /* sanity check the size */
- assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1);
- switch (surface_type) {
- case GEN6_SURFTYPE_1D:
- assert(width <= 8192 && height == 1 && depth <= 512);
- assert(first_layer < 512 && num_layers <= 512);
- break;
- case GEN6_SURFTYPE_2D:
- assert(width <= 8192 && height <= 8192 && depth <= 512);
- assert(first_layer < 512 && num_layers <= 512);
- break;
- case GEN6_SURFTYPE_3D:
- assert(width <= 2048 && height <= 2048 && depth <= 2048);
- assert(first_layer < 2048 && num_layers <= 512);
- if (!is_rt)
- assert(first_layer == 0);
- break;
- case GEN6_SURFTYPE_CUBE:
- assert(width <= 8192 && height <= 8192 && depth <= 85);
- assert(width == height);
- assert(first_layer < 512 && num_layers <= 512);
- if (is_rt)
- assert(first_layer == 0);
- break;
- default:
- assert(!"unexpected surface type");
- break;
- }
-
- /* non-full array spacing is supported only on GEN7+ */
- assert(img->walk != ILO_IMAGE_WALK_LOD);
- /* non-interleaved samples are supported only on GEN7+ */
- if (img->sample_count > 1)
- assert(img->interleaved_samples);
-
- if (is_rt) {
- assert(num_levels == 1);
- lod = first_level;
- }
- else {
- lod = num_levels - 1;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 76:
- *
- * "Linear render target surface base addresses must be element-size
- * aligned, for non-YUV surface formats, or a multiple of 2
- * element-sizes for YUV surface formats. Other linear surfaces have
- * no alignment requirements (byte alignment is sufficient.)"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "For linear render target surfaces, the pitch must be a multiple
- * of the element size for non-YUV surface formats. Pitch must be a
- * multiple of 2 * element size for YUV surface formats."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 86:
- *
- * "For linear surfaces, this field (X Offset) must be zero"
- */
- if (img->tiling == GEN6_TILING_NONE) {
- if (is_rt) {
- const int elem_size = util_format_get_blocksize(format);
- assert(pitch % elem_size == 0);
- }
- }
-
- STATIC_ASSERT(Elements(surf->payload) >= 6);
- dw = surf->payload;
-
- dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT |
- surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT |
- GEN6_SURFACE_DW0_MIPLAYOUT_BELOW;
-
- if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt) {
- dw[0] |= 1 << 9 |
- GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
- }
-
- dw[1] = 0;
-
- dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- (width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT |
- lod << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
-
- assert(img->tiling != GEN8_TILING_W);
- dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- (pitch - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
- img->tiling;
-
- dw[4] = first_level << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
- first_layer << 17 |
- (num_layers - 1) << 8 |
- ((img->sample_count > 1) ? GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 :
- GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1);
-
- dw[5] = 0;
-
- assert(img->align_j == 2 || img->align_j == 4);
- if (img->align_j == 4)
- dw[5] |= GEN6_SURFACE_DW5_VALIGN_4;
-}
-
-static void
-view_init_null_gen7(const struct ilo_dev *dev,
- unsigned width, unsigned height,
- unsigned depth, unsigned level,
- struct ilo_view_surface *surf)
-{
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- assert(width >= 1 && height >= 1 && depth >= 1);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 62:
- *
- * "A null surface is used in instances where an actual surface is not
- * bound. When a write message is generated to a null surface, no
- * actual surface is written to. When a read message (including any
- * sampling engine message) is generated to a null surface, the result
- * is all zeros. Note that a null surface type is allowed to be used
- * with all messages, even if it is not specificially indicated as
- * supported. All of the remaining fields in surface state are ignored
- * for null surfaces, with the following exceptions:
- *
- * * Width, Height, Depth, LOD, and Render Target View Extent fields
- * must match the depth buffer's corresponding state for all render
- * target surfaces, including null.
- * * All sampling engine and data port messages support null surfaces
- * with the above behavior, even if not mentioned as specifically
- * supported, except for the following:
- * * Data Port Media Block Read/Write messages.
- * * The Surface Type of a surface used as a render target (accessed
- * via the Data Port's Render Target Write message) must be the same
- * as the Surface Type of all other render targets and of the depth
- * buffer (defined in 3DSTATE_DEPTH_BUFFER), unless either the depth
- * buffer or render targets are SURFTYPE_NULL."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 65:
- *
- * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must be
- * true"
- */
-
- STATIC_ASSERT(Elements(surf->payload) >= 13);
- dw = surf->payload;
-
- dw[0] = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_B8G8R8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw[0] |= GEN6_TILING_X << GEN8_SURFACE_DW0_TILING__SHIFT;
- else
- dw[0] |= GEN6_TILING_X << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- dw[1] = 0;
-
- dw[2] = GEN_SHIFT32(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
- GEN_SHIFT32(width - 1, GEN7_SURFACE_DW2_WIDTH);
-
- dw[3] = GEN_SHIFT32(depth - 1, GEN7_SURFACE_DW3_DEPTH);
-
- dw[4] = 0;
- dw[5] = level;
-
- dw[6] = 0;
- dw[7] = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- memset(&dw[8], 0, sizeof(*dw) * (13 - 8));
-}
-
-static void
-view_init_for_buffer_gen7(const struct ilo_dev *dev,
- const struct ilo_buffer *buf,
- unsigned offset, unsigned size,
- unsigned struct_size,
- enum pipe_format elem_format,
- bool is_rt, struct ilo_view_surface *surf)
-{
- const bool typed = (elem_format != PIPE_FORMAT_NONE);
- const bool structured = (!typed && struct_size > 1);
- const int elem_size = (typed) ?
- util_format_get_blocksize(elem_format) : 1;
- int width, height, depth, pitch;
- int surface_type, surface_format, num_entries;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- surface_type = (structured) ? GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
-
- surface_format = (typed) ?
- ilo_format_translate_color(dev, elem_format) : GEN6_FORMAT_RAW;
-
- num_entries = size / struct_size;
- /* see if there is enough space to fit another element */
- if (size % struct_size >= elem_size && !structured)
- num_entries++;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 67:
- *
- * "For SURFTYPE_BUFFER render targets, this field (Surface Base
- * Address) specifies the base address of first element of the
- * surface. The surface is interpreted as a simple array of that
- * single element type. The address must be naturally-aligned to the
- * element size (e.g., a buffer containing R32G32B32A32_FLOAT elements
- * must be 16-byte aligned)
- *
- * For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
- * the base address of the first element of the surface, computed in
- * software by adding the surface base address to the byte offset of
- * the element in the buffer."
- */
- if (is_rt)
- assert(offset % elem_size == 0);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "For typed buffer and structured buffer surfaces, the number of
- * entries in the buffer ranges from 1 to 2^27. For raw buffer
- * surfaces, the number of entries in the buffer is the number of
- * bytes which can range from 1 to 2^30."
- */
- assert(num_entries >= 1 &&
- num_entries <= 1 << ((typed || structured) ? 27 : 30));
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 69:
- *
- * "For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
- * 11 if the Surface Format is RAW (the size of the buffer must be a
- * multiple of 4 bytes)."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 70:
- *
- * "For surfaces of type SURFTYPE_BUFFER and SURFTYPE_STRBUF, this
- * field (Surface Pitch) indicates the size of the structure."
- *
- * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the pitch
- * must be a multiple of 4 bytes."
- */
- if (structured)
- assert(struct_size % 4 == 0);
- else if (!typed)
- assert(num_entries % 4 == 0);
-
- pitch = struct_size;
-
- pitch--;
- num_entries--;
- /* bits [6:0] */
- width = (num_entries & 0x0000007f);
- /* bits [20:7] */
- height = (num_entries & 0x001fff80) >> 7;
- /* bits [30:21] */
- depth = (num_entries & 0x7fe00000) >> 21;
- /* limit to [26:21] */
- if (typed || structured)
- depth &= 0x3f;
-
- STATIC_ASSERT(Elements(surf->payload) >= 13);
- dw = surf->payload;
-
- dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw[8] = offset;
- memset(&dw[9], 0, sizeof(*dw) * (13 - 9));
- } else {
- dw[1] = offset;
- }
-
- dw[2] = GEN_SHIFT32(height, GEN7_SURFACE_DW2_HEIGHT) |
- GEN_SHIFT32(width, GEN7_SURFACE_DW2_WIDTH);
-
- dw[3] = GEN_SHIFT32(depth, GEN7_SURFACE_DW3_DEPTH) |
- pitch;
-
- dw[4] = 0;
- dw[5] = 0;
-
- dw[6] = 0;
- dw[7] = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw[7] |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-}
-
-static void
-view_init_for_image_gen7(const struct ilo_dev *dev,
- const struct ilo_image *img,
- enum pipe_format format,
- unsigned first_level,
- unsigned num_levels,
- unsigned first_layer,
- unsigned num_layers,
- bool is_rt,
- struct ilo_view_surface *surf)
-{
- int surface_type, surface_format;
- int width, height, depth, pitch, lod;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- surface_type = ilo_gpe_gen6_translate_texture(img->target);
- assert(surface_type != GEN6_SURFTYPE_BUFFER);
-
- if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && img->separate_stencil)
- format = PIPE_FORMAT_Z32_FLOAT;
-
- if (is_rt)
- surface_format = ilo_format_translate_render(dev, format);
- else
- surface_format = ilo_format_translate_texture(dev, format);
- assert(surface_format >= 0);
-
- width = img->width0;
- height = img->height0;
- depth = (img->target == PIPE_TEXTURE_3D) ? img->depth0 : num_layers;
- pitch = img->bo_stride;
-
- if (surface_type == GEN6_SURFTYPE_CUBE) {
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 70:
- *
- * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of
- * this field is [0,340], indicating the number of cube array
- * elements (equal to the number of underlying 2D array elements
- * divided by 6). For other surfaces, this field must be zero."
- *
- * When is_rt is true, we treat the texture as a 2D one to avoid the
- * restriction.
- */
- if (is_rt) {
- surface_type = GEN6_SURFTYPE_2D;
- }
- else {
- assert(num_layers % 6 == 0);
- depth = num_layers / 6;
- }
- }
-
- /* sanity check the size */
- assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1);
- assert(first_layer < 2048 && num_layers <= 2048);
- switch (surface_type) {
- case GEN6_SURFTYPE_1D:
- assert(width <= 16384 && height == 1 && depth <= 2048);
- break;
- case GEN6_SURFTYPE_2D:
- assert(width <= 16384 && height <= 16384 && depth <= 2048);
- break;
- case GEN6_SURFTYPE_3D:
- assert(width <= 2048 && height <= 2048 && depth <= 2048);
- if (!is_rt)
- assert(first_layer == 0);
- break;
- case GEN6_SURFTYPE_CUBE:
- assert(width <= 16384 && height <= 16384 && depth <= 86);
- assert(width == height);
- if (is_rt)
- assert(first_layer == 0);
- break;
- default:
- assert(!"unexpected surface type");
- break;
- }
-
- if (is_rt) {
- assert(num_levels == 1);
- lod = first_level;
- }
- else {
- lod = num_levels - 1;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "The Base Address for linear render target surfaces and surfaces
- * accessed with the typed surface read/write data port messages must
- * be element-size aligned, for non-YUV surface formats, or a multiple
- * of 2 element-sizes for YUV surface formats. Other linear surfaces
- * have no alignment requirements (byte alignment is sufficient)."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 70:
- *
- * "For linear render target surfaces and surfaces accessed with the
- * typed data port messages, the pitch must be a multiple of the
- * element size for non-YUV surface formats. Pitch must be a multiple
- * of 2 * element size for YUV surface formats. For linear surfaces
- * with Surface Type of SURFTYPE_STRBUF, the pitch must be a multiple
- * of 4 bytes.For other linear surfaces, the pitch can be any multiple
- * of bytes."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 74:
- *
- * "For linear surfaces, this field (X Offset) must be zero."
- */
- if (img->tiling == GEN6_TILING_NONE) {
- if (is_rt) {
- const int elem_size = util_format_get_blocksize(format);
- assert(pitch % elem_size == 0);
- }
- }
-
- STATIC_ASSERT(Elements(surf->payload) >= 13);
- dw = surf->payload;
-
- dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "If this field (Surface Array) is enabled, the Surface Type must be
- * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
- * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
- * SURFTYPE_CUBE, the Depth field must be set to zero."
- *
- * For non-3D sampler surfaces, resinfo (the sampler message) always
- * returns zero for the number of layers when this field is not set.
- */
- if (surface_type != GEN6_SURFTYPE_3D) {
- switch (img->target) {
- case PIPE_TEXTURE_1D_ARRAY:
- case PIPE_TEXTURE_2D_ARRAY:
- case PIPE_TEXTURE_CUBE_ARRAY:
- dw[0] |= GEN7_SURFACE_DW0_IS_ARRAY;
- break;
- default:
- assert(depth == 1);
- break;
- }
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- switch (img->align_j) {
- case 4:
- dw[0] |= GEN7_SURFACE_DW0_VALIGN_4;
- break;
- case 8:
- dw[0] |= GEN8_SURFACE_DW0_VALIGN_8;
- break;
- case 16:
- dw[0] |= GEN8_SURFACE_DW0_VALIGN_16;
- break;
- default:
- assert(!"unsupported valign");
- break;
- }
-
- switch (img->align_i) {
- case 4:
- dw[0] |= GEN8_SURFACE_DW0_HALIGN_4;
- break;
- case 8:
- dw[0] |= GEN8_SURFACE_DW0_HALIGN_8;
- break;
- case 16:
- dw[0] |= GEN8_SURFACE_DW0_HALIGN_16;
- break;
- default:
- assert(!"unsupported halign");
- break;
- }
-
- dw[0] |= img->tiling << GEN8_SURFACE_DW0_TILING__SHIFT;
- } else {
- assert(img->align_i == 4 || img->align_i == 8);
- assert(img->align_j == 2 || img->align_j == 4);
-
- if (img->align_j == 4)
- dw[0] |= GEN7_SURFACE_DW0_VALIGN_4;
-
- if (img->align_i == 8)
- dw[0] |= GEN7_SURFACE_DW0_HALIGN_8;
-
- assert(img->tiling != GEN8_TILING_W);
- dw[0] |= img->tiling << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- if (img->walk == ILO_IMAGE_WALK_LOD)
- dw[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
- else
- dw[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL;
- }
-
- if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt)
- dw[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- assert(img->walk_layer_height % 4 == 0);
- dw[1] = img->walk_layer_height / 4;
- } else {
- dw[1] = 0;
- }
-
- dw[2] = GEN_SHIFT32(height - 1, GEN7_SURFACE_DW2_HEIGHT) |
- GEN_SHIFT32(width - 1, GEN7_SURFACE_DW2_WIDTH);
-
- dw[3] = GEN_SHIFT32(depth - 1, GEN7_SURFACE_DW3_DEPTH) |
- (pitch - 1);
-
- dw[4] = first_layer << 18 |
- (num_layers - 1) << 7;
-
- /*
- * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
- * means the samples are interleaved. The layouts are the same when the
- * number of samples is 1.
- */
- if (img->interleaved_samples && img->sample_count > 1) {
- assert(!is_rt);
- dw[4] |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL;
- }
- else {
- dw[4] |= GEN7_SURFACE_DW4_MSFMT_MSS;
- }
-
- switch (img->sample_count) {
- case 0:
- case 1:
- default:
- dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
- break;
- case 2:
- dw[4] |= GEN8_SURFACE_DW4_MULTISAMPLECOUNT_2;
- break;
- case 4:
- dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4;
- break;
- case 8:
- dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8;
- break;
- case 16:
- dw[4] |= GEN8_SURFACE_DW4_MULTISAMPLECOUNT_16;
- break;
- }
-
- dw[5] = GEN_SHIFT32(first_level, GEN7_SURFACE_DW5_MIN_LOD) |
- lod;
-
- dw[6] = 0;
- dw[7] = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw[7] |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- memset(&dw[8], 0, sizeof(*dw) * (13 - 8));
-}
-
-void
-ilo_gpe_init_view_surface_null(const struct ilo_dev *dev,
- unsigned width, unsigned height,
- unsigned depth, unsigned level,
- struct ilo_view_surface *surf)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- view_init_null_gen7(dev,
- width, height, depth, level, surf);
- } else {
- view_init_null_gen6(dev,
- width, height, depth, level, surf);
- }
-
- surf->bo = NULL;
- surf->scanout = false;
-}
-
-void
-ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev *dev,
- const struct ilo_buffer *buf,
- unsigned offset, unsigned size,
- unsigned struct_size,
- enum pipe_format elem_format,
- bool is_rt,
- struct ilo_view_surface *surf)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- view_init_for_buffer_gen7(dev, buf, offset, size,
- struct_size, elem_format, is_rt, surf);
- } else {
- view_init_for_buffer_gen6(dev, buf, offset, size,
- struct_size, elem_format, is_rt, surf);
- }
-
- /* do not increment reference count */
- surf->bo = buf->bo;
- surf->scanout = false;
-}
-
-void
-ilo_gpe_init_view_surface_for_image(const struct ilo_dev *dev,
- const struct ilo_image *img,
- enum pipe_format format,
- unsigned first_level,
- unsigned num_levels,
- unsigned first_layer,
- unsigned num_layers,
- bool is_rt,
- struct ilo_view_surface *surf)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- view_init_for_image_gen7(dev, img, format,
- first_level, num_levels, first_layer, num_layers,
- is_rt, surf);
- } else {
- view_init_for_image_gen6(dev, img, format,
- first_level, num_levels, first_layer, num_layers,
- is_rt, surf);
- }
-
- surf->scanout = img->scanout;
- /* do not increment reference count */
- surf->bo = img->bo;
-}
-
-static void
sampler_init_border_color_gen6(const struct ilo_dev *dev,
const union pipe_color_union *color,
uint32_t *dw, int num_dwords)
diff --git a/src/gallium/drivers/ilo/ilo_render_dynamic.c b/src/gallium/drivers/ilo/ilo_render_dynamic.c
index ef92b12da83..a346ebb3201 100644
--- a/src/gallium/drivers/ilo/ilo_render_dynamic.c
+++ b/src/gallium/drivers/ilo/ilo_render_dynamic.c
@@ -234,13 +234,13 @@ gen6_emit_draw_dynamic_pcb(struct ilo_render *r,
const struct ilo_cbuf_state *cbuf =
&vec->cbuf[PIPE_SHADER_VERTEX];
- if (cbuf0_size <= cbuf->cso[0].user_buffer_size) {
+ if (cbuf0_size <= cbuf->cso[0].info.size) {
memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
} else {
memcpy(pcb, cbuf->cso[0].user_buffer,
- cbuf->cso[0].user_buffer_size);
- memset(pcb + cbuf->cso[0].user_buffer_size, 0,
- cbuf0_size - cbuf->cso[0].user_buffer_size);
+ cbuf->cso[0].info.size);
+ memset(pcb + cbuf->cso[0].info.size, 0,
+ cbuf0_size - cbuf->cso[0].info.size);
}
pcb += cbuf0_size;
@@ -271,13 +271,13 @@ gen6_emit_draw_dynamic_pcb(struct ilo_render *r,
gen6_push_constant_buffer(r->builder, cbuf0_size, &pcb);
r->state.wm.PUSH_CONSTANT_BUFFER_size = cbuf0_size;
- if (cbuf0_size <= cbuf->cso[0].user_buffer_size) {
+ if (cbuf0_size <= cbuf->cso[0].info.size) {
memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
} else {
memcpy(pcb, cbuf->cso[0].user_buffer,
- cbuf->cso[0].user_buffer_size);
- memset(pcb + cbuf->cso[0].user_buffer_size, 0,
- cbuf0_size - cbuf->cso[0].user_buffer_size);
+ cbuf->cso[0].info.size);
+ memset(pcb + cbuf->cso[0].info.size, 0,
+ cbuf0_size - cbuf->cso[0].info.size);
}
session->pcb_fs_changed = true;
diff --git a/src/gallium/drivers/ilo/ilo_render_surface.c b/src/gallium/drivers/ilo/ilo_render_surface.c
index 52b1cb42c06..729cb604eaf 100644
--- a/src/gallium/drivers/ilo/ilo_render_surface.c
+++ b/src/gallium/drivers/ilo/ilo_render_surface.c
@@ -64,11 +64,9 @@ gen6_emit_draw_surface_rt(struct ilo_render *r,
(const struct ilo_surface_cso *) fb->state.cbufs[i];
assert(surface->is_rt);
- surface_state[i] =
- gen6_SURFACE_STATE(r->builder, &surface->u.rt, true);
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &surface->u.rt);
} else {
- surface_state[i] =
- gen6_SURFACE_STATE(r->builder, &fb->null_rt, true);
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &fb->null_rt);
}
}
}
@@ -173,8 +171,7 @@ gen6_emit_draw_surface_view(struct ilo_render *r,
const struct ilo_view_cso *cso =
(const struct ilo_view_cso *) view->states[i];
- surface_state[i] =
- gen6_SURFACE_STATE(r->builder, &cso->surface, false);
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
} else {
surface_state[i] = 0;
}
@@ -228,12 +225,10 @@ gen6_emit_draw_surface_const(struct ilo_render *r,
for (i = 0; i < count; i++) {
const struct ilo_cbuf_cso *cso = &cbuf->cso[i];
- if (cso->resource) {
- surface_state[i] = gen6_SURFACE_STATE(r->builder,
- &cso->surface, false);
- } else {
+ if (cso->resource)
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
+ else
surface_state[i] = 0;
- }
}
}
@@ -406,8 +401,7 @@ gen6_emit_launch_grid_surface_view(struct ilo_render *r,
const struct ilo_view_cso *cso =
(const struct ilo_view_cso *) view->states[i];
- surface_state[i] =
- gen6_SURFACE_STATE(r->builder, &cso->surface, false);
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
} else {
surface_state[i] = 0;
}
@@ -421,7 +415,8 @@ gen6_emit_launch_grid_surface_const(struct ilo_render *r,
{
const struct ilo_shader_state *cs = vec->cs;
uint32_t *surface_state = r->state.cs.SURFACE_STATE;
- struct ilo_view_surface view;
+ struct ilo_state_surface_buffer_info info;
+ struct ilo_state_surface surf;
int base, count;
ILO_DEV_ASSERT(r->dev, 7, 7.5);
@@ -432,15 +427,22 @@ gen6_emit_launch_grid_surface_const(struct ilo_render *r,
if (!count)
return;
- ilo_gpe_init_view_surface_for_buffer(r->dev,
- ilo_buffer(session->input->buffer),
- session->input->buffer_offset,
- session->input->buffer_size,
- 1, PIPE_FORMAT_NONE,
- false, &view);
+ memset(&info, 0, sizeof(info));
+ info.buf = ilo_buffer(session->input->buffer);
+ info.access = ILO_STATE_SURFACE_ACCESS_DP_UNTYPED;
+ info.format = GEN6_FORMAT_RAW;
+ info.format_size = 1;
+ info.struct_size = 1;
+ info.readonly = true;
+ info.offset = session->input->buffer_offset;
+ info.size = session->input->buffer_size;
+
+ memset(&surf, 0, sizeof(surf));
+ ilo_state_surface_init_for_buffer(&surf, r->dev, &info);
+ surf.bo = info.buf->bo;
assert(count == 1 && session->input->buffer);
- surface_state[base] = gen6_SURFACE_STATE(r->builder, &view, false);
+ surface_state[base] = gen6_SURFACE_STATE(r->builder, &surf);
}
static void
@@ -483,14 +485,24 @@ gen6_emit_launch_grid_surface_global(struct ilo_render *r,
for (i = 0; i < count; i++) {
if (i < vec->global_binding.count && bindings[i].resource) {
const struct ilo_buffer *buf = ilo_buffer(bindings[i].resource);
- struct ilo_view_surface view;
+ struct ilo_state_surface_buffer_info info;
+ struct ilo_state_surface surf;
assert(bindings[i].resource->target == PIPE_BUFFER);
- ilo_gpe_init_view_surface_for_buffer(r->dev, buf, 0, buf->bo_size,
- 1, PIPE_FORMAT_NONE, true, &view);
- surface_state[i] =
- gen6_SURFACE_STATE(r->builder, &view, true);
+ memset(&info, 0, sizeof(info));
+ info.buf = buf;
+ info.access = ILO_STATE_SURFACE_ACCESS_DP_UNTYPED;
+ info.format = GEN6_FORMAT_RAW;
+ info.format_size = 1;
+ info.struct_size = 1;
+ info.size = buf->bo_size;
+
+ memset(&surf, 0, sizeof(surf));
+ ilo_state_surface_init_for_buffer(&surf, r->dev, &info);
+ surf.bo = info.buf->bo;
+
+ surface_state[i] = gen6_SURFACE_STATE(r->builder, &surf);
} else {
surface_state[i] = 0;
}
diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
index 80e01c7bd1d..b75a2590b2b 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -345,7 +345,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_FUNC:
return true;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
+ return (ilo_dev_gen(&is->dev) >= ILO_GEN(7.5)) ? 2048 : 512;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
diff --git a/src/gallium/drivers/ilo/ilo_state.c b/src/gallium/drivers/ilo/ilo_state.c
index 4e298254ce8..060f8ae4453 100644
--- a/src/gallium/drivers/ilo/ilo_state.c
+++ b/src/gallium/drivers/ilo/ilo_state.c
@@ -25,9 +25,11 @@
* Chia-I Wu <[email protected]>
*/
+#include "core/ilo_format.h"
#include "core/ilo_state_3d.h"
#include "util/u_dynarray.h"
#include "util/u_helpers.h"
+#include "util/u_resource.h"
#include "util/u_upload_mgr.h"
#include "ilo_context.h"
@@ -97,7 +99,6 @@ finalize_cbuf_state(struct ilo_context *ilo,
~ilo_shader_get_kernel_param(sh, ILO_KERNEL_SKIP_CBUF0_UPLOAD);
while (upload_mask) {
- const enum pipe_format elem_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
unsigned offset, i;
i = u_bit_scan(&upload_mask);
@@ -105,14 +106,16 @@ finalize_cbuf_state(struct ilo_context *ilo,
if (cbuf->cso[i].resource)
continue;
- u_upload_data(ilo->uploader, 0, cbuf->cso[i].user_buffer_size,
+ u_upload_data(ilo->uploader, 0, cbuf->cso[i].info.size,
cbuf->cso[i].user_buffer, &offset, &cbuf->cso[i].resource);
- ilo_gpe_init_view_surface_for_buffer(ilo->dev,
- ilo_buffer(cbuf->cso[i].resource),
- offset, cbuf->cso[i].user_buffer_size,
- util_format_get_blocksize(elem_format), elem_format,
- false, &cbuf->cso[i].surface);
+ cbuf->cso[i].info.buf = ilo_buffer(cbuf->cso[i].resource);
+ cbuf->cso[i].info.offset = offset;
+
+ memset(&cbuf->cso[i].surface, 0, sizeof(cbuf->cso[i].surface));
+ ilo_state_surface_init_for_buffer(&cbuf->cso[i].surface,
+ ilo->dev, &cbuf->cso[i].info);
+ cbuf->cso[i].surface.bo = cbuf->cso[i].info.buf->bo;
ilo->state_vector.dirty |= ILO_DIRTY_CBUF;
}
@@ -675,47 +678,47 @@ ilo_set_constant_buffer(struct pipe_context *pipe,
pipe_resource_reference(&cso->resource, buf[i].buffer);
+ cso->info.access = ILO_STATE_SURFACE_ACCESS_DP_DATA;
+ cso->info.format = GEN6_FORMAT_R32G32B32A32_FLOAT;
+ cso->info.format_size = 16;
+ cso->info.struct_size = 16;
+ cso->info.readonly = true;
+ cso->info.size = buf[i].buffer_size;
+
if (buf[i].buffer) {
- const enum pipe_format elem_format =
- PIPE_FORMAT_R32G32B32A32_FLOAT;
+ cso->info.buf = ilo_buffer(buf[i].buffer);
+ cso->info.offset = buf[i].buffer_offset;
- ilo_gpe_init_view_surface_for_buffer(dev,
- ilo_buffer(buf[i].buffer),
- buf[i].buffer_offset, buf[i].buffer_size,
- util_format_get_blocksize(elem_format), elem_format,
- false, &cso->surface);
+ memset(&cso->surface, 0, sizeof(cso->surface));
+ ilo_state_surface_init_for_buffer(&cso->surface, dev, &cso->info);
+ cso->surface.bo = cso->info.buf->bo;
cso->user_buffer = NULL;
- cso->user_buffer_size = 0;
cbuf->enabled_mask |= 1 << (index + i);
- }
- else if (buf[i].user_buffer) {
- cso->surface.bo = NULL;
-
+ } else if (buf[i].user_buffer) {
+ cso->info.buf = NULL;
/* buffer_offset does not apply for user buffer */
cso->user_buffer = buf[i].user_buffer;
- cso->user_buffer_size = buf[i].buffer_size;
cbuf->enabled_mask |= 1 << (index + i);
- }
- else {
- cso->surface.bo = NULL;
+ } else {
+ cso->info.buf = NULL;
+ cso->info.size = 0;
cso->user_buffer = NULL;
- cso->user_buffer_size = 0;
cbuf->enabled_mask &= ~(1 << (index + i));
}
}
- }
- else {
+ } else {
for (i = 0; i < count; i++) {
struct ilo_cbuf_cso *cso = &cbuf->cso[index + i];
pipe_resource_reference(&cso->resource, NULL);
- cso->surface.bo = NULL;
+
+ cso->info.buf = NULL;
+ cso->info.size = 0;
cso->user_buffer = NULL;
- cso->user_buffer_size = 0;
cbuf->enabled_mask &= ~(1 << (index + i));
}
@@ -991,7 +994,7 @@ ilo_create_sampler_view(struct pipe_context *pipe,
const struct ilo_dev *dev = ilo_context(pipe)->dev;
struct ilo_view_cso *view;
- view = MALLOC_STRUCT(ilo_view_cso);
+ view = CALLOC_STRUCT(ilo_view_cso);
assert(view);
view->base = *templ;
@@ -1001,16 +1004,24 @@ ilo_create_sampler_view(struct pipe_context *pipe,
view->base.context = pipe;
if (res->target == PIPE_BUFFER) {
- const unsigned elem_size = util_format_get_blocksize(templ->format);
- const unsigned first_elem = templ->u.buf.first_element;
- const unsigned num_elems = templ->u.buf.last_element - first_elem + 1;
+ struct ilo_state_surface_buffer_info info;
- ilo_gpe_init_view_surface_for_buffer(dev, ilo_buffer(res),
- first_elem * elem_size, num_elems * elem_size,
- elem_size, templ->format, false, &view->surface);
- }
- else {
+ memset(&info, 0, sizeof(info));
+ info.buf = ilo_buffer(res);
+ info.access = ILO_STATE_SURFACE_ACCESS_SAMPLER;
+ info.format = ilo_format_translate_color(dev, templ->format);
+ info.format_size = util_format_get_blocksize(templ->format);
+ info.struct_size = info.format_size;
+ info.readonly = true;
+ info.offset = templ->u.buf.first_element * info.struct_size;
+ info.size = (templ->u.buf.last_element -
+ templ->u.buf.first_element + 1) * info.struct_size;
+
+ ilo_state_surface_init_for_buffer(&view->surface, dev, &info);
+ view->surface.bo = info.buf->bo;
+ } else {
struct ilo_texture *tex = ilo_texture(res);
+ struct ilo_state_surface_image_info info;
/* warn about degraded performance because of a missing binding flag */
if (tex->image.tiling == GEN6_TILING_NONE &&
@@ -1019,12 +1030,33 @@ ilo_create_sampler_view(struct pipe_context *pipe,
"not created for sampling\n");
}
- ilo_gpe_init_view_surface_for_image(dev, &tex->image, templ->format,
- templ->u.tex.first_level,
- templ->u.tex.last_level - templ->u.tex.first_level + 1,
- templ->u.tex.first_layer,
- templ->u.tex.last_layer - templ->u.tex.first_layer + 1,
- false, &view->surface);
+ memset(&info, 0, sizeof(info));
+ info.img = &tex->image;
+
+ info.access = ILO_STATE_SURFACE_ACCESS_SAMPLER;
+
+ if (templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
+ tex->image.separate_stencil) {
+ info.format = ilo_format_translate_texture(dev,
+ PIPE_FORMAT_Z32_FLOAT);
+ } else {
+ info.format = ilo_format_translate_texture(dev, templ->format);
+ }
+
+ info.is_cube_map = (tex->image.target == PIPE_TEXTURE_CUBE ||
+ tex->image.target == PIPE_TEXTURE_CUBE_ARRAY);
+ info.is_array = util_resource_is_array_texture(&tex->base);
+ info.readonly = true;
+
+ info.level_base = templ->u.tex.first_level;
+ info.level_count = templ->u.tex.last_level -
+ templ->u.tex.first_level + 1;
+ info.slice_base = templ->u.tex.first_layer;
+ info.slice_count = templ->u.tex.last_layer -
+ templ->u.tex.first_layer + 1;
+
+ ilo_state_surface_init_for_image(&view->surface, dev, &info);
+ view->surface.bo = info.img->bo;
}
return &view->base;
@@ -1062,14 +1094,24 @@ ilo_create_surface(struct pipe_context *pipe,
surf->is_rt = !util_format_is_depth_or_stencil(templ->format);
if (surf->is_rt) {
+ struct ilo_state_surface_image_info info;
+
/* relax this? */
assert(tex->base.target != PIPE_BUFFER);
- ilo_gpe_init_view_surface_for_image(dev, &tex->image,
- templ->format, templ->u.tex.level, 1,
- templ->u.tex.first_layer,
- templ->u.tex.last_layer - templ->u.tex.first_layer + 1,
- true, &surf->u.rt);
+ memset(&info, 0, sizeof(info));
+ info.img = &tex->image;
+ info.access = ILO_STATE_SURFACE_ACCESS_DP_RENDER;
+ info.format = ilo_format_translate_render(dev, templ->format);
+ info.is_array = util_resource_is_array_texture(&tex->base);
+ info.level_base = templ->u.tex.level;
+ info.level_count = 1;
+ info.slice_base = templ->u.tex.first_layer;
+ info.slice_count = templ->u.tex.last_layer -
+ templ->u.tex.first_layer + 1;
+
+ ilo_state_surface_init_for_image(&surf->u.rt, dev, &info);
+ surf->u.rt.bo = info.img->bo;
} else {
struct ilo_state_zs_info info;
@@ -1313,6 +1355,7 @@ ilo_state_vector_init(const struct ilo_dev *dev,
{
ilo_gpe_set_scissor_null(dev, &vec->scissor);
+ ilo_state_surface_init_for_null(&vec->fb.null_rt, dev);
ilo_state_zs_init_for_null(&vec->fb.null_zs, dev);
util_dynarray_init(&vec->global_binding.bindings);
diff --git a/src/gallium/drivers/ilo/ilo_state.h b/src/gallium/drivers/ilo/ilo_state.h
index fd0a3156ebc..9a7d196a2a6 100644
--- a/src/gallium/drivers/ilo/ilo_state.h
+++ b/src/gallium/drivers/ilo/ilo_state.h
@@ -29,6 +29,8 @@
#define ILO_STATE_H
#include "core/ilo_state_3d.h"
+#include "core/ilo_state_surface.h"
+#include "core/ilo_state_zs.h"
#include "pipe/p_state.h"
#include "util/u_dynarray.h"
@@ -121,6 +123,39 @@ enum ilo_dirty_flags {
struct ilo_context;
+struct ilo_cbuf_cso {
+ struct pipe_resource *resource;
+ struct ilo_state_surface_buffer_info info;
+ struct ilo_state_surface surface;
+
+ /*
+ * this CSO is not so constant because user buffer needs to be uploaded in
+ * finalize_constant_buffers()
+ */
+ const void *user_buffer;
+};
+
+struct ilo_cbuf_state {
+ struct ilo_cbuf_cso cso[ILO_MAX_CONST_BUFFERS];
+ uint32_t enabled_mask;
+};
+
+struct ilo_resource_state {
+ struct pipe_surface *states[PIPE_MAX_SHADER_RESOURCES];
+ unsigned count;
+};
+
+struct ilo_view_cso {
+ struct pipe_sampler_view base;
+
+ struct ilo_state_surface surface;
+};
+
+struct ilo_view_state {
+ struct pipe_sampler_view *states[ILO_MAX_SAMPLER_VIEWS];
+ unsigned count;
+};
+
struct ilo_global_binding_cso {
struct pipe_resource *resource;
uint32_t *handle;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 22:18:51 +0000