diff options
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600d.h | 3 |
3 files changed, 12 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index fc54ae7606a..6f277906f59 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1381,7 +1381,10 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, } log_samples = util_logbase2(rctx->framebuffer.nr_samples); - if (rctx->b.chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) { + /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */ + if ((rctx->b.chip_class == CAYMAN || + rctx->b.family == CHIP_RV770) && + rctx->db_misc_state.log_samples != log_samples) { rctx->db_misc_state.log_samples = log_samples; rctx->db_misc_state.atom.dirty = true; } diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 99cfe6f8e66..ffcceacfb81 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1615,6 +1615,11 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1); } + /* RV770 workaround for a hang with 8x MSAA. */ + if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) { + db_render_override |= S_028D10_MAX_TILES_IN_DTT(6); + } + r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index f787803a53e..1684429ba20 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -818,6 +818,9 @@ #define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) #define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) #define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define S_028D10_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) +#define G_028D10_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) +#define C_028D10_MAX_TILES_IN_DTT 0xFC1FFFFF #define R_02880C_DB_SHADER_CONTROL 0x02880C #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) |