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-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.c5
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c1
2 files changed, 4 insertions, 2 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 92d5394b121..d9a95c05093 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -800,10 +800,11 @@ static void amdgpu_set_ib_size(struct amdgpu_ib *ib)
}
}
-static void amdgpu_ib_finalize(struct amdgpu_ib *ib)
+static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
{
amdgpu_set_ib_size(ib);
ib->used_ib_space += ib->base.current.cdw * 4;
+ ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_start_alignment);
ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw);
}
@@ -1561,7 +1562,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
struct amdgpu_cs_context *cur = cs->csc;
/* Set IB sizes. */
- amdgpu_ib_finalize(&cs->main);
+ amdgpu_ib_finalize(ws, &cs->main);
/* Create a fence. */
amdgpu_fence_reference(&cur->fence, NULL);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 85a186af978..036e9861f5f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -527,6 +527,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+ ws->info.ib_start_alignment = 4096;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;