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-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.c8
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_cs.c11
2 files changed, 10 insertions, 9 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 84fc40b923d..9a89ba85a29 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -409,7 +409,7 @@ static unsigned amdgpu_add_reloc(struct amdgpu_cs *cs,
unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
int i = -1;
- priority = MIN2(priority, 15);
+ assert(priority < 64);
*added_domains = 0;
i = amdgpu_get_reloc(cs, bo);
@@ -419,7 +419,7 @@ static unsigned amdgpu_add_reloc(struct amdgpu_cs *cs,
reloc->usage |= usage;
*added_domains = domains & ~reloc->domains;
reloc->domains |= domains;
- cs->flags[i] = MAX2(cs->flags[i], priority);
+ cs->flags[i] = MAX2(cs->flags[i], priority / 4);
return i;
}
@@ -441,7 +441,7 @@ static unsigned amdgpu_add_reloc(struct amdgpu_cs *cs,
cs->buffers[cs->num_buffers].bo = NULL;
amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
cs->handles[cs->num_buffers] = bo->bo;
- cs->flags[cs->num_buffers] = priority;
+ cs->flags[cs->num_buffers] = priority / 4;
p_atomic_inc(&bo->num_cs_references);
reloc = &cs->buffers[cs->num_buffers];
reloc->bo = bo;
@@ -622,7 +622,7 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
}
amdgpu_cs_add_reloc(rcs, (void*)cs->big_ib_winsys_buffer,
- RADEON_USAGE_READ, 0, RADEON_PRIO_MIN);
+ RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
/* If the CS is not empty or overflowed.... */
if (cs->base.cdw && cs->base.cdw <= cs->base.max_dw && !debug_get_option_noop()) {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 2c4f990944c..b277efecf61 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -263,14 +263,14 @@ static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
int i = -1;
- priority = MIN2(priority, 15);
+ assert(priority < 64);
*added_domains = 0;
i = radeon_get_reloc(csc, bo);
if (i >= 0) {
reloc = &csc->relocs[i];
- update_reloc(reloc, rd, wd, priority, added_domains);
+ update_reloc(reloc, rd, wd, priority / 4, added_domains);
/* For async DMA, every add_reloc call must add a buffer to the list
* no matter how many duplicates there are. This is due to the fact
@@ -309,7 +309,7 @@ static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
reloc->handle = bo->handle;
reloc->read_domains = rd;
reloc->write_domain = wd;
- reloc->flags = priority;
+ reloc->flags = priority / 4;
csc->reloc_indices_hashlist[hash] = csc->crelocs;
@@ -328,7 +328,8 @@ static unsigned radeon_drm_cs_add_reloc(struct radeon_winsys_cs *rcs,
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_bo *bo = (struct radeon_bo*)buf;
enum radeon_bo_domain added_domains;
- unsigned index = radeon_add_reloc(cs, bo, usage, domains, priority, &added_domains);
+ unsigned index = radeon_add_reloc(cs, bo, usage, domains, priority,
+ &added_domains);
if (added_domains & RADEON_DOMAIN_GTT)
cs->csc->used_gart += bo->base.size;
@@ -633,7 +634,7 @@ radeon_cs_create_fence(struct radeon_winsys_cs *rcs)
/* Add the fence as a dummy relocation. */
cs->ws->base.cs_add_reloc(rcs, cs->ws->base.buffer_get_cs_handle(fence),
RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,
- RADEON_PRIO_MIN);
+ RADEON_PRIO_FENCE);
return (struct pipe_fence_handle*)fence;
}