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-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_cs.c29
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_cs.h5
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c14
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.h1
4 files changed, 43 insertions, 6 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 7de748a4aff..566f132bdd5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -73,14 +73,32 @@ static void radeon_fence_reference(struct pipe_fence_handle **dst,
static struct radeon_winsys_ctx *radeon_drm_ctx_create(struct radeon_winsys *ws)
{
- /* No context support here. Just return the winsys pointer
- * as the "context". */
- return (struct radeon_winsys_ctx*)ws;
+ struct radeon_ctx *ctx = CALLOC_STRUCT(radeon_ctx);
+ if (!ctx)
+ return NULL;
+
+ ctx->ws = (struct radeon_drm_winsys*)ws;
+ ctx->gpu_reset_counter = radeon_drm_get_gpu_reset_counter(ctx->ws);
+ return (struct radeon_winsys_ctx*)ctx;
}
static void radeon_drm_ctx_destroy(struct radeon_winsys_ctx *ctx)
{
- /* No context support here. */
+ FREE(ctx);
+}
+
+static enum pipe_reset_status
+radeon_drm_ctx_query_reset_status(struct radeon_winsys_ctx *rctx)
+{
+ struct radeon_ctx *ctx = (struct radeon_ctx*)rctx;
+
+ unsigned latest = radeon_drm_get_gpu_reset_counter(ctx->ws);
+
+ if (ctx->gpu_reset_counter == latest)
+ return PIPE_NO_RESET;
+
+ ctx->gpu_reset_counter = latest;
+ return PIPE_UNKNOWN_CONTEXT_RESET;
}
static bool radeon_init_cs_context(struct radeon_cs_context *csc,
@@ -153,7 +171,7 @@ radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
void *flush_ctx,
bool stop_exec_on_failure)
{
- struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)ctx;
+ struct radeon_drm_winsys *ws = ((struct radeon_ctx*)ctx)->ws;
struct radeon_drm_cs *cs;
cs = CALLOC_STRUCT(radeon_drm_cs);
@@ -820,6 +838,7 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.ctx_create = radeon_drm_ctx_create;
ws->base.ctx_destroy = radeon_drm_ctx_destroy;
+ ws->base.ctx_query_reset_status = radeon_drm_ctx_query_reset_status;
ws->base.cs_create = radeon_drm_cs_create;
ws->base.cs_destroy = radeon_drm_cs_destroy;
ws->base.cs_add_buffer = radeon_drm_cs_add_buffer;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index f4c6cbe1fa7..4fa007afa00 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -29,6 +29,11 @@
#include "radeon_drm_bo.h"
+struct radeon_ctx {
+ struct radeon_drm_winsys *ws;
+ uint32_t gpu_reset_counter;
+};
+
struct radeon_bo_item {
struct radeon_bo *bo;
union {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 225cc01a33d..4cfbbbf8501 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -572,7 +572,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.drm_minor >= 38;
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
- ws->info.has_gpu_reset_status_query = false;
+ ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
@@ -656,6 +656,18 @@ static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
return false;
}
+uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
+{
+ uint64_t retval = 0;
+
+ if (!ws->info.has_gpu_reset_status_query)
+ return 0;
+
+ radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
+ "gpu-reset-counter", (uint32_t*)&retval);
+ return retval;
+}
+
static uint64_t radeon_query_value(struct radeon_winsys *rws,
enum radeon_value_id value)
{
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index 03d96ea4c10..3ebe1d7708c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -109,6 +109,7 @@ radeon_drm_winsys(struct radeon_winsys *base)
return (struct radeon_drm_winsys*)base;
}
+uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws);
void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
#endif