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-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_bo.c1
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_bo.c8
2 files changed, 0 insertions, 9 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 0ed9529a449..6a79e388311 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -420,7 +420,6 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
}
static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_winsys_cs *rcs,
struct radeon_bo_metadata *md)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index ce91af4486f..cd769f7ade9 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -671,21 +671,13 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
}
static void radeon_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_winsys_cs *rcs,
struct radeon_bo_metadata *md)
{
struct radeon_bo *bo = radeon_bo(_buf);
- struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct drm_radeon_gem_set_tiling args;
memset(&args, 0, sizeof(args));
- /* Tiling determines how DRM treats the buffer data.
- * We must flush CS when changing it if the buffer is referenced. */
- if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
- cs->flush_cs(cs->flush_data, 0, NULL);
- }
-
os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
if (md->microtile == RADEON_LAYOUT_TILED)