2 files changed, 11 insertions, 9 deletions

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 8c57287f073..deae4dd3a1f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -191,7 +191,6 @@ static int compute_level(struct amdgpu_winsys *ws,
    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
    surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
-   surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
    surf_level->nblk_x = AddrSurfInfoOut->pitch;
    surf_level->nblk_y = AddrSurfInfoOut->height;
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index fed96ee88eb..95ec0eb8742 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -67,25 +67,27 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
 }
 
 static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
-                                     const struct radeon_surf_level *level_ws)
+                                     const struct radeon_surf_level *level_ws,
+                                     unsigned bpe)
 {
     level_drm->offset = level_ws->offset;
     level_drm->slice_size = level_ws->slice_size;
     level_drm->nblk_x = level_ws->nblk_x;
     level_drm->nblk_y = level_ws->nblk_y;
-    level_drm->pitch_bytes = level_ws->pitch_bytes;
+    level_drm->pitch_bytes = level_ws->nblk_x * bpe;
     level_drm->mode = level_ws->mode;
 }
 
 static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
-                                     const struct radeon_surface_level *level_drm)
+                                     const struct radeon_surface_level *level_drm,
+                                     unsigned bpe)
 {
     level_ws->offset = level_drm->offset;
     level_ws->slice_size = level_drm->slice_size;
     level_ws->nblk_x = level_drm->nblk_x;
     level_ws->nblk_y = level_drm->nblk_y;
-    level_ws->pitch_bytes = level_drm->pitch_bytes;
     level_ws->mode = level_drm->mode;
+    assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
 }
 
 static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
@@ -156,9 +158,9 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
     surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
 
     for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
-        surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
+        surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i], bpe);
         surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
-                                 &surf_ws->stencil_level[i]);
+                                 &surf_ws->stencil_level[i], bpe);
 
         surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
         surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
@@ -190,9 +192,10 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
     surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
 
     for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
-        surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
+        surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
+                                 surf_drm->bpe * surf_drm->nsamples);
         surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
-                                 &surf_drm->stencil_level[i]);
+                                 &surf_drm->stencil_level[i], surf_drm->nsamples);
 
         surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
         surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];