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-rw-r--r--src/gallium/winsys/r600/drm/r600_state.c36
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h25
-rw-r--r--src/gallium/winsys/r600/drm/r600d.h1
-rw-r--r--src/gallium/winsys/r600/drm/radeon_ctx.c36
4 files changed, 88 insertions, 10 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 2facec75dec..9b7c11bdc06 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -38,6 +38,8 @@ static int r600_state_pm4_shader(struct radeon_state *state);
static int r600_state_pm4_draw(struct radeon_state *state);
static int r600_state_pm4_config(struct radeon_state *state);
static int r600_state_pm4_generic(struct radeon_state *state);
+static int r600_state_pm4_query_begin(struct radeon_state *state);
+static int r600_state_pm4_query_end(struct radeon_state *state);
static int r700_state_pm4_config(struct radeon_state *state);
static int r700_state_pm4_cb0(struct radeon_state *state);
static int r700_state_pm4_db(struct radeon_state *state);
@@ -240,6 +242,40 @@ static int r600_state_pm4_config(struct radeon_state *state)
return r600_state_pm4_generic(state);
}
+static int r600_state_pm4_query_begin(struct radeon_state *state)
+{
+ int r;
+
+ state->cpm4 = 0;
+ state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+ state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+ state->pm4[state->cpm4++] = state->states[0];
+ state->pm4[state->cpm4++] = 0x0;
+ state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+ r = radeon_state_reloc(state, state->cpm4, 0);
+ if (r)
+ return r;
+ state->pm4[state->cpm4++] = state->bo[0]->handle;
+ return 0;
+}
+
+static int r600_state_pm4_query_end(struct radeon_state *state)
+{
+ int r;
+
+ state->cpm4 = 0;
+ state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+ state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+ state->pm4[state->cpm4++] = state->states[0];
+ state->pm4[state->cpm4++] = 0x0;
+ state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+ r = radeon_state_reloc(state, state->cpm4, 0);
+ if (r)
+ return r;
+ state->pm4[state->cpm4++] = state->bo[0]->handle;
+ return 0;
+}
+
static int r700_state_pm4_config(struct radeon_state *state)
{
state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 2d7a1d31c8c..b5365e4275a 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -479,6 +479,10 @@ static const struct radeon_register R600_DRAW_names[] = {
{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
};
+static const struct radeon_register R600_VGT_EVENT_names[] = {
+ {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
+};
+
static struct radeon_type R600_types[] = {
{ 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
{ 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
@@ -509,11 +513,12 @@ static struct radeon_type R600_types[] = {
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
- { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
- { 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
- { 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-
+ { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+ { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+ { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+ { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+ { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+ { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
static struct radeon_type R700_types[] = {
@@ -546,10 +551,12 @@ static struct radeon_type R700_types[] = {
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
- { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
- { 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
- { 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
- { 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+ { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+ { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+ { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+ { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+ { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+ { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
#endif
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 235b2b3d976..e8c2dc0651c 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -82,6 +82,7 @@
#define PKT3_SET_CTL_CONST 0x6F
#define PKT3_SURFACE_BASE_UPDATE 0x73
+#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 45b706bb0f9..bd050c4cf90 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -224,6 +224,41 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
return 0;
}
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
+{
+ void *tmp;
+ int r = 0;
+
+ /* !!! ONLY ACCEPT QUERY STATE HERE !!! */
+ if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+ return -EINVAL;
+ }
+ r = radeon_state_pm4(state);
+ if (r)
+ return r;
+ if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
+ /* need to flush */
+ return -EBUSY;
+ }
+ if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
+ fprintf(stderr, "%s single state too big %d, max %d\n",
+ __func__, state->cpm4, RADEON_CTX_MAX_PM4);
+ return -EINVAL;
+ }
+ tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
+ if (tmp == NULL)
+ return -ENOMEM;
+ ctx->state = tmp;
+ ctx->state[ctx->nstate++] = radeon_state_incref(state);
+ /* BEGIN/END query are balanced in the same cs so account for END
+ * END query when scheduling BEGIN query
+ */
+ if (state->type == R600_QUERY_BEGIN_TYPE) {
+ ctx->draw_cpm4 += state->cpm4 * 2;
+ }
+ return 0;
+}
+
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
{
struct radeon_draw *pdraw = NULL;
@@ -366,7 +401,6 @@ printf("%d pm4\n", ctx->cpm4);
if (bo == NULL)
goto out_err;
size = bof_int32(ctx->bo[i]->size);
-printf("[%d] %d bo\n", i, size);
if (size == NULL)
goto out_err;
if (bof_object_set(bo, "size", size))
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 14:29:45 +0000