3 files changed, 31 insertions, 7 deletions

diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c
index 7d54ff18fc2..9b9aec5f64c 100644
--- a/src/gallium/winsys/r600/drm/r600_bo.c
+++ b/src/gallium/winsys/r600/drm/r600_bo.c
@@ -29,23 +29,37 @@
 #include "radeon_drm.h"
 #include "r600_priv.h"
 #include "r600d.h"
+#include "radeon_drm.h"
 
 struct r600_bo *r600_bo(struct radeon *radeon,
-				  unsigned size, unsigned alignment, unsigned usage)
+			unsigned size, unsigned alignment,
+			unsigned binding, unsigned usage)
 {
 	struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
 	struct pb_desc desc;
 	struct pb_manager *man;
 
 	desc.alignment = alignment;
-	desc.usage = usage;
+	desc.usage = (PB_USAGE_CPU_READ_WRITE | PB_USAGE_GPU_READ_WRITE);
 	ws_bo->size = size;
 
-	if (usage & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
+	if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
 		man = radeon->cman;
 	else
 		man = radeon->kman;
 
+	/* Staging resources particpate in transfers and blits only
+	 * and are used for uploads and downloads from regular
+	 * resources.  We generate them internally for some transfers.
+	 */
+	if (usage == PIPE_USAGE_STAGING)
+                ws_bo->domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT;
+        else
+                ws_bo->domains = (RADEON_GEM_DOMAIN_CPU |
+                                  RADEON_GEM_DOMAIN_GTT |
+                                  RADEON_GEM_DOMAIN_VRAM);
+
+
 	ws_bo->pb = man->create_buffer(man, size, &desc);
 	if (ws_bo->pb == NULL) {
 		free(ws_bo);
@@ -69,6 +83,10 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon,
 	}
 	bo = radeon_bo_pb_get_bo(ws_bo->pb);
 	ws_bo->size = bo->size;
+	ws_bo->domains = (RADEON_GEM_DOMAIN_CPU |
+			  RADEON_GEM_DOMAIN_GTT |
+			  RADEON_GEM_DOMAIN_VRAM);
+
 	pipe_reference_init(&ws_bo->reference, 1);
 
 	radeon_bo_get_tiling_flags(radeon, bo, &ws_bo->tiling_flags,
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 82d5deaad28..8b4521b86cd 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -44,7 +44,7 @@
 int r600_context_init_fence(struct r600_context *ctx)
 {
 	ctx->fence = 1;
-	ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0);
+	ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
 	if (ctx->fence_bo == NULL) {
 		return -ENOMEM;
 	}
@@ -787,8 +787,8 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r
 	bo->reloc = &ctx->reloc[ctx->creloc];
 	bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
 	ctx->reloc[ctx->creloc].handle = bo->handle;
-	ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
-	ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
+	ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
+	ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
 	ctx->reloc[ctx->creloc].flags = 0;
 	radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
 	ctx->creloc++;
@@ -1306,7 +1306,12 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned
 	query->type = query_type;
 	query->buffer_size = 4096;
 
-	query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0);
+	/* As of GL4, query buffers are normally read by the CPU after
+	 * being written by the gpu, hence staging is probably a good
+	 * usage pattern.
+	 */
+	query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
+				PIPE_USAGE_STAGING);
 	if (!query->buffer) {
 		free(query);
 		return NULL;
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index efecfebc2b1..97c582397a7 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -79,6 +79,7 @@ struct r600_bo {
 	unsigned			size;
 	unsigned			tiling_flags;
 	unsigned                        kernel_pitch;
+	unsigned			domains;
 };