diff options
Diffstat (limited to 'src/gallium/winsys/r600/drm')
| -rw-r--r-- | src/gallium/winsys/r600/drm/Makefile | 4 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/SConscript | 2 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/evergreen_hw_context.c | 23 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600.c | 13 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_bo.c | 171 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_bomgr.c | 161 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_drm.c | 33 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_hw_context.c | 60 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_priv.h | 124 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600d.h | 10 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/radeon_bo_pb.c | 287 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/radeon_pciid.c | 76 |
12 files changed, 458 insertions, 506 deletions
diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile index a396205f897..91c65012c83 100644 --- a/src/gallium/winsys/r600/drm/Makefile +++ b/src/gallium/winsys/r600/drm/Makefile @@ -8,12 +8,12 @@ C_SOURCES = \ bof.c \ evergreen_hw_context.c \ radeon_bo.c \ - radeon_bo_pb.c \ radeon_pciid.c \ r600.c \ r600_bo.c \ r600_drm.c \ - r600_hw_context.c + r600_hw_context.c \ + r600_bomgr.c LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \ $(shell pkg-config libdrm --cflags-only-I) diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript index cc053c06dd0..dac0097f144 100644 --- a/src/gallium/winsys/r600/drm/SConscript +++ b/src/gallium/winsys/r600/drm/SConscript @@ -6,12 +6,12 @@ r600_sources = [ 'bof.c', 'evergreen_hw_context.c', 'radeon_bo.c', - 'radeon_bo_pb.c', 'radeon_pciid.c', 'r600.c', 'r600_bo.c', 'r600_drm.c', 'r600_hw_context.c', + 'r600_bomgr.c', ] env.ParseConfig('pkg-config --cflags libdrm_radeon') diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c index 7f21b53ace0..2175d578ec7 100644 --- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -36,7 +36,6 @@ #include "pipe/p_compiler.h" #include "util/u_inlines.h" #include "util/u_memory.h" -#include <pipebuffer/pb_bufmgr.h> #include "r600_priv.h" #define GROUP_FORCE_NEW_BLOCK 0 @@ -577,6 +576,12 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) if (r) goto out_err; } + /* FS RESOURCE */ + for (int j = 0, offset = 0x7C00; j < 16; j++, offset += 0x20) { + r = evergreen_state_resource_init(ctx, offset); + if (r) + goto out_err; + } /* PS loop const */ evergreen_loop_const_init(ctx, 0); @@ -686,6 +691,13 @@ void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, stru evergreen_context_pipe_state_set_resource(ctx, state, offset); } +void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x7C00 + 0x20 * rid; + + evergreen_context_pipe_state_set_resource(ctx, state, offset); +} + static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) { struct r600_range *range; @@ -842,7 +854,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; } ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); /* flush color buffer */ for (int i = 0; i < 12; i++) { @@ -917,3 +929,10 @@ void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state evergreen_resource_set(ctx, state, offset); } + +void evergreen_fs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_RESOURCE0_WORD0 + 0x7C00 + 0x20 * rid; + + evergreen_resource_set(ctx, state, offset); +} diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c index 0a4d2e791db..b88733f80f1 100644 --- a/src/gallium/winsys/r600/drm/r600.c +++ b/src/gallium/winsys/r600/drm/r600.c @@ -27,7 +27,6 @@ #include "radeon_drm.h" #include "pipe/p_compiler.h" #include "util/u_inlines.h" -#include <pipebuffer/pb_bufmgr.h> #include "r600_priv.h" enum radeon_family r600_get_family(struct radeon *r600) @@ -93,6 +92,12 @@ struct radeon *r600_new(int fd, unsigned device) case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + case CHIP_PALM: break; case CHIP_R100: case CHIP_RV100: @@ -121,11 +126,6 @@ struct radeon *r600_new(int fd, unsigned device) case CHIP_RV560: case CHIP_RV570: case CHIP_R580: - case CHIP_CEDAR: - case CHIP_REDWOOD: - case CHIP_JUNIPER: - case CHIP_CYPRESS: - case CHIP_HEMLOCK: default: R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device); break; @@ -154,6 +154,7 @@ struct radeon *r600_new(int fd, unsigned device) case CHIP_JUNIPER: case CHIP_CYPRESS: case CHIP_HEMLOCK: + case CHIP_PALM: r600->chip_class = EVERGREEN; break; default: diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c index 251f009a6b0..6a3737f0a4a 100644 --- a/src/gallium/winsys/r600/drm/r600_bo.c +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -36,142 +36,153 @@ struct r600_bo *r600_bo(struct radeon *radeon, unsigned size, unsigned alignment, unsigned binding, unsigned usage) { - struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); - struct pb_desc desc; - struct pb_manager *man; + struct r600_bo *bo; + struct radeon_bo *rbo; - desc.alignment = alignment; - desc.usage = (PB_USAGE_CPU_READ_WRITE | PB_USAGE_GPU_READ_WRITE); - ws_bo->size = size; + if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) { + bo = r600_bomgr_bo_create(radeon->bomgr, size, alignment, *radeon->cfence); + if (bo) { + return bo; + } + } - if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) - man = radeon->cman; - else - man = radeon->kman; + rbo = radeon_bo(radeon, 0, size, alignment); + if (rbo == NULL) { + return NULL; + } + + bo = calloc(1, sizeof(struct r600_bo)); + bo->size = size; + bo->alignment = alignment; + bo->bo = rbo; + if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) { + r600_bomgr_bo_init(radeon->bomgr, bo); + } /* Staging resources particpate in transfers and blits only * and are used for uploads and downloads from regular * resources. We generate them internally for some transfers. */ if (usage == PIPE_USAGE_STAGING) - ws_bo->domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT; - else - ws_bo->domains = (RADEON_GEM_DOMAIN_CPU | - RADEON_GEM_DOMAIN_GTT | - RADEON_GEM_DOMAIN_VRAM); - - - ws_bo->pb = man->create_buffer(man, size, &desc); - if (ws_bo->pb == NULL) { - free(ws_bo); - return NULL; - } + bo->domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT; + else + bo->domains = (RADEON_GEM_DOMAIN_CPU | + RADEON_GEM_DOMAIN_GTT | + RADEON_GEM_DOMAIN_VRAM); - pipe_reference_init(&ws_bo->reference, 1); - return ws_bo; + pipe_reference_init(&bo->reference, 1); + return bo; } struct r600_bo *r600_bo_handle(struct radeon *radeon, unsigned handle, unsigned *array_mode) { - struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); - struct radeon_bo *bo; + struct r600_bo *bo = calloc(1, sizeof(struct r600_bo)); + struct radeon_bo *rbo; - ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle); - if (!ws_bo->pb) { - free(ws_bo); + rbo = bo->bo = radeon_bo(radeon, handle, 0, 0); + if (rbo == NULL) { + free(bo); return NULL; } - bo = radeon_bo_pb_get_bo(ws_bo->pb); - ws_bo->size = bo->size; - ws_bo->domains = (RADEON_GEM_DOMAIN_CPU | - RADEON_GEM_DOMAIN_GTT | - RADEON_GEM_DOMAIN_VRAM); + bo->size = rbo->size; + bo->domains = (RADEON_GEM_DOMAIN_CPU | + RADEON_GEM_DOMAIN_GTT | + RADEON_GEM_DOMAIN_VRAM); - pipe_reference_init(&ws_bo->reference, 1); + pipe_reference_init(&bo->reference, 1); - radeon_bo_get_tiling_flags(radeon, bo, &ws_bo->tiling_flags, - &ws_bo->kernel_pitch); + radeon_bo_get_tiling_flags(radeon, rbo, &bo->tiling_flags, &bo->kernel_pitch); if (array_mode) { - if (ws_bo->tiling_flags) { - if (ws_bo->tiling_flags & RADEON_TILING_MICRO) + if (bo->tiling_flags) { + if (bo->tiling_flags & RADEON_TILING_MICRO) *array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; - if ((ws_bo->tiling_flags & (RADEON_TILING_MICRO | RADEON_TILING_MACRO)) == + if ((bo->tiling_flags & (RADEON_TILING_MICRO | RADEON_TILING_MACRO)) == (RADEON_TILING_MICRO | RADEON_TILING_MACRO)) *array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; } else { *array_mode = 0; } } - return ws_bo; + return bo; } void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx) { - return pb_map(bo->pb, usage, ctx); + struct pipe_context *pctx = ctx; + + if (usage & PB_USAGE_UNSYNCHRONIZED) { + radeon_bo_map(radeon, bo->bo); + return (uint8_t *) bo->bo->data + bo->offset; + } + + if (p_atomic_read(&bo->bo->reference.count) > 1) { + if (usage & PB_USAGE_DONTBLOCK) { + return NULL; + } + if (ctx) { + pctx->flush(pctx, 0, NULL); + } + } + + if (usage & PB_USAGE_DONTBLOCK) { + uint32_t domain; + + if (radeon_bo_busy(radeon, bo->bo, &domain)) + return NULL; + if (radeon_bo_map(radeon, bo->bo)) { + return NULL; + } + goto out; + } + + radeon_bo_map(radeon, bo->bo); + if (radeon_bo_wait(radeon, bo->bo)) { + radeon_bo_unmap(radeon, bo->bo); + return NULL; + } + +out: + return (uint8_t *) bo->bo->data + bo->offset; } void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo) { - pb_unmap(bo->pb); + radeon_bo_unmap(radeon, bo->bo); } -static void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo) +void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo) { - if (bo->pb) - pb_reference(&bo->pb, NULL); + if (bo->manager_id) { + if (!r600_bomgr_bo_destroy(radeon->bomgr, bo)) { + /* destroy is delayed by buffer manager */ + return; + } + } + radeon_bo_reference(radeon, &bo->bo, NULL); free(bo); } -void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, - struct r600_bo *src) +void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src) { struct r600_bo *old = *dst; - + if (pipe_reference(&(*dst)->reference, &src->reference)) { r600_bo_destroy(radeon, old); } *dst = src; } -unsigned r600_bo_get_handle(struct r600_bo *pb_bo) -{ - struct radeon_bo *bo; - - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return 0; - - return bo->handle; -} - -unsigned r600_bo_get_size(struct r600_bo *pb_bo) -{ - struct radeon_bo *bo; - - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return 0; - - return bo->size; -} - -boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo, +boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *bo, unsigned stride, struct winsys_handle *whandle) { - struct radeon_bo *bo; - - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return FALSE; - whandle->stride = stride; switch(whandle->type) { case DRM_API_HANDLE_TYPE_KMS: - whandle->handle = r600_bo_get_handle(pb_bo); + whandle->handle = r600_bo_get_handle(bo); break; case DRM_API_HANDLE_TYPE_SHARED: - if (radeon_bo_get_name(radeon, bo, &whandle->handle)) + if (radeon_bo_get_name(radeon, bo->bo, &whandle->handle)) return FALSE; break; default: diff --git a/src/gallium/winsys/r600/drm/r600_bomgr.c b/src/gallium/winsys/r600/drm/r600_bomgr.c new file mode 100644 index 00000000000..446ef0f9cfc --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_bomgr.c @@ -0,0 +1,161 @@ +/* + * Copyright 2010 VMWare. + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jose Fonseca <jrfonseca-at-vmware-dot-com> + * Thomas Hellström <thomas-at-vmware-dot-com> + * Jerome Glisse <[email protected]> + */ +#include <util/u_memory.h> +#include <util/u_double_list.h> +#include <util/u_time.h> +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +static void r600_bomgr_timeout_flush(struct r600_bomgr *mgr) +{ + struct r600_bo *bo, *tmp; + int64_t now; + + now = os_time_get(); + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &mgr->delayed, list) { + if(!os_time_timeout(bo->start, bo->end, now)) + break; + + mgr->num_delayed--; + bo->manager_id = 0; + LIST_DEL(&bo->list); + r600_bo_destroy(mgr->radeon, bo); + } +} + +static INLINE int r600_bo_is_compat(struct r600_bomgr *mgr, + struct r600_bo *bo, + unsigned size, + unsigned alignment, + unsigned cfence) +{ + if(bo->size < size) { + return 0; + } + + /* be lenient with size */ + if(bo->size >= 2*size) { + return 0; + } + + if(!pb_check_alignment(alignment, bo->alignment)) { + return 0; + } + + if (!fence_is_after(cfence, bo->fence)) { + return 0; + } + + return 1; +} + +struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr, + unsigned size, + unsigned alignment, + unsigned cfence) +{ + struct r600_bo *bo, *tmp; + int64_t now; + + + pipe_mutex_lock(mgr->mutex); + + now = os_time_get(); + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &mgr->delayed, list) { + if(r600_bo_is_compat(mgr, bo, size, alignment, cfence)) { + LIST_DEL(&bo->list); + --mgr->num_delayed; + r600_bomgr_timeout_flush(mgr); + pipe_mutex_unlock(mgr->mutex); + LIST_INITHEAD(&bo->list); + pipe_reference_init(&bo->reference, 1); + return bo; + } + + if(os_time_timeout(bo->start, bo->end, now)) { + mgr->num_delayed--; + bo->manager_id = 0; + LIST_DEL(&bo->list); + r600_bo_destroy(mgr->radeon, bo); + } + } + + pipe_mutex_unlock(mgr->mutex); + return NULL; +} + +void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo) +{ + LIST_INITHEAD(&bo->list); + bo->manager_id = 1; +} + +bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo) +{ + bo->start = os_time_get(); + bo->end = bo->start + mgr->usecs; + pipe_mutex_lock(mgr->mutex); + LIST_ADDTAIL(&bo->list, &mgr->delayed); + ++mgr->num_delayed; + pipe_mutex_unlock(mgr->mutex); + return FALSE; +} + +void r600_bomgr_destroy(struct r600_bomgr *mgr) +{ + struct r600_bo *bo, *tmp; + + pipe_mutex_lock(mgr->mutex); + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &mgr->delayed, list) { + mgr->num_delayed--; + bo->manager_id = 0; + LIST_DEL(&bo->list); + r600_bo_destroy(mgr->radeon, bo); + } + pipe_mutex_unlock(mgr->mutex); + + FREE(mgr); +} + +struct r600_bomgr *r600_bomgr_create(struct radeon *radeon, unsigned usecs) +{ + struct r600_bomgr *mgr; + + mgr = CALLOC_STRUCT(r600_bomgr); + if (mgr == NULL) + return NULL; + + mgr->radeon = radeon; + mgr->usecs = usecs; + LIST_INITHEAD(&mgr->delayed); + mgr->num_delayed = 0; + pipe_mutex_init(mgr->mutex); + + return mgr; +} diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c index 60c2f51fac0..3cbbf91878d 100644 --- a/src/gallium/winsys/r600/drm/r600_drm.c +++ b/src/gallium/winsys/r600/drm/r600_drm.c @@ -30,7 +30,6 @@ #include <sys/ioctl.h> #include "util/u_inlines.h" #include "util/u_debug.h" -#include <pipebuffer/pb_bufmgr.h> #include "r600.h" #include "r600_priv.h" #include "r600_drm_public.h" @@ -40,6 +39,9 @@ #ifndef RADEON_INFO_TILING_CONFIG #define RADEON_INFO_TILING_CONFIG 0x6 #endif + +static struct radeon *radeon_new(int fd, unsigned device); + static int radeon_get_device(struct radeon *radeon) { struct drm_radeon_info info; @@ -108,7 +110,7 @@ static int radeon_drm_get_tiling(struct radeon *radeon) return 0; } -struct radeon *radeon_new(int fd, unsigned device) +static struct radeon *radeon_new(int fd, unsigned device) { struct radeon *radeon; int r; @@ -150,6 +152,7 @@ struct radeon *radeon_new(int fd, unsigned device) case CHIP_JUNIPER: case CHIP_CYPRESS: case CHIP_HEMLOCK: + case CHIP_PALM: break; case CHIP_R100: case CHIP_RV100: @@ -195,19 +198,26 @@ struct radeon *radeon_new(int fd, unsigned device) case CHIP_RS780: case CHIP_RS880: radeon->chip_class = R600; + /* set default group bytes, overridden by tiling info ioctl */ + radeon->tiling_info.group_bytes = 256; break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: radeon->chip_class = R700; + /* set default group bytes, overridden by tiling info ioctl */ + radeon->tiling_info.group_bytes = 256; break; case CHIP_CEDAR: case CHIP_REDWOOD: case CHIP_JUNIPER: case CHIP_CYPRESS: case CHIP_HEMLOCK: + case CHIP_PALM: radeon->chip_class = EVERGREEN; + /* set default group bytes, overridden by tiling info ioctl */ + radeon->tiling_info.group_bytes = 512; break; default: fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", @@ -219,12 +229,10 @@ struct radeon *radeon_new(int fd, unsigned device) if (radeon_drm_get_tiling(radeon)) return NULL; } - radeon->kman = radeon_bo_pbmgr_create(radeon); - if (!radeon->kman) - return NULL; - radeon->cman = pb_cache_manager_create(radeon->kman, 100000); - if (!radeon->cman) + radeon->bomgr = r600_bomgr_create(radeon, 1000000); + if (radeon->bomgr == NULL) { return NULL; + } return radeon; } @@ -241,14 +249,11 @@ struct radeon *radeon_decref(struct radeon *radeon) return NULL; } - if (radeon->cman) - radeon->cman->destroy(radeon->cman); - - if (radeon->kman) - radeon->kman->destroy(radeon->kman); + if (radeon->bomgr) + r600_bomgr_destroy(radeon->bomgr); - if (radeon->fd >= 0) - drmClose(radeon->fd); + if (radeon->fd >= 0) + drmClose(radeon->fd); free(radeon); return NULL; diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 37e5baf8de8..d01ec3ee9b0 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -28,16 +28,15 @@ #include <string.h> #include <stdlib.h> #include <assert.h> +#include <pipe/p_compiler.h> +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include <pipebuffer/pb_bufmgr.h> #include "xf86drm.h" -#include "r600.h" -#include "r600d.h" #include "radeon_drm.h" -#include "bof.h" -#include "pipe/p_compiler.h" -#include "util/u_inlines.h" -#include "util/u_memory.h" -#include <pipebuffer/pb_bufmgr.h> #include "r600_priv.h" +#include "bof.h" +#include "r600d.h" #define GROUP_FORCE_NEW_BLOCK 0 @@ -50,6 +49,7 @@ int r600_context_init_fence(struct r600_context *ctx) } ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL); *ctx->cfence = 0; + ctx->radeon->cfence = ctx->cfence; LIST_INITHEAD(&ctx->fenced_bo); return 0; } @@ -593,6 +593,17 @@ static int r600_loop_const_init(struct r600_context *ctx, u32 offset) return r600_context_add_block(ctx, r600_loop_consts, nreg); } +static void r600_context_clear_fenced_bo(struct r600_context *ctx) +{ + struct radeon_bo *bo, *tmp; + + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + bo->ctx = NULL; + } +} + /* initialize */ void r600_context_fini(struct r600_context *ctx) { @@ -607,6 +618,9 @@ void r600_context_fini(struct r600_context *ctx) range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL; } + for (int k = 1; k <= block->nbo; k++) { + r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL); + } free(block); } } @@ -616,6 +630,8 @@ void r600_context_fini(struct r600_context *ctx) free(ctx->reloc); free(ctx->bo); free(ctx->pm4); + + r600_context_clear_fenced_bo(ctx); if (ctx->fence_bo) { r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL); } @@ -693,6 +709,12 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon) if (r) goto out_err; } + /* FS RESOURCE */ + for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) { + r = r600_state_resource_init(ctx, offset); + if (r) + goto out_err; + } /* PS loop const */ r600_loop_const_init(ctx, 0); @@ -792,6 +814,7 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM); ctx->reloc[ctx->creloc].flags = 0; radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo); + rbo->fence = ctx->fence; ctx->creloc++; /* set PKT3 to point to proper reloc */ *pm4 = bo->reloc_id; @@ -814,6 +837,7 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat /* find relocation */ id = block->pm4_bo_index[id]; r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo); + state->regs[i].bo->fence = ctx->fence; } if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { block->status |= R600_BLOCK_STATUS_ENABLED; @@ -853,10 +877,13 @@ static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx */ r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + state->regs[0].bo->fence = ctx->fence; } else { /* TEXTURE RESOURCE */ r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + state->regs[2].bo->fence = ctx->fence; + state->regs[3].bo->fence = ctx->fence; } if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { block->status |= R600_BLOCK_STATUS_ENABLED; @@ -880,6 +907,13 @@ void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r6 r600_context_pipe_state_set_resource(ctx, state, offset); } +void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid; + + r600_context_pipe_state_set_resource(ctx, state, offset); +} + static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) { struct r600_range *range; @@ -1049,7 +1083,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; } ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); /* flush color buffer */ for (int i = 0; i < 8; i++) { @@ -1082,11 +1116,11 @@ void r600_context_flush(struct r600_context *ctx) /* suspend queries */ r600_context_queries_suspend(ctx); - radeon_bo_pbmgr_flush_maps(ctx->radeon->kman); - /* emit fence */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT | (5 << 8); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); ctx->pm4[ctx->pm4_cdwords++] = ctx->fence; @@ -1266,7 +1300,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) /* emit begin query */ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); @@ -1282,7 +1316,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query) { /* emit begin query */ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h index 9fd77b71c77..056d0255be2 100644 --- a/src/gallium/winsys/r600/drm/r600_priv.h +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -30,24 +30,24 @@ #include <stdint.h> #include <stdlib.h> #include <assert.h> -#include <pipebuffer/pb_bufmgr.h> -#include "util/u_double_list.h" +#include <util/u_double_list.h> +#include <util/u_inlines.h> +#include <os/os_thread.h> #include "r600.h" +struct r600_bomgr; + struct radeon { int fd; int refcount; unsigned device; unsigned family; enum chip_class chip_class; - struct pb_manager *kman; /* kernel bo manager */ - struct pb_manager *cman; /* cached bo manager */ - struct r600_tiling_info tiling_info; + struct r600_tiling_info tiling_info; + struct r600_bomgr *bomgr; + unsigned *cfence; }; -struct radeon *r600_new(int fd, unsigned device); -void r600_delete(struct radeon *r600); - struct r600_reg { unsigned opcode; unsigned offset_base; @@ -75,28 +75,49 @@ struct radeon_bo { struct r600_bo { struct pipe_reference reference; - struct pb_buffer *pb; unsigned size; unsigned tiling_flags; - unsigned kernel_pitch; + unsigned kernel_pitch; unsigned domains; + struct radeon_bo *bo; + unsigned fence; + /* manager data */ + struct list_head list; + unsigned manager_id; + unsigned alignment; + unsigned offset; + int64_t start; + int64_t end; }; +struct r600_bomgr { + struct radeon *radeon; + unsigned usecs; + pipe_mutex mutex; + struct list_head delayed; + unsigned num_delayed; +}; -/* radeon_pciid.c */ -unsigned radeon_family_from_device(unsigned device); +/* + * r600_drm.c + */ +struct radeon *r600_new(int fd, unsigned device); +void r600_delete(struct radeon *r600); -/* r600_drm.c */ -struct radeon *radeon_decref(struct radeon *radeon); +/* + * radeon_pciid.c + */ +unsigned radeon_family_from_device(unsigned device); -/* radeon_bo.c */ +/* + * radeon_bo.c + */ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, unsigned size, unsigned alignment); void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst, struct radeon_bo *src); int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain); -void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr); int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo); int radeon_bo_get_tiling_flags(struct radeon *radeon, struct radeon_bo *bo, @@ -106,13 +127,9 @@ int radeon_bo_get_name(struct radeon *radeon, struct radeon_bo *bo, uint32_t *name); -/* radeon_bo_pb.c */ -struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf); -struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon); -struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, - uint32_t handle); - -/* r600_hw_context.c */ +/* + * r600_hw_context.c + */ int r600_context_init_fence(struct r600_context *ctx); void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo); void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, @@ -120,14 +137,27 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg); -/* r600_bo.c */ -unsigned r600_bo_get_handle(struct r600_bo *bo); -unsigned r600_bo_get_size(struct r600_bo *bo); -static INLINE struct radeon_bo *r600_bo_get_bo(struct r600_bo *bo) -{ - return radeon_bo_pb_get_bo(bo->pb); -} +/* + * r600_bo.c + */ +void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo); +/* + * r600_bomgr.c + */ +struct r600_bomgr *r600_bomgr_create(struct radeon *radeon, unsigned usecs); +void r600_bomgr_destroy(struct r600_bomgr *mgr); +bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo); +void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo); +struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr, + unsigned size, + unsigned alignment, + unsigned cfence); + + +/* + * helpers + */ #define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255) #define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1)) @@ -175,6 +205,9 @@ static inline void r600_context_block_emit_dirty(struct r600_context *ctx, struc LIST_DELINIT(&block->list); } +/* + * radeon_bo.c + */ static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) { bo->map_count++; @@ -187,4 +220,35 @@ static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo) assert(bo->map_count >= 0); } +/* + * r600_bo + */ +static inline struct radeon_bo *r600_bo_get_bo(struct r600_bo *bo) +{ + return bo->bo; +} + +static unsigned inline r600_bo_get_handle(struct r600_bo *bo) +{ + return bo->bo->handle; +} + +static unsigned inline r600_bo_get_size(struct r600_bo *bo) +{ + return bo->size; +} + +/* + * fence + */ +static inline bool fence_is_after(unsigned fence, unsigned ofence) +{ + /* handle wrap around */ + if (fence < 0x80000000 && ofence > 0x80000000) + return TRUE; + if (fence > ofence) + return TRUE; + return FALSE; +} + #endif diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h index 5ca7456e906..1c1ac76fe69 100644 --- a/src/gallium/winsys/r600/drm/r600d.h +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -91,9 +91,19 @@ #define PKT3_SET_CTL_CONST 0x6F #define PKT3_SURFACE_BASE_UPDATE 0x73 +#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 #define EVENT_TYPE_ZPASS_DONE 0x15 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + * 5 - TS events + */ #define PKT_TYPE_S(x) (((x) & 0x3) << 30) #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c deleted file mode 100644 index 312552f0758..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_bo_pb.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright 2010 Dave Airlie - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Dave Airlie - */ -#include <util/u_inlines.h> -#include <util/u_memory.h> -#include <util/u_double_list.h> -#include <pipebuffer/pb_buffer.h> -#include <pipebuffer/pb_bufmgr.h> -#include "r600_priv.h" - -struct radeon_bo_pb { - struct pb_buffer b; - struct radeon_bo *bo; - - struct radeon_bo_pbmgr *mgr; - struct list_head maplist; -}; - -extern const struct pb_vtbl radeon_bo_pb_vtbl; - -static INLINE struct radeon_bo_pb *radeon_bo_pb(struct pb_buffer *buf) -{ - assert(buf); - assert(buf->vtbl == &radeon_bo_pb_vtbl); - return (struct radeon_bo_pb *)buf; -} - -struct radeon_bo_pbmgr { - struct pb_manager b; - struct radeon *radeon; - struct list_head buffer_map_list; -}; - -static INLINE struct radeon_bo_pbmgr *radeon_bo_pbmgr(struct pb_manager *mgr) -{ - assert(mgr); - return (struct radeon_bo_pbmgr *)mgr; -} - -static void radeon_bo_pb_destroy(struct pb_buffer *_buf) -{ - struct radeon_bo_pb *buf = radeon_bo_pb(_buf); - - /* If this buffer is on the list of buffers to unmap, - * do the unmapping now. - */ - if (!LIST_IS_EMPTY(&buf->maplist)) - radeon_bo_unmap(buf->mgr->radeon, buf->bo); - - LIST_DEL(&buf->maplist); - radeon_bo_reference(buf->mgr->radeon, &buf->bo, NULL); - FREE(buf); -} - -static void * -radeon_bo_pb_map_internal(struct pb_buffer *_buf, - unsigned flags, void *ctx) -{ - struct radeon_bo_pb *buf = radeon_bo_pb(_buf); - struct pipe_context *pctx = ctx; - - if (flags & PB_USAGE_UNSYNCHRONIZED) { - if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { - return NULL; - } - LIST_DELINIT(&buf->maplist); - return buf->bo->data; - } - - if (p_atomic_read(&buf->bo->reference.count) > 1) { - if (flags & PB_USAGE_DONTBLOCK) { - return NULL; - } - if (ctx) { - pctx->flush(pctx, 0, NULL); - } - } - - if (flags & PB_USAGE_DONTBLOCK) { - uint32_t domain; - if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain)) - return NULL; - if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { - return NULL; - } - goto out; - } - - if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { - return NULL; - } - if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) { - radeon_bo_unmap(buf->mgr->radeon, buf->bo); - return NULL; - } -out: - LIST_DELINIT(&buf->maplist); - return buf->bo->data; -} - -static void radeon_bo_pb_unmap_internal(struct pb_buffer *_buf) -{ - struct radeon_bo_pb *buf = radeon_bo_pb(_buf); - LIST_ADDTAIL(&buf->maplist, &buf->mgr->buffer_map_list); -} - -static void -radeon_bo_pb_get_base_buffer(struct pb_buffer *buf, - struct pb_buffer **base_buf, - unsigned *offset) -{ - *base_buf = buf; - *offset = 0; -} - -static enum pipe_error -radeon_bo_pb_validate(struct pb_buffer *_buf, - struct pb_validate *vl, - unsigned flags) -{ - /* Always pinned */ - return PIPE_OK; -} - -static void -radeon_bo_pb_fence(struct pb_buffer *buf, - struct pipe_fence_handle *fence) -{ -} - -const struct pb_vtbl radeon_bo_pb_vtbl = { - radeon_bo_pb_destroy, - radeon_bo_pb_map_internal, - radeon_bo_pb_unmap_internal, - radeon_bo_pb_validate, - radeon_bo_pb_fence, - radeon_bo_pb_get_base_buffer, -}; - -struct pb_buffer * -radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, - uint32_t handle) -{ - struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); - struct radeon *radeon = mgr->radeon; - struct radeon_bo_pb *bo; - struct radeon_bo *hw_bo; - - hw_bo = radeon_bo(radeon, handle, 0, 0); - if (hw_bo == NULL) - return NULL; - - bo = CALLOC_STRUCT(radeon_bo_pb); - if (!bo) { - radeon_bo_reference(radeon, &hw_bo, NULL); - return NULL; - } - - LIST_INITHEAD(&bo->maplist); - pipe_reference_init(&bo->b.base.reference, 1); - bo->b.base.alignment = 0; - bo->b.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; - bo->b.base.size = hw_bo->size; - bo->b.vtbl = &radeon_bo_pb_vtbl; - bo->mgr = mgr; - - bo->bo = hw_bo; - - return &bo->b; -} - -static struct pb_buffer * -radeon_bo_pb_create_buffer(struct pb_manager *_mgr, - pb_size size, - const struct pb_desc *desc) -{ - struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); - struct radeon *radeon = mgr->radeon; - struct radeon_bo_pb *bo; - - bo = CALLOC_STRUCT(radeon_bo_pb); - if (!bo) - goto error1; - - pipe_reference_init(&bo->b.base.reference, 1); - bo->b.base.alignment = desc->alignment; - bo->b.base.usage = desc->usage; - bo->b.base.size = size; - bo->b.vtbl = &radeon_bo_pb_vtbl; - bo->mgr = mgr; - - LIST_INITHEAD(&bo->maplist); - - bo->bo = radeon_bo(radeon, 0, size, desc->alignment); - if (bo->bo == NULL) - goto error2; - return &bo->b; - -error2: - FREE(bo); -error1: - return NULL; -} - -static void -radeon_bo_pbmgr_flush(struct pb_manager *mgr) -{ - /* NOP */ -} - -static void -radeon_bo_pbmgr_destroy(struct pb_manager *_mgr) -{ - struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); - FREE(mgr); -} - -struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon) -{ - struct radeon_bo_pbmgr *mgr; - - mgr = CALLOC_STRUCT(radeon_bo_pbmgr); - if (!mgr) - return NULL; - - mgr->b.destroy = radeon_bo_pbmgr_destroy; - mgr->b.create_buffer = radeon_bo_pb_create_buffer; - mgr->b.flush = radeon_bo_pbmgr_flush; - - mgr->radeon = radeon; - LIST_INITHEAD(&mgr->buffer_map_list); - return &mgr->b; -} - -void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr) -{ - struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); - struct radeon_bo_pb *rpb = NULL; - struct radeon_bo_pb *t_rpb; - - LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, &mgr->buffer_map_list, maplist) { - radeon_bo_unmap(mgr->radeon, rpb->bo); - LIST_DELINIT(&rpb->maplist); - } - - LIST_INITHEAD(&mgr->buffer_map_list); -} - -struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf) -{ - struct radeon_bo_pb *buf; - if (_buf->vtbl == &radeon_bo_pb_vtbl) { - buf = radeon_bo_pb(_buf); - return buf->bo; - } else { - struct pb_buffer *base_buf; - pb_size offset; - pb_get_base_buffer(_buf, &base_buf, &offset); - if (base_buf->vtbl == &radeon_bo_pb_vtbl) { - buf = radeon_bo_pb(base_buf); - return buf->bo; - } - } - return NULL; -} diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c index 08cc1c41e37..92560a488ae 100644 --- a/src/gallium/winsys/r600/drm/radeon_pciid.c +++ b/src/gallium/winsys/r600/drm/radeon_pciid.c @@ -24,7 +24,7 @@ * Jerome Glisse */ #include <stdlib.h> -#include "r600.h" +#include "r600_priv.h" struct pci_id { unsigned vendor; @@ -441,6 +441,10 @@ struct pci_id radeon_pci_id[] = { {0x1002, 0x9713, CHIP_RS880}, {0x1002, 0x9714, CHIP_RS880}, {0x1002, 0x9715, CHIP_RS880}, + {0x1002, 0x9802, CHIP_PALM}, + {0x1002, 0x9803, CHIP_PALM}, + {0x1002, 0x9804, CHIP_PALM}, + {0x1002, 0x9805, CHIP_PALM}, {0, 0}, }; @@ -456,73 +460,3 @@ unsigned radeon_family_from_device(unsigned device) } return CHIP_UNKNOWN; } - -int radeon_is_family_compatible(unsigned family1, unsigned family2) -{ - switch (family1) { - case CHIP_R600: - case CHIP_RV610: - case CHIP_RV630: - case CHIP_RV670: - case CHIP_RV620: - case CHIP_RV635: - case CHIP_RS780: - case CHIP_RS880: - case CHIP_RV770: - case CHIP_RV730: - case CHIP_RV710: - case CHIP_RV740: - switch (family2) { - case CHIP_R600: - case CHIP_RV610: - case CHIP_RV630: - case CHIP_RV670: - case CHIP_RV620: - case CHIP_RV635: - case CHIP_RS780: - case CHIP_RS880: - case CHIP_RV770: - case CHIP_RV730: - case CHIP_RV710: - case CHIP_RV740: - return 1; - default: - return 0; - } - break; - case CHIP_R100: - case CHIP_RV100: - case CHIP_RS100: - case CHIP_RV200: - case CHIP_RS200: - case CHIP_R200: - case CHIP_RV250: - case CHIP_RS300: - case CHIP_RV280: - case CHIP_R300: - case CHIP_R350: - case CHIP_RV350: - case CHIP_RV380: - case CHIP_R420: - case CHIP_R423: - case CHIP_RV410: - case CHIP_RS400: - case CHIP_RS480: - case CHIP_RS600: - case CHIP_RS690: - case CHIP_RS740: - case CHIP_RV515: - case CHIP_R520: - case CHIP_RV530: - case CHIP_RV560: - case CHIP_RV570: - case CHIP_R580: - case CHIP_CEDAR: - case CHIP_REDWOOD: - case CHIP_JUNIPER: - case CHIP_CYPRESS: - case CHIP_HEMLOCK: - default: - return 0; - } -} |