diff options
Diffstat (limited to 'src/gallium/winsys/intel')
| -rw-r--r-- | src/gallium/winsys/intel/drm/intel_drm_winsys.c | 52 | ||||
| -rw-r--r-- | src/gallium/winsys/intel/intel_winsys.h | 23 |
2 files changed, 43 insertions, 32 deletions
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c b/src/gallium/winsys/intel/drm/intel_drm_winsys.c index f94a1cb9f33..c8ae6c16a8c 100644 --- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c +++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c @@ -195,12 +195,7 @@ intel_winsys_create_for_fd(int fd) /* * No need to implicitly set up a fence register for each non-linear reloc - * entry. When a fence register is needed for a reloc entry, - * drm_intel_bo_emit_reloc_fence() will be called explicitly. - * - * intel_bo_add_reloc() currently lacks "bool fenced" for this to work. - * But we never need a fence register on GEN4+ so we do not need to worry - * about it yet. + * entry. INTEL_RELOC_FENCE will be set on reloc entries that need them. */ drm_intel_bufmgr_gem_enable_fenced_relocs(winsys->bufmgr); @@ -266,10 +261,8 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys, enum intel_tiling_mode tiling, unsigned long pitch, unsigned long height, - uint32_t initial_domain) + bool cpu_init) { - const bool for_render = - (initial_domain & (INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION)); const unsigned int alignment = 4096; /* always page-aligned */ unsigned long size; drm_intel_bo *bo; @@ -292,12 +285,12 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys, size = pitch * height; - if (for_render) { - bo = drm_intel_bo_alloc_for_render(winsys->bufmgr, - name, size, alignment); + if (cpu_init) { + bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment); } else { - bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment); + bo = drm_intel_bo_alloc_for_render(winsys->bufmgr, + name, size, alignment); } if (bo && tiling != INTEL_TILING_NONE) { @@ -558,14 +551,37 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset, int intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset, struct intel_bo *target_bo, uint32_t target_offset, - uint32_t read_domains, uint32_t write_domain, - uint64_t *presumed_offset) + uint32_t flags, uint64_t *presumed_offset) { + uint32_t read_domains, write_domain; int err; - err = drm_intel_bo_emit_reloc(gem_bo(bo), offset, - gem_bo(target_bo), target_offset, - read_domains, write_domain); + if (flags & INTEL_RELOC_WRITE) { + /* + * Because of the translation to domains, INTEL_RELOC_GGTT should only + * be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL. The + * kernel will translate it back to INTEL_RELOC_GGTT. + */ + write_domain = (flags & INTEL_RELOC_GGTT) ? + I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER; + read_domains = write_domain; + } else { + write_domain = 0; + read_domains = I915_GEM_DOMAIN_RENDER | + I915_GEM_DOMAIN_SAMPLER | + I915_GEM_DOMAIN_INSTRUCTION | + I915_GEM_DOMAIN_VERTEX; + } + + if (flags & INTEL_RELOC_FENCE) { + err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset, + gem_bo(target_bo), target_offset, + read_domains, write_domain); + } else { + err = drm_intel_bo_emit_reloc(gem_bo(bo), offset, + gem_bo(target_bo), target_offset, + read_domains, write_domain); + } *presumed_offset = gem_bo(target_bo)->offset64 + target_offset; diff --git a/src/gallium/winsys/intel/intel_winsys.h b/src/gallium/winsys/intel/intel_winsys.h index 679f24817b8..bc18bb69be5 100644 --- a/src/gallium/winsys/intel/intel_winsys.h +++ b/src/gallium/winsys/intel/intel_winsys.h @@ -44,14 +44,10 @@ enum intel_exec_flag { }; /* this is compatible with i915_drm.h's definitions */ -enum intel_domain_flag { - INTEL_DOMAIN_CPU = 0x00000001, - INTEL_DOMAIN_RENDER = 0x00000002, - INTEL_DOMAIN_SAMPLER = 0x00000004, - INTEL_DOMAIN_COMMAND = 0x00000008, - INTEL_DOMAIN_INSTRUCTION = 0x00000010, - INTEL_DOMAIN_VERTEX = 0x00000020, - INTEL_DOMAIN_GTT = 0x00000040, +enum intel_reloc_flag { + INTEL_RELOC_FENCE = 1 << 0, + INTEL_RELOC_GGTT = 1 << 1, + INTEL_RELOC_WRITE = 1 << 2, }; /* this is compatible with i915_drm.h's definitions */ @@ -126,7 +122,7 @@ intel_winsys_read_reg(struct intel_winsys *winsys, * \param tiling Tiling mode. * \param pitch Pitch of the bo. * \param height Height of the bo. - * \param initial_domain Initial (write) domain. + * \param cpu_init Will be initialized by CPU. */ struct intel_bo * intel_winsys_alloc_bo(struct intel_winsys *winsys, @@ -134,7 +130,7 @@ intel_winsys_alloc_bo(struct intel_winsys *winsys, enum intel_tiling_mode tiling, unsigned long pitch, unsigned long height, - uint32_t initial_domain); + bool cpu_init); /** * Allocate a linear buffer object. @@ -143,10 +139,10 @@ static inline struct intel_bo * intel_winsys_alloc_buffer(struct intel_winsys *winsys, const char *name, unsigned long size, - uint32_t initial_domain) + bool cpu_init) { return intel_winsys_alloc_bo(winsys, name, - INTEL_TILING_NONE, size, 1, initial_domain); + INTEL_TILING_NONE, size, 1, cpu_init); } /** @@ -275,8 +271,7 @@ intel_bo_pread(struct intel_bo *bo, unsigned long offset, int intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset, struct intel_bo *target_bo, uint32_t target_offset, - uint32_t read_domains, uint32_t write_domain, - uint64_t *presumed_offset); + uint32_t flags, uint64_t *presumed_offset); /** * Return the current number of relocations. |