2 files changed, 21 insertions, 0 deletions
diff --git a/src/gallium/include/pipe/p_context.h b/src/gallium/include/pipe/p_context.h
index 7cf037f1abd..dd1f5ed192c 100644
--- a/src/gallium/include/pipe/p_context.h
+++ b/src/gallium/include/pipe/p_context.h
@@ -927,6 +927,13 @@ struct pipe_context {
     */
    void (*callback)(struct pipe_context *ctx, void (*fn)(void *), void *data,
                     bool asap);
+
+   /**
+    * Set a context parameter See enum pipe_context_param for more details.
+    */
+   void (*set_context_param)(struct pipe_context *ctx,
+                             enum pipe_context_param param,
+                             unsigned value);
 };
 
 
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 22515504f6c..f6052196733 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -953,6 +953,20 @@ enum pipe_compute_cap
 };
 
 /**
+ * Types of parameters for pipe_context::set_context_param.
+ */
+enum pipe_context_param
+{
+   /* A hint for the driver that it should pin its execution threads to
+    * a group of cores sharing a specific L3 cache if the CPU has multiple
+    * L3 caches. This is needed for good multithreading performance on
+    * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
+    * any internal threads or don't run on affected CPUs can ignore this.
+    */
+   PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
+};
+
+/**
  * Composite query types
  */