6 files changed, 20 insertions, 25 deletions

diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c
index 42eac72f372..a6925a55731 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.c
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.c
@@ -370,22 +370,22 @@ calculate_tiles(struct fd_context *ctx)
 		max_width = 256;
 //	}
 
-	bin_w = ALIGN(width, 32);
-	bin_h = ALIGN(height, 32);
+	bin_w = align(width, 32);
+	bin_h = align(height, 32);
 
 	/* first, find a bin width that satisfies the maximum width
 	 * restrictions:
 	 */
 	while (bin_w > max_width) {
 		nbins_x++;
-		bin_w = ALIGN(width / nbins_x, 32);
+		bin_w = align(width / nbins_x, 32);
 	}
 
 	/* then find a bin height that satisfies the memory constraints:
 	 */
 	while ((bin_w * bin_h * cpp) > gmem_size) {
 		nbins_y++;
-		bin_h = ALIGN(height / nbins_y, 32);
+		bin_h = align(height / nbins_y, 32);
 	}
 
 	DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
@@ -431,7 +431,7 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 	OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 	OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
 			A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
-	reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem->bin_w * gmem->bin_h, 4));
+	reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
 	if (pfb->zsbuf)
 		reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 	OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
@@ -442,13 +442,13 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 		uint32_t bh = gmem->bin_h;
 
 		/* clip bin height: */
-		bh = min(bh, gmem->height - yoff);
+		bh = MIN2(bh, gmem->height - yoff);
 
 		for (j = 0; j < gmem->nbins_x; j++) {
 			uint32_t bw = gmem->bin_w;
 
 			/* clip bin width: */
-			bw = min(bw, gmem->width - xoff);
+			bw = MIN2(bw, gmem->width - xoff);
 
 			DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 					bh, yoff, bw, xoff);
diff --git a/src/gallium/drivers/freedreno/freedreno_program.c b/src/gallium/drivers/freedreno/freedreno_program.c
index 22573df9fe1..3857a1cfe17 100644
--- a/src/gallium/drivers/freedreno/freedreno_program.c
+++ b/src/gallium/drivers/freedreno/freedreno_program.c
@@ -298,7 +298,7 @@ fd_program_emit(struct fd_ringbuffer *ring,
 
 	vs_gprs = (vsi->max_reg < 0) ? 0x80 : vsi->max_reg;
 	fs_gprs = (fsi->max_reg < 0) ? 0x80 : fsi->max_reg;
-	vs_export = max(1, prog->num_exports) - 1;
+	vs_export = MAX2(1, prog->num_exports) - 1;
 
 	OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 	OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL));
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
index d89650a0636..b5efdce469d 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -151,7 +151,7 @@ fd_resource_create(struct pipe_screen *pscreen,
 	prsc->screen = pscreen;
 
 	rsc->base.vtbl = &fd_resource_vtbl;
-	rsc->pitch = ALIGN(tmpl->width0, 32);
+	rsc->pitch = align(tmpl->width0, 32);
 	rsc->cpp = util_format_get_blocksize(tmpl->format);
 
 	size = rsc->pitch * tmpl->height0 * rsc->cpp;
@@ -193,7 +193,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
 	rsc->bo = fd_screen_bo_from_handle(pscreen, handle, &rsc->pitch);
 
 	rsc->base.vtbl = &fd_resource_vtbl;
-	rsc->pitch = ALIGN(tmpl->width0, 32);
+	rsc->pitch = align(tmpl->width0, 32);
 
 	return prsc;
 }
diff --git a/src/gallium/drivers/freedreno/freedreno_state.c b/src/gallium/drivers/freedreno/freedreno_state.c
index c8b5240afa4..070a0429a0c 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.c
+++ b/src/gallium/drivers/freedreno/freedreno_state.c
@@ -238,10 +238,10 @@ emit_constants(struct fd_ringbuffer *ring, uint32_t base,
 	while (enabled_mask) {
 		unsigned index = ffs(enabled_mask) - 1;
 		struct pipe_constant_buffer *cb = &constbuf->cb[index];
-		unsigned size = ALIGN(cb->buffer_size, 4) / 4; /* size in dwords */
+		unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
 
 		// I expect that size should be a multiple of vec4's:
-		assert(size == ALIGN(size, 4));
+		assert(size == align(size, 4));
 
 		/* hmm, sometimes we still seem to end up with consts bound,
 		 * even if shader isn't using them, which ends up overwriting
@@ -417,10 +417,10 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
 		OUT_RING(ring, xy2d(ctx->scissor.maxx,   /* PA_SC_WINDOW_SCISSOR_BR */
 				ctx->scissor.maxy));
 
-		ctx->max_scissor.minx = min(ctx->max_scissor.minx, ctx->scissor.minx);
-		ctx->max_scissor.miny = min(ctx->max_scissor.miny, ctx->scissor.miny);
-		ctx->max_scissor.maxx = max(ctx->max_scissor.maxx, ctx->scissor.maxx);
-		ctx->max_scissor.maxy = max(ctx->max_scissor.maxy, ctx->scissor.maxy);
+		ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, ctx->scissor.minx);
+		ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, ctx->scissor.miny);
+		ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, ctx->scissor.maxx);
+		ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, ctx->scissor.maxy);
 	}
 
 	if (dirty & FD_DIRTY_VIEWPORT) {
diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h
index 45f5d2fc48a..c9af4715454 100644
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -57,14 +57,9 @@ extern int fd_mesa_debug;
 			debug_printf("%s:%d: "fmt "\n", \
 				__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
 
-#define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1))
 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 
 
-#define min(a, b) (((a) < (b)) ? (a) : (b))
-#define max(a, b) (((a) > (b)) ? (a) : (b))
-
-
 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 
 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
diff --git a/src/gallium/drivers/freedreno/ir-a2xx.c b/src/gallium/drivers/freedreno/ir-a2xx.c
index 9d81e2e6f11..2448a782ddb 100644
--- a/src/gallium/drivers/freedreno/ir-a2xx.c
+++ b/src/gallium/drivers/freedreno/ir-a2xx.c
@@ -55,7 +55,7 @@ static uint32_t reg_alu_src_swiz(struct ir2_register *reg);
 static void * ir2_alloc(struct ir2_shader *shader, int sz)
 {
 	void *ptr = &shader->heap[shader->heap_idx];
-	shader->heap_idx += ALIGN(sz, 4);
+	shader->heap_idx += align(sz, 4);
 	return ptr;
 }
 
@@ -136,7 +136,7 @@ void * ir2_shader_assemble(struct ir2_shader *shader, struct ir2_shader_info *in
 	info->regs_written  = 0;
 
 	/* we need an even # of CF's.. insert a NOP if needed */
-	if (shader->cfs_count != ALIGN(shader->cfs_count, 2))
+	if (shader->cfs_count != align(shader->cfs_count, 2))
 		ir2_cf_create(shader, NOP);
 
 	/* first pass, resolve sizes and addresses: */
@@ -505,7 +505,7 @@ static void reg_update_stats(struct ir2_register *reg,
 		struct ir2_shader_info *info, bool dest)
 {
 	if (!(reg->flags & (IR2_REG_CONST|IR2_REG_EXPORT))) {
-		info->max_reg = max(info->max_reg, reg->num);
+		info->max_reg = MAX2(info->max_reg, reg->num);
 
 		if (dest) {
 			info->regs_written |= (1 << reg->num);
@@ -514,7 +514,7 @@ static void reg_update_stats(struct ir2_register *reg,
 			 * input register that the thread scheduler (presumably?)
 			 * needs to know about:
 			 */
-			info->max_input_reg = max(info->max_input_reg, reg->num);
+			info->max_input_reg = MAX2(info->max_input_reg, reg->num);
 		}
 	}
 }