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-rw-r--r--src/gallium/drivers/r600/evergreen_hw_context.c2
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c24
-rw-r--r--src/gallium/drivers/r600/r600_hw_context.c2
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h6
-rw-r--r--src/gallium/drivers/r600/r600_state.c17
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c12
6 files changed, 27 insertions, 36 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index f684a5a6cb5..0ca7f9e0512 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -91,7 +91,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
- {R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
@@ -159,7 +158,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_0286E0_SPI_BARYC_CNTL, 0, 0},
{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
- {R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 2e58a287a08..37f139274e8 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1639,6 +1639,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
rctx->db_misc_state.atom.dirty = true;
}
+ evergreen_update_db_shader_control(rctx);
+
/* Calculate the CS size. */
rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
@@ -2107,6 +2109,7 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_
r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
+ r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
}
static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
@@ -2410,7 +2413,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
- r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
+ r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
@@ -3367,26 +3370,19 @@ void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
}
-void evergreen_update_dual_export_state(struct r600_context * rctx)
+void evergreen_update_db_shader_control(struct r600_context * rctx)
{
bool dual_export = rctx->framebuffer.export_16bpc &&
!rctx->ps_shader->current->ps_depth_export;
- unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
- V_02880C_EXPORT_DB_FULL;
-
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
- S_02880C_DB_SOURCE_FORMAT(db_source_format) |
+ S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
+ V_02880C_EXPORT_DB_FULL) |
S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
- if (db_shader_control != rctx->db_shader_control) {
- struct r600_pipe_state rstate;
-
- rctx->db_shader_control = db_shader_control;
-
- rstate.nregs = 0;
- r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- r600_context_pipe_state_set(rctx, &rstate);
+ if (db_shader_control != rctx->db_misc_state.db_shader_control) {
+ rctx->db_misc_state.db_shader_control = db_shader_control;
+ rctx->db_misc_state.atom.dirty = true;
}
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 015c12abbde..884813b2037 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -219,8 +219,6 @@ static const struct r600_reg r600_config_reg_list[] = {
};
static const struct r600_reg r600_context_reg_list[] = {
- {R_02880C_DB_SHADER_CONTROL, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028614_SPI_VS_OUT_ID_0, 0, 0},
{R_028618_SPI_VS_OUT_ID_1, 0, 0},
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 144e4674599..1be9ff465c6 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -72,6 +72,7 @@ struct r600_db_misc_state {
bool copy_depth, copy_stencil;
unsigned copy_sample;
unsigned log_samples;
+ unsigned db_shader_control;
};
struct r600_cb_misc_state {
@@ -434,7 +435,6 @@ struct r600_context {
/* Additional context states. */
unsigned flags;
unsigned compute_cb_target_mask;
- unsigned db_shader_control;
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
struct r600_rasterizer_state *rasterizer;
@@ -543,7 +543,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
struct r600_surface *surf);
void evergreen_init_color_surface_rat(struct r600_context *rctx,
struct r600_surface *surf);
-void evergreen_update_dual_export_state(struct r600_context * rctx);
+void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
void r600_copy_buffer(struct pipe_context *ctx, struct
@@ -614,7 +614,7 @@ boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
-void r600_update_dual_export_state(struct r600_context * rctx);
+void r600_update_db_shader_control(struct r600_context * rctx);
/* r600_texture.c */
void r600_init_screen_texture_functions(struct pipe_screen *screen);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 567835f9c98..1cff200d34e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1550,6 +1550,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
rctx->alphatest_state.atom.dirty = true;
}
+ r600_update_db_shader_control(rctx);
+
/* Calculate the CS size. */
rctx->framebuffer.atom.num_dw =
10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
@@ -1857,6 +1859,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
+ r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
}
static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
@@ -2160,7 +2163,7 @@ void r600_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
- r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
+ r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
@@ -2826,7 +2829,7 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx)
return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
}
-void r600_update_dual_export_state(struct r600_context * rctx)
+void r600_update_db_shader_control(struct r600_context * rctx)
{
bool dual_export = rctx->framebuffer.export_16bpc &&
!rctx->ps_shader->current->ps_depth_export;
@@ -2834,12 +2837,8 @@ void r600_update_dual_export_state(struct r600_context * rctx)
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export);
- if (db_shader_control != rctx->db_shader_control) {
- struct r600_pipe_state rstate;
-
- rctx->db_shader_control = db_shader_control;
- rstate.nregs = 0;
- r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- r600_context_pipe_state_set(rctx, &rstate);
+ if (db_shader_control != rctx->db_misc_state.db_shader_control) {
+ rctx->db_misc_state.db_shader_control = db_shader_control;
+ rctx->db_misc_state.atom.dirty = true;
}
}
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 8f9f19b05fd..3d58addc62b 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -821,6 +821,12 @@ static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
rctx->cb_misc_state.atom.dirty = true;
}
+
+ if (rctx->chip_class >= EVERGREEN) {
+ evergreen_update_db_shader_control(rctx);
+ } else {
+ r600_update_db_shader_control(rctx);
+ }
}
static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
@@ -1071,12 +1077,6 @@ static void r600_update_derived_state(struct r600_context *rctx)
rctx->blend_state.cso,
blend_disable);
}
-
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_update_dual_export_state(rctx);
- } else {
- r600_update_dual_export_state(rctx);
- }
}
static unsigned r600_conv_prim_to_gs_out(unsigned mode)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 17:11:23 +0000