diff options
Diffstat (limited to 'src/gallium/drivers')
134 files changed, 17167 insertions, 14840 deletions
diff --git a/src/gallium/drivers/cell/ppu/cell_screen.c b/src/gallium/drivers/cell/ppu/cell_screen.c index 0f12e0667eb..8d2b4b96438 100644 --- a/src/gallium/drivers/cell/ppu/cell_screen.c +++ b/src/gallium/drivers/cell/ppu/cell_screen.c @@ -90,8 +90,6 @@ cell_get_param(struct pipe_screen *screen, enum pipe_cap param) return 1; /* XXX not really true */ case PIPE_CAP_TEXTURE_MIRROR_CLAMP: return 0; /* XXX to do */ - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 1; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: return 1; @@ -105,6 +103,20 @@ cell_get_param(struct pipe_screen *screen, enum pipe_cap param) } } +static int +cell_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) + { + case PIPE_SHADER_FRAGMENT: + return tgsi_exec_get_shader_param(param); + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_GEOMETRY: + return draw_get_shader_param(shader, param); + default: + return 0; + } +} static float cell_get_paramf(struct pipe_screen *screen, enum pipe_cap param) @@ -200,6 +212,7 @@ cell_create_screen(struct sw_winsys *winsys) screen->base.get_name = cell_get_name; screen->base.get_vendor = cell_get_vendor; screen->base.get_param = cell_get_param; + screen->base.get_shader_param = cell_get_shader_param; screen->base.get_paramf = cell_get_paramf; screen->base.is_format_supported = cell_is_format_supported; screen->base.context_create = cell_create_context; diff --git a/src/gallium/drivers/failover/fo_context.c b/src/gallium/drivers/failover/fo_context.c index 761a0fce721..ec3609291e9 100644 --- a/src/gallium/drivers/failover/fo_context.c +++ b/src/gallium/drivers/failover/fo_context.c @@ -116,6 +116,7 @@ struct pipe_context *failover_create( struct pipe_context *hw, failover->pipe.get_name = hw->get_name; failover->pipe.get_vendor = hw->get_vendor; failover->pipe.get_param = hw->get_param; + failover->pipe.get_shader_param = hw->get_shader_param; failover->pipe.get_paramf = hw->get_paramf; #endif diff --git a/src/gallium/drivers/galahad/glhd_context.c b/src/gallium/drivers/galahad/glhd_context.c index 383c4489261..ff6d2aa00ab 100644 --- a/src/gallium/drivers/galahad/glhd_context.c +++ b/src/gallium/drivers/galahad/glhd_context.c @@ -54,6 +54,10 @@ galahad_draw_vbo(struct pipe_context *_pipe, struct galahad_context *glhd_pipe = galahad_context(_pipe); struct pipe_context *pipe = glhd_pipe->pipe; + /* XXX we should check that all bound resources are unmapped + * before drawing. + */ + pipe->draw_vbo(pipe, info); } @@ -465,11 +469,11 @@ galahad_set_constant_buffer(struct pipe_context *_pipe, if (index && index >= - pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_CONST_BUFFERS)) { + pipe->screen->get_shader_param(pipe->screen, shader, PIPE_SHADER_CAP_MAX_CONST_BUFFERS)) { glhd_error("Access to constant buffer %u requested, " "but only %d are supported", index, - pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_CONST_BUFFERS)); + pipe->screen->get_shader_param(pipe->screen, shader, PIPE_SHADER_CAP_MAX_CONST_BUFFERS)); } /* XXX hmm? unwrap the input state */ @@ -860,6 +864,10 @@ galahad_context_transfer_map(struct pipe_context *_context, struct pipe_context *context = glhd_context->pipe; struct pipe_transfer *transfer = glhd_transfer->transfer; + struct galahad_resource *glhd_resource = galahad_resource(_transfer->resource); + + glhd_resource->map_count++; + return context->transfer_map(context, transfer); } @@ -890,6 +898,14 @@ galahad_context_transfer_unmap(struct pipe_context *_context, struct galahad_transfer *glhd_transfer = galahad_transfer(_transfer); struct pipe_context *context = glhd_context->pipe; struct pipe_transfer *transfer = glhd_transfer->transfer; + struct galahad_resource *glhd_resource = galahad_resource(_transfer->resource); + + if (glhd_resource->map_count < 1) { + glhd_warn("context::transfer_unmap() called too many times" + " (count = %d)\n", glhd_resource->map_count); + } + + glhd_resource->map_count--; context->transfer_unmap(context, transfer); diff --git a/src/gallium/drivers/galahad/glhd_objects.h b/src/gallium/drivers/galahad/glhd_objects.h index 935803915db..dc74c5bebc9 100644 --- a/src/gallium/drivers/galahad/glhd_objects.h +++ b/src/gallium/drivers/galahad/glhd_objects.h @@ -42,6 +42,8 @@ struct galahad_resource struct pipe_resource base; struct pipe_resource *resource; + + int map_count; }; diff --git a/src/gallium/drivers/galahad/glhd_screen.c b/src/gallium/drivers/galahad/glhd_screen.c index 75e4c2d82e9..288941b1066 100644 --- a/src/gallium/drivers/galahad/glhd_screen.c +++ b/src/gallium/drivers/galahad/glhd_screen.c @@ -79,6 +79,17 @@ galahad_screen_get_param(struct pipe_screen *_screen, param); } +static int +galahad_screen_get_shader_param(struct pipe_screen *_screen, + unsigned shader, enum pipe_shader_cap param) +{ + struct galahad_screen *glhd_screen = galahad_screen(_screen); + struct pipe_screen *screen = glhd_screen->screen; + + return screen->get_shader_param(screen, shader, + param); +} + static float galahad_screen_get_paramf(struct pipe_screen *_screen, enum pipe_cap param) @@ -341,6 +352,7 @@ galahad_screen_create(struct pipe_screen *screen) glhd_screen->base.get_name = galahad_screen_get_name; glhd_screen->base.get_vendor = galahad_screen_get_vendor; glhd_screen->base.get_param = galahad_screen_get_param; + glhd_screen->base.get_shader_param = galahad_screen_get_shader_param; glhd_screen->base.get_paramf = galahad_screen_get_paramf; glhd_screen->base.is_format_supported = galahad_screen_is_format_supported; glhd_screen->base.context_create = galahad_screen_context_create; diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 77345d5f711..a3e7c5c5772 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -26,6 +26,7 @@ **************************************************************************/ +#include "draw/draw_context.h" #include "util/u_inlines.h" #include "util/u_memory.h" #include "util/u_string.h" @@ -139,6 +140,50 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap param) } } +static int +i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) { + case PIPE_SHADER_VERTEX: + return draw_get_shader_param(shader, param); + case PIPE_SHADER_FRAGMENT: + break; + default: + return 0; + } + + /* XXX: these are just shader model 2.0 values, fix this! */ + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + return 96; + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + return 64; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + return 32; + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 8; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return 0; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 10; + case PIPE_SHADER_CAP_MAX_CONSTS: + return 32; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 12; /* XXX: 12 -> 32 ? */ + case PIPE_SHADER_CAP_MAX_ADDRS: + return 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 0; + default: + assert(0); + return 0; + } +} + static float i915_get_paramf(struct pipe_screen *screen, enum pipe_cap param) { @@ -320,6 +365,7 @@ i915_screen_create(struct i915_winsys *iws) is->base.get_name = i915_get_name; is->base.get_vendor = i915_get_vendor; is->base.get_param = i915_get_param; + is->base.get_shader_param = i915_get_shader_param; is->base.get_paramf = i915_get_paramf; is->base.is_format_supported = i915_is_format_supported; diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c index bdfead73cc8..864b21fa53c 100644 --- a/src/gallium/drivers/i965/brw_screen.c +++ b/src/gallium/drivers/i965/brw_screen.c @@ -197,6 +197,50 @@ brw_get_param(struct pipe_screen *screen, enum pipe_cap param) } } +static int +brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) { + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_FRAGMENT: + case PIPE_SHADER_GEOMETRY: + break; + default: + return 0; + } + + /* XXX: these are just shader model 4.0 values, fix this! */ + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 65536; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return 65536; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 32; + case PIPE_SHADER_CAP_MAX_CONSTS: + return 4096; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return PIPE_MAX_CONSTANT_BUFFERS; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 4096; + case PIPE_SHADER_CAP_MAX_ADDRS: + return 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + default: + assert(0); + return 0; + } +} + static float brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param) { @@ -410,6 +454,7 @@ brw_screen_create(struct brw_winsys_screen *sws) bscreen->base.get_name = brw_get_name; bscreen->base.get_vendor = brw_get_vendor; bscreen->base.get_param = brw_get_param; + bscreen->base.get_shader_param = brw_get_shader_param; bscreen->base.get_paramf = brw_get_paramf; bscreen->base.is_format_supported = brw_is_format_supported; bscreen->base.context_create = brw_create_context; diff --git a/src/gallium/drivers/identity/id_screen.c b/src/gallium/drivers/identity/id_screen.c index f71585e06f8..5fb464b4148 100644 --- a/src/gallium/drivers/identity/id_screen.c +++ b/src/gallium/drivers/identity/id_screen.c @@ -76,6 +76,17 @@ identity_screen_get_param(struct pipe_screen *_screen, param); } +static int +identity_screen_get_shader_param(struct pipe_screen *_screen, + unsigned shader, enum pipe_shader_cap param) +{ + struct identity_screen *id_screen = identity_screen(_screen); + struct pipe_screen *screen = id_screen->screen; + + return screen->get_shader_param(screen, shader, + param); +} + static float identity_screen_get_paramf(struct pipe_screen *_screen, enum pipe_cap param) @@ -304,6 +315,7 @@ identity_screen_create(struct pipe_screen *screen) id_screen->base.get_name = identity_screen_get_name; id_screen->base.get_vendor = identity_screen_get_vendor; id_screen->base.get_param = identity_screen_get_param; + id_screen->base.get_shader_param = identity_screen_get_shader_param; id_screen->base.get_paramf = identity_screen_get_paramf; id_screen->base.is_format_supported = identity_screen_is_format_supported; id_screen->base.context_create = identity_screen_context_create; diff --git a/src/gallium/drivers/llvmpipe/Makefile b/src/gallium/drivers/llvmpipe/Makefile index dec874623e5..55b877b4ab9 100644 --- a/src/gallium/drivers/llvmpipe/Makefile +++ b/src/gallium/drivers/llvmpipe/Makefile @@ -22,6 +22,7 @@ C_SOURCES = \ lp_perf.c \ lp_query.c \ lp_rast.c \ + lp_rast_debug.c \ lp_rast_tri.c \ lp_scene.c \ lp_scene_queue.c \ diff --git a/src/gallium/drivers/llvmpipe/SConscript b/src/gallium/drivers/llvmpipe/SConscript index 8d57db72cfb..650435f0f19 100644 --- a/src/gallium/drivers/llvmpipe/SConscript +++ b/src/gallium/drivers/llvmpipe/SConscript @@ -55,6 +55,7 @@ llvmpipe = env.ConvenienceLibrary( 'lp_perf.c', 'lp_query.c', 'lp_rast.c', + 'lp_rast_debug.c', 'lp_rast_tri.c', 'lp_scene.c', 'lp_scene_queue.c', diff --git a/src/gallium/drivers/llvmpipe/lp_bld_alpha.c b/src/gallium/drivers/llvmpipe/lp_bld_alpha.c index 8514030cde4..e28efe778f9 100644 --- a/src/gallium/drivers/llvmpipe/lp_bld_alpha.c +++ b/src/gallium/drivers/llvmpipe/lp_bld_alpha.c @@ -44,21 +44,20 @@ void lp_build_alpha_test(LLVMBuilderRef builder, - const struct pipe_alpha_state *state, + unsigned func, struct lp_type type, struct lp_build_mask_context *mask, LLVMValueRef alpha, LLVMValueRef ref) { struct lp_build_context bld; + LLVMValueRef test; lp_build_context_init(&bld, builder, type); - if(state->enabled) { - LLVMValueRef test = lp_build_cmp(&bld, state->func, alpha, ref); + test = lp_build_cmp(&bld, func, alpha, ref); - lp_build_name(test, "alpha_mask"); + lp_build_name(test, "alpha_mask"); - lp_build_mask_update(mask, test); - } + lp_build_mask_update(mask, test); } diff --git a/src/gallium/drivers/llvmpipe/lp_bld_alpha.h b/src/gallium/drivers/llvmpipe/lp_bld_alpha.h index 0f99fec65ed..44603b418c0 100644 --- a/src/gallium/drivers/llvmpipe/lp_bld_alpha.h +++ b/src/gallium/drivers/llvmpipe/lp_bld_alpha.h @@ -44,7 +44,7 @@ struct lp_build_mask_context; void lp_build_alpha_test(LLVMBuilderRef builder, - const struct pipe_alpha_state *state, + unsigned func, struct lp_type type, struct lp_build_mask_context *mask, LLVMValueRef alpha, diff --git a/src/gallium/drivers/llvmpipe/lp_bld_blend_aos.c b/src/gallium/drivers/llvmpipe/lp_bld_blend_aos.c index 09e98330571..b5924cbb7dc 100644 --- a/src/gallium/drivers/llvmpipe/lp_bld_blend_aos.c +++ b/src/gallium/drivers/llvmpipe/lp_bld_blend_aos.c @@ -197,7 +197,7 @@ lp_build_blend_swizzle(struct lp_build_blend_aos_context *bld, swizzled_rgb = rgb; break; case LP_BUILD_BLEND_SWIZZLE_AAAA: - swizzled_rgb = lp_build_broadcast_aos(&bld->base, rgb, alpha_swizzle); + swizzled_rgb = lp_build_swizzle_scalar_aos(&bld->base, rgb, alpha_swizzle); break; default: assert(0); @@ -205,9 +205,8 @@ lp_build_blend_swizzle(struct lp_build_blend_aos_context *bld, } if (rgb != alpha) { - boolean cond[4] = {0, 0, 0, 0}; - cond[alpha_swizzle] = 1; - swizzled_rgb = lp_build_select_aos(&bld->base, alpha, swizzled_rgb, cond); + swizzled_rgb = lp_build_select_aos(&bld->base, 1 << alpha_swizzle, + alpha, swizzled_rgb); } return swizzled_rgb; diff --git a/src/gallium/drivers/llvmpipe/lp_bld_interp.c b/src/gallium/drivers/llvmpipe/lp_bld_interp.c index 2cf6f38c4b8..2a374f8c390 100644 --- a/src/gallium/drivers/llvmpipe/lp_bld_interp.c +++ b/src/gallium/drivers/llvmpipe/lp_bld_interp.c @@ -75,6 +75,33 @@ */ +/** + * Do one perspective divide per quad. + * + * For perspective interpolation, the final attribute value is given + * + * a' = a/w = a * oow + * + * where + * + * a = a0 + dadx*x + dady*y + * w = w0 + dwdx*x + dwdy*y + * oow = 1/w = 1/(w0 + dwdx*x + dwdy*y) + * + * Instead of computing the division per pixel, with this macro we compute the + * division on the upper left pixel of each quad, and use a linear + * approximation in the remaining pixels, given by: + * + * da'dx = (dadx - dwdx*a)*oow + * da'dy = (dady - dwdy*a)*oow + * + * Ironically, this actually makes things slower -- probably because the + * divide hardware unit is rarely used, whereas the multiply unit is typically + * already saturated. + */ +#define PERSPECTIVE_DIVIDE_PER_QUAD 0 + + static const unsigned char quad_offset_x[4] = {0, 1, 0, 1}; static const unsigned char quad_offset_y[4] = {0, 0, 1, 1}; @@ -107,7 +134,6 @@ coeffs_init(struct lp_build_interp_soa_context *bld, LLVMValueRef i1 = LLVMConstInt(LLVMInt32Type(), 1, 0); LLVMValueRef i2 = LLVMConstInt(LLVMInt32Type(), 2, 0); LLVMValueRef i3 = LLVMConstInt(LLVMInt32Type(), 3, 0); - LLVMValueRef oow = NULL; unsigned attrib; unsigned chan; @@ -213,22 +239,22 @@ coeffs_init(struct lp_build_interp_soa_context *bld, a = LLVMBuildFAdd(builder, a, dadq2, ""); +#if PERSPECTIVE_DIVIDE_PER_QUAD /* - * a *= 1 / w - * dadq *= 1 / w + * a *= 1 / w */ if (interp == LP_INTERP_PERSPECTIVE) { LLVMValueRef w = bld->a[0][3]; assert(attrib != 0); assert(bld->mask[0] & TGSI_WRITEMASK_W); - if (!oow) { - oow = lp_build_rcp(coeff_bld, w); - lp_build_name(oow, "oow"); + if (!bld->oow) { + bld->oow = lp_build_rcp(coeff_bld, w); + lp_build_name(bld->oow, "oow"); } - a = lp_build_mul(coeff_bld, a, oow); - dadq = lp_build_mul(coeff_bld, dadq, oow); + a = lp_build_mul(coeff_bld, a, bld->oow); } +#endif attrib_name(a, attrib, chan, ".a"); attrib_name(dadq, attrib, chan, ".dadq"); @@ -250,6 +276,7 @@ attribs_update(struct lp_build_interp_soa_context *bld, int quad_index) { struct lp_build_context *coeff_bld = &bld->coeff_bld; LLVMValueRef shuffle = lp_build_const_int_vec(coeff_bld->type, quad_index); + LLVMValueRef oow = NULL; unsigned attrib; unsigned chan; @@ -270,6 +297,8 @@ attribs_update(struct lp_build_interp_soa_context *bld, int quad_index) a = bld->attribs[0][chan]; } else { + LLVMValueRef dadq; + a = bld->a[attrib][chan]; /* @@ -280,10 +309,46 @@ attribs_update(struct lp_build_interp_soa_context *bld, int quad_index) a, coeff_bld->undef, shuffle, ""); /* + * Get the derivatives. + */ + + dadq = bld->dadq[attrib][chan]; + +#if PERSPECTIVE_DIVIDE_PER_QUAD + if (interp == LP_INTERP_PERSPECTIVE) { + LLVMValueRef dwdq = bld->dadq[0][3]; + + if (oow == NULL) { + assert(bld->oow); + oow = LLVMBuildShuffleVector(coeff_bld->builder, + bld->oow, coeff_bld->undef, + shuffle, ""); + } + + dadq = lp_build_sub(coeff_bld, + dadq, + lp_build_mul(coeff_bld, a, dwdq)); + dadq = lp_build_mul(coeff_bld, dadq, oow); + } +#endif + + /* * Add the derivatives */ - a = lp_build_add(coeff_bld, a, bld->dadq[attrib][chan]); + a = lp_build_add(coeff_bld, a, dadq); + +#if !PERSPECTIVE_DIVIDE_PER_QUAD + if (interp == LP_INTERP_PERSPECTIVE) { + if (oow == NULL) { + LLVMValueRef w = bld->attribs[0][3]; + assert(attrib != 0); + assert(bld->mask[0] & TGSI_WRITEMASK_W); + oow = lp_build_rcp(coeff_bld, w); + } + a = lp_build_mul(coeff_bld, a, oow); + } +#endif attrib_name(a, attrib, chan, ""); } diff --git a/src/gallium/drivers/llvmpipe/lp_bld_interp.h b/src/gallium/drivers/llvmpipe/lp_bld_interp.h index 29055133011..3054030f739 100644 --- a/src/gallium/drivers/llvmpipe/lp_bld_interp.h +++ b/src/gallium/drivers/llvmpipe/lp_bld_interp.h @@ -64,6 +64,8 @@ struct lp_build_interp_soa_context LLVMValueRef a [1 + PIPE_MAX_SHADER_INPUTS][NUM_CHANNELS]; LLVMValueRef dadq[1 + PIPE_MAX_SHADER_INPUTS][NUM_CHANNELS]; + LLVMValueRef oow; + LLVMValueRef attribs[1 + PIPE_MAX_SHADER_INPUTS][NUM_CHANNELS]; /* diff --git a/src/gallium/drivers/llvmpipe/lp_debug.h b/src/gallium/drivers/llvmpipe/lp_debug.h index a928ee38bec..add43e4fca2 100644 --- a/src/gallium/drivers/llvmpipe/lp_debug.h +++ b/src/gallium/drivers/llvmpipe/lp_debug.h @@ -48,6 +48,7 @@ st_print_current(void); #define DEBUG_COUNTERS 0x800 #define DEBUG_SCENE 0x1000 #define DEBUG_FENCE 0x2000 +#define DEBUG_MEM 0x4000 #ifdef DEBUG diff --git a/src/gallium/drivers/llvmpipe/lp_perf.h b/src/gallium/drivers/llvmpipe/lp_perf.h index c28652fc305..b23a100b873 100644 --- a/src/gallium/drivers/llvmpipe/lp_perf.h +++ b/src/gallium/drivers/llvmpipe/lp_perf.h @@ -74,7 +74,7 @@ extern struct lp_counters lp_count; #define LP_COUNT_GET(counter) (lp_count.counter) #else #define LP_COUNT(counter) -#define LP_COUNT_ADD(counter, incr) (void) incr +#define LP_COUNT_ADD(counter, incr) (void)(incr) #define LP_COUNT_GET(counter) 0 #endif diff --git a/src/gallium/drivers/llvmpipe/lp_query.c b/src/gallium/drivers/llvmpipe/lp_query.c index 67fd797af22..ff0e207a54b 100644 --- a/src/gallium/drivers/llvmpipe/lp_query.c +++ b/src/gallium/drivers/llvmpipe/lp_query.c @@ -54,9 +54,6 @@ llvmpipe_create_query(struct pipe_context *pipe, assert(type == PIPE_QUERY_OCCLUSION_COUNTER); pq = CALLOC_STRUCT( llvmpipe_query ); - if (pq) { - pipe_mutex_init(pq->mutex); - } return (struct pipe_query *) pq; } @@ -66,12 +63,20 @@ static void llvmpipe_destroy_query(struct pipe_context *pipe, struct pipe_query *q) { struct llvmpipe_query *pq = llvmpipe_query(q); - /* query might still be in process if we never waited for the result */ - if (!pq->done) { - llvmpipe_finish(pipe, __FUNCTION__); + + /* Ideally we would refcount queries & not get destroyed until the + * last scene had finished with us. + */ + if (pq->fence) { + if (!lp_fence_issued(pq->fence)) + llvmpipe_flush(pipe, 0, NULL, __FUNCTION__); + + if (!lp_fence_signalled(pq->fence)) + lp_fence_wait(pq->fence); + + lp_fence_reference(&pq->fence, NULL); } - pipe_mutex_destroy(pq->mutex); FREE(pq); } @@ -84,22 +89,31 @@ llvmpipe_get_query_result(struct pipe_context *pipe, { struct llvmpipe_query *pq = llvmpipe_query(q); uint64_t *result = (uint64_t *)vresult; + int i; + + if (!pq->fence) { + assert(0); /* query not in issued state */ + return FALSE; + } - if (!pq->done) { - if (wait) { - llvmpipe_finish(pipe, __FUNCTION__); - } - /* this is a bit inconsequent but should be ok */ - else { + if (!lp_fence_signalled(pq->fence)) { + if (!lp_fence_issued(pq->fence)) llvmpipe_flush(pipe, 0, NULL, __FUNCTION__); - } + + if (!wait) + return FALSE; + + lp_fence_wait(pq->fence); } - if (pq->done) { - *result = pq->result; + /* Sum the results from each of the threads: + */ + *result = 0; + for (i = 0; i < LP_MAX_THREADS; i++) { + *result += pq->count[i]; } - return pq->done; + return TRUE; } @@ -113,10 +127,12 @@ llvmpipe_begin_query(struct pipe_context *pipe, struct pipe_query *q) * flush the scene now. Real apps shouldn't re-use a query in a * frame of rendering. */ - if (pq->binned) { + if (pq->fence && !lp_fence_issued(pq->fence)) { llvmpipe_finish(pipe, __FUNCTION__); } + + memset(pq->count, 0, sizeof(pq->count)); lp_setup_begin_query(llvmpipe->setup, pq); llvmpipe->active_query_count++; diff --git a/src/gallium/drivers/llvmpipe/lp_query.h b/src/gallium/drivers/llvmpipe/lp_query.h index 721c41cb5c9..e93842a2fd0 100644 --- a/src/gallium/drivers/llvmpipe/lp_query.h +++ b/src/gallium/drivers/llvmpipe/lp_query.h @@ -43,13 +43,7 @@ struct llvmpipe_context; struct llvmpipe_query { uint64_t count[LP_MAX_THREADS]; /**< a counter for each thread */ - uint64_t result; /**< total of all counters */ - - pipe_mutex mutex; - unsigned num_tiles, tile_count; - - boolean done; - boolean binned; /**< has this query been binned in the scene? */ + struct lp_fence *fence; /* fence from last scene this was binned in */ }; diff --git a/src/gallium/drivers/llvmpipe/lp_rast.c b/src/gallium/drivers/llvmpipe/lp_rast.c index b1c306bbe94..d7e6415e139 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast.c +++ b/src/gallium/drivers/llvmpipe/lp_rast.c @@ -30,6 +30,7 @@ #include "util/u_math.h" #include "util/u_rect.h" #include "util/u_surface.h" +#include "util/u_pack_color.h" #include "lp_scene_queue.h" #include "lp_debug.h" @@ -57,39 +58,12 @@ static void lp_rast_begin( struct lp_rasterizer *rast, struct lp_scene *scene ) { - const struct pipe_framebuffer_state *fb = &scene->fb; - int i; rast->curr_scene = scene; LP_DBG(DEBUG_RAST, "%s\n", __FUNCTION__); - rast->state.nr_cbufs = scene->fb.nr_cbufs; - - for (i = 0; i < rast->state.nr_cbufs; i++) { - struct pipe_surface *cbuf = scene->fb.cbufs[i]; - llvmpipe_resource_map(cbuf->texture, - cbuf->face, - cbuf->level, - cbuf->zslice, - LP_TEX_USAGE_READ_WRITE, - LP_TEX_LAYOUT_LINEAR); - } - - if (fb->zsbuf) { - struct pipe_surface *zsbuf = scene->fb.zsbuf; - rast->zsbuf.stride = llvmpipe_resource_stride(zsbuf->texture, zsbuf->level); - rast->zsbuf.blocksize = - util_format_get_blocksize(zsbuf->texture->format); - - rast->zsbuf.map = llvmpipe_resource_map(zsbuf->texture, - zsbuf->face, - zsbuf->level, - zsbuf->zslice, - LP_TEX_USAGE_READ_WRITE, - LP_TEX_LAYOUT_NONE); - } - + lp_scene_begin_rasterization( scene ); lp_scene_bin_iter_begin( scene ); } @@ -97,29 +71,7 @@ lp_rast_begin( struct lp_rasterizer *rast, static void lp_rast_end( struct lp_rasterizer *rast ) { - struct lp_scene *scene = rast->curr_scene; - unsigned i; - - /* Unmap color buffers */ - for (i = 0; i < rast->state.nr_cbufs; i++) { - struct pipe_surface *cbuf = scene->fb.cbufs[i]; - llvmpipe_resource_unmap(cbuf->texture, - cbuf->face, - cbuf->level, - cbuf->zslice); - } - - /* Unmap z/stencil buffer */ - if (rast->zsbuf.map) { - struct pipe_surface *zsbuf = scene->fb.zsbuf; - llvmpipe_resource_unmap(zsbuf->texture, - zsbuf->face, - zsbuf->level, - zsbuf->zslice); - rast->zsbuf.map = NULL; - } - - lp_scene_reset( rast->curr_scene ); + lp_scene_end_rasterization( rast->curr_scene ); rast->curr_scene = NULL; @@ -138,26 +90,23 @@ lp_rast_end( struct lp_rasterizer *rast ) */ static void lp_rast_tile_begin(struct lp_rasterizer_task *task, - unsigned x, unsigned y) + const struct cmd_bin *bin) { - struct lp_rasterizer *rast = task->rast; - struct lp_scene *scene = rast->curr_scene; + const struct lp_scene *scene = task->scene; enum lp_texture_usage usage; - LP_DBG(DEBUG_RAST, "%s %d,%d\n", __FUNCTION__, x, y); - - assert(x % TILE_SIZE == 0); - assert(y % TILE_SIZE == 0); + LP_DBG(DEBUG_RAST, "%s %d,%d\n", __FUNCTION__, bin->x, bin->y); - task->x = x; - task->y = y; + task->bin = bin; + task->x = bin->x * TILE_SIZE; + task->y = bin->y * TILE_SIZE; /* reset pointers to color tile(s) */ memset(task->color_tiles, 0, sizeof(task->color_tiles)); /* get pointer to depth/stencil tile */ { - struct pipe_surface *zsbuf = rast->curr_scene->fb.zsbuf; + struct pipe_surface *zsbuf = task->scene->fb.zsbuf; if (zsbuf) { struct llvmpipe_resource *lpt = llvmpipe_resource(zsbuf->texture); @@ -173,11 +122,14 @@ lp_rast_tile_begin(struct lp_rasterizer_task *task, zsbuf->face + zsbuf->zslice, zsbuf->level, usage, - x, y); + task->x, + task->y); /* Get actual pointer to the tile data. Note that depth/stencil * data is tiled differently than color data. */ - task->depth_tile = lp_rast_get_depth_block_pointer(task, x, y); + task->depth_tile = lp_rast_get_depth_block_pointer(task, + task->x, + task->y); assert(task->depth_tile); } @@ -192,11 +144,11 @@ lp_rast_tile_begin(struct lp_rasterizer_task *task, * Clear the rasterizer's current color tile. * This is a bin command called during bin processing. */ -void +static void lp_rast_clear_color(struct lp_rasterizer_task *task, const union lp_rast_cmd_arg arg) { - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; const uint8_t *clear_color = arg.clear_color; unsigned i; @@ -211,7 +163,7 @@ lp_rast_clear_color(struct lp_rasterizer_task *task, clear_color[1] == clear_color[2] && clear_color[2] == clear_color[3]) { /* clear to grayscale value {x, x, x, x} */ - for (i = 0; i < rast->state.nr_cbufs; i++) { + for (i = 0; i < scene->fb.nr_cbufs; i++) { uint8_t *ptr = lp_rast_get_color_tile_pointer(task, i, LP_TEX_USAGE_WRITE_ALL); memset(ptr, clear_color[0], TILE_SIZE * TILE_SIZE * 4); @@ -224,7 +176,7 @@ lp_rast_clear_color(struct lp_rasterizer_task *task, * works. */ const unsigned chunk = TILE_SIZE / 4; - for (i = 0; i < rast->state.nr_cbufs; i++) { + for (i = 0; i < scene->fb.nr_cbufs; i++) { uint8_t *c = lp_rast_get_color_tile_pointer(task, i, LP_TEX_USAGE_WRITE_ALL); unsigned j; @@ -246,22 +198,25 @@ lp_rast_clear_color(struct lp_rasterizer_task *task, } + + + + /** * Clear the rasterizer's current z/stencil tile. * This is a bin command called during bin processing. */ -void +static void lp_rast_clear_zstencil(struct lp_rasterizer_task *task, const union lp_rast_cmd_arg arg) { - struct lp_rasterizer *rast = task->rast; - const struct lp_rast_clearzs *clearzs = arg.clear_zstencil; - unsigned clear_value = clearzs->clearzs_value; - unsigned clear_mask = clearzs->clearzs_mask; + const struct lp_scene *scene = task->scene; + unsigned clear_value = arg.clear_zstencil.value; + unsigned clear_mask = arg.clear_zstencil.mask; const unsigned height = TILE_SIZE / TILE_VECTOR_HEIGHT; const unsigned width = TILE_SIZE * TILE_VECTOR_HEIGHT; - const unsigned block_size = rast->zsbuf.blocksize; - const unsigned dst_stride = rast->zsbuf.stride * TILE_VECTOR_HEIGHT; + const unsigned block_size = scene->zsbuf.blocksize; + const unsigned dst_stride = scene->zsbuf.stride * TILE_VECTOR_HEIGHT; uint8_t *dst; unsigned i, j; @@ -327,15 +282,13 @@ lp_rast_clear_zstencil(struct lp_rasterizer_task *task, * threading/parallelism. * This is a bin command which is stored in all bins. */ -void -lp_rast_store_linear_color( struct lp_rasterizer_task *task, - const union lp_rast_cmd_arg arg) +static void +lp_rast_store_linear_color( struct lp_rasterizer_task *task ) { - struct lp_rasterizer *rast = task->rast; - struct lp_scene *scene = rast->curr_scene; + const struct lp_scene *scene = task->scene; unsigned buf; - for (buf = 0; buf < rast->state.nr_cbufs; buf++) { + for (buf = 0; buf < scene->fb.nr_cbufs; buf++) { struct pipe_surface *cbuf = scene->fb.cbufs[buf]; const unsigned face_slice = cbuf->face + cbuf->zslice; const unsigned level = cbuf->level; @@ -359,17 +312,22 @@ lp_rast_store_linear_color( struct lp_rasterizer_task *task, * completely contained inside a triangle. * This is a bin command called during bin processing. */ -void +static void lp_rast_shade_tile(struct lp_rasterizer_task *task, const union lp_rast_cmd_arg arg) { - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; const struct lp_rast_shader_inputs *inputs = arg.shade_tile; const struct lp_rast_state *state = inputs->state; struct lp_fragment_shader_variant *variant = state->variant; const unsigned tile_x = task->x, tile_y = task->y; unsigned x, y; + if (inputs->disable) { + /* This command was partially binned and has been disabled */ + return; + } + LP_DBG(DEBUG_RAST, "%s\n", __FUNCTION__); /* render the whole 64x64 tile in 4x4 chunks */ @@ -380,7 +338,7 @@ lp_rast_shade_tile(struct lp_rasterizer_task *task, unsigned i; /* color buffer */ - for (i = 0; i < rast->state.nr_cbufs; i++) + for (i = 0; i < scene->fb.nr_cbufs; i++) color[i] = lp_rast_get_color_block_pointer(task, i, tile_x + x, tile_y + y); @@ -410,17 +368,17 @@ lp_rast_shade_tile(struct lp_rasterizer_task *task, * completely contained inside a triangle, and the shader is opaque. * This is a bin command called during bin processing. */ -void +static void lp_rast_shade_tile_opaque(struct lp_rasterizer_task *task, const union lp_rast_cmd_arg arg) { - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; unsigned i; LP_DBG(DEBUG_RAST, "%s\n", __FUNCTION__); /* this will prevent converting the layout from tiled to linear */ - for (i = 0; i < rast->state.nr_cbufs; i++) { + for (i = 0; i < scene->fb.nr_cbufs; i++) { (void)lp_rast_get_color_tile_pointer(task, i, LP_TEX_USAGE_WRITE_ALL); } @@ -442,7 +400,7 @@ lp_rast_shade_quads_mask(struct lp_rasterizer_task *task, { const struct lp_rast_state *state = inputs->state; struct lp_fragment_shader_variant *variant = state->variant; - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; uint8_t *color[PIPE_MAX_COLOR_BUFS]; void *depth; unsigned i; @@ -457,7 +415,7 @@ lp_rast_shade_quads_mask(struct lp_rasterizer_task *task, assert((y % 4) == 0); /* color buffer */ - for (i = 0; i < rast->state.nr_cbufs; i++) { + for (i = 0; i < scene->fb.nr_cbufs; i++) { color[i] = lp_rast_get_color_block_pointer(task, i, x, y); assert(lp_check_alignment(color[i], 16)); } @@ -486,6 +444,38 @@ lp_rast_shade_quads_mask(struct lp_rasterizer_task *task, /** + * Begin a new occlusion query. + * This is a bin command put in all bins. + * Called per thread. + */ +static void +lp_rast_begin_query(struct lp_rasterizer_task *task, + const union lp_rast_cmd_arg arg) +{ + struct llvmpipe_query *pq = arg.query_obj; + + assert(task->query == NULL); + task->vis_counter = 0; + task->query = pq; +} + + +/** + * End the current occlusion query. + * This is a bin command put in all bins. + * Called per thread. + */ +static void +lp_rast_end_query(struct lp_rasterizer_task *task, + const union lp_rast_cmd_arg arg) +{ + task->query->count[task->thread_index] += task->vis_counter; + task->query = NULL; +} + + + +/** * Set top row and left column of the tile's pixels to white. For debugging. */ static void @@ -546,10 +536,10 @@ lp_rast_tile_end(struct lp_rasterizer_task *task) { #ifdef DEBUG if (LP_DEBUG & (DEBUG_SHOW_SUBTILES | DEBUG_SHOW_TILES)) { - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; unsigned buf; - for (buf = 0; buf < rast->state.nr_cbufs; buf++) { + for (buf = 0; buf < scene->fb.nr_cbufs; buf++) { uint8_t *color = lp_rast_get_color_block_pointer(task, buf, task->x, task->y); @@ -563,83 +553,56 @@ lp_rast_tile_end(struct lp_rasterizer_task *task) (void) outline_subtiles; #endif - { + lp_rast_store_linear_color(task); + + if (task->query) { union lp_rast_cmd_arg dummy = {0}; - lp_rast_store_linear_color(task, dummy); + lp_rast_end_query(task, dummy); } /* debug */ memset(task->color_tiles, 0, sizeof(task->color_tiles)); task->depth_tile = NULL; -} - - - -/** - * Signal on a fence. This is called during bin execution/rasterization. - * Called per thread. - */ -void -lp_rast_fence(struct lp_rasterizer_task *task, - const union lp_rast_cmd_arg arg) -{ - struct lp_fence *fence = arg.fence; - lp_fence_signal(fence); -} - -/** - * Begin a new occlusion query. - * This is a bin command put in all bins. - * Called per thread. - */ -void -lp_rast_begin_query(struct lp_rasterizer_task *task, - const union lp_rast_cmd_arg arg) -{ - /* Reset the per-task counter */ - task->vis_counter = 0; + task->bin = NULL; } - -/** - * End the current occlusion query. - * This is a bin command put in all bins. - * Called per thread. - */ -void -lp_rast_end_query(struct lp_rasterizer_task *task, - const union lp_rast_cmd_arg arg) +static lp_rast_cmd_func dispatch[LP_RAST_OP_MAX] = { - struct llvmpipe_query *pq = arg.query_obj; - - pipe_mutex_lock(pq->mutex); - { - /* Accumulate the visible fragment counter from this tile in - * the query object. - */ - pq->count[task->thread_index] += task->vis_counter; + lp_rast_clear_color, + lp_rast_clear_zstencil, + lp_rast_triangle_1, + lp_rast_triangle_2, + lp_rast_triangle_3, + lp_rast_triangle_4, + lp_rast_triangle_5, + lp_rast_triangle_6, + lp_rast_triangle_7, + lp_rast_triangle_8, + lp_rast_triangle_3_4, + lp_rast_triangle_3_16, + lp_rast_shade_tile, + lp_rast_shade_tile_opaque, + lp_rast_begin_query, + lp_rast_end_query, +}; - /* check if this is the last tile in the scene */ - pq->tile_count++; - if (pq->tile_count == pq->num_tiles) { - uint i; - /* sum the per-thread counters for the query */ - pq->result = 0; - for (i = 0; i < LP_MAX_THREADS; i++) { - pq->result += pq->count[i]; - } +static void +do_rasterize_bin(struct lp_rasterizer_task *task, + const struct cmd_bin *bin) +{ + const struct cmd_block *block; + unsigned k; - /* reset counters (in case this query is re-used in the scene) */ - memset(pq->count, 0, sizeof(pq->count)); + if (0) + lp_debug_bin(bin); - pq->tile_count = 0; - pq->binned = FALSE; - pq->done = TRUE; + for (block = bin->head; block; block = block->next) { + for (k = 0; k < block->count; k++) { + dispatch[block->cmd[k]]( task, block->arg[k] ); } } - pipe_mutex_unlock(pq->mutex); } @@ -652,74 +615,26 @@ lp_rast_end_query(struct lp_rasterizer_task *task, */ static void rasterize_bin(struct lp_rasterizer_task *task, - const struct cmd_bin *bin, - int x, int y) + const struct cmd_bin *bin ) { - const struct cmd_block_list *commands = &bin->commands; - struct cmd_block *block; - unsigned k; + lp_rast_tile_begin( task, bin ); - lp_rast_tile_begin( task, x * TILE_SIZE, y * TILE_SIZE ); - - /* simply execute each of the commands in the block list */ - for (block = commands->head; block; block = block->next) { - for (k = 0; k < block->count; k++) { - block->cmd[k]( task, block->arg[k] ); - } - } + do_rasterize_bin(task, bin); lp_rast_tile_end(task); - /* Free data for this bin. - */ - lp_scene_bin_reset( task->rast->curr_scene, x, y); -} - -#define RAST(x) { lp_rast_##x, #x } - -static struct { - lp_rast_cmd cmd; - const char *name; -} cmd_names[] = -{ - RAST(clear_color), - RAST(clear_zstencil), - RAST(triangle_1), - RAST(triangle_2), - RAST(triangle_3), - RAST(triangle_4), - RAST(triangle_5), - RAST(triangle_6), - RAST(triangle_7), - RAST(shade_tile), - RAST(shade_tile_opaque), - RAST(store_linear_color), - RAST(fence), - RAST(begin_query), - RAST(end_query), -}; - -static void -debug_bin( const struct cmd_bin *bin ) -{ - const struct cmd_block *head = bin->commands.head; - int i, j; - - for (i = 0; i < head->count; i++) { - debug_printf("%d: ", i); - for (j = 0; j < Elements(cmd_names); j++) { - if (head->cmd[i] == cmd_names[j].cmd) { - debug_printf("%s\n", cmd_names[j].name); - break; - } - } - if (j == Elements(cmd_names)) - debug_printf("...other\n"); + /* Debug/Perf flags: + */ + if (bin->head->count == 1) { + if (bin->head->cmd[0] == LP_RAST_OP_SHADE_TILE_OPAQUE) + LP_COUNT(nr_pure_shade_opaque_64); + else if (bin->head->cmd[0] == LP_RAST_OP_SHADE_TILE) + LP_COUNT(nr_pure_shade_64); } - } + /* An empty bin is one that just loads the contents of the tile and * stores them again unchanged. This typically happens when bins have * been flushed for some reason in the middle of a frame, or when @@ -730,12 +645,10 @@ debug_bin( const struct cmd_bin *bin ) static boolean is_empty_bin( const struct cmd_bin *bin ) { - if (0) debug_bin(bin); - return bin->commands.head->count == 0; + return bin->head == NULL; } - /** * Rasterize/execute all bins within a scene. * Called per thread. @@ -744,6 +657,7 @@ static void rasterize_scene(struct lp_rasterizer_task *task, struct lp_scene *scene) { + task->scene = scene; /* loop over scene bins, rasterize each */ #if 0 { @@ -758,19 +672,20 @@ rasterize_scene(struct lp_rasterizer_task *task, #else { struct cmd_bin *bin; - int x, y; assert(scene); - while ((bin = lp_scene_bin_iter_next(scene, &x, &y))) { + while ((bin = lp_scene_bin_iter_next(scene))) { if (!is_empty_bin( bin )) - rasterize_bin(task, bin, x, y); + rasterize_bin(task, bin); } } #endif if (scene->fence) { - lp_rast_fence(task, lp_rast_arg_fence(scene->fence)); + lp_fence_signal(scene->fence); } + + task->scene = NULL; } @@ -790,8 +705,6 @@ lp_rast_queue_scene( struct lp_rasterizer *rast, rasterize_scene( &rast->tasks[0], scene ); - lp_scene_reset( scene ); - lp_rast_end( rast ); rast->curr_scene = NULL; diff --git a/src/gallium/drivers/llvmpipe/lp_rast.h b/src/gallium/drivers/llvmpipe/lp_rast.h index b4564ef33bd..57676679354 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast.h +++ b/src/gallium/drivers/llvmpipe/lp_rast.h @@ -79,6 +79,8 @@ struct lp_rast_state { */ struct lp_rast_shader_inputs { float facing; /** Positive for front-facing, negative for back-facing */ + boolean disable:1; /** Partially binned, disable this command */ + boolean opaque:1; /** Is opaque */ float (*a0)[4]; float (*dadx)[4]; @@ -87,10 +89,6 @@ struct lp_rast_shader_inputs { const struct lp_rast_state *state; }; -struct lp_rast_clearzs { - unsigned clearzs_value; - unsigned clearzs_mask; -}; struct lp_rast_plane { /* one-pixel sized trivial accept offsets for each plane */ @@ -150,7 +148,10 @@ union lp_rast_cmd_arg { } triangle; const struct lp_rast_state *set_state; uint8_t clear_color[4]; - const struct lp_rast_clearzs *clear_zstencil; + struct { + unsigned value; + unsigned mask; + } clear_zstencil; struct lp_fence *fence; struct llvmpipe_query *query_obj; }; @@ -194,10 +195,20 @@ lp_rast_arg_fence( struct lp_fence *fence ) static INLINE union lp_rast_cmd_arg -lp_rast_arg_clearzs( const struct lp_rast_clearzs *clearzs ) +lp_rast_arg_clearzs( unsigned value, unsigned mask ) { union lp_rast_cmd_arg arg; - arg.clear_zstencil = clearzs; + arg.clear_zstencil.value = value; + arg.clear_zstencil.mask = mask; + return arg; +} + + +static INLINE union lp_rast_cmd_arg +lp_rast_arg_query( struct llvmpipe_query *pq ) +{ + union lp_rast_cmd_arg arg; + arg.query_obj = pq; return arg; } @@ -215,52 +226,32 @@ lp_rast_arg_null( void ) * These get put into bins by the setup code and are called when * the bins are executed. */ +#define LP_RAST_OP_CLEAR_COLOR 0x0 +#define LP_RAST_OP_CLEAR_ZSTENCIL 0x1 +#define LP_RAST_OP_TRIANGLE_1 0x2 +#define LP_RAST_OP_TRIANGLE_2 0x3 +#define LP_RAST_OP_TRIANGLE_3 0x4 +#define LP_RAST_OP_TRIANGLE_4 0x5 +#define LP_RAST_OP_TRIANGLE_5 0x6 +#define LP_RAST_OP_TRIANGLE_6 0x7 +#define LP_RAST_OP_TRIANGLE_7 0x8 +#define LP_RAST_OP_TRIANGLE_8 0x9 +#define LP_RAST_OP_TRIANGLE_3_4 0xa +#define LP_RAST_OP_TRIANGLE_3_16 0xb +#define LP_RAST_OP_SHADE_TILE 0xc +#define LP_RAST_OP_SHADE_TILE_OPAQUE 0xd +#define LP_RAST_OP_BEGIN_QUERY 0xe +#define LP_RAST_OP_END_QUERY 0xf + +#define LP_RAST_OP_MAX 0x10 +#define LP_RAST_OP_MASK 0xff -void lp_rast_clear_color( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_clear_zstencil( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_triangle_1( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_2( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_3( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_4( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_5( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_6( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_7( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); -void lp_rast_triangle_8( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_shade_tile( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_shade_tile_opaque( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_fence( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_store_linear_color( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - - -void lp_rast_begin_query(struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - -void lp_rast_end_query(struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); - void -lp_rast_triangle_3_16(struct lp_rasterizer_task *task, - const union lp_rast_cmd_arg arg); +lp_debug_bins( struct lp_scene *scene ); +void +lp_debug_draw_bins_by_cmd_length( struct lp_scene *scene ); +void +lp_debug_draw_bins_by_coverage( struct lp_scene *scene ); #endif diff --git a/src/gallium/drivers/llvmpipe/lp_rast_debug.c b/src/gallium/drivers/llvmpipe/lp_rast_debug.c new file mode 100644 index 00000000000..9fc78645a3a --- /dev/null +++ b/src/gallium/drivers/llvmpipe/lp_rast_debug.c @@ -0,0 +1,410 @@ +#include "util/u_math.h" +#include "lp_rast_priv.h" +#include "lp_state_fs.h" + +static INLINE int u_bit_scan(unsigned *mask) +{ + int i = ffs(*mask) - 1; + *mask &= ~(1 << i); + return i; +} + +struct tile { + int coverage; + int overdraw; + char data[TILE_SIZE][TILE_SIZE]; +}; + +static char get_label( int i ) +{ + static const char *cmd_labels = "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"; + unsigned max_label = (2*26+10); + + if (i < max_label) + return cmd_labels[i]; + else + return '?'; +} + + + +static const char *cmd_names[LP_RAST_OP_MAX] = +{ + "clear_color", + "clear_zstencil", + "triangle_1", + "triangle_2", + "triangle_3", + "triangle_4", + "triangle_5", + "triangle_6", + "triangle_7", + "triangle_8", + "triangle_3_4", + "triangle_3_16", + "shade_tile", + "shade_tile_opaque", + "begin_query", + "end_query", +}; + +static const char *cmd_name(unsigned cmd) +{ + assert(Elements(cmd_names) > cmd); + return cmd_names[cmd]; +} + +static const struct lp_fragment_shader_variant * +get_variant( const struct cmd_block *block, + int k ) +{ + if (block->cmd[k] == LP_RAST_OP_SHADE_TILE || + block->cmd[k] == LP_RAST_OP_SHADE_TILE_OPAQUE) + return block->arg[k].shade_tile->state->variant; + + if (block->cmd[k] == LP_RAST_OP_TRIANGLE_1 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_2 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_3 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_4 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_5 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_6 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_7) + return block->arg[k].triangle.tri->inputs.state->variant; + + return NULL; +} + + +static boolean +is_blend( const struct cmd_block *block, + int k ) +{ + const struct lp_fragment_shader_variant *variant = get_variant(block, k); + + if (variant) + return variant->key.blend.rt[0].blend_enable; + + return FALSE; +} + + + +static void +debug_bin( const struct cmd_bin *bin ) +{ + const struct cmd_block *head = bin->head; + int i, j = 0; + + debug_printf("bin %d,%d:\n", bin->x, bin->y); + + while (head) { + for (i = 0; i < head->count; i++, j++) { + debug_printf("%d: %s %s\n", j, + cmd_name(head->cmd[i]), + is_blend(head, i) ? "blended" : ""); + } + head = head->next; + } +} + + +static void plot(struct tile *tile, + int x, int y, + char val, + boolean blend) +{ + if (tile->data[x][y] == ' ') + tile->coverage++; + else + tile->overdraw++; + + tile->data[x][y] = val; +} + + + + + + +static int +debug_shade_tile(int x, int y, + const union lp_rast_cmd_arg arg, + struct tile *tile, + char val) +{ + const struct lp_rast_shader_inputs *inputs = arg.shade_tile; + boolean blend = inputs->state->variant->key.blend.rt[0].blend_enable; + unsigned i,j; + + if (inputs->disable) + return 0; + + for (i = 0; i < TILE_SIZE; i++) + for (j = 0; j < TILE_SIZE; j++) + plot(tile, i, j, val, blend); + + return TILE_SIZE * TILE_SIZE; +} + +static int +debug_clear_tile(int x, int y, + const union lp_rast_cmd_arg arg, + struct tile *tile, + char val) +{ + unsigned i,j; + + for (i = 0; i < TILE_SIZE; i++) + for (j = 0; j < TILE_SIZE; j++) + plot(tile, i, j, val, FALSE); + + return TILE_SIZE * TILE_SIZE; + +} + + +static int +debug_triangle(int tilex, int tiley, + const union lp_rast_cmd_arg arg, + struct tile *tile, + char val) +{ + const struct lp_rast_triangle *tri = arg.triangle.tri; + unsigned plane_mask = arg.triangle.plane_mask; + struct lp_rast_plane plane[8]; + int x, y; + int count = 0; + unsigned i, nr_planes = 0; + boolean blend = tri->inputs.state->variant->key.blend.rt[0].blend_enable; + + if (tri->inputs.disable) { + /* This triangle was partially binned and has been disabled */ + return 0; + } + + while (plane_mask) { + plane[nr_planes] = tri->plane[u_bit_scan(&plane_mask)]; + plane[nr_planes].c = (plane[nr_planes].c + + plane[nr_planes].dcdy * tiley - + plane[nr_planes].dcdx * tilex); + nr_planes++; + } + + for(y = 0; y < TILE_SIZE; y++) + { + for(x = 0; x < TILE_SIZE; x++) + { + for (i = 0; i < nr_planes; i++) + if (plane[i].c <= 0) + goto out; + + plot(tile, x, y, val, blend); + count++; + + out: + for (i = 0; i < nr_planes; i++) + plane[i].c -= plane[i].dcdx; + } + + for (i = 0; i < nr_planes; i++) { + plane[i].c += plane[i].dcdx * TILE_SIZE; + plane[i].c += plane[i].dcdy; + } + } + return count; +} + + + + + +static void +do_debug_bin( struct tile *tile, + const struct cmd_bin *bin, + boolean print_cmds) +{ + unsigned k, j = 0; + const struct cmd_block *block; + + int tx = bin->x * TILE_SIZE; + int ty = bin->y * TILE_SIZE; + + memset(tile->data, ' ', sizeof tile->data); + tile->coverage = 0; + tile->overdraw = 0; + + for (block = bin->head; block; block = block->next) { + for (k = 0; k < block->count; k++, j++) { + boolean blend = is_blend(block, k); + char val = get_label(j); + int count = 0; + + if (print_cmds) + debug_printf("%c: %15s", val, cmd_name(block->cmd[k])); + + if (block->cmd[k] == LP_RAST_OP_CLEAR_COLOR || + block->cmd[k] == LP_RAST_OP_CLEAR_ZSTENCIL) + count = debug_clear_tile(tx, ty, block->arg[k], tile, val); + + if (block->cmd[k] == LP_RAST_OP_SHADE_TILE || + block->cmd[k] == LP_RAST_OP_SHADE_TILE_OPAQUE) + count = debug_shade_tile(tx, ty, block->arg[k], tile, val); + + if (block->cmd[k] == LP_RAST_OP_TRIANGLE_1 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_2 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_3 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_4 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_5 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_6 || + block->cmd[k] == LP_RAST_OP_TRIANGLE_7) + count = debug_triangle(tx, ty, block->arg[k], tile, val); + + if (print_cmds) { + debug_printf(" % 5d", count); + + if (blend) + debug_printf(" blended"); + + debug_printf("\n"); + } + } + } +} + +void +lp_debug_bin( const struct cmd_bin *bin) +{ + struct tile tile; + int x,y; + + if (bin->head) { + do_debug_bin(&tile, bin, TRUE); + + debug_printf("------------------------------------------------------------------\n"); + for (y = 0; y < TILE_SIZE; y++) { + for (x = 0; x < TILE_SIZE; x++) { + debug_printf("%c", tile.data[y][x]); + } + debug_printf("|\n"); + } + debug_printf("------------------------------------------------------------------\n"); + + debug_printf("each pixel drawn avg %f times\n", + ((float)tile.overdraw + tile.coverage)/(float)tile.coverage); + } +} + + + + + + +/** Return number of bytes used for a single bin */ +static unsigned +lp_scene_bin_size( const struct lp_scene *scene, unsigned x, unsigned y ) +{ + struct cmd_bin *bin = lp_scene_get_bin((struct lp_scene *) scene, x, y); + const struct cmd_block *cmd; + unsigned size = 0; + for (cmd = bin->head; cmd; cmd = cmd->next) { + size += (cmd->count * + (sizeof(uint8_t) + sizeof(union lp_rast_cmd_arg))); + } + return size; +} + + + +void +lp_debug_draw_bins_by_coverage( struct lp_scene *scene ) +{ + unsigned x, y; + unsigned total = 0; + unsigned possible = 0; + static unsigned long long _total; + static unsigned long long _possible; + + for (x = 0; x < scene->tiles_x; x++) + debug_printf("-"); + debug_printf("\n"); + + for (y = 0; y < scene->tiles_y; y++) { + for (x = 0; x < scene->tiles_x; x++) { + struct cmd_bin *bin = lp_scene_get_bin(scene, x, y); + const char *bits = "0123456789"; + struct tile tile; + + if (bin->head) { + //lp_debug_bin(bin); + + do_debug_bin(&tile, bin, FALSE); + + total += tile.coverage; + possible += 64*64; + + if (tile.coverage == 64*64) + debug_printf("*"); + else if (tile.coverage) { + int bit = tile.coverage/(64.0*64.0)*10; + debug_printf("%c", bits[MIN2(bit,10)]); + } + else + debug_printf("?"); + } + else { + debug_printf(" "); + } + } + debug_printf("|\n"); + } + + for (x = 0; x < scene->tiles_x; x++) + debug_printf("-"); + debug_printf("\n"); + + debug_printf("this tile total: %u possible %u: percentage: %f\n", + total, + possible, + total * 100.0 / (float)possible); + + _total += total; + _possible += possible; + + debug_printf("overall total: %llu possible %llu: percentage: %f\n", + _total, + _possible, + _total * 100.0 / (double)_possible); +} + + +void +lp_debug_draw_bins_by_cmd_length( struct lp_scene *scene ) +{ + unsigned x, y; + + for (y = 0; y < scene->tiles_y; y++) { + for (x = 0; x < scene->tiles_x; x++) { + const char *bits = " ...,-~:;=o+xaw*#XAWWWWWWWWWWWWWWWW"; + int sz = lp_scene_bin_size(scene, x, y); + int sz2 = util_unsigned_logbase2(sz); + debug_printf("%c", bits[MIN2(sz2,32)]); + } + debug_printf("\n"); + } +} + + +void +lp_debug_bins( struct lp_scene *scene ) +{ + unsigned x, y; + + for (y = 0; y < scene->tiles_y; y++) { + for (x = 0; x < scene->tiles_x; x++) { + struct cmd_bin *bin = lp_scene_get_bin(scene, x, y); + if (bin->head) { + debug_bin(bin); + } + } + } +} diff --git a/src/gallium/drivers/llvmpipe/lp_rast_priv.h b/src/gallium/drivers/llvmpipe/lp_rast_priv.h index fae7f6d3dc2..7370119e966 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast_priv.h +++ b/src/gallium/drivers/llvmpipe/lp_rast_priv.h @@ -69,13 +69,16 @@ extern const struct lp_rast_state *jit_state; struct lp_rasterizer; - +struct cmd_bin; /** * Per-thread rasterization state */ struct lp_rasterizer_task { + const struct cmd_bin *bin; + + struct lp_scene *scene; unsigned x, y; /**< Pos of this tile in framebuffer, in pixels */ uint8_t *color_tiles[PIPE_MAX_COLOR_BUFS]; @@ -89,6 +92,7 @@ struct lp_rasterizer_task /* occlude counter for visiable pixels */ uint32_t vis_counter; + struct llvmpipe_query *query; pipe_semaphore work_ready; pipe_semaphore work_done; @@ -104,33 +108,9 @@ struct lp_rasterizer { boolean exit_flag; - /* Framebuffer stuff - */ - struct { - uint8_t *map; - unsigned stride; - unsigned blocksize; - } zsbuf; - - struct { - unsigned nr_cbufs; - unsigned clear_color; - unsigned clear_depth; - char clear_stencil; - } state; - /** The incoming queue of scenes ready to rasterize */ struct lp_scene_queue *full_scenes; - /** - * The outgoing queue of processed scenes to return to setup module - * - * XXX: while scenes are per-context but the rasterizer is - * (potentially) shared, these empty scenes should be returned to - * the context which created them rather than retained here. - */ - /* struct lp_scene_queue *empty_scenes; */ - /** The scene currently being rasterized by the threads */ struct lp_scene *curr_scene; @@ -164,13 +144,13 @@ static INLINE void * lp_rast_get_depth_block_pointer(struct lp_rasterizer_task *task, unsigned x, unsigned y) { - const struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; void *depth; assert((x % TILE_VECTOR_WIDTH) == 0); assert((y % TILE_VECTOR_HEIGHT) == 0); - if (!rast->zsbuf.map) { + if (!scene->zsbuf.map) { /* Either out of memory or no zsbuf. Can't tell without access * to the state. Just use dummy tile memory, but don't print * the oom warning as this most likely because there is no @@ -179,9 +159,9 @@ lp_rast_get_depth_block_pointer(struct lp_rasterizer_task *task, return lp_dummy_tile; } - depth = (rast->zsbuf.map + - rast->zsbuf.stride * y + - rast->zsbuf.blocksize * x * TILE_VECTOR_HEIGHT); + depth = (scene->zsbuf.map + + scene->zsbuf.stride * y + + scene->zsbuf.blocksize * x * TILE_VECTOR_HEIGHT); assert(lp_check_alignment(depth, 16)); return depth; @@ -195,14 +175,14 @@ static INLINE uint8_t * lp_rast_get_color_tile_pointer(struct lp_rasterizer_task *task, unsigned buf, enum lp_texture_usage usage) { - struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; assert(task->x % TILE_SIZE == 0); assert(task->y % TILE_SIZE == 0); - assert(buf < rast->state.nr_cbufs); + assert(buf < scene->fb.nr_cbufs); if (!task->color_tiles[buf]) { - struct pipe_surface *cbuf = rast->curr_scene->fb.cbufs[buf]; + struct pipe_surface *cbuf = scene->fb.cbufs[buf]; struct llvmpipe_resource *lpt; assert(cbuf); lpt = llvmpipe_resource(cbuf->texture); @@ -263,7 +243,7 @@ lp_rast_shade_quads_all( struct lp_rasterizer_task *task, const struct lp_rast_shader_inputs *inputs, unsigned x, unsigned y ) { - const struct lp_rasterizer *rast = task->rast; + const struct lp_scene *scene = task->scene; const struct lp_rast_state *state = inputs->state; struct lp_fragment_shader_variant *variant = state->variant; uint8_t *color[PIPE_MAX_COLOR_BUFS]; @@ -271,7 +251,7 @@ lp_rast_shade_quads_all( struct lp_rasterizer_task *task, unsigned i; /* color buffer */ - for (i = 0; i < rast->state.nr_cbufs; i++) + for (i = 0; i < scene->fb.nr_cbufs; i++) color[i] = lp_rast_get_color_block_pointer(task, i, x, y); depth = lp_rast_get_depth_block_pointer(task, x, y); @@ -291,5 +271,29 @@ lp_rast_shade_quads_all( struct lp_rasterizer_task *task, END_JIT_CALL(); } +void lp_rast_triangle_1( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_2( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_3( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_4( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_5( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_6( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_7( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void lp_rast_triangle_8( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); + +void lp_rast_triangle_3_4(struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); + +void lp_rast_triangle_3_16( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); +void +lp_debug_bin( const struct cmd_bin *bin ); #endif diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c index dbaa8e023a4..a1f309d4b01 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c +++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c @@ -68,36 +68,6 @@ block_full_16(struct lp_rasterizer_task *task, } #if !defined(PIPE_ARCH_SSE) -static INLINE unsigned -build_mask(int c, int dcdx, int dcdy) -{ - int mask = 0; - - int c0 = c; - int c1 = c0 + dcdx; - int c2 = c1 + dcdx; - int c3 = c2 + dcdx; - - mask |= ((c0 + 0 * dcdy) >> 31) & (1 << 0); - mask |= ((c0 + 1 * dcdy) >> 31) & (1 << 2); - mask |= ((c0 + 2 * dcdy) >> 31) & (1 << 8); - mask |= ((c0 + 3 * dcdy) >> 31) & (1 << 10); - mask |= ((c1 + 0 * dcdy) >> 31) & (1 << 1); - mask |= ((c1 + 1 * dcdy) >> 31) & (1 << 3); - mask |= ((c1 + 2 * dcdy) >> 31) & (1 << 9); - mask |= ((c1 + 3 * dcdy) >> 31) & (1 << 11); - mask |= ((c2 + 0 * dcdy) >> 31) & (1 << 4); - mask |= ((c2 + 1 * dcdy) >> 31) & (1 << 6); - mask |= ((c2 + 2 * dcdy) >> 31) & (1 << 12); - mask |= ((c2 + 3 * dcdy) >> 31) & (1 << 14); - mask |= ((c3 + 0 * dcdy) >> 31) & (1 << 5); - mask |= ((c3 + 1 * dcdy) >> 31) & (1 << 7); - mask |= ((c3 + 2 * dcdy) >> 31) & (1 << 13); - mask |= ((c3 + 3 * dcdy) >> 31) & (1 << 15); - - return mask; -} - static INLINE unsigned build_mask_linear(int c, int dcdx, int dcdy) @@ -142,6 +112,23 @@ build_masks(int c, *partmask |= build_mask_linear(c + cdiff, dcdx, dcdy); } +void +lp_rast_triangle_3_16(struct lp_rasterizer_task *task, + const union lp_rast_cmd_arg arg) +{ + union lp_rast_cmd_arg arg2; + arg2.triangle.tri = arg.triangle.tri; + arg2.triangle.plane_mask = (1<<3)-1; + lp_rast_triangle_3(task, arg2); +} + +void +lp_rast_triangle_3_4(struct lp_rasterizer_task *task, + const union lp_rast_cmd_arg arg) +{ + lp_rast_triangle_3_16(task, arg); +} + #else #include <emmintrin.h> #include "util/u_sse.h" @@ -220,79 +207,28 @@ build_mask_linear(int c, int dcdx, int dcdy) } static INLINE unsigned -build_mask(int c, int dcdx, int dcdy) +sign_bits4(const __m128i *cstep, int cdiff) { - __m128i step = _mm_setr_epi32(0, dcdx, dcdy, dcdx + dcdy); - __m128i c0 = _mm_set1_epi32(c); - - /* Get values across the quad - */ - __m128i cstep0 = _mm_add_epi32(c0, step); - - /* Scale up step for moving between quads. - */ - __m128i step4 = _mm_add_epi32(step, step); - /* Get values for the remaining quads: + /* Adjust the step values */ - __m128i cstep1 = _mm_add_epi32(cstep0, - _mm_shuffle_epi32(step4, _MM_SHUFFLE(1,1,1,1))); - __m128i cstep2 = _mm_add_epi32(cstep0, - _mm_shuffle_epi32(step4, _MM_SHUFFLE(2,2,2,2))); - __m128i cstep3 = _mm_add_epi32(cstep2, - _mm_shuffle_epi32(step4, _MM_SHUFFLE(1,1,1,1))); + __m128i cio4 = _mm_set1_epi32(cdiff); + __m128i cstep0 = _mm_add_epi32(cstep[0], cio4); + __m128i cstep1 = _mm_add_epi32(cstep[1], cio4); + __m128i cstep2 = _mm_add_epi32(cstep[2], cio4); + __m128i cstep3 = _mm_add_epi32(cstep[3], cio4); - /* pack pairs of results into epi16 + /* Pack down to epi8 */ __m128i cstep01 = _mm_packs_epi32(cstep0, cstep1); __m128i cstep23 = _mm_packs_epi32(cstep2, cstep3); - - /* pack into epi8, preserving sign bits - */ __m128i result = _mm_packs_epi16(cstep01, cstep23); - /* extract sign bits to create mask + /* Extract the sign bits */ return _mm_movemask_epi8(result); } -#endif - - - - -#define TAG(x) x##_1 -#define NR_PLANES 1 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_2 -#define NR_PLANES 2 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_3 -#define NR_PLANES 3 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_4 -#define NR_PLANES 4 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_5 -#define NR_PLANES 5 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_6 -#define NR_PLANES 6 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_7 -#define NR_PLANES 7 -#include "lp_rast_tri_tmp.h" - -#define TAG(x) x##_8 -#define NR_PLANES 8 -#include "lp_rast_tri_tmp.h" - /* Special case for 3 plane triangle which is contained entirely * within a 16x16 block. @@ -304,29 +240,32 @@ lp_rast_triangle_3_16(struct lp_rasterizer_task *task, const struct lp_rast_triangle *tri = arg.triangle.tri; const struct lp_rast_plane *plane = tri->plane; unsigned mask = arg.triangle.plane_mask; - const int x = task->x + (mask & 0xf) * 16; - const int y = task->y + (mask >> 4) * 16; + const int x = task->x + (mask & 0xff); + const int y = task->y + (mask >> 8); unsigned outmask, inmask, partmask, partial_mask; unsigned j; - int c[3]; + __m128i cstep4[3][4]; outmask = 0; /* outside one or more trivial reject planes */ partmask = 0; /* outside one or more trivial accept planes */ for (j = 0; j < 3; j++) { - c[j] = plane[j].c + plane[j].dcdy * y - plane[j].dcdx * x; + const int dcdx = -plane[j].dcdx * 4; + const int dcdy = plane[j].dcdy * 4; + __m128i xdcdy = _mm_set1_epi32(dcdy); + + cstep4[j][0] = _mm_setr_epi32(0, dcdx, dcdx*2, dcdx*3); + cstep4[j][1] = _mm_add_epi32(cstep4[j][0], xdcdy); + cstep4[j][2] = _mm_add_epi32(cstep4[j][1], xdcdy); + cstep4[j][3] = _mm_add_epi32(cstep4[j][2], xdcdy); { - const int dcdx = -plane[j].dcdx * 4; - const int dcdy = plane[j].dcdy * 4; + const int c = plane[j].c + plane[j].dcdy * y - plane[j].dcdx * x; const int cox = plane[j].eo * 4; const int cio = plane[j].ei * 4 - 1; - build_masks(c[j] + cox, - cio - cox, - dcdx, dcdy, - &outmask, /* sign bits from c[i][0..15] + cox */ - &partmask); /* sign bits from c[i][0..15] + cio */ + outmask |= sign_bits4(cstep4[j], c + cox); + partmask |= sign_bits4(cstep4[j], c + cio); } } @@ -352,16 +291,20 @@ lp_rast_triangle_3_16(struct lp_rasterizer_task *task, int iy = (i >> 2) * 4; int px = x + ix; int py = y + iy; - int cx[3]; + unsigned mask = 0xffff; partial_mask &= ~(1 << i); - for (j = 0; j < 3; j++) - cx[j] = (c[j] - - plane[j].dcdx * ix - + plane[j].dcdy * iy); + for (j = 0; j < 3; j++) { + const int cx = (plane[j].c + - plane[j].dcdx * px + + plane[j].dcdy * py) * 4; + + mask &= ~sign_bits4(cstep4[j], cx); + } - do_block_4_3(task, tri, plane, px, py, cx); + if (mask) + lp_rast_shade_quads_mask(task, &tri->inputs, px, py, mask); } /* Iterate over fulls: @@ -378,3 +321,87 @@ lp_rast_triangle_3_16(struct lp_rasterizer_task *task, block_full_4(task, tri, px, py); } } + + +void +lp_rast_triangle_3_4(struct lp_rasterizer_task *task, + const union lp_rast_cmd_arg arg) +{ + const struct lp_rast_triangle *tri = arg.triangle.tri; + const struct lp_rast_plane *plane = tri->plane; + unsigned mask = arg.triangle.plane_mask; + const int x = task->x + (mask & 0xff); + const int y = task->y + (mask >> 8); + unsigned j; + + /* Iterate over partials: + */ + { + unsigned mask = 0xffff; + + for (j = 0; j < 3; j++) { + const int cx = (plane[j].c + - plane[j].dcdx * x + + plane[j].dcdy * y); + + const int dcdx = -plane[j].dcdx; + const int dcdy = plane[j].dcdy; + __m128i xdcdy = _mm_set1_epi32(dcdy); + + __m128i cstep0 = _mm_setr_epi32(cx, cx + dcdx, cx + dcdx*2, cx + dcdx*3); + __m128i cstep1 = _mm_add_epi32(cstep0, xdcdy); + __m128i cstep2 = _mm_add_epi32(cstep1, xdcdy); + __m128i cstep3 = _mm_add_epi32(cstep2, xdcdy); + + __m128i cstep01 = _mm_packs_epi32(cstep0, cstep1); + __m128i cstep23 = _mm_packs_epi32(cstep2, cstep3); + __m128i result = _mm_packs_epi16(cstep01, cstep23); + + /* Extract the sign bits + */ + mask &= ~_mm_movemask_epi8(result); + } + + if (mask) + lp_rast_shade_quads_mask(task, &tri->inputs, x, y, mask); + } +} + + +#endif + + + + +#define TAG(x) x##_1 +#define NR_PLANES 1 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_2 +#define NR_PLANES 2 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_3 +#define NR_PLANES 3 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_4 +#define NR_PLANES 4 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_5 +#define NR_PLANES 5 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_6 +#define NR_PLANES 6 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_7 +#define NR_PLANES 7 +#include "lp_rast_tri_tmp.h" + +#define TAG(x) x##_8 +#define NR_PLANES 8 +#include "lp_rast_tri_tmp.h" + diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h index 99a0bae45db..9830a43ba55 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h +++ b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h @@ -50,9 +50,9 @@ TAG(do_block_4)(struct lp_rasterizer_task *task, int j; for (j = 0; j < NR_PLANES; j++) { - mask &= ~build_mask(c[j] - 1, - -plane[j].dcdx, - plane[j].dcdy); + mask &= ~build_mask_linear(c[j] - 1, + -plane[j].dcdx, + plane[j].dcdy); } /* Now pass to the shader: @@ -162,6 +162,11 @@ TAG(lp_rast_triangle)(struct lp_rasterizer_task *task, unsigned outmask, inmask, partmask, partial_mask; unsigned j = 0; + if (tri->inputs.disable) { + /* This triangle was partially binned and has been disabled */ + return; + } + outmask = 0; /* outside one or more trivial reject planes */ partmask = 0; /* outside one or more trivial accept planes */ diff --git a/src/gallium/drivers/llvmpipe/lp_scene.c b/src/gallium/drivers/llvmpipe/lp_scene.c index 15a09b71006..c0732e4ab78 100644 --- a/src/gallium/drivers/llvmpipe/lp_scene.c +++ b/src/gallium/drivers/llvmpipe/lp_scene.c @@ -30,17 +30,20 @@ #include "util/u_memory.h" #include "util/u_inlines.h" #include "util/u_simple_list.h" +#include "util/u_format.h" #include "lp_scene.h" -#include "lp_scene_queue.h" #include "lp_fence.h" +#include "lp_debug.h" -/** List of texture references */ -struct texture_ref { - struct pipe_resource *texture; - struct texture_ref *prev, *next; /**< linked list w/ u_simple_list.h */ -}; +#define RESOURCE_REF_SZ 32 +/** List of resource references */ +struct resource_ref { + struct pipe_resource *resource[RESOURCE_REF_SZ]; + int count; + struct resource_ref *next; +}; /** @@ -48,28 +51,16 @@ struct texture_ref { * \param queue the queue to put newly rendered/emptied scenes into */ struct lp_scene * -lp_scene_create( struct pipe_context *pipe, - struct lp_scene_queue *queue ) +lp_scene_create( struct pipe_context *pipe ) { - unsigned i, j; struct lp_scene *scene = CALLOC_STRUCT(lp_scene); if (!scene) return NULL; scene->pipe = pipe; - scene->empty_queue = queue; - - for (i = 0; i < TILES_X; i++) { - for (j = 0; j < TILES_Y; j++) { - struct cmd_bin *bin = lp_scene_get_bin(scene, i, j); - bin->commands.head = bin->commands.tail = CALLOC_STRUCT(cmd_block); - } - } scene->data.head = - scene->data.tail = CALLOC_STRUCT(data_block); - - make_empty_list(&scene->resources); + CALLOC_STRUCT(data_block); pipe_mutex_init(scene->mutex); @@ -83,24 +74,9 @@ lp_scene_create( struct pipe_context *pipe, void lp_scene_destroy(struct lp_scene *scene) { - unsigned i, j; - - lp_scene_reset(scene); - - for (i = 0; i < TILES_X; i++) - for (j = 0; j < TILES_Y; j++) { - struct cmd_bin *bin = lp_scene_get_bin(scene, i, j); - assert(bin->commands.head == bin->commands.tail); - FREE(bin->commands.head); - bin->commands.head = NULL; - bin->commands.tail = NULL; - } - - FREE(scene->data.head); - scene->data.head = NULL; - pipe_mutex_destroy(scene->mutex); - + assert(scene->data.head->next == NULL); + FREE(scene->data.head); FREE(scene); } @@ -117,8 +93,7 @@ lp_scene_is_empty(struct lp_scene *scene ) for (y = 0; y < TILES_Y; y++) { for (x = 0; x < TILES_X; x++) { const struct cmd_bin *bin = lp_scene_get_bin(scene, x, y); - const struct cmd_block_list *list = &bin->commands; - if (list->head != list->tail || list->head->count > 0) { + if (bin->head) { return FALSE; } } @@ -127,45 +102,108 @@ lp_scene_is_empty(struct lp_scene *scene ) } -/* Free data for one particular bin. May be called from the - * rasterizer thread(s). +/* Returns true if there has ever been a failed allocation attempt in + * this scene. Used in triangle emit to avoid having to check success + * at each bin. + */ +boolean +lp_scene_is_oom(struct lp_scene *scene) +{ + return scene->alloc_failed; +} + + +/* Remove all commands from a bin. Tries to reuse some of the memory + * allocated to the bin, however. */ void lp_scene_bin_reset(struct lp_scene *scene, unsigned x, unsigned y) { struct cmd_bin *bin = lp_scene_get_bin(scene, x, y); - struct cmd_block_list *list = &bin->commands; - struct cmd_block *block; - struct cmd_block *tmp; - assert(x < TILES_X); - assert(y < TILES_Y); + bin->head = bin->tail; + if (bin->tail) { + bin->tail->next = NULL; + bin->tail->count = 0; + } +} + - for (block = list->head; block != list->tail; block = tmp) { - tmp = block->next; - FREE(block); +void +lp_scene_begin_rasterization(struct lp_scene *scene) +{ + const struct pipe_framebuffer_state *fb = &scene->fb; + int i; + + //LP_DBG(DEBUG_RAST, "%s\n", __FUNCTION__); + + for (i = 0; i < scene->fb.nr_cbufs; i++) { + struct pipe_surface *cbuf = scene->fb.cbufs[i]; + scene->cbufs[i].stride = llvmpipe_resource_stride(cbuf->texture, + cbuf->level); + + scene->cbufs[i].map = llvmpipe_resource_map(cbuf->texture, + cbuf->face, + cbuf->level, + cbuf->zslice, + LP_TEX_USAGE_READ_WRITE, + LP_TEX_LAYOUT_LINEAR); } - assert(list->tail->next == NULL); - list->head = list->tail; - list->head->count = 0; + if (fb->zsbuf) { + struct pipe_surface *zsbuf = scene->fb.zsbuf; + scene->zsbuf.stride = llvmpipe_resource_stride(zsbuf->texture, zsbuf->level); + scene->zsbuf.blocksize = + util_format_get_blocksize(zsbuf->texture->format); + + scene->zsbuf.map = llvmpipe_resource_map(zsbuf->texture, + zsbuf->face, + zsbuf->level, + zsbuf->zslice, + LP_TEX_USAGE_READ_WRITE, + LP_TEX_LAYOUT_NONE); + } } + + /** - * Free all the temporary data in a scene. May be called from the - * rasterizer thread(s). + * Free all the temporary data in a scene. */ void -lp_scene_reset(struct lp_scene *scene ) +lp_scene_end_rasterization(struct lp_scene *scene ) { - unsigned i, j; + int i, j; + + /* Unmap color buffers */ + for (i = 0; i < scene->fb.nr_cbufs; i++) { + if (scene->cbufs[i].map) { + struct pipe_surface *cbuf = scene->fb.cbufs[i]; + llvmpipe_resource_unmap(cbuf->texture, + cbuf->face, + cbuf->level, + cbuf->zslice); + scene->cbufs[i].map = NULL; + } + } - /* Free all but last binner command lists: + /* Unmap z/stencil buffer */ + if (scene->zsbuf.map) { + struct pipe_surface *zsbuf = scene->fb.zsbuf; + llvmpipe_resource_unmap(zsbuf->texture, + zsbuf->face, + zsbuf->level, + zsbuf->zslice); + scene->zsbuf.map = NULL; + } + + /* Reset all command lists: */ for (i = 0; i < scene->tiles_x; i++) { for (j = 0; j < scene->tiles_y; j++) { - lp_scene_bin_reset(scene, i, j); + struct cmd_bin *bin = lp_scene_get_bin(scene, i, j); + bin->head = bin->tail = NULL; } } @@ -174,40 +212,56 @@ lp_scene_reset(struct lp_scene *scene ) */ assert(lp_scene_is_empty(scene)); - /* Free all but last binned data block: + /* Decrement texture ref counts */ { - struct data_block_list *list = &scene->data; - struct data_block *block, *tmp; - - for (block = list->head; block != list->tail; block = tmp) { - tmp = block->next; - FREE(block); + struct resource_ref *ref; + int i, j = 0; + + for (ref = scene->resources; ref; ref = ref->next) { + for (i = 0; i < ref->count; i++) { + if (LP_DEBUG & DEBUG_SETUP) + debug_printf("resource %d: %p %dx%d sz %d\n", + j, + ref->resource[i], + ref->resource[i]->width0, + ref->resource[i]->height0, + llvmpipe_resource_size(ref->resource[i])); + j++; + pipe_resource_reference(&ref->resource[i], NULL); + } } - - assert(list->tail->next == NULL); - list->head = list->tail; - list->head->used = 0; + + if (LP_DEBUG & DEBUG_SETUP) + debug_printf("scene %d resources, sz %d\n", + j, scene->resource_reference_size); } - /* Release texture refs + /* Free all scene data blocks: */ { - struct resource_ref *ref, *next, *ref_list = &scene->resources; - for (ref = ref_list->next; ref != ref_list; ref = next) { - next = next_elem(ref); - pipe_resource_reference(&ref->resource, NULL); - FREE(ref); + struct data_block_list *list = &scene->data; + struct data_block *block, *tmp; + + for (block = list->head->next; block; block = tmp) { + tmp = block->next; + FREE(block); } - make_empty_list(ref_list); + + list->head->next = NULL; + list->head->used = 0; } lp_fence_reference(&scene->fence, NULL); + scene->resources = NULL; scene->scene_size = 0; + scene->resource_reference_size = 0; - scene->has_color_clear = FALSE; scene->has_depthstencil_clear = FALSE; + scene->alloc_failed = FALSE; + + util_unreference_framebuffer_state( &scene->fb ); } @@ -216,12 +270,20 @@ lp_scene_reset(struct lp_scene *scene ) struct cmd_block * -lp_bin_new_cmd_block( struct cmd_block_list *list ) +lp_scene_new_cmd_block( struct lp_scene *scene, + struct cmd_bin *bin ) { - struct cmd_block *block = MALLOC_STRUCT(cmd_block); + struct cmd_block *block = lp_scene_alloc(scene, sizeof(struct cmd_block)); if (block) { - list->tail->next = block; - list->tail = block; + if (bin->tail) { + bin->tail->next = block; + bin->tail = block; + } + else { + bin->head = block; + bin->tail = block; + } + //memset(block, 0, sizeof *block); block->next = NULL; block->count = 0; } @@ -230,16 +292,26 @@ lp_bin_new_cmd_block( struct cmd_block_list *list ) struct data_block * -lp_bin_new_data_block( struct data_block_list *list ) +lp_scene_new_data_block( struct lp_scene *scene ) { - struct data_block *block = MALLOC_STRUCT(data_block); - if (block) { - list->tail->next = block; - list->tail = block; - block->next = NULL; + if (scene->scene_size + DATA_BLOCK_SIZE > LP_SCENE_MAX_SIZE) { + if (0) debug_printf("%s: failed\n", __FUNCTION__); + scene->alloc_failed = TRUE; + return NULL; + } + else { + struct data_block *block = MALLOC_STRUCT(data_block); + if (block == NULL) + return NULL; + + scene->scene_size += sizeof *block; + block->used = 0; + block->next = scene->data.head; + scene->data.head = block; + + return block; } - return block; } @@ -247,7 +319,7 @@ lp_bin_new_data_block( struct data_block_list *list ) * Return number of bytes used for all bin data within a scene. * This does not include resources (textures) referenced by the scene. */ -unsigned +static unsigned lp_scene_data_size( const struct lp_scene *scene ) { unsigned size = 0; @@ -259,36 +331,63 @@ lp_scene_data_size( const struct lp_scene *scene ) } -/** Return number of bytes used for a single bin */ -unsigned -lp_scene_bin_size( const struct lp_scene *scene, unsigned x, unsigned y ) -{ - struct cmd_bin *bin = lp_scene_get_bin((struct lp_scene *) scene, x, y); - const struct cmd_block *cmd; - unsigned size = 0; - for (cmd = bin->commands.head; cmd; cmd = cmd->next) { - size += (cmd->count * - (sizeof(lp_rast_cmd) + sizeof(union lp_rast_cmd_arg))); - } - return size; -} - /** * Add a reference to a resource by the scene. */ -void +boolean lp_scene_add_resource_reference(struct lp_scene *scene, - struct pipe_resource *resource) + struct pipe_resource *resource, + boolean initializing_scene) { - struct resource_ref *ref = CALLOC_STRUCT(resource_ref); - if (ref) { - struct resource_ref *ref_list = &scene->resources; - pipe_resource_reference(&ref->resource, resource); - insert_at_tail(ref_list, ref); + struct resource_ref *ref, **last = &scene->resources; + int i; + + /* Look at existing resource blocks: + */ + for (ref = scene->resources; ref; ref = ref->next) { + last = &ref->next; + + /* Search for this resource: + */ + for (i = 0; i < ref->count; i++) + if (ref->resource[i] == resource) + return TRUE; + + if (ref->count < RESOURCE_REF_SZ) { + /* If the block is half-empty, then append the reference here. + */ + break; + } + } + + /* Create a new block if no half-empty block was found. + */ + if (!ref) { + assert(*last == NULL); + *last = lp_scene_alloc(scene, sizeof *ref); + if (*last == NULL) + return FALSE; + + ref = *last; + memset(ref, 0, sizeof *ref); } - scene->scene_size += llvmpipe_resource_size(resource); + /* Append the reference to the reference block. + */ + pipe_resource_reference(&ref->resource[ref->count++], resource); + scene->resource_reference_size += llvmpipe_resource_size(resource); + + /* Heuristic to advise scene flushes. This isn't helpful in the + * initial setup of the scene, but after that point flush on the + * next resource added which exceeds 64MB in referenced texture + * data. + */ + if (!initializing_scene && + scene->resource_reference_size >= LP_SCENE_MAX_RESOURCE_SIZE) + return FALSE; + + return TRUE; } @@ -299,12 +398,15 @@ boolean lp_scene_is_resource_referenced(const struct lp_scene *scene, const struct pipe_resource *resource) { - const struct resource_ref *ref_list = &scene->resources; const struct resource_ref *ref; - foreach (ref, ref_list) { - if (ref->resource == resource) - return TRUE; + int i; + + for (ref = scene->resources; ref; ref = ref->next) { + for (i = 0; i < ref->count; i++) + if (ref->resource[i] == resource) + return TRUE; } + return FALSE; } @@ -342,7 +444,7 @@ lp_scene_bin_iter_begin( struct lp_scene *scene ) * of work (a bin) to work on. */ struct cmd_bin * -lp_scene_bin_iter_next( struct lp_scene *scene, int *bin_x, int *bin_y ) +lp_scene_bin_iter_next( struct lp_scene *scene ) { struct cmd_bin *bin = NULL; @@ -359,8 +461,6 @@ lp_scene_bin_iter_next( struct lp_scene *scene, int *bin_x, int *bin_y ) } bin = lp_scene_get_bin(scene, scene->curr_x, scene->curr_y); - *bin_x = scene->curr_x; - *bin_y = scene->curr_y; end: /*printf("return bin %p at %d, %d\n", (void *) bin, *bin_x, *bin_y);*/ @@ -384,34 +484,16 @@ void lp_scene_begin_binning( struct lp_scene *scene, } -void lp_scene_rasterize( struct lp_scene *scene, - struct lp_rasterizer *rast ) +void lp_scene_end_binning( struct lp_scene *scene ) { - if (0) { - unsigned x, y; + if (LP_DEBUG & DEBUG_SCENE) { debug_printf("rasterize scene:\n"); - debug_printf(" data size: %u\n", lp_scene_data_size(scene)); - for (y = 0; y < scene->tiles_y; y++) { - for (x = 0; x < scene->tiles_x; x++) { - debug_printf(" bin %u, %u size: %u\n", x, y, - lp_scene_bin_size(scene, x, y)); - } - } - } - - /* Enqueue the scene for rasterization, then immediately wait for - * it to finish. - */ - lp_rast_queue_scene( rast, scene ); + debug_printf(" scene_size: %u\n", + scene->scene_size); + debug_printf(" data size: %u\n", + lp_scene_data_size(scene)); - /* Currently just wait for the rasterizer to finish. Some - * threading interactions need to be worked out, particularly once - * transfers become per-context: - */ - lp_rast_finish( rast ); - - util_unreference_framebuffer_state( &scene->fb ); - - /* put scene into the empty list */ - lp_scene_enqueue( scene->empty_queue, scene ); + if (0) + lp_debug_bins( scene ); + } } diff --git a/src/gallium/drivers/llvmpipe/lp_scene.h b/src/gallium/drivers/llvmpipe/lp_scene.h index fa1b311fa17..dbef7692e42 100644 --- a/src/gallium/drivers/llvmpipe/lp_scene.h +++ b/src/gallium/drivers/llvmpipe/lp_scene.h @@ -38,6 +38,7 @@ #include "os/os_thread.h" #include "lp_tile_soa.h" #include "lp_rast.h" +#include "lp_debug.h" struct lp_scene_queue; @@ -49,58 +50,71 @@ struct lp_scene_queue; #define CMD_BLOCK_MAX 128 -#define DATA_BLOCK_SIZE (16 * 1024 - sizeof(unsigned) - sizeof(void *)) - +#define DATA_BLOCK_SIZE (64 * 1024) + +/* Scene temporary storage is clamped to this size: + */ +#define LP_SCENE_MAX_SIZE (4*1024*1024) + +/* The maximum amount of texture storage referenced by a scene is + * clamped ot this size: + */ +#define LP_SCENE_MAX_RESOURCE_SIZE (64*1024*1024) /* switch to a non-pointer value for this: */ -typedef void (*lp_rast_cmd)( struct lp_rasterizer_task *, - const union lp_rast_cmd_arg ); +typedef void (*lp_rast_cmd_func)( struct lp_rasterizer_task *, + const union lp_rast_cmd_arg ); + struct cmd_block { - lp_rast_cmd cmd[CMD_BLOCK_MAX]; + uint8_t cmd[CMD_BLOCK_MAX]; union lp_rast_cmd_arg arg[CMD_BLOCK_MAX]; unsigned count; struct cmd_block *next; }; +struct cmd_block_list { + struct cmd_block *head; + struct cmd_block *tail; +}; + struct data_block { ubyte data[DATA_BLOCK_SIZE]; unsigned used; struct data_block *next; }; -struct cmd_block_list { - struct cmd_block *head; - struct cmd_block *tail; -}; + /** * For each screen tile we have one of these bins. */ struct cmd_bin { - struct cmd_block_list commands; + ushort x; + ushort y; + struct cmd_block *head; + struct cmd_block *tail; }; /** - * This stores bulk data which is shared by all bins within a scene. + * This stores bulk data which is used for all memory allocations + * within a scene. + * * Examples include triangle data and state data. The commands in * the per-tile bins will point to chunks of data in this structure. + * + * Include the first block of data statically to ensure we can always + * initiate a scene without relying on malloc succeeding. */ struct data_block_list { + struct data_block first; struct data_block *head; - struct data_block *tail; -}; - - -/** List of resource references */ -struct resource_ref { - struct pipe_resource *resource; - struct resource_ref *prev, *next; /**< linked list w/ u_simple_list.h */ }; +struct resource_ref; /** * All bins and bin data are contained here. @@ -114,18 +128,33 @@ struct lp_scene { struct pipe_context *pipe; struct lp_fence *fence; + /* Framebuffer mappings - valid only between begin_rasterization() + * and end_rasterization(). + */ + struct { + uint8_t *map; + unsigned stride; + unsigned blocksize; + } zsbuf, cbufs[PIPE_MAX_COLOR_BUFS]; + /** the framebuffer to render the scene into */ struct pipe_framebuffer_state fb; /** list of resources referenced by the scene commands */ - struct resource_ref resources; + struct resource_ref *resources; - /** Approx memory used by the scene (in bytes). This includes the - * shared and per-tile bins plus any referenced resources/textures. + /** Total memory used by the scene (in bytes). This sums all the + * data blocks and counts all bins, state, resource references and + * other random allocations within the scene. */ unsigned scene_size; - boolean has_color_clear; + /** Sum of sizes of all resources referenced by the scene. Sums + * all the textures read by the scene: + */ + unsigned resource_reference_size; + + boolean alloc_failed; boolean has_depthstencil_clear; /** @@ -137,38 +166,28 @@ struct lp_scene { int curr_x, curr_y; /**< for iterating over bins */ pipe_mutex mutex; - /* Where to place this scene once it has been rasterized: - */ - struct lp_scene_queue *empty_queue; - struct cmd_bin tile[TILES_X][TILES_Y]; struct data_block_list data; }; -struct lp_scene *lp_scene_create(struct pipe_context *pipe, - struct lp_scene_queue *empty_queue); +struct lp_scene *lp_scene_create(struct pipe_context *pipe); void lp_scene_destroy(struct lp_scene *scene); - - boolean lp_scene_is_empty(struct lp_scene *scene ); - -void lp_scene_reset(struct lp_scene *scene ); +boolean lp_scene_is_oom(struct lp_scene *scene ); -struct data_block *lp_bin_new_data_block( struct data_block_list *list ); +struct data_block *lp_scene_new_data_block( struct lp_scene *scene ); -struct cmd_block *lp_bin_new_cmd_block( struct cmd_block_list *list ); +struct cmd_block *lp_scene_new_cmd_block( struct lp_scene *scene, + struct cmd_bin *bin ); -unsigned lp_scene_data_size( const struct lp_scene *scene ); - -unsigned lp_scene_bin_size( const struct lp_scene *scene, unsigned x, unsigned y ); - -void lp_scene_add_resource_reference(struct lp_scene *scene, - struct pipe_resource *resource); +boolean lp_scene_add_resource_reference(struct lp_scene *scene, + struct pipe_resource *resource, + boolean initializing_scene); boolean lp_scene_is_resource_referenced(const struct lp_scene *scene, const struct pipe_resource *resource ); @@ -182,21 +201,27 @@ static INLINE void * lp_scene_alloc( struct lp_scene *scene, unsigned size) { struct data_block_list *list = &scene->data; - struct data_block *tail = list->tail; + struct data_block *block = list->head; - if (tail->used + size > DATA_BLOCK_SIZE) { - tail = lp_bin_new_data_block( list ); - if (!tail) { + assert(size <= DATA_BLOCK_SIZE); + assert(block != NULL); + + if (LP_DEBUG & DEBUG_MEM) + debug_printf("alloc %u block %u/%u tot %u/%u\n", + size, block->used, DATA_BLOCK_SIZE, + scene->scene_size, LP_SCENE_MAX_SIZE); + + if (block->used + size > DATA_BLOCK_SIZE) { + block = lp_scene_new_data_block( scene ); + if (!block) { /* out of memory */ return NULL; } } - scene->scene_size += size; - { - ubyte *data = tail->data + tail->used; - tail->used += size; + ubyte *data = block->data + block->used; + block->used += size; return data; } } @@ -210,20 +235,26 @@ lp_scene_alloc_aligned( struct lp_scene *scene, unsigned size, unsigned alignment ) { struct data_block_list *list = &scene->data; - struct data_block *tail = list->tail; - - if (tail->used + size + alignment - 1 > DATA_BLOCK_SIZE) { - tail = lp_bin_new_data_block( list ); - if (!tail) + struct data_block *block = list->head; + + assert(block != NULL); + + if (LP_DEBUG & DEBUG_MEM) + debug_printf("alloc %u block %u/%u tot %u/%u\n", + size + alignment - 1, + block->used, DATA_BLOCK_SIZE, + scene->scene_size, LP_SCENE_MAX_SIZE); + + if (block->used + size + alignment - 1 > DATA_BLOCK_SIZE) { + block = lp_scene_new_data_block( scene ); + if (!block) return NULL; } - scene->scene_size += size; - { - ubyte *data = tail->data + tail->used; + ubyte *data = block->data + block->used; unsigned offset = (((uintptr_t)data + alignment - 1) & ~(alignment - 1)) - (uintptr_t)data; - tail->used += offset + size; + block->used += offset + size; return data + offset; } } @@ -235,9 +266,8 @@ static INLINE void lp_scene_putback_data( struct lp_scene *scene, unsigned size) { struct data_block_list *list = &scene->data; - scene->scene_size -= size; - assert(list->tail->used >= size); - list->tail->used -= size; + assert(list->head && list->head->used >= size); + list->head->used -= size; } @@ -256,55 +286,55 @@ lp_scene_bin_reset(struct lp_scene *scene, unsigned x, unsigned y); /* Add a command to bin[x][y]. */ -static INLINE void +static INLINE boolean lp_scene_bin_command( struct lp_scene *scene, - unsigned x, unsigned y, - lp_rast_cmd cmd, - union lp_rast_cmd_arg arg ) + unsigned x, unsigned y, + unsigned cmd, + union lp_rast_cmd_arg arg ) { struct cmd_bin *bin = lp_scene_get_bin(scene, x, y); - struct cmd_block_list *list = &bin->commands; - struct cmd_block *tail = list->tail; + struct cmd_block *tail = bin->tail; assert(x < scene->tiles_x); assert(y < scene->tiles_y); + assert(cmd <= LP_RAST_OP_END_QUERY); - if (tail->count == CMD_BLOCK_MAX) { - tail = lp_bin_new_cmd_block( list ); + if (tail == NULL || tail->count == CMD_BLOCK_MAX) { + tail = lp_scene_new_cmd_block( scene, bin ); if (!tail) { - /* out of memory - simply ignore this command (for now) */ - return; + return FALSE; } assert(tail->count == 0); } { unsigned i = tail->count; - tail->cmd[i] = cmd; + tail->cmd[i] = cmd & LP_RAST_OP_MASK; tail->arg[i] = arg; tail->count++; } + + return TRUE; } /* Add a command to all active bins. */ -static INLINE void +static INLINE boolean lp_scene_bin_everywhere( struct lp_scene *scene, - lp_rast_cmd cmd, + unsigned cmd, const union lp_rast_cmd_arg arg ) { unsigned i, j; - for (i = 0; i < scene->tiles_x; i++) - for (j = 0; j < scene->tiles_y; j++) - lp_scene_bin_command( scene, i, j, cmd, arg ); -} - + for (i = 0; i < scene->tiles_x; i++) { + for (j = 0; j < scene->tiles_y; j++) { + if (!lp_scene_bin_command( scene, i, j, cmd, arg )) + return FALSE; + } + } -void -lp_scene_bin_state_command( struct lp_scene *scene, - lp_rast_cmd cmd, - const union lp_rast_cmd_arg arg ); + return TRUE; +} static INLINE unsigned @@ -318,23 +348,30 @@ void lp_scene_bin_iter_begin( struct lp_scene *scene ); struct cmd_bin * -lp_scene_bin_iter_next( struct lp_scene *scene, int *bin_x, int *bin_y ); +lp_scene_bin_iter_next( struct lp_scene *scene ); -void -lp_scene_rasterize( struct lp_scene *scene, - struct lp_rasterizer *rast ); +/* Begin/end binning of a scene + */ void lp_scene_begin_binning( struct lp_scene *scene, struct pipe_framebuffer_state *fb ); +void +lp_scene_end_binning( struct lp_scene *scene ); + + +/* Begin/end rasterization of a scene + */ +void +lp_scene_begin_rasterization(struct lp_scene *scene); + +void +lp_scene_end_rasterization(struct lp_scene *scene ); + + -static INLINE unsigned -lp_scene_get_size(const struct lp_scene *scene) -{ - return scene->scene_size; -} #endif /* LP_BIN_H */ diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 1e65a91fc67..0d40dc50201 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -33,8 +33,8 @@ #include "util/u_format_s3tc.h" #include "pipe/p_defines.h" #include "pipe/p_screen.h" +#include "draw/draw_context.h" -#include "gallivm/lp_bld_limits.h" #include "lp_texture.h" #include "lp_fence.h" #include "lp_jit.h" @@ -63,6 +63,7 @@ static const struct debug_named_value lp_debug_flags[] = { { "counters", DEBUG_COUNTERS, NULL }, { "scene", DEBUG_SCENE, NULL }, { "fence", DEBUG_FENCE, NULL }, + { "mem", DEBUG_MEM, NULL }, DEBUG_NAMED_VALUE_END }; #endif @@ -131,8 +132,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return LP_MAX_TEXTURE_3D_LEVELS; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return LP_MAX_TEXTURE_2D_LEVELS; - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 1; case PIPE_CAP_BLEND_EQUATION_SEPARATE: return 1; case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -145,47 +144,29 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: return 0; - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - /* There is no limit in number of instructions beyond available memory */ - return 32768; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - return LP_MAX_TGSI_NESTING; - case PIPE_CAP_MAX_VS_INPUTS: - case PIPE_CAP_MAX_FS_INPUTS: - return PIPE_MAX_ATTRIBS; - case PIPE_CAP_MAX_FS_CONSTS: - case PIPE_CAP_MAX_VS_CONSTS: - /* There is no limit in number of constants beyond available memory */ - return 32768; - case PIPE_CAP_MAX_VS_TEMPS: - case PIPE_CAP_MAX_FS_TEMPS: - return LP_MAX_TGSI_TEMPS; - case PIPE_CAP_MAX_VS_ADDRS: - case PIPE_CAP_MAX_FS_ADDRS: - return LP_MAX_TGSI_ADDRS; - case PIPE_CAP_MAX_VS_PREDS: - case PIPE_CAP_MAX_FS_PREDS: - return LP_MAX_TGSI_PREDS; case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: return 1; - case PIPE_CAP_GEOMETRY_SHADER4: - return 1; case PIPE_CAP_DEPTH_CLAMP: return 0; default: - assert(0); return 0; } } +static int +llvmpipe_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) + { + case PIPE_SHADER_FRAGMENT: + return tgsi_exec_get_shader_param(param); + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_GEOMETRY: + return draw_get_shader_param(shader, param); + default: + return 0; + } +} static float llvmpipe_get_paramf(struct pipe_screen *screen, enum pipe_cap param) @@ -401,6 +382,7 @@ llvmpipe_create_screen(struct sw_winsys *winsys) screen->base.get_name = llvmpipe_get_name; screen->base.get_vendor = llvmpipe_get_vendor; screen->base.get_param = llvmpipe_get_param; + screen->base.get_shader_param = llvmpipe_get_shader_param; screen->base.get_paramf = llvmpipe_get_paramf; screen->base.is_format_supported = llvmpipe_is_format_supported; diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c index 3da9097154e..e6a81967615 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup.c +++ b/src/gallium/drivers/llvmpipe/lp_setup.c @@ -42,7 +42,6 @@ #include "lp_context.h" #include "lp_memory.h" #include "lp_scene.h" -#include "lp_scene_queue.h" #include "lp_texture.h" #include "lp_debug.h" #include "lp_fence.h" @@ -57,36 +56,31 @@ #include "draw/draw_vbuf.h" -static void set_scene_state( struct lp_setup_context *, enum setup_state ); +static void set_scene_state( struct lp_setup_context *, enum setup_state, + const char *reason); +static boolean try_update_scene_state( struct lp_setup_context *setup ); -struct lp_scene * -lp_setup_get_current_scene(struct lp_setup_context *setup) +static void +lp_setup_get_empty_scene(struct lp_setup_context *setup) { - if (!setup->scene) { - set_scene_state( setup, SETUP_EMPTY ); - } - return setup->scene; -} + assert(setup->scene == NULL); + setup->scene_idx++; + setup->scene_idx %= Elements(setup->scenes); -/** - * Check if the size of the current scene has exceeded the limit. - * If so, flush/render it. - */ -static void -setup_check_scene_size_and_flush(struct lp_setup_context *setup) -{ - if (setup->scene) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); - unsigned size = lp_scene_get_size(scene); + setup->scene = setup->scenes[setup->scene_idx]; - if (size > LP_MAX_SCENE_SIZE) { - /*printf("LLVMPIPE: scene size = %u, flushing.\n", size);*/ - set_scene_state( setup, SETUP_FLUSHED ); - /*assert(lp_scene_get_size(scene) == 0);*/ - } + if (setup->scene->fence) { + if (LP_DEBUG & DEBUG_SETUP) + debug_printf("%s: wait for scene %d\n", + __FUNCTION__, setup->scene->fence->id); + + lp_fence_wait(setup->scene->fence); } + + lp_scene_begin_binning(setup->scene, &setup->fb); + } @@ -96,7 +90,7 @@ first_triangle( struct lp_setup_context *setup, const float (*v1)[4], const float (*v2)[4]) { - set_scene_state( setup, SETUP_ACTIVE ); + assert(setup->state == SETUP_ACTIVE); lp_setup_choose_triangle( setup ); setup->triangle( setup, v0, v1, v2 ); } @@ -106,7 +100,7 @@ first_line( struct lp_setup_context *setup, const float (*v0)[4], const float (*v1)[4]) { - set_scene_state( setup, SETUP_ACTIVE ); + assert(setup->state == SETUP_ACTIVE); lp_setup_choose_line( setup ); setup->line( setup, v0, v1 ); } @@ -115,12 +109,12 @@ static void first_point( struct lp_setup_context *setup, const float (*v0)[4]) { - set_scene_state( setup, SETUP_ACTIVE ); + assert(setup->state == SETUP_ACTIVE); lp_setup_choose_point( setup ); setup->point( setup, v0 ); } -static void reset_context( struct lp_setup_context *setup ) +static void lp_setup_reset( struct lp_setup_context *setup ) { LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__); @@ -135,8 +129,7 @@ static void reset_context( struct lp_setup_context *setup ) /* Reset some state: */ - setup->clear.flags = 0; - setup->clear.clearzs.clearzs_mask = 0; + memset(&setup->clear, 0, sizeof setup->clear); /* Have an explicit "start-binning" call and get rid of this * pointer twiddling? @@ -151,14 +144,23 @@ static void reset_context( struct lp_setup_context *setup ) static void lp_setup_rasterize_scene( struct lp_setup_context *setup ) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); + struct lp_scene *scene = setup->scene; struct llvmpipe_screen *screen = llvmpipe_screen(scene->pipe->screen); + lp_scene_end_binning(scene); + + lp_fence_reference(&setup->last_fence, scene->fence); + + if (setup->last_fence) + setup->last_fence->issued = TRUE; + pipe_mutex_lock(screen->rast_mutex); - lp_scene_rasterize(scene, screen->rast); + lp_rast_queue_scene(screen->rast, scene); + lp_rast_finish(screen->rast); pipe_mutex_unlock(screen->rast_mutex); - reset_context( setup ); + lp_scene_end_rasterization(setup->scene); + lp_setup_reset( setup ); LP_DBG(DEBUG_SETUP, "%s done \n", __FUNCTION__); } @@ -168,8 +170,30 @@ lp_setup_rasterize_scene( struct lp_setup_context *setup ) static void begin_binning( struct lp_setup_context *setup ) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); + struct lp_scene *scene = setup->scene; boolean need_zsload = FALSE; + boolean ok; + unsigned i, j; + + assert(scene); + assert(scene->fence == NULL); + + /* Always create a fence: + */ + scene->fence = lp_fence_create(MAX2(1, setup->num_threads)); + + /* Initialize the bin flags and x/y coords: + */ + for (i = 0; i < scene->tiles_x; i++) { + for (j = 0; j < scene->tiles_y; j++) { + scene->tile[i][j].x = i; + scene->tile[i][j].y = j; + } + } + + ok = try_update_scene_state(setup); + assert(ok); + if (setup->fb.zsbuf && ((setup->clear.flags & PIPE_CLEAR_DEPTHSTENCIL) != PIPE_CLEAR_DEPTHSTENCIL) && util_format_is_depth_and_stencil(setup->fb.zsbuf->format)) @@ -181,10 +205,10 @@ begin_binning( struct lp_setup_context *setup ) if (setup->fb.nr_cbufs) { if (setup->clear.flags & PIPE_CLEAR_COLOR) { - lp_scene_bin_everywhere( scene, - lp_rast_clear_color, - setup->clear.color ); - scene->has_color_clear = TRUE; + ok = lp_scene_bin_everywhere( scene, + LP_RAST_OP_CLEAR_COLOR, + setup->clear.color ); + assert(ok); } } @@ -192,12 +216,27 @@ begin_binning( struct lp_setup_context *setup ) if (setup->clear.flags & PIPE_CLEAR_DEPTHSTENCIL) { if (!need_zsload) scene->has_depthstencil_clear = TRUE; - lp_scene_bin_everywhere( scene, - lp_rast_clear_zstencil, - lp_rast_arg_clearzs(&setup->clear.clearzs) ); + ok = lp_scene_bin_everywhere( scene, + LP_RAST_OP_CLEAR_ZSTENCIL, + lp_rast_arg_clearzs( + setup->clear.zsvalue, + setup->clear.zsmask)); + assert(ok); } } + if (setup->active_query) { + ok = lp_scene_bin_everywhere( scene, + LP_RAST_OP_BEGIN_QUERY, + lp_rast_arg_query(setup->active_query) ); + assert(ok); + } + + + setup->clear.flags = 0; + setup->clear.zsmask = 0; + setup->clear.zsvalue = 0; + LP_DBG(DEBUG_SETUP, "%s done\n", __FUNCTION__); } @@ -213,51 +252,56 @@ execute_clears( struct lp_setup_context *setup ) LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__); begin_binning( setup ); - lp_setup_rasterize_scene( setup ); } +const char *states[] = { + "FLUSHED", + "EMPTY ", + "CLEARED", + "ACTIVE " +}; + static void set_scene_state( struct lp_setup_context *setup, - enum setup_state new_state ) + enum setup_state new_state, + const char *reason) { unsigned old_state = setup->state; if (old_state == new_state) return; - - LP_DBG(DEBUG_SETUP, "%s old %d new %d\n", __FUNCTION__, old_state, new_state); - - switch (new_state) { - case SETUP_EMPTY: - assert(old_state == SETUP_FLUSHED); - assert(setup->scene == NULL); + + if (LP_DEBUG & DEBUG_SCENE) { + debug_printf("%s old %s new %s%s%s\n", + __FUNCTION__, + states[old_state], + states[new_state], + (new_state == SETUP_FLUSHED) ? ": " : "", + (new_state == SETUP_FLUSHED) ? reason : ""); + + if (new_state == SETUP_FLUSHED && setup->scene) + lp_debug_draw_bins_by_cmd_length(setup->scene); + } - /* wait for a free/empty scene - */ - setup->scene = lp_scene_dequeue(setup->empty_scenes, TRUE); - assert(lp_scene_is_empty(setup->scene)); - lp_scene_begin_binning(setup->scene, - &setup->fb ); - break; + /* wait for a free/empty scene + */ + if (old_state == SETUP_FLUSHED) + lp_setup_get_empty_scene(setup); + switch (new_state) { case SETUP_CLEARED: - assert(old_state == SETUP_EMPTY); - assert(setup->scene != NULL); break; case SETUP_ACTIVE: - assert(old_state == SETUP_EMPTY || - old_state == SETUP_CLEARED); - assert(setup->scene != NULL); begin_binning( setup ); break; case SETUP_FLUSHED: if (old_state == SETUP_CLEARED) execute_clears( setup ); - else - lp_setup_rasterize_scene( setup ); + + lp_setup_rasterize_scene( setup ); assert(setup->scene == NULL); break; @@ -278,21 +322,11 @@ lp_setup_flush( struct lp_setup_context *setup, struct pipe_fence_handle **fence, const char *reason) { - LP_DBG(DEBUG_SETUP, "%s %s\n", __FUNCTION__, reason); - - if (setup->scene) { - if (fence) { - /* if we're going to flush the setup/rasterization modules, emit - * a fence. - */ - *fence = lp_setup_fence( setup ); - } + set_scene_state( setup, SETUP_FLUSHED, reason ); - if (setup->scene->fence) - setup->scene->fence->issued = TRUE; + if (fence) { + lp_fence_reference((struct lp_fence **)fence, setup->last_fence); } - - set_scene_state( setup, SETUP_FLUSHED ); } @@ -304,7 +338,7 @@ lp_setup_bind_framebuffer( struct lp_setup_context *setup, /* Flush any old scene. */ - set_scene_state( setup, SETUP_FLUSHED ); + set_scene_state( setup, SETUP_FLUSHED, __FUNCTION__ ); /* * Ensure the old scene is not reused. @@ -323,78 +357,41 @@ lp_setup_bind_framebuffer( struct lp_setup_context *setup, } -void -lp_setup_clear( struct lp_setup_context *setup, - const float *color, - double depth, - unsigned stencil, - unsigned flags ) +static boolean +lp_setup_try_clear( struct lp_setup_context *setup, + const float *color, + double depth, + unsigned stencil, + unsigned flags ) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); + uint32_t zsmask = 0; + uint32_t zsvalue = 0; + union lp_rast_cmd_arg color_arg; unsigned i; - boolean full_zs_clear = TRUE; - uint32_t mask = 0; LP_DBG(DEBUG_SETUP, "%s state %d\n", __FUNCTION__, setup->state); - if (flags & PIPE_CLEAR_COLOR) { - for (i = 0; i < 4; ++i) - setup->clear.color.clear_color[i] = float_to_ubyte(color[i]); + for (i = 0; i < 4; i++) + color_arg.clear_color[i] = float_to_ubyte(color[i]); } if (flags & PIPE_CLEAR_DEPTHSTENCIL) { - if (setup->fb.zsbuf && - ((flags & PIPE_CLEAR_DEPTHSTENCIL) != PIPE_CLEAR_DEPTHSTENCIL) && - util_format_is_depth_and_stencil(setup->fb.zsbuf->format)) - full_zs_clear = FALSE; - - if (full_zs_clear) { - setup->clear.clearzs.clearzs_value = - util_pack_z_stencil(setup->fb.zsbuf->format, - depth, - stencil); - setup->clear.clearzs.clearzs_mask = 0xffffffff; - } - else { - /* hmm */ - uint32_t tmpval; - if (flags & PIPE_CLEAR_DEPTH) { - tmpval = util_pack_z(setup->fb.zsbuf->format, - depth); - switch (setup->fb.zsbuf->format) { - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: - mask = 0xffffff; - break; - case PIPE_FORMAT_S8_USCALED_Z24_UNORM: - mask = 0xffffff00; - break; - default: - assert(0); - } - } - else { - switch (setup->fb.zsbuf->format) { - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: - mask = 0xff000000; - tmpval = stencil << 24; - break; - case PIPE_FORMAT_S8_USCALED_Z24_UNORM: - mask = 0xff; - tmpval = stencil; - break; - default: - assert(0); - tmpval = 0; - } - } - setup->clear.clearzs.clearzs_mask |= mask; - setup->clear.clearzs.clearzs_value = - (setup->clear.clearzs.clearzs_value & ~mask) | (tmpval & mask); - } + unsigned zmask = (flags & PIPE_CLEAR_DEPTH) ? ~0 : 0; + unsigned smask = (flags & PIPE_CLEAR_STENCIL) ? ~0 : 0; + + zsvalue = util_pack_z_stencil(setup->fb.zsbuf->format, + depth, + stencil); + + zsmask = util_pack_uint_z_stencil(setup->fb.zsbuf->format, + zmask, + smask); } if (setup->state == SETUP_ACTIVE) { + struct lp_scene *scene = setup->scene; + /* Add the clear to existing scene. In the unusual case where * both color and depth-stencil are being cleared when there's * already been some rendering, we could discard the currently @@ -402,24 +399,18 @@ lp_setup_clear( struct lp_setup_context *setup, * a common usage. */ if (flags & PIPE_CLEAR_COLOR) { - lp_scene_bin_everywhere( scene, - lp_rast_clear_color, - setup->clear.color ); - scene->has_color_clear = TRUE; + if (!lp_scene_bin_everywhere( scene, + LP_RAST_OP_CLEAR_COLOR, + color_arg )) + return FALSE; } if (flags & PIPE_CLEAR_DEPTHSTENCIL) { - if (full_zs_clear) - scene->has_depthstencil_clear = TRUE; - else - setup->clear.clearzs.clearzs_mask = mask; - lp_scene_bin_everywhere( scene, - lp_rast_clear_zstencil, - lp_rast_arg_clearzs(&setup->clear.clearzs) ); - - + if (!lp_scene_bin_everywhere( scene, + LP_RAST_OP_CLEAR_ZSTENCIL, + lp_rast_arg_clearzs(zsvalue, zsmask) )) + return FALSE; } - } else { /* Put ourselves into the 'pre-clear' state, specifically to try @@ -427,42 +418,43 @@ lp_setup_clear( struct lp_setup_context *setup, * buffers which the app or state-tracker might issue * separately. */ - set_scene_state( setup, SETUP_CLEARED ); + set_scene_state( setup, SETUP_CLEARED, __FUNCTION__ ); setup->clear.flags |= flags; + + if (flags & PIPE_CLEAR_DEPTHSTENCIL) { + setup->clear.zsmask |= zsmask; + setup->clear.zsvalue = + (setup->clear.zsvalue & ~zsmask) | (zsvalue & zsmask); + } + + if (flags & PIPE_CLEAR_COLOR) { + memcpy(setup->clear.color.clear_color, + &color_arg, + sizeof color_arg); + } } + + return TRUE; } - -/** - * Emit a fence. - */ -struct pipe_fence_handle * -lp_setup_fence( struct lp_setup_context *setup ) +void +lp_setup_clear( struct lp_setup_context *setup, + const float *color, + double depth, + unsigned stencil, + unsigned flags ) { - if (setup->scene == NULL) - return NULL; - else if (setup->num_threads == 0) - return NULL; - else - { - struct lp_scene *scene = lp_setup_get_current_scene(setup); - const unsigned rank = setup->num_threads; + if (!lp_setup_try_clear( setup, color, depth, stencil, flags )) { + lp_setup_flush(setup, 0, NULL, __FUNCTION__); - set_scene_state( setup, SETUP_ACTIVE ); - - assert(scene->fence == NULL); + if (!lp_setup_try_clear( setup, color, depth, stencil, flags )) + assert(0); + } +} - /* The caller gets a reference, we keep a copy too, so need to - * bump the refcount: - */ - lp_fence_reference(&scene->fence, lp_fence_create(rank)); - LP_DBG(DEBUG_SETUP, "%s rank %u\n", __FUNCTION__, rank); - return (struct pipe_fence_handle *) scene->fence; - } -} void @@ -725,58 +717,33 @@ lp_setup_is_resource_referenced( const struct lp_setup_context *setup, /** * Called by vbuf code when we're about to draw something. */ -void -lp_setup_update_state( struct lp_setup_context *setup ) +static boolean +try_update_scene_state( struct lp_setup_context *setup ) { - struct lp_scene *scene; + boolean new_scene = (setup->fs.stored == NULL); + struct lp_scene *scene = setup->scene; - LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__); - - setup_check_scene_size_and_flush(setup); - - scene = lp_setup_get_current_scene(setup); - - assert(setup->fs.current.variant); - - /* Some of the 'draw' pipeline stages may have changed some driver state. - * Make sure we've processed those state changes before anything else. - * - * XXX this is the only place where llvmpipe_context is used in the - * setup code. This may get refactored/changed... - */ - { - struct llvmpipe_context *lp = llvmpipe_context(scene->pipe); - - /* Will probably need to move this somewhere else, just need - * to know about vertex shader point size attribute. - */ - setup->psize = lp->psize_slot; - - if (lp->dirty) { - llvmpipe_update_derived(lp); - } - assert(lp->dirty == 0); - } + assert(scene); if(setup->dirty & LP_SETUP_NEW_BLEND_COLOR) { uint8_t *stored; unsigned i, j; stored = lp_scene_alloc_aligned(scene, 4 * 16, 16); + if (!stored) { + assert(!new_scene); + return FALSE; + } - if (stored) { - /* smear each blend color component across 16 ubyte elements */ - for (i = 0; i < 4; ++i) { - uint8_t c = float_to_ubyte(setup->blend_color.current.color[i]); - for (j = 0; j < 16; ++j) - stored[i*16 + j] = c; - } - - setup->blend_color.stored = stored; - - setup->fs.current.jit_context.blend_color = setup->blend_color.stored; + /* smear each blend color component across 16 ubyte elements */ + for (i = 0; i < 4; ++i) { + uint8_t c = float_to_ubyte(setup->blend_color.current.color[i]); + for (j = 0; j < 16; ++j) + stored[i*16 + j] = c; } + setup->blend_color.stored = stored; + setup->fs.current.jit_context.blend_color = setup->blend_color.stored; setup->dirty |= LP_SETUP_NEW_FS; } @@ -797,13 +764,16 @@ lp_setup_update_state( struct lp_setup_context *setup ) void *stored; stored = lp_scene_alloc(scene, current_size); - if(stored) { - memcpy(stored, - current_data, - current_size); - setup->constants.stored_size = current_size; - setup->constants.stored_data = stored; + if (!stored) { + assert(!new_scene); + return FALSE; } + + memcpy(stored, + current_data, + current_size); + setup->constants.stored_size = current_size; + setup->constants.stored_data = stored; } } else { @@ -816,31 +786,42 @@ lp_setup_update_state( struct lp_setup_context *setup ) } - if(setup->dirty & LP_SETUP_NEW_FS) { - if(!setup->fs.stored || - memcmp(setup->fs.stored, - &setup->fs.current, - sizeof setup->fs.current) != 0) { + if (setup->dirty & LP_SETUP_NEW_FS) { + if (!setup->fs.stored || + memcmp(setup->fs.stored, + &setup->fs.current, + sizeof setup->fs.current) != 0) + { + struct lp_rast_state *stored; + uint i; + /* The fs state that's been stored in the scene is different from * the new, current state. So allocate a new lp_rast_state object * and append it to the bin's setup data buffer. */ - uint i; - struct lp_rast_state *stored = - (struct lp_rast_state *) lp_scene_alloc(scene, sizeof *stored); - if(stored) { - memcpy(stored, - &setup->fs.current, - sizeof setup->fs.current); - setup->fs.stored = stored; + stored = (struct lp_rast_state *) lp_scene_alloc(scene, sizeof *stored); + if (!stored) { + assert(!new_scene); + return FALSE; } + memcpy(stored, + &setup->fs.current, + sizeof setup->fs.current); + setup->fs.stored = stored; + /* The scene now references the textures in the rasterization * state record. Note that now. */ for (i = 0; i < Elements(setup->fs.current_tex); i++) { - if (setup->fs.current_tex[i]) - lp_scene_add_resource_reference(scene, setup->fs.current_tex[i]); + if (setup->fs.current_tex[i]) { + if (!lp_scene_add_resource_reference(scene, + setup->fs.current_tex[i], + new_scene)) { + assert(!new_scene); + return FALSE; + } + } } } } @@ -856,6 +837,47 @@ lp_setup_update_state( struct lp_setup_context *setup ) setup->dirty = 0; assert(setup->fs.stored); + return TRUE; +} + +void +lp_setup_update_state( struct lp_setup_context *setup, + boolean update_scene ) +{ + /* Some of the 'draw' pipeline stages may have changed some driver state. + * Make sure we've processed those state changes before anything else. + * + * XXX this is the only place where llvmpipe_context is used in the + * setup code. This may get refactored/changed... + */ + { + struct llvmpipe_context *lp = llvmpipe_context(setup->pipe); + if (lp->dirty) { + llvmpipe_update_derived(lp); + } + + /* Will probably need to move this somewhere else, just need + * to know about vertex shader point size attribute. + */ + setup->psize = lp->psize_slot; + + assert(lp->dirty == 0); + } + + if (update_scene) + set_scene_state( setup, SETUP_ACTIVE, __FUNCTION__ ); + + /* Only call into update_scene_state() if we already have a + * scene: + */ + if (update_scene && setup->scene) { + assert(setup->state == SETUP_ACTIVE); + if (!try_update_scene_state(setup)) { + lp_setup_flush_and_restart(setup); + if (!try_update_scene_state(setup)) + assert(0); + } + } } @@ -867,7 +889,7 @@ lp_setup_destroy( struct lp_setup_context *setup ) { uint i; - reset_context( setup ); + lp_setup_reset( setup ); util_unreference_framebuffer_state(&setup->fb); @@ -878,15 +900,15 @@ lp_setup_destroy( struct lp_setup_context *setup ) pipe_resource_reference(&setup->constants.current, NULL); /* free the scenes in the 'empty' queue */ - while (1) { - struct lp_scene *scene = lp_scene_dequeue(setup->empty_scenes, FALSE); - if (!scene) - break; + for (i = 0; i < Elements(setup->scenes); i++) { + struct lp_scene *scene = setup->scenes[i]; + + if (scene->fence) + lp_fence_wait(scene->fence); + lp_scene_destroy(scene); } - lp_scene_queue_destroy(setup->empty_scenes); - FREE( setup ); } @@ -908,10 +930,11 @@ lp_setup_create( struct pipe_context *pipe, return NULL; lp_setup_init_vbuf(setup); + + /* Used only in update_state(): + */ + setup->pipe = pipe; - setup->empty_scenes = lp_scene_queue_create(); - if (!setup->empty_scenes) - goto fail; setup->num_threads = screen->num_threads; setup->vbuf = draw_vbuf_stage(draw, &setup->base); @@ -923,9 +946,7 @@ lp_setup_create( struct pipe_context *pipe, /* create some empty scenes */ for (i = 0; i < MAX_SCENES; i++) { - setup->scenes[i] = lp_scene_create( pipe, setup->empty_scenes ); - - lp_scene_enqueue(setup->empty_scenes, setup->scenes[i]); + setup->scenes[i] = lp_scene_create( pipe ); } setup->triangle = first_triangle; @@ -940,9 +961,6 @@ fail: if (setup->vbuf) ; - if (setup->empty_scenes) - lp_scene_queue_destroy(setup->empty_scenes); - FREE(setup); return NULL; } @@ -955,22 +973,26 @@ void lp_setup_begin_query(struct lp_setup_context *setup, struct llvmpipe_query *pq) { - struct lp_scene * scene = lp_setup_get_current_scene(setup); - union lp_rast_cmd_arg cmd_arg; - /* init the query to its beginning state */ - pq->done = FALSE; - pq->tile_count = 0; - pq->num_tiles = scene->tiles_x * scene->tiles_y; - assert(pq->num_tiles > 0); + assert(setup->active_query == NULL); + + if (setup->scene) { + if (!lp_scene_bin_everywhere(setup->scene, + LP_RAST_OP_BEGIN_QUERY, + lp_rast_arg_query(pq))) { - memset(pq->count, 0, sizeof(pq->count)); /* reset all counters */ + lp_setup_flush_and_restart(setup); - set_scene_state( setup, SETUP_ACTIVE ); + if (!lp_scene_bin_everywhere(setup->scene, + LP_RAST_OP_BEGIN_QUERY, + lp_rast_arg_query(pq))) { + assert(0); + return; + } + } + } - cmd_arg.query_obj = pq; - lp_scene_bin_everywhere(scene, lp_rast_begin_query, cmd_arg); - pq->binned = TRUE; + setup->active_query = pq; } @@ -980,11 +1002,42 @@ lp_setup_begin_query(struct lp_setup_context *setup, void lp_setup_end_query(struct lp_setup_context *setup, struct llvmpipe_query *pq) { - struct lp_scene * scene = lp_setup_get_current_scene(setup); - union lp_rast_cmd_arg cmd_arg; + union lp_rast_cmd_arg dummy = { 0 }; + + assert(setup->active_query == pq); + setup->active_query = NULL; - set_scene_state( setup, SETUP_ACTIVE ); + /* Setup will automatically re-issue any query which carried over a + * scene boundary, and the rasterizer automatically "ends" queries + * which are active at the end of a scene, so there is no need to + * retry this commands on failure. + */ + if (setup->scene) { + /* pq->fence should be the fence of the *last* scene which + * contributed to the query result. + */ + lp_fence_reference(&pq->fence, setup->scene->fence); - cmd_arg.query_obj = pq; - lp_scene_bin_everywhere(scene, lp_rast_end_query, cmd_arg); + if (!lp_scene_bin_everywhere(setup->scene, + LP_RAST_OP_END_QUERY, + dummy)) { + lp_setup_flush(setup, 0, NULL, __FUNCTION__); + } + } + else { + lp_fence_reference(&pq->fence, setup->last_fence); + } } + + +void +lp_setup_flush_and_restart(struct lp_setup_context *setup) +{ + if (0) debug_printf("%s\n", __FUNCTION__); + + assert(setup->state == SETUP_ACTIVE); + set_scene_state(setup, SETUP_FLUSHED, __FUNCTION__); + lp_setup_update_state(setup, TRUE); +} + + diff --git a/src/gallium/drivers/llvmpipe/lp_setup.h b/src/gallium/drivers/llvmpipe/lp_setup.h index 821ebb1087d..b94061b7d49 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup.h +++ b/src/gallium/drivers/llvmpipe/lp_setup.h @@ -65,6 +65,7 @@ struct pipe_framebuffer_state; struct lp_fragment_shader_variant; struct lp_jit_context; struct llvmpipe_query; +struct pipe_fence_handle; struct lp_setup_context * @@ -78,8 +79,6 @@ lp_setup_clear(struct lp_setup_context *setup, unsigned clear_stencil, unsigned flags); -struct pipe_fence_handle * -lp_setup_fence( struct lp_setup_context *setup ); void diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef.c b/src/gallium/drivers/llvmpipe/lp_setup_coef.c index 95e3e8fffe8..8dc2688ddb6 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_coef.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_coef.c @@ -187,11 +187,32 @@ static void setup_facing_coef( struct lp_rast_shader_inputs *inputs, */ void lp_setup_tri_coef( struct lp_setup_context *setup, struct lp_rast_shader_inputs *inputs, - const struct lp_tri_info *info) + const float (*v0)[4], + const float (*v1)[4], + const float (*v2)[4], + boolean frontfacing) { unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ; unsigned slot; unsigned i; + struct lp_tri_info info; + float dx01 = v0[0][0] - v1[0][0]; + float dy01 = v0[0][1] - v1[0][1]; + float dx20 = v2[0][0] - v0[0][0]; + float dy20 = v2[0][1] - v0[0][1]; + float oneoverarea = 1.0f / (dx01 * dy20 - dx20 * dy01); + + info.v0 = v0; + info.v1 = v1; + info.v2 = v2; + info.frontfacing = frontfacing; + info.x0_center = v0[0][0] - setup->pixel_offset; + info.y0_center = v0[0][1] - setup->pixel_offset; + info.dx01_ooa = dx01 * oneoverarea; + info.dx20_ooa = dx20 * oneoverarea; + info.dy01_ooa = dy01 * oneoverarea; + info.dy20_ooa = dy20 * oneoverarea; + /* setup interpolation for all the remaining attributes: */ @@ -204,25 +225,25 @@ void lp_setup_tri_coef( struct lp_setup_context *setup, if (setup->flatshade_first) { for (i = 0; i < NUM_CHANNELS; i++) if (usage_mask & (1 << i)) - constant_coef(inputs, slot+1, info->v0[vert_attr][i], i); + constant_coef(inputs, slot+1, info.v0[vert_attr][i], i); } else { for (i = 0; i < NUM_CHANNELS; i++) if (usage_mask & (1 << i)) - constant_coef(inputs, slot+1, info->v2[vert_attr][i], i); + constant_coef(inputs, slot+1, info.v2[vert_attr][i], i); } break; case LP_INTERP_LINEAR: for (i = 0; i < NUM_CHANNELS; i++) if (usage_mask & (1 << i)) - linear_coef(inputs, info, slot+1, vert_attr, i); + linear_coef(inputs, &info, slot+1, vert_attr, i); break; case LP_INTERP_PERSPECTIVE: for (i = 0; i < NUM_CHANNELS; i++) if (usage_mask & (1 << i)) - perspective_coef(inputs, info, slot+1, vert_attr, i); + perspective_coef(inputs, &info, slot+1, vert_attr, i); fragcoord_usage_mask |= TGSI_WRITEMASK_W; break; @@ -236,7 +257,7 @@ void lp_setup_tri_coef( struct lp_setup_context *setup, break; case LP_INTERP_FACING: - setup_facing_coef(inputs, slot+1, info->frontfacing, usage_mask); + setup_facing_coef(inputs, slot+1, info.frontfacing, usage_mask); break; default: @@ -246,7 +267,7 @@ void lp_setup_tri_coef( struct lp_setup_context *setup, /* The internal position input is in slot zero: */ - setup_fragcoord_coef(inputs, info, 0, fragcoord_usage_mask); + setup_fragcoord_coef(inputs, &info, 0, fragcoord_usage_mask); } #else diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef.h b/src/gallium/drivers/llvmpipe/lp_setup_coef.h index d68b39c603f..87a3255ccc6 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_coef.h +++ b/src/gallium/drivers/llvmpipe/lp_setup_coef.h @@ -56,6 +56,9 @@ struct lp_tri_info { void lp_setup_tri_coef( struct lp_setup_context *setup, struct lp_rast_shader_inputs *inputs, - const struct lp_tri_info *info); + const float (*v0)[4], + const float (*v1)[4], + const float (*v2)[4], + boolean frontfacing); #endif diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c index 73fb70599c9..3742fd672b2 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c @@ -151,13 +151,34 @@ static void perspective_coef( struct lp_rast_shader_inputs *inputs, */ void lp_setup_tri_coef( struct lp_setup_context *setup, struct lp_rast_shader_inputs *inputs, - const struct lp_tri_info *info) + const float (*v0)[4], + const float (*v1)[4], + const float (*v2)[4], + boolean frontfacing) { unsigned slot; + struct lp_tri_info info; + float dx01 = v0[0][0] - v1[0][0]; + float dy01 = v0[0][1] - v1[0][1]; + float dx20 = v2[0][0] - v0[0][0]; + float dy20 = v2[0][1] - v0[0][1]; + float oneoverarea = 1.0f / (dx01 * dy20 - dx20 * dy01); + + info.v0 = v0; + info.v1 = v1; + info.v2 = v2; + info.frontfacing = frontfacing; + info.x0_center = v0[0][0] - setup->pixel_offset; + info.y0_center = v0[0][1] - setup->pixel_offset; + info.dx01_ooa = dx01 * oneoverarea; + info.dx20_ooa = dx20 * oneoverarea; + info.dy01_ooa = dy01 * oneoverarea; + info.dy20_ooa = dy20 * oneoverarea; + /* The internal position input is in slot zero: */ - linear_coef(inputs, info, 0, 0); + linear_coef(inputs, &info, 0, 0); /* setup interpolation for all the remaining attributes: */ @@ -167,19 +188,19 @@ void lp_setup_tri_coef( struct lp_setup_context *setup, switch (setup->fs.input[slot].interp) { case LP_INTERP_CONSTANT: if (setup->flatshade_first) { - constant_coef4(inputs, info, slot+1, info->v0[vert_attr]); + constant_coef4(inputs, &info, slot+1, info.v0[vert_attr]); } else { - constant_coef4(inputs, info, slot+1, info->v2[vert_attr]); + constant_coef4(inputs, &info, slot+1, info.v2[vert_attr]); } break; case LP_INTERP_LINEAR: - linear_coef(inputs, info, slot+1, vert_attr); + linear_coef(inputs, &info, slot+1, vert_attr); break; case LP_INTERP_PERSPECTIVE: - perspective_coef(inputs, info, slot+1, vert_attr); + perspective_coef(inputs, &info, slot+1, vert_attr); break; case LP_INTERP_POSITION: @@ -190,7 +211,7 @@ void lp_setup_tri_coef( struct lp_setup_context *setup, break; case LP_INTERP_FACING: - setup_facing_coef(inputs, info, slot+1); + setup_facing_coef(inputs, &info, slot+1); break; default: diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h index 877a492c6d8..80b356476ab 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_context.h +++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h @@ -49,8 +49,6 @@ #define LP_SETUP_NEW_SCISSOR 0x08 -struct lp_scene_queue; - /** Max number of scenes */ #define MAX_SCENES 2 @@ -70,6 +68,7 @@ struct lp_setup_context { struct vbuf_render base; + struct pipe_context *pipe; struct vertex_info *vertex_info; uint prim; uint vertex_size; @@ -83,9 +82,12 @@ struct lp_setup_context */ struct draw_stage *vbuf; unsigned num_threads; + unsigned scene_idx; struct lp_scene *scenes[MAX_SCENES]; /**< all the scenes */ struct lp_scene *scene; /**< current scene being built */ - struct lp_scene_queue *empty_scenes; /**< queue of empty scenes */ + + struct lp_fence *last_fence; + struct llvmpipe_query *active_query; boolean flatshade_first; boolean ccw_is_frontface; @@ -105,12 +107,12 @@ struct lp_setup_context struct { unsigned flags; union lp_rast_cmd_arg color; /**< lp_rast_clear_color() cmd */ - struct lp_rast_clearzs clearzs; /**< lp_rast_clear_zstencil() cmd */ + unsigned zsmask; + unsigned zsvalue; /**< lp_rast_clear_zstencil() cmd */ } clear; enum setup_state { SETUP_FLUSHED, /**< scene is null */ - SETUP_EMPTY, /**< scene exists but has only state changes */ SETUP_CLEARED, /**< scene exists but has only clears */ SETUP_ACTIVE /**< scene exists and has at least one draw/query */ } state; @@ -156,14 +158,15 @@ void lp_setup_choose_triangle( struct lp_setup_context *setup ); void lp_setup_choose_line( struct lp_setup_context *setup ); void lp_setup_choose_point( struct lp_setup_context *setup ); -struct lp_scene *lp_setup_get_current_scene(struct lp_setup_context *setup); - void lp_setup_init_vbuf(struct lp_setup_context *setup); -void lp_setup_update_state( struct lp_setup_context *setup ); +void lp_setup_update_state( struct lp_setup_context *setup, + boolean update_scene); void lp_setup_destroy( struct lp_setup_context *setup ); +void lp_setup_flush_and_restart(struct lp_setup_context *setup); + void lp_setup_print_triangle(struct lp_setup_context *setup, const float (*v0)[4], @@ -182,11 +185,12 @@ lp_setup_alloc_triangle(struct lp_scene *scene, unsigned nr_planes, unsigned *tri_size); -void +boolean lp_setup_bin_triangle( struct lp_setup_context *setup, struct lp_rast_triangle *tri, const struct u_rect *bbox, int nr_planes ); -#endif +void lp_setup_flush_and_restart(struct lp_setup_context *setup); +#endif diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c index ce2da55cf49..9f090d1992e 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_line.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c @@ -263,12 +263,12 @@ static INLINE float fracf(float f) -static void -lp_setup_line( struct lp_setup_context *setup, +static boolean +try_setup_line( struct lp_setup_context *setup, const float (*v1)[4], const float (*v2)[4]) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); + struct lp_scene *scene = setup->scene; struct lp_rast_triangle *line; struct lp_line_info info; float width = MAX2(1.0, setup->line_width); @@ -536,13 +536,13 @@ lp_setup_line( struct lp_setup_context *setup, bbox.y1 < bbox.y0) { if (0) debug_printf("empty bounding box\n"); LP_COUNT(nr_culled_tris); - return; + return TRUE; } if (!u_rect_test_intersection(&setup->draw_region, &bbox)) { if (0) debug_printf("offscreen\n"); LP_COUNT(nr_culled_tris); - return; + return TRUE; } u_rect_find_intersection(&setup->draw_region, &bbox); @@ -552,7 +552,7 @@ lp_setup_line( struct lp_setup_context *setup, nr_planes, &tri_bytes); if (!line) - return; + return FALSE; #ifdef DEBUG line->v[0][0] = v1[0][0]; @@ -585,6 +585,8 @@ lp_setup_line( struct lp_setup_context *setup, line->inputs.facing = 1.0F; line->inputs.state = setup->fs.stored; + line->inputs.disable = FALSE; + line->inputs.opaque = FALSE; for (i = 0; i < 4; i++) { struct lp_rast_plane *plane = &line->plane[i]; @@ -687,9 +689,23 @@ lp_setup_line( struct lp_setup_context *setup, line->plane[7].eo = 0; } - lp_setup_bin_triangle(setup, line, &bbox, nr_planes); + return lp_setup_bin_triangle(setup, line, &bbox, nr_planes); } - + + +static void lp_setup_line( struct lp_setup_context *setup, + const float (*v0)[4], + const float (*v1)[4] ) +{ + if (!try_setup_line( setup, v0, v1 )) + { + lp_setup_flush_and_restart(setup); + + if (!try_setup_line( setup, v0, v1 )) + assert(0); + } +} + void lp_setup_choose_line( struct lp_setup_context *setup ) { diff --git a/src/gallium/drivers/llvmpipe/lp_setup_point.c b/src/gallium/drivers/llvmpipe/lp_setup_point.c index 6ae318d328d..55389871518 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_point.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_point.c @@ -210,8 +210,9 @@ subpixel_snap(float a) } -static void lp_setup_point( struct lp_setup_context *setup, - const float (*v0)[4] ) +static boolean +try_setup_point( struct lp_setup_context *setup, + const float (*v0)[4] ) { /* x/y positions in fixed point */ const int sizeAttr = setup->psize; @@ -228,7 +229,7 @@ static void lp_setup_point( struct lp_setup_context *setup, const int x0 = subpixel_snap(v0[0][0] - setup->pixel_offset) - fixed_width/2; const int y0 = subpixel_snap(v0[0][1] - setup->pixel_offset) - fixed_width/2; - struct lp_scene *scene = lp_setup_get_current_scene(setup); + struct lp_scene *scene = setup->scene; struct lp_rast_triangle *point; unsigned bytes; struct u_rect bbox; @@ -259,7 +260,7 @@ static void lp_setup_point( struct lp_setup_context *setup, if (!u_rect_test_intersection(&setup->draw_region, &bbox)) { if (0) debug_printf("offscreen\n"); LP_COUNT(nr_culled_tris); - return; + return TRUE; } u_rect_find_intersection(&setup->draw_region, &bbox); @@ -269,7 +270,7 @@ static void lp_setup_point( struct lp_setup_context *setup, nr_planes, &bytes); if (!point) - return; + return FALSE; #ifdef DEBUG point->v[0][0] = v0[0][0]; @@ -288,6 +289,8 @@ static void lp_setup_point( struct lp_setup_context *setup, point->inputs.facing = 1.0F; point->inputs.state = setup->fs.stored; + point->inputs.disable = FALSE; + point->inputs.opaque = FALSE; { point->plane[0].dcdx = -1; @@ -315,7 +318,20 @@ static void lp_setup_point( struct lp_setup_context *setup, point->plane[3].eo = 0; } - lp_setup_bin_triangle(setup, point, &bbox, nr_planes); + return lp_setup_bin_triangle(setup, point, &bbox, nr_planes); +} + + +static void lp_setup_point( struct lp_setup_context *setup, + const float (*v0)[4] ) +{ + if (!try_setup_point( setup, v0 )) + { + lp_setup_flush_and_restart(setup); + + if (!try_setup_point( setup, v0 )) + assert(0); + } } diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c index 0180d95090f..5090f82ab5f 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c @@ -160,44 +160,79 @@ lp_setup_print_triangle(struct lp_setup_context *setup, } -lp_rast_cmd lp_rast_tri_tab[9] = { - NULL, /* should be impossible */ - lp_rast_triangle_1, - lp_rast_triangle_2, - lp_rast_triangle_3, - lp_rast_triangle_4, - lp_rast_triangle_5, - lp_rast_triangle_6, - lp_rast_triangle_7, - lp_rast_triangle_8 +static unsigned +lp_rast_tri_tab[9] = { + 0, /* should be impossible */ + LP_RAST_OP_TRIANGLE_1, + LP_RAST_OP_TRIANGLE_2, + LP_RAST_OP_TRIANGLE_3, + LP_RAST_OP_TRIANGLE_4, + LP_RAST_OP_TRIANGLE_5, + LP_RAST_OP_TRIANGLE_6, + LP_RAST_OP_TRIANGLE_7, + LP_RAST_OP_TRIANGLE_8 }; + + +/** + * The primitive covers the whole tile- shade whole tile. + * + * \param tx, ty the tile position in tiles, not pixels + */ +static boolean +lp_setup_whole_tile(struct lp_setup_context *setup, + const struct lp_rast_shader_inputs *inputs, + int tx, int ty) +{ + struct lp_scene *scene = setup->scene; + + LP_COUNT(nr_fully_covered_64); + + /* if variant is opaque and scissor doesn't effect the tile */ + if (inputs->opaque) { + if (!scene->fb.zsbuf) { + /* + * All previous rendering will be overwritten so reset the bin. + */ + lp_scene_bin_reset( scene, tx, ty ); + } + + LP_COUNT(nr_shade_opaque_64); + return lp_scene_bin_command( scene, tx, ty, + LP_RAST_OP_SHADE_TILE_OPAQUE, + lp_rast_arg_inputs(inputs) ); + } else { + LP_COUNT(nr_shade_64); + return lp_scene_bin_command( scene, tx, ty, + LP_RAST_OP_SHADE_TILE, + lp_rast_arg_inputs(inputs) ); + } +} + + /** * Do basic setup for triangle rasterization and determine which * framebuffer tiles are touched. Put the triangle in the scene's * bins for the tiles which we overlap. */ -static void +static boolean do_triangle_ccw(struct lp_setup_context *setup, const float (*v0)[4], const float (*v1)[4], const float (*v2)[4], boolean frontfacing ) { - struct lp_scene *scene = lp_setup_get_current_scene(setup); + struct lp_scene *scene = setup->scene; struct lp_rast_triangle *tri; int x[3]; int y[3]; - float dy01, dy20; - float dx01, dx20; - float oneoverarea; - struct lp_tri_info info; int area; struct u_rect bbox; unsigned tri_bytes; int i; int nr_planes = 3; - + if (0) lp_setup_print_triangle(setup, v0, v1, v2); @@ -241,13 +276,13 @@ do_triangle_ccw(struct lp_setup_context *setup, bbox.y1 < bbox.y0) { if (0) debug_printf("empty bounding box\n"); LP_COUNT(nr_culled_tris); - return; + return TRUE; } if (!u_rect_test_intersection(&setup->draw_region, &bbox)) { if (0) debug_printf("offscreen\n"); LP_COUNT(nr_culled_tris); - return; + return TRUE; } u_rect_find_intersection(&setup->draw_region, &bbox); @@ -257,7 +292,7 @@ do_triangle_ccw(struct lp_setup_context *setup, nr_planes, &tri_bytes); if (!tri) - return; + return FALSE; #ifdef DEBUG tri->v[0][0] = v0[0][0]; @@ -288,37 +323,18 @@ do_triangle_ccw(struct lp_setup_context *setup, if (area <= 0) { lp_scene_putback_data( scene, tri_bytes ); LP_COUNT(nr_culled_tris); - return; + return TRUE; } - - /* - */ - dx01 = v0[0][0] - v1[0][0]; - dy01 = v0[0][1] - v1[0][1]; - dx20 = v2[0][0] - v0[0][0]; - dy20 = v2[0][1] - v0[0][1]; - oneoverarea = 1.0f / (dx01 * dy20 - dx20 * dy01); - - info.v0 = v0; - info.v1 = v1; - info.v2 = v2; - info.frontfacing = frontfacing; - info.x0_center = v0[0][0] - setup->pixel_offset; - info.y0_center = v0[0][1] - setup->pixel_offset; - info.dx01_ooa = dx01 * oneoverarea; - info.dx20_ooa = dx20 * oneoverarea; - info.dy01_ooa = dy01 * oneoverarea; - info.dy20_ooa = dy20 * oneoverarea; - /* Setup parameter interpolants: */ - lp_setup_tri_coef( setup, &tri->inputs, &info ); + lp_setup_tri_coef( setup, &tri->inputs, v0, v1, v2, frontfacing ); tri->inputs.facing = frontfacing ? 1.0F : -1.0F; + tri->inputs.disable = FALSE; + tri->inputs.opaque = setup->fs.current.variant->opaque; tri->inputs.state = setup->fs.stored; - for (i = 0; i < 3; i++) { struct lp_rast_plane *plane = &tri->plane[i]; @@ -420,70 +436,98 @@ do_triangle_ccw(struct lp_setup_context *setup, tri->plane[6].eo = 0; } - lp_setup_bin_triangle( setup, tri, &bbox, nr_planes ); + return lp_setup_bin_triangle( setup, tri, &bbox, nr_planes ); +} + +/* + * Round to nearest less or equal power of two of the input. + * + * Undefined if no bit set exists, so code should check against 0 first. + */ +static INLINE uint32_t +floor_pot(uint32_t n) +{ +#if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86) + if (n == 0) + return 0; + + __asm__("bsr %1,%0" + : "=r" (n) + : "rm" (n)); + return 1 << n; +#else + n |= (n >> 1); + n |= (n >> 2); + n |= (n >> 4); + n |= (n >> 8); + n |= (n >> 16); + return n - (n >> 1); +#endif } -void +boolean lp_setup_bin_triangle( struct lp_setup_context *setup, struct lp_rast_triangle *tri, const struct u_rect *bbox, int nr_planes ) { struct lp_scene *scene = setup->scene; - struct lp_fragment_shader_variant *variant = setup->fs.current.variant; - int ix0, ix1, iy0, iy1; int i; - /* - * All fields of 'tri' are now set. The remaining code here is - * concerned with binning. + /* What is the largest power-of-two boundary this triangle crosses: */ + int dx = floor_pot((bbox->x0 ^ bbox->x1) | + (bbox->y0 ^ bbox->y1)); - /* Convert to tile coordinates, and inclusive ranges: + /* The largest dimension of the rasterized area of the triangle + * (aligned to a 4x4 grid), rounded down to the nearest power of two: */ + int sz = floor_pot((bbox->x1 - (bbox->x0 & ~3)) | + (bbox->y1 - (bbox->y0 & ~3))); + if (nr_planes == 3) { - int ix0 = bbox->x0 / 16; - int iy0 = bbox->y0 / 16; - int ix1 = bbox->x1 / 16; - int iy1 = bbox->y1 / 16; - - if (iy0 == iy1 && ix0 == ix1) + if (sz < 4 && dx < 64) { + /* Triangle is contained in a single 4x4 stamp: + */ + int mask = (bbox->x0 & 63 & ~3) | ((bbox->y0 & 63 & ~3) << 8); + + return lp_scene_bin_command( scene, + bbox->x0/64, bbox->y0/64, + LP_RAST_OP_TRIANGLE_3_4, + lp_rast_arg_triangle(tri, mask) ); + } + + if (sz < 16 && dx < 64) + { + int mask = (bbox->x0 & 63 & ~3) | ((bbox->y0 & 63 & ~3) << 8); /* Triangle is contained in a single 16x16 block: */ - int mask = (ix0 & 3) | ((iy0 & 3) << 4); - - lp_scene_bin_command( scene, ix0/4, iy0/4, - lp_rast_triangle_3_16, - lp_rast_arg_triangle(tri, mask) ); - return; + return lp_scene_bin_command( scene, + bbox->x0/64, bbox->y0/64, + LP_RAST_OP_TRIANGLE_3_16, + lp_rast_arg_triangle(tri, mask) ); } } - ix0 = bbox->x0 / TILE_SIZE; - iy0 = bbox->y0 / TILE_SIZE; - ix1 = bbox->x1 / TILE_SIZE; - iy1 = bbox->y1 / TILE_SIZE; - - /* - * Clamp to framebuffer size - */ - assert(ix0 == MAX2(ix0, 0)); - assert(iy0 == MAX2(iy0, 0)); - assert(ix1 == MIN2(ix1, scene->tiles_x - 1)); - assert(iy1 == MIN2(iy1, scene->tiles_y - 1)); /* Determine which tile(s) intersect the triangle's bounding box */ - if (iy0 == iy1 && ix0 == ix1) + if (dx < TILE_SIZE) { + int ix0 = bbox->x0 / TILE_SIZE; + int iy0 = bbox->y0 / TILE_SIZE; + + assert(iy0 == bbox->y1 / TILE_SIZE && + ix0 == bbox->x1 / TILE_SIZE); + /* Triangle is contained in a single tile: */ - lp_scene_bin_command( scene, ix0, iy0, - lp_rast_tri_tab[nr_planes], - lp_rast_arg_triangle(tri, (1<<nr_planes)-1) ); + return lp_scene_bin_command( scene, ix0, iy0, + lp_rast_tri_tab[nr_planes], + lp_rast_arg_triangle(tri, (1<<nr_planes)-1) ); } else { @@ -493,6 +537,11 @@ lp_setup_bin_triangle( struct lp_setup_context *setup, int xstep[7]; int ystep[7]; int x, y; + + int ix0 = bbox->x0 / TILE_SIZE; + int iy0 = bbox->y0 / TILE_SIZE; + int ix1 = bbox->x1 / TILE_SIZE; + int iy1 = bbox->y1 / TILE_SIZE; for (i = 0; i < nr_planes; i++) { c[i] = (tri->plane[i].c + @@ -544,9 +593,10 @@ lp_setup_bin_triangle( struct lp_setup_context *setup, */ int count = util_bitcount(partial); in = TRUE; - lp_scene_bin_command( scene, x, y, - lp_rast_tri_tab[count], - lp_rast_arg_triangle(tri, partial) ); + if (!lp_scene_bin_command( scene, x, y, + lp_rast_tri_tab[count], + lp_rast_arg_triangle(tri, partial) )) + goto fail; LP_COUNT(nr_partially_covered_64); } @@ -554,13 +604,8 @@ lp_setup_bin_triangle( struct lp_setup_context *setup, /* triangle covers the whole tile- shade whole tile */ LP_COUNT(nr_fully_covered_64); in = TRUE; - if (variant->opaque && - !setup->fb.zsbuf) { - lp_scene_bin_reset( scene, x, y ); - } - lp_scene_bin_command( scene, x, y, - lp_rast_shade_tile, - lp_rast_arg_inputs(&tri->inputs) ); + if (!lp_setup_whole_tile(setup, &tri->inputs, x, y)) + goto fail; } /* Iterate cx values across the region: @@ -575,6 +620,16 @@ lp_setup_bin_triangle( struct lp_setup_context *setup, c[i] += ystep[i]; } } + + return TRUE; + +fail: + /* Need to disable any partially binned triangle. This is easier + * than trying to locate all the triangle, shade-tile, etc, + * commands which may have been binned. + */ + tri->inputs.disable = TRUE; + return FALSE; } @@ -586,7 +641,13 @@ static void triangle_cw( struct lp_setup_context *setup, const float (*v1)[4], const float (*v2)[4] ) { - do_triangle_ccw( setup, v1, v0, v2, !setup->ccw_is_frontface ); + if (!do_triangle_ccw( setup, v1, v0, v2, !setup->ccw_is_frontface )) + { + lp_setup_flush_and_restart(setup); + + if (!do_triangle_ccw( setup, v1, v0, v2, !setup->ccw_is_frontface )) + assert(0); + } } @@ -598,7 +659,12 @@ static void triangle_ccw( struct lp_setup_context *setup, const float (*v1)[4], const float (*v2)[4] ) { - do_triangle_ccw( setup, v0, v1, v2, setup->ccw_is_frontface ); + if (!do_triangle_ccw( setup, v0, v1, v2, setup->ccw_is_frontface )) + { + lp_setup_flush_and_restart(setup); + if (!do_triangle_ccw( setup, v0, v1, v2, setup->ccw_is_frontface )) + assert(0); + } } diff --git a/src/gallium/drivers/llvmpipe/lp_setup_vbuf.c b/src/gallium/drivers/llvmpipe/lp_setup_vbuf.c index 51948f5bf29..6308561f242 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup_vbuf.c +++ b/src/gallium/drivers/llvmpipe/lp_setup_vbuf.c @@ -64,7 +64,7 @@ lp_setup_get_vertex_info(struct vbuf_render *vbr) /* Vertex size/info depends on the latest state. * The draw module may have issued additional state-change commands. */ - lp_setup_update_state(setup); + lp_setup_update_state(setup, FALSE); return setup->vertex_info; } @@ -141,7 +141,7 @@ lp_setup_draw_elements(struct vbuf_render *vbr, const ushort *indices, uint nr) const boolean flatshade_first = setup->flatshade_first; unsigned i; - lp_setup_update_state(setup); + lp_setup_update_state(setup, TRUE); switch (setup->prim) { case PIPE_PRIM_POINTS: @@ -338,7 +338,7 @@ lp_setup_draw_arrays(struct vbuf_render *vbr, uint start, uint nr) const boolean flatshade_first = setup->flatshade_first; unsigned i; - lp_setup_update_state(setup); + lp_setup_update_state(setup, TRUE); switch (setup->prim) { case PIPE_PRIM_POINTS: diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c index 33c1a49efec..8101e2d843d 100644 --- a/src/gallium/drivers/llvmpipe/lp_state_fs.c +++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c @@ -186,6 +186,7 @@ generate_quad_mask(LLVMBuilderRef builder, LLVMTypeRef i32t = LLVMInt32Type(); LLVMValueRef bits[4]; LLVMValueRef mask; + int shift; /* * XXX: We'll need a different path for 16 x u8 @@ -197,10 +198,28 @@ generate_quad_mask(LLVMBuilderRef builder, /* * mask_input >>= (quad * 4) */ + + switch (quad) { + case 0: + shift = 0; + break; + case 1: + shift = 2; + break; + case 2: + shift = 8; + break; + case 3: + shift = 10; + break; + default: + assert(0); + shift = 0; + } mask_input = LLVMBuildLShr(builder, mask_input, - LLVMConstInt(i32t, quad * 4, 0), + LLVMConstInt(i32t, shift, 0), ""); /* @@ -211,9 +230,9 @@ generate_quad_mask(LLVMBuilderRef builder, bits[0] = LLVMConstInt(i32t, 1 << 0, 0); bits[1] = LLVMConstInt(i32t, 1 << 1, 0); - bits[2] = LLVMConstInt(i32t, 1 << 2, 0); - bits[3] = LLVMConstInt(i32t, 1 << 3, 0); - + bits[2] = LLVMConstInt(i32t, 1 << 4, 0); + bits[3] = LLVMConstInt(i32t, 1 << 5, 0); + mask = LLVMBuildAnd(builder, mask, LLVMConstVector(bits, 4), ""); /* @@ -332,14 +351,13 @@ generate_fs(struct llvmpipe_context *lp, lp_build_name(out, "color%u.%u.%c", i, attrib, "rgba"[chan]); /* Alpha test */ - /* XXX: should the alpha reference value be passed separately? */ /* XXX: should only test the final assignment to alpha */ - if(cbuf == 0 && chan == 3) { + if (cbuf == 0 && chan == 3 && key->alpha.enabled) { LLVMValueRef alpha = out; LLVMValueRef alpha_ref_value; alpha_ref_value = lp_jit_context_alpha_ref_value(builder, context_ptr); alpha_ref_value = lp_build_broadcast(builder, vec_type, alpha_ref_value); - lp_build_alpha_test(builder, &key->alpha, type, + lp_build_alpha_test(builder, key->alpha.func, type, &mask, alpha, alpha_ref_value); } @@ -728,6 +746,9 @@ dump_fs_variant_key(const struct lp_fragment_shader_variant_key *key) debug_printf("fs variant %p:\n", (void *) key); + for (i = 0; i < key->nr_cbufs; ++i) { + debug_printf("cbuf_format[%u] = %s\n", i, util_format_name(key->cbuf_format[i])); + } if (key->depth.enabled) { debug_printf("depth.format = %s\n", util_format_name(key->zsbuf_format)); debug_printf("depth.func = %s\n", util_dump_func(key->depth.func, TRUE)); @@ -747,7 +768,6 @@ dump_fs_variant_key(const struct lp_fragment_shader_variant_key *key) if (key->alpha.enabled) { debug_printf("alpha.func = %s\n", util_dump_func(key->alpha.func, TRUE)); - debug_printf("alpha.ref_value = %f\n", key->alpha.ref_value); } if (key->blend.logicop_enable) { @@ -791,6 +811,16 @@ dump_fs_variant_key(const struct lp_fragment_shader_variant_key *key) } +void +lp_debug_fs_variant(const struct lp_fragment_shader_variant *variant) +{ + debug_printf("llvmpipe: Fragment shader #%u variant #%u:\n", + variant->shader->no, variant->no); + tgsi_dump(variant->shader->base.tokens, 0); + dump_fs_variant_key(&variant->key); + debug_printf("variant->opaque = %u\n", variant->opaque); + debug_printf("\n"); +} static struct lp_fragment_shader_variant * generate_variant(struct llvmpipe_context *lp, @@ -798,6 +828,7 @@ generate_variant(struct llvmpipe_context *lp, const struct lp_fragment_shader_variant_key *key) { struct lp_fragment_shader_variant *variant; + boolean fullcolormask; variant = CALLOC_STRUCT(lp_fragment_shader_variant); if(!variant) @@ -810,27 +841,43 @@ generate_variant(struct llvmpipe_context *lp, memcpy(&variant->key, key, shader->variant_key_size); - if (gallivm_debug & GALLIVM_DEBUG_IR) { - debug_printf("llvmpipe: Creating fragment shader #%u variant #%u:\n", - shader->no, variant->no); - tgsi_dump(shader->base.tokens, 0); - dump_fs_variant_key(key); + /* + * Determine whether we are touching all channels in the color buffer. + */ + fullcolormask = FALSE; + if (key->nr_cbufs == 1) { + const struct util_format_description *format_desc; + format_desc = util_format_description(key->cbuf_format[0]); + if ((~key->blend.rt[0].colormask & + util_format_colormask(format_desc)) == 0) { + fullcolormask = TRUE; + } } - generate_fragment(lp, shader, variant, RAST_WHOLE); - generate_fragment(lp, shader, variant, RAST_EDGE_TEST); - - /* TODO: most of these can be relaxed, in particular the colormask */ variant->opaque = !key->blend.logicop_enable && !key->blend.rt[0].blend_enable && - key->blend.rt[0].colormask == 0xf && + fullcolormask && !key->stencil[0].enabled && !key->alpha.enabled && !key->depth.enabled && !shader->info.uses_kill ? TRUE : FALSE; + + if (gallivm_debug & GALLIVM_DEBUG_IR) { + lp_debug_fs_variant(variant); + } + + generate_fragment(lp, shader, variant, RAST_EDGE_TEST); + + if (variant->opaque) { + /* Specialized shader, which doesn't need to read the color buffer. */ + generate_fragment(lp, shader, variant, RAST_WHOLE); + } else { + variant->jit_function[RAST_WHOLE] = variant->jit_function[RAST_EDGE_TEST]; + } + return variant; } @@ -1056,25 +1103,22 @@ make_variant_key(struct llvmpipe_context *lp, key->nr_cbufs = lp->framebuffer.nr_cbufs; for (i = 0; i < lp->framebuffer.nr_cbufs; i++) { + enum pipe_format format = lp->framebuffer.cbufs[i]->format; struct pipe_rt_blend_state *blend_rt = &key->blend.rt[i]; const struct util_format_description *format_desc; - unsigned chan; - format_desc = util_format_description(lp->framebuffer.cbufs[i]->format); + key->cbuf_format[i] = format; + + format_desc = util_format_description(format); assert(format_desc->colorspace == UTIL_FORMAT_COLORSPACE_RGB || format_desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB); blend_rt->colormask = lp->blend->rt[i].colormask; - /* mask out color channels not present in the color buffer. - * Should be simple to incorporate per-cbuf writemasks: + /* + * Mask out color channels not present in the color buffer. */ - for(chan = 0; chan < 4; ++chan) { - enum util_format_swizzle swizzle = format_desc->swizzle[chan]; - - if(swizzle > UTIL_FORMAT_SWIZZLE_W) - blend_rt->colormask &= ~(1 << chan); - } + blend_rt->colormask &= util_format_colormask(format_desc); /* * Our swizzled render tiles always have an alpha channel, but the linear diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.h b/src/gallium/drivers/llvmpipe/lp_state_fs.h index 33c480010dd..2914e7d7efd 100644 --- a/src/gallium/drivers/llvmpipe/lp_state_fs.h +++ b/src/gallium/drivers/llvmpipe/lp_state_fs.h @@ -49,14 +49,21 @@ struct lp_fragment_shader_variant_key { struct pipe_depth_state depth; struct pipe_stencil_state stencil[2]; - struct pipe_alpha_state alpha; struct pipe_blend_state blend; - enum pipe_format zsbuf_format; + + struct { + unsigned enabled:1; + unsigned func:3; + } alpha; + unsigned nr_cbufs:8; unsigned nr_samplers:8; /* actually derivable from just the shader */ unsigned flatshade:1; unsigned occlusion_count:1; + enum pipe_format zsbuf_format; + enum pipe_format cbuf_format[PIPE_MAX_COLOR_BUFS]; + struct lp_sampler_static_state sampler[PIPE_MAX_SAMPLERS]; }; @@ -101,4 +108,8 @@ struct lp_fragment_shader }; +void +lp_debug_fs_variant(const struct lp_fragment_shader_variant *variant); + + #endif /* LP_STATE_FS_H_ */ diff --git a/src/gallium/drivers/llvmpipe/lp_surface.c b/src/gallium/drivers/llvmpipe/lp_surface.c index 63ddc669c2c..164242eda67 100644 --- a/src/gallium/drivers/llvmpipe/lp_surface.c +++ b/src/gallium/drivers/llvmpipe/lp_surface.c @@ -68,16 +68,16 @@ lp_resource_copy(struct pipe_context *pipe, 0, /* flush_flags */ FALSE, /* read_only */ TRUE, /* cpu_access */ - FALSE, - "blit dst"); /* do_not_block */ + FALSE, /* do_not_block */ + "blit dest"); llvmpipe_flush_resource(pipe, src, subsrc.face, subsrc.level, 0, /* flush_flags */ TRUE, /* read_only */ TRUE, /* cpu_access */ - FALSE, - "blit src"); /* do_not_block */ + FALSE, /* do_not_block */ + "blit src"); /* printf("surface copy from %u to %u: %u,%u to %u,%u %u x %u\n", diff --git a/src/gallium/drivers/llvmpipe/lp_texture.c b/src/gallium/drivers/llvmpipe/lp_texture.c index 5832ea27445..a4b9f2590af 100644 --- a/src/gallium/drivers/llvmpipe/lp_texture.c +++ b/src/gallium/drivers/llvmpipe/lp_texture.c @@ -585,7 +585,7 @@ llvmpipe_get_transfer(struct pipe_context *pipe, read_only, TRUE, /* cpu_access */ do_not_block, - "transfer dest")) { + __FUNCTION__)) { /* * It would have blocked, but state tracker requested no to. */ diff --git a/src/gallium/drivers/llvmpipe/sse_mathfun.h b/src/gallium/drivers/llvmpipe/sse_mathfun.h index 8ac2064b7bb..0077f34b5c8 100644 --- a/src/gallium/drivers/llvmpipe/sse_mathfun.h +++ b/src/gallium/drivers/llvmpipe/sse_mathfun.h @@ -94,55 +94,6 @@ v4sf sin_ps(v4sf x); v4sf cos_ps(v4sf x); void sincos_ps(v4sf x, v4sf *s, v4sf *c); -#if defined (__MINGW32__) - -/* the ugly part below: many versions of gcc used to be completely buggy with respect to some intrinsics - The movehl_ps is fixed in mingw 3.4.5, but I found out that all the _mm_cmp* intrinsics were completely - broken on my mingw gcc 3.4.5 ... - - Note that the bug on _mm_cmp* does occur only at -O0 optimization level -*/ - -inline __m128 my_movehl_ps(__m128 a, const __m128 b) { - asm ( - "movhlps %2,%0\n\t" - : "=x" (a) - : "0" (a), "x"(b) - ); - return a; } -#warning "redefined _mm_movehl_ps (see gcc bug 21179)" -#define _mm_movehl_ps my_movehl_ps - -inline __m128 my_cmplt_ps(__m128 a, const __m128 b) { - asm ( - "cmpltps %2,%0\n\t" - : "=x" (a) - : "0" (a), "x"(b) - ); - return a; - } -inline __m128 my_cmpgt_ps(__m128 a, const __m128 b) { - asm ( - "cmpnleps %2,%0\n\t" - : "=x" (a) - : "0" (a), "x"(b) - ); - return a; -} -inline __m128 my_cmpeq_ps(__m128 a, const __m128 b) { - asm ( - "cmpeqps %2,%0\n\t" - : "=x" (a) - : "0" (a), "x"(b) - ); - return a; -} -#warning "redefined _mm_cmpxx_ps functions..." -#define _mm_cmplt_ps my_cmplt_ps -#define _mm_cmpgt_ps my_cmpgt_ps -#define _mm_cmpeq_ps my_cmpeq_ps -#endif - #ifndef USE_SSE2 typedef union xmm_mm_union { __m128 xmm; diff --git a/src/gallium/drivers/nouveau/nouveau_class.h b/src/gallium/drivers/nouveau/nouveau_class.h deleted file mode 100644 index d9f35b4c4b9..00000000000 --- a/src/gallium/drivers/nouveau/nouveau_class.h +++ /dev/null @@ -1,10059 +0,0 @@ -/************************************************************************* - - Autogenerated file, do not edit ! - - This file was generated by renouveau-gen from renouveau.xml, the - XML database of nvidia objects and methods. renouveau-gen and - renouveau.xml can be found in CVS module renouveau of sourceforge.net - project nouveau: - -cvs -z3 -d:pserver:[email protected]:/cvsroot/nouveau co -P renouveau - -************************************************************************** - - Copyright (C) 2006-2008 : - Dmitry Baryshkov, - Laurent Carlier, - Matthieu Castet, - Dawid Gajownik, - Jeremy Kolb, - Stephane Loeuillet, - Patrice Mandin, - Stephane Marchesin, - Serge Martin, - Sylvain Munaut, - Simon Raffeiner, - Ben Skeggs, - Erik Waling, - koala_br, - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -*************************************************************************/ - - -#ifndef NOUVEAU_REG_H -#define NOUVEAU_REG_H 1 - - -#define NV01_ROOT 0x00000001 - - - -#define NV01_CONTEXT_DMA 0x00000002 - - - -#define NV01_DEVICE 0x00000003 - - - -#define NV01_TIMER 0x00000004 - -#define NV01_TIMER_SYNCHRONIZE 0x00000100 -#define NV01_TIMER_STOP_ALARM 0x00000104 -#define NV01_TIMER_DMA_NOTIFY 0x00000180 -#define NV01_TIMER_TIME(x) (0x00000300+((x)*4)) -#define NV01_TIMER_TIME__SIZE 0x00000002 -#define NV01_TIMER_ALARM_NOTIFY 0x00000308 - - -#define NV01_CONTEXT_BETA1 0x00000012 - -#define NV01_CONTEXT_BETA1_NOP 0x00000100 -#define NV01_CONTEXT_BETA1_NOTIFY 0x00000104 -#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180 -#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300 - - -#define NV01_CONTEXT_COLOR_KEY 0x00000017 - -#define NV01_CONTEXT_COLOR_KEY_NOP 0x00000100 -#define NV01_CONTEXT_COLOR_KEY_NOTIFY 0x00000104 -#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A8Y8 0x00000001 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X24Y8 0x00000002 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000003 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X17R5G5B5 0x00000004 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000005 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X8R8G8B8 0x00000006 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16Y16 0x00000007 -#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16Y16 0x00000008 -#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304 - - -#define NV04_CONTEXT_COLOR_KEY 0x00000057 - - - -#define NV01_CONTEXT_PATTERN 0x00000018 - -#define NV01_CONTEXT_PATTERN_NOP 0x00000100 -#define NV01_CONTEXT_PATTERN_NOTIFY 0x00000104 -#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180 -#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300 -#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304 -#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308 -#define NV01_CONTEXT_PATTERN_COLOR(x) (0x00000310+((x)*4)) -#define NV01_CONTEXT_PATTERN_COLOR__SIZE 0x00000002 -#define NV01_CONTEXT_PATTERN_PATTERN(x) (0x00000318+((x)*4)) -#define NV01_CONTEXT_PATTERN_PATTERN__SIZE 0x00000002 - - -#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019 - -#define NV01_CONTEXT_CLIP_RECTANGLE_NOP 0x00000100 -#define NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY 0x00000104 -#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180 -#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300 -#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_SHIFT 0 -#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_MASK 0x0000ffff -#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_SHIFT 16 -#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_MASK 0xffff0000 -#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304 -#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_SHIFT 0 -#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_MASK 0x0000ffff -#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_SHIFT 16 -#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_MASK 0xffff0000 - - -#define NV01_RENDER_SOLID_LINE 0x0000001c - -#define NV01_RENDER_SOLID_LINE_NOP 0x00000100 -#define NV01_RENDER_SOLID_LINE_NOTIFY 0x00000104 -#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c -#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180 -#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184 -#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188 -#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c -#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190 -#define NV01_RENDER_SOLID_LINE_SURFACE 0x00000194 -#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc -#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000 -#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001 -#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002 -#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003 -#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A8Y8 0x00000001 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X24Y8 0x00000002 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000003 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X17R5G5B5 0x00000004 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000005 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X8R8G8B8 0x00000006 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16Y16 0x00000007 -#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16Y16 0x00000008 -#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304 -#define NV01_RENDER_SOLID_LINE_LINE_POINT0(x) (0x00000400+((x)*8)) -#define NV01_RENDER_SOLID_LINE_LINE_POINT0__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_SHIFT 0 -#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_SHIFT 16 -#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_LINE_LINE_POINT1(x) (0x00000404+((x)*8)) -#define NV01_RENDER_SOLID_LINE_LINE_POINT1__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_SHIFT 0 -#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_SHIFT 16 -#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(x) (0x00000480+((x)*16)) -#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(x) (0x00000484+((x)*16)) -#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(x) (0x00000488+((x)*16)) -#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(x) (0x0000048c+((x)*16)) -#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_POLYLINE(x) (0x00000500+((x)*4)) -#define NV01_RENDER_SOLID_LINE_POLYLINE__SIZE 0x00000020 -#define NV01_RENDER_SOLID_LINE_POLYLINE_X_SHIFT 0 -#define NV01_RENDER_SOLID_LINE_POLYLINE_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_SHIFT 16 -#define NV01_RENDER_SOLID_LINE_POLYLINE_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(x) (0x00000580+((x)*8)) -#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(x) (0x00000584+((x)*8)) -#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(x) (0x00000600+((x)*8)) -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(x) (0x00000604+((x)*8)) -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__SIZE 0x00000010 -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_SHIFT 0 -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_SHIFT 16 -#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK 0xffff0000 - - -#define NV04_RENDER_SOLID_LINE 0x0000005c - -#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194 -#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198 - - -#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d - -#define NV01_RENDER_SOLID_TRIANGLE_NOP 0x00000100 -#define NV01_RENDER_SOLID_TRIANGLE_NOTIFY 0x00000104 -#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c -#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180 -#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184 -#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 -#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c -#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190 -#define NV01_RENDER_SOLID_TRIANGLE_SURFACE 0x00000194 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005 -#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300 -#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330 -#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(x) (0x00000400+((x)*4)) -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__SIZE 0x00000020 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(x) (0x00000480+((x)*8)) -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__SIZE 0x00000010 -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(x) (0x00000484+((x)*8)) -#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__SIZE 0x00000010 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(x) (0x00000500+((x)*16)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__SIZE 0x00000008 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(x) (0x00000504+((x)*16)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__SIZE 0x00000008 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(x) (0x00000508+((x)*16)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__SIZE 0x00000008 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(x) (0x0000050c+((x)*16)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__SIZE 0x00000008 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(x) (0x00000580+((x)*8)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__SIZE 0x00000010 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(x) (0x00000584+((x)*8)) -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__SIZE 0x00000010 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_SHIFT 0 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_SHIFT 16 -#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK 0xffff0000 - - -#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d - -#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194 -#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198 - - -#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e - -#define NV01_RENDER_SOLID_RECTANGLE_NOP 0x00000100 -#define NV01_RENDER_SOLID_RECTANGLE_NOTIFY 0x00000104 -#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c -#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180 -#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184 -#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 -#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c -#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190 -#define NV01_RENDER_SOLID_RECTANGLE_SURFACE 0x00000194 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005 -#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300 -#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(x) (0x00000400+((x)*8)) -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__SIZE 0x00000010 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_SHIFT 0 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_MASK 0x0000ffff -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_SHIFT 16 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_MASK 0xffff0000 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(x) (0x00000404+((x)*8)) -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__SIZE 0x00000010 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_SHIFT 0 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_MASK 0x0000ffff -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_SHIFT 16 -#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK 0xffff0000 - - -#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e - -#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194 -#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198 - - -#define NV01_IMAGE_BLIT 0x0000001f - -#define NV01_IMAGE_BLIT_NOP 0x00000100 -#define NV01_IMAGE_BLIT_NOTIFY 0x00000104 -#define NV01_IMAGE_BLIT_PATCH 0x0000010c -#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180 -#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184 -#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188 -#define NV01_IMAGE_BLIT_PATTERN 0x0000018c -#define NV01_IMAGE_BLIT_ROP 0x00000190 -#define NV01_IMAGE_BLIT_BETA1 0x00000194 -#define NV01_IMAGE_BLIT_SURFACE 0x0000019c -#define NV01_IMAGE_BLIT_OPERATION 0x000002fc -#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000 -#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001 -#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002 -#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003 -#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005 -#define NV01_IMAGE_BLIT_IMAGE_INPUT 0x00000204 -#define NV01_IMAGE_BLIT_POINT_IN 0x00000300 -#define NV01_IMAGE_BLIT_POINT_IN_X_SHIFT 0 -#define NV01_IMAGE_BLIT_POINT_IN_X_MASK 0x0000ffff -#define NV01_IMAGE_BLIT_POINT_IN_Y_SHIFT 16 -#define NV01_IMAGE_BLIT_POINT_IN_Y_MASK 0xffff0000 -#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304 -#define NV01_IMAGE_BLIT_POINT_OUT_X_SHIFT 0 -#define NV01_IMAGE_BLIT_POINT_OUT_X_MASK 0x0000ffff -#define NV01_IMAGE_BLIT_POINT_OUT_Y_SHIFT 16 -#define NV01_IMAGE_BLIT_POINT_OUT_Y_MASK 0xffff0000 -#define NV01_IMAGE_BLIT_SIZE 0x00000308 -#define NV01_IMAGE_BLIT_SIZE_W_SHIFT 0 -#define NV01_IMAGE_BLIT_SIZE_W_MASK 0x0000ffff -#define NV01_IMAGE_BLIT_SIZE_H_SHIFT 16 -#define NV01_IMAGE_BLIT_SIZE_H_MASK 0xffff0000 - - -#define NV04_IMAGE_BLIT 0x0000005f - -#define NV04_IMAGE_BLIT_ROP 0x00000190 -#define NV04_IMAGE_BLIT_BETA4 0x00000198 -#define NV04_IMAGE_BLIT_SURFACE 0x0000019c - - -#define NV12_IMAGE_BLIT 0x0000009f - -#define NV12_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108 - - -#define NV01_IMAGE_FROM_CPU 0x00000021 - -#define NV01_IMAGE_FROM_CPU_NOP 0x00000100 -#define NV01_IMAGE_FROM_CPU_NOTIFY 0x00000104 -#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c -#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 -#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 -#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 -#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c -#define NV01_IMAGE_FROM_CPU_ROP 0x00000190 -#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194 -#define NV01_IMAGE_FROM_CPU_SURFACE 0x00000198 -#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc -#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000 -#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001 -#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002 -#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003 -#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_Y8 0x00000001 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004 -#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005 -#define NV01_IMAGE_FROM_CPU_POINT 0x00000304 -#define NV01_IMAGE_FROM_CPU_POINT_X_SHIFT 0 -#define NV01_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff -#define NV01_IMAGE_FROM_CPU_POINT_Y_SHIFT 16 -#define NV01_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000 -#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 -#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_SHIFT 0 -#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W_MASK 0x0000ffff -#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_SHIFT 16 -#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H_MASK 0xffff0000 -#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c -#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0 -#define NV01_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff -#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16 -#define NV01_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000 -#define NV01_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) -#define NV01_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020 - - -#define NV04_IMAGE_FROM_CPU 0x00000061 - -#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198 -#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c - - -#define NV05_IMAGE_FROM_CPU 0x00000065 - -#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 - - -#define NV10_IMAGE_FROM_CPU 0x0000008a - -#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 - - -#define NV30_IMAGE_FROM_CPU 0x0000038a - - - -#define NV40_IMAGE_FROM_CPU 0x0000308a - - - -#define NV01_NULL 0x00000030 - - - -#define NV03_STRETCHED_IMAGE_FROM_CPU 0x00000036 - -#define NV03_STRETCHED_IMAGE_FROM_CPU_NOP 0x00000100 -#define NV03_STRETCHED_IMAGE_FROM_CPU_NOTIFY 0x00000104 -#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c -#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 -#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 -#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 -#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c -#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190 -#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000194 -#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc -#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 -#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304 -#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT 0 -#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_MASK 0x0000ffff -#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT 16 -#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_MASK 0xffff0000 -#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308 -#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_SHIFT 0 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_MASK 0x0000ffff -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_SHIFT 16 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_MASK 0xffff0000 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_SHIFT 0 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_MASK 0x0000ffff -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_SHIFT 16 -#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_MASK 0xffff0000 -#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318 -#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_SHIFT 0 -#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_MASK 0x0000ffff -#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_SHIFT 16 -#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_MASK 0xffff0000 -#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) -#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020 - - -#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076 - -#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194 -#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198 - - -#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066 - -#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 - - -#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366 - - - -#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066 - - - -#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037 - -#define NV03_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100 -#define NV03_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104 -#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180 -#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184 -#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 -#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c -#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190 -#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000194 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008 -#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK 0xffff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK 0xffff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK 0xffff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 -#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c -#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 -#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK 0xffff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000 -#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 -#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c -#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_SHIFT 0 -#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_MASK 0x0000ffff -#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_SHIFT 16 -#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_MASK 0xffff0000 - - -#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077 - -#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194 -#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 - - -#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063 - -#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc -#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000 -#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001 -#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002 - - -#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089 - -#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108 - - -#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389 - - - -#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089 - - - -#define NV04_DVD_SUBPICTURE 0x00000038 - -#define NV04_DVD_SUBPICTURE_NOP 0x00000100 -#define NV04_DVD_SUBPICTURE_NOTIFY 0x00000104 -#define NV04_DVD_SUBPICTURE_DMA_NOTIFY 0x00000180 -#define NV04_DVD_SUBPICTURE_DMA_OVERLAY 0x00000184 -#define NV04_DVD_SUBPICTURE_DMA_IMAGEIN 0x00000188 -#define NV04_DVD_SUBPICTURE_DMA_IMAGEOUT 0x0000018c -#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT 0x00000300 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE 0x00000304 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT 0x00000308 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_IMAGEOUT_OFFSET 0x0000030c -#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DU_DX 0x00000310 -#define NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DV_DY 0x00000314 -#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE 0x00000318 -#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT 0x0000031c -#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_IMAGEIN_OFFSET 0x00000320 -#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT 0x00000324 -#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_SHIFT 0 -#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_SHIFT 16 -#define NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DU_DX 0x00000328 -#define NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DV_DY 0x0000032c -#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE 0x00000330 -#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_SHIFT 0 -#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_SHIFT 16 -#define NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT 0x00000334 -#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_SHIFT 0 -#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_SHIFT 16 -#define NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_MASK 0xffff0000 -#define NV04_DVD_SUBPICTURE_OVERLAY_OFFSET 0x00000338 -#define NV04_DVD_SUBPICTURE_OVERLAY_POINT 0x0000033c -#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_SHIFT 0 -#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_MASK 0x0000ffff -#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_SHIFT 16 -#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK 0xffff0000 - - -#define NV10_DVD_SUBPICTURE 0x00000088 - -#define NV10_DVD_SUBPICTURE_WAIT_FOR_IDLE 0x00000108 - - -#define NV04_MEMORY_TO_MEMORY_FORMAT 0x00000039 - -#define NV04_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV04_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN 0x00000184 -#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT 0x00000188 -#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c -#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310 -#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 -#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 -#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c -#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 -#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324 -#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT 0 -#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x000000ff -#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT 8 -#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x0000ff00 -#define NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328 - - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 - -#define NV50_MEMORY_TO_MEMORY_FORMAT_SERIALIZE 0x00000110 -#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN 0x00000210 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z 0x00000214 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_SHIFT 0 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_MASK 0x0000ffff -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_SHIFT 16 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_MASK 0xffff0000 -#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT 0x0000022c -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z 0x00000230 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_SHIFT 0 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_MASK 0x0000ffff -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_SHIFT 16 -#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_MASK 0xffff0000 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - - -#define NVC0_MEMORY_TO_MEMORY_FORMAT 0x00009039 - -#define NVC0_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_SERIALIZE 0x00000110 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN 0x00000210 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z 0x00000214 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT 0x0000022c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z 0x00000230 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x00000238 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_LOW 0x0000023c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC 0x00000300 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_PUSH (1 << 0) -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_LINEAR_IN (1 << 4) -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_LINEAR_OUT (1 << 8) -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_NOTIFY (1 << 13) -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_INC_SHIFT 20 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_EXEC_INC_MASK 0x00f00000 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_DATA 0x00000304 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x0000030c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_LOW 0x00000310 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_NOTIFY_ADDRESS_HIGH 0x0000032c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_NOTIFY_ADDRESS_LOW 0x00000330 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000334 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X 0x00000344 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y 0x00000348 -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X 0x0000034c -#define NVC0_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y 0x00000350 - - -#define NV01_MEMORY_LOCAL_BANKED 0x0000003d - - - -#define NV01_MAPPING_SYSTEM 0x0000003e - - - -#define NV03_MEMORY_LOCAL_CURSOR 0x0000003f - - - -#define NV01_MEMORY_LOCAL_LINEAR 0x00000040 - - - -#define NV01_MAPPING_LOCAL 0x00000041 - - - -#define NV04_CONTEXT_SURFACES_2D 0x00000042 - -#define NV04_CONTEXT_SURFACES_2D_NOP 0x00000100 -#define NV04_CONTEXT_SURFACES_2D_NOTIFY 0x00000104 -#define NV04_CONTEXT_SURFACES_2D_PM_TRIGGER 0x00000140 -#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 -#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184 -#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188 -#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009 -#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a -#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b -#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 -#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0 -#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff -#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16 -#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000 -#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 -#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c - - -#define NV10_CONTEXT_SURFACES_2D 0x00000062 - - - -#define NV30_CONTEXT_SURFACES_2D 0x00000362 - - - -#define NV40_CONTEXT_SURFACES_2D 0x00003062 - - - -#define NV03_CONTEXT_ROP 0x00000043 - -#define NV03_CONTEXT_ROP_NOP 0x00000100 -#define NV03_CONTEXT_ROP_NOTIFY 0x00000104 -#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180 -#define NV03_CONTEXT_ROP_ROP 0x00000300 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SHIFT 0 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_MASK 0x0000000f -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_CLEAR 0x00000000 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOR 0x00000001 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_INVERTED 0x00000002 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY_INVERTED 0x00000003 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_REVERSE 0x00000004 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_INVERT 0x00000005 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_XOR 0x00000006 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NAND 0x00000007 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND 0x00000008 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_EQUI 0x00000009 -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOOP 0x0000000a -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_INVERTED 0x0000000b -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY 0x0000000c -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_REVERSE 0x0000000d -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR 0x0000000e -#define NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SET 0x0000000f -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SHIFT 4 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_MASK 0x000000f0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_CLEAR 0x00000000 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOR 0x00000010 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_INVERTED 0x00000020 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY_INVERTED 0x00000030 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_REVERSE 0x00000040 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_INVERT 0x00000050 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_XOR 0x00000060 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NAND 0x00000070 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND 0x00000080 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_EQUI 0x00000090 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOOP 0x000000a0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_INVERTED 0x000000b0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY 0x000000c0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_REVERSE 0x000000d0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR 0x000000e0 -#define NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SET 0x000000f0 - - -#define NV04_IMAGE_PATTERN 0x00000044 - -#define NV04_IMAGE_PATTERN_NOP 0x00000100 -#define NV04_IMAGE_PATTERN_NOTIFY 0x00000104 -#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180 -#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300 -#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001 -#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002 -#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003 -#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304 -#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001 -#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002 -#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308 -#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000 -#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001 -#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002 -#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c -#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001 -#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002 -#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310 -#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314 -#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318 -#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c -#define NV04_IMAGE_PATTERN_PATTERN_Y8(x) (0x00000400+((x)*4)) -#define NV04_IMAGE_PATTERN_PATTERN_Y8__SIZE 0x00000010 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_SHIFT 0 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_MASK 0x000000ff -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_SHIFT 8 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_MASK 0x0000ff00 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_SHIFT 16 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_MASK 0x00ff0000 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_SHIFT 24 -#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_MASK 0xff000000 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(x) (0x00000500+((x)*4)) -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__SIZE 0x00000020 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_SHIFT 0 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_MASK 0x0000001f -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_SHIFT 5 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_MASK 0x000007e0 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_SHIFT 11 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_MASK 0x0000f800 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_SHIFT 16 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_MASK 0x001f0000 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_SHIFT 21 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_MASK 0x07e00000 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_SHIFT 27 -#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_MASK 0xf8000000 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(x) (0x00000600+((x)*4)) -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__SIZE 0x00000020 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_SHIFT 0 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_MASK 0x0000001f -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_SHIFT 5 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_MASK 0x000003e0 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_SHIFT 10 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_MASK 0x00007c00 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_SHIFT 16 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_MASK 0x001f0000 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_SHIFT 21 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_MASK 0x03e00000 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_SHIFT 26 -#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_MASK 0x7c000000 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(x) (0x00000700+((x)*4)) -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__SIZE 0x00000040 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_SHIFT 0 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_MASK 0x000000ff -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_SHIFT 8 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_MASK 0x0000ff00 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_SHIFT 16 -#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_MASK 0x00ff0000 - - -#define NV03_VIDEO_LUT_CURSOR_DAC 0x00000046 - -#define NV03_VIDEO_LUT_CURSOR_DAC_SYNCHRONIZE 0x00000100 -#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_IMAGE 0x00000104 -#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_CURSOR 0x00000108 -#define NV03_VIDEO_LUT_CURSOR_DAC_STOP_DAC 0x0000010c -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_NOTIFY 0x00000180 -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE(x) (0x00000184+((x)*4)) -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT(x) (0x0000018c+((x)*4)) -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR(x) (0x00000194+((x)*4)) -#define NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_GET 0x000002fc -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET(x) (0x00000300+((x)*8)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT(x) (0x00000304+((x)*8)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_MASK 0x0fff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_SHIFT 28 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_MASK 0xf0000000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET(x) (0x00000340+((x)*12)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT(x) (0x00000344+((x)*12)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_MASK 0xffff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT(x) (0x00000348+((x)*12)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A 0x00000358 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_MASK 0xffff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE(x) (0x00000380+((x)*16)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_MASK 0xffff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC(x) (0x00000384+((x)*16)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_MASK 0x0fff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_SHIFT 28 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_MASK 0xf0000000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC(x) (0x00000388+((x)*16)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_MASK 0x0fff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_SHIFT 28 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_MASK 0xf0000000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE(x) (0x0000038c+((x)*16)) -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE__SIZE 0x00000002 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_SHIFT 0 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_MASK 0x0000ffff -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_SHIFT 16 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_MASK 0x0fff0000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_SHIFT 28 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_MASK 0xf0000000 -#define NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK 0x000003a0 - - -#define NV03_TEXTURED_TRIANGLE 0x00000048 - -#define NV03_TEXTURED_TRIANGLE_NOP 0x00000100 -#define NV03_TEXTURED_TRIANGLE_NOTIFY 0x00000104 -#define NV03_TEXTURED_TRIANGLE_PATCH 0x0000010c -#define NV03_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180 -#define NV03_TEXTURED_TRIANGLE_DMA_TEXTURE 0x00000184 -#define NV03_TEXTURED_TRIANGLE_CLIP_RECTANGLE 0x00000188 -#define NV03_TEXTURED_TRIANGLE_SURFACE 0x0000018c -#define NV03_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK 0x0000ffff -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT 16 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK 0x000f0000 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 20 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00f00000 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT 24 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK 0x0f000000 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT 28 -#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK 0xf0000000 -#define NV03_TEXTURED_TRIANGLE_FILTER 0x0000030c -#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK 0x0000001f -#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT 8 -#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK 0x00001f00 -#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT 16 -#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK 0x00ff0000 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR 0x00000310 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK 0x000000ff -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT 8 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK 0x0000ff00 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT 16 -#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK 0x00ff0000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT 0x00000314 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK 0x0000000f -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT 4 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK 0x00000030 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT 6 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK 0x000000c0 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT 8 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK 0x00000f00 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT 12 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK 0x00007000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE (1 << 15) -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT 16 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK 0x000f0000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT 20 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK 0x00f00000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT 24 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK 0x07000000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT 27 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK 0x18000000 -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_BETA (1 << 29) -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND (1 << 30) -#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND (1 << 31) -#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL 0x00000318 -#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK 0x000000ff -#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT 8 -#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK 0xffffff00 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00001000+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_SHIFT 0 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_MASK 0x0000000f -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_SHIFT 4 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_MASK 0x000000f0 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_SHIFT 8 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_MASK 0x00000f00 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_SHIFT 12 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_MASK 0x0000f000 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_SHIFT 16 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_MASK 0x000f0000 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_SHIFT 20 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_MASK 0x00f00000 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00001004+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00001008+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x0000100c+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00001010+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x00001014+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00001018+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000080 -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000101c+((x)*32)) -#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000080 - - -#define NV04_GDI_RECTANGLE_TEXT 0x0000004a - -#define NV04_GDI_RECTANGLE_TEXT_NOP 0x00000100 -#define NV04_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104 -#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c -#define NV04_GDI_RECTANGLE_TEXT_PM_TRIGGER 0x00000140 -#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 -#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184 -#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188 -#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c -#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190 -#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194 -#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005 -#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 -#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001 -#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002 -#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003 -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001 -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002 -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(x) (0x00000400+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__SIZE 0x00000020 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(x) (0x00000404+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__SIZE 0x00000020 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(x) (0x00000600+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__SIZE 0x00000020 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(x) (0x00000604+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__SIZE 0x00000020 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc -#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000800+((x)*4)) -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000080 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc -#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00000c00+((x)*4)) -#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000080 -#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0 -#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_MASK 0x0fffffff -#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_SHIFT 28 -#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_MASK 0xf0000000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(x) (0x00001000+((x)*4)) -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__SIZE 0x00000100 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_MASK 0x000000ff -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_SHIFT 8 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_MASK 0x000fff00 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_SHIFT 20 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_MASK 0xfff00000 -#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0 -#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_MASK 0x0fffffff -#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_SHIFT 28 -#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_MASK 0xf0000000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(x) (0x00001800+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__SIZE 0x00000100 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_SHIFT 0 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_MASK 0x0000ffff -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_SHIFT 16 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_MASK 0xffff0000 -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(x) (0x00001804+((x)*8)) -#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__SIZE 0x00000100 - - -#define NV03_GDI_RECTANGLE_TEXT 0x0000004b - -#define NV03_GDI_RECTANGLE_TEXT_NOP 0x00000100 -#define NV03_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104 -#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 -#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184 -#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188 -#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000018c -#define NV03_GDI_RECTANGLE_TEXT_SURFACE 0x00000190 -#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc -#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 -#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc -#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x) (0x00000c00+((x)*4)) -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE 0x00000020 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc -#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(x) (0x00001000+((x)*4)) -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__SIZE 0x00000020 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec -#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc -#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT 0 -#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X_MASK 0x0000ffff -#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT 16 -#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK 0xffff0000 -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x) (0x00001400+((x)*4)) -#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE 0x00000020 - - -#define NV04_SWIZZLED_SURFACE 0x00000052 - -#define NV04_SWIZZLED_SURFACE_NOP 0x00000100 -#define NV04_SWIZZLED_SURFACE_NOTIFY 0x00000104 -#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180 -#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184 -#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_SHIFT 0 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x000000ff -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009 -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a -#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b -#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT 16 -#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_MASK 0x00ff0000 -#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT 24 -#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_MASK 0xff000000 -#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304 - - -#define NV20_SWIZZLED_SURFACE 0x0000009e - - - -#define NV30_SWIZZLED_SURFACE 0x0000039e - - - -#define NV40_SWIZZLED_SURFACE 0x0000309e - - - -#define NV04_CONTEXT_SURFACES_3D 0x00000053 - -#define NV04_CONTEXT_SURFACES_3D_NOP 0x00000100 -#define NV04_CONTEXT_SURFACES_3D_NOTIFY 0x00000104 -#define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180 -#define NV04_CONTEXT_SURFACES_3D_DMA_COLOR 0x00000184 -#define NV04_CONTEXT_SURFACES_3D_DMA_ZETA 0x00000188 -#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL 0x000002f8 -#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_SHIFT 0 -#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK 0x0000ffff -#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_SHIFT 16 -#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_MASK 0xffff0000 -#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL 0x000002fc -#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_SHIFT 0 -#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK 0x0000ffff -#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_SHIFT 16 -#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_MASK 0xffff0000 -#define NV04_CONTEXT_SURFACES_3D_FORMAT 0x00000300 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_SHIFT 0 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK 0x000000ff -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000001 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000002 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5 0x00000003 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000004 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000005 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000007 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8 0x00000008 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT 8 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK 0x0000ff00 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH 0x00000100 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE 0x00000200 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_SHIFT 16 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_MASK 0x00ff0000 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_SHIFT 24 -#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_MASK 0xff000000 -#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE 0x00000304 -#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_SHIFT 0 -#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_MASK 0x0000ffff -#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_SHIFT 16 -#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_MASK 0xffff0000 -#define NV04_CONTEXT_SURFACES_3D_PITCH 0x00000308 -#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_SHIFT 0 -#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK 0x0000ffff -#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT 16 -#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK 0xffff0000 -#define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x0000030c -#define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310 - - -#define NV10_CONTEXT_SURFACES_3D 0x00000093 - - - -#define NV04_TEXTURED_TRIANGLE 0x00000054 - -#define NV04_TEXTURED_TRIANGLE_NOP 0x00000100 -#define NV04_TEXTURED_TRIANGLE_NOTIFY 0x00000104 -#define NV04_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180 -#define NV04_TEXTURED_TRIANGLE_DMA_A 0x00000184 -#define NV04_TEXTURED_TRIANGLE_DMA_B 0x00000188 -#define NV04_TEXTURED_TRIANGLE_SURFACE 0x0000018c -#define NV04_TEXTURED_TRIANGLE_COLORKEY 0x00000300 -#define NV04_TEXTURED_TRIANGLE_OFFSET 0x00000304 -#define NV04_TEXTURED_TRIANGLE_FORMAT 0x00000308 -#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_A (1 << 0) -#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_B (1 << 1) -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT 2 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK 0x0000000c -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER 0x00000010 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 0x00000020 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER 0x00000040 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER 0x00000080 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8 0x00000100 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5 0x00000200 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5 0x00000300 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4 0x00000400 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5 0x00000500 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8 0x00000600 -#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8 0x00000700 -#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12 -#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20 -#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT 0x01000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT 0x02000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE 0x03000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER 0x04000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP 0x05000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPU (1 << 27) -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT 0x10000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT 0x20000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE 0x30000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER 0x40000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP 0x50000000 -#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPV (1 << 31) -#define NV04_TEXTURED_TRIANGLE_FILTER 0x0000030c -#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff -#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00 -#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15) -#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK 0x07000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST 0x01000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR 0x02000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27) -#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT 28 -#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST 0x10000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR 0x20000000 -#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31) -#define NV04_TEXTURED_TRIANGLE_BLEND 0x00000310 -#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK 0x0000000f -#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT 4 -#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030 -#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6 -#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0 -#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040 -#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080 -#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0 -#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8) -#define NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE (1 << 12) -#define NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE (1 << 16) -#define NV04_TEXTURED_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20) -#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000 -#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28 -#define NV04_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000 -#define NV04_TEXTURED_TRIANGLE_CONTROL 0x00000314 -#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK 0x000000ff -#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK 0x00000f00 -#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE (1 << 12) -#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN (1 << 13) -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE (1 << 14) -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK 0x000f0000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT 20 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK 0x00300000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_BOTH 0x00000000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_NONE 0x00100000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CW 0x00200000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW 0x00300000 -#define NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE (1 << 22) -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE (1 << 23) -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE (1 << 24) -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT 30 -#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK 0xc0000000 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR 0x00000318 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK 0xff000000 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00000400+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x00000404+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00000408+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x0000040c+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00000410+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK 0x000000ff -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK 0x0000ff00 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK 0x00ff0000 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK 0xff000000 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00000414+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK 0x000000ff -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK 0x0000ff00 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK 0x00ff0000 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00000418+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000041c+((x)*32)) -#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000010 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(x) (0x00000600+((x)*4)) -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000040 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20 -#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000 - - -#define NV10_TEXTURED_TRIANGLE 0x00000094 - - - -#define NV04_MULTITEX_TRIANGLE 0x00000055 - -#define NV04_MULTITEX_TRIANGLE_NOP 0x00000100 -#define NV04_MULTITEX_TRIANGLE_NOTIFY 0x00000104 -#define NV04_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180 -#define NV04_MULTITEX_TRIANGLE_DMA_A 0x00000184 -#define NV04_MULTITEX_TRIANGLE_DMA_B 0x00000188 -#define NV04_MULTITEX_TRIANGLE_SURFACE 0x0000018c -#define NV04_MULTITEX_TRIANGLE_OFFSET(x) (0x00000308+((x)*4)) -#define NV04_MULTITEX_TRIANGLE_OFFSET__SIZE 0x00000002 -#define NV04_MULTITEX_TRIANGLE_FORMAT(x) (0x00000310+((x)*4)) -#define NV04_MULTITEX_TRIANGLE_FORMAT__SIZE 0x00000002 -#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_A (1 << 0) -#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_B (1 << 1) -#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0 -#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00 -#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12 -#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000 -#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000 -#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20 -#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000 -#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPU (1 << 27) -#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28 -#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000 -#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPV (1 << 31) -#define NV04_MULTITEX_TRIANGLE_FILTER(x) (0x00000318+((x)*4)) -#define NV04_MULTITEX_TRIANGLE_FILTER__SIZE 0x00000002 -#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00 -#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15) -#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK 0x07000000 -#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27) -#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT 28 -#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000 -#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA(x) (0x00000320+((x)*12)) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__SIZE 0x00000002 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE0 (1 << 0) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_SHIFT 2 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_MASK 0x000000fc -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_ZERO 0x00000004 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_CONSTANT 0x00000008 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PRIMARY_COLOR 0x0000000c -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PREVIOUS 0x00000010 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE0 0x00000014 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE1 0x00000018 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE1 (1 << 8) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_SHIFT 10 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_MASK 0x0000fc00 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_ZERO 0x00000400 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_CONSTANT 0x00000800 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PRIMARY_COLOR 0x00000c00 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PREVIOUS 0x00001000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE0 0x00001400 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE1 0x00001800 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE2 (1 << 16) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_SHIFT 18 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_MASK 0x00fc0000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_ZERO 0x00040000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_CONSTANT 0x00080000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PRIMARY_COLOR 0x000c0000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PREVIOUS 0x00100000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE0 0x00140000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE1 0x00180000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE3 (1 << 24) -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_SHIFT 26 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_MASK 0x1c000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_ZERO 0x04000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_CONSTANT 0x08000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PRIMARY_COLOR 0x0c000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PREVIOUS 0x10000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE0 0x14000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE1 0x18000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SHIFT 29 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_MASK 0xe0000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_IDENTITY 0x20000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE2 0x40000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE4 0x60000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS 0x80000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS_SCALE2 0xe0000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR(x) (0x00000324+((x)*12)) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__SIZE 0x00000002 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE0 (1 << 0) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0 (1 << 1) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_SHIFT 2 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_MASK 0x000000fc -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_ZERO 0x00000004 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_CONSTANT 0x00000008 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PRIMARY_COLOR 0x0000000c -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PREVIOUS 0x00000010 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE0 0x00000014 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE1 0x00000018 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE1 (1 << 8) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA1 (1 << 9) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_SHIFT 10 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_MASK 0x0000fc00 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_ZERO 0x00000400 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_CONSTANT 0x00000800 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PRIMARY_COLOR 0x00000c00 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PREVIOUS 0x00001000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE0 0x00001400 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE1 0x00001800 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE2 (1 << 16) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA2 (1 << 17) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_SHIFT 18 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_MASK 0x00fc0000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_ZERO 0x00040000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_CONSTANT 0x00080000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PRIMARY_COLOR 0x000c0000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PREVIOUS 0x00100000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE0 0x00140000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE1 0x00180000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE3 (1 << 24) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA3 (1 << 25) -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_SHIFT 26 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_MASK 0x1c000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_ZERO 0x04000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_CONSTANT 0x08000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PRIMARY_COLOR 0x0c000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PREVIOUS 0x10000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE0 0x14000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE1 0x18000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SHIFT 29 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_MASK 0xe0000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_IDENTITY 0x20000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE2 0x40000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE4 0x60000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS 0x80000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS_SCALE2 0xe0000000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK 0x0000ff00 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK 0xff000000 -#define NV04_MULTITEX_TRIANGLE_BLEND 0x00000338 -#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT 4 -#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030 -#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6 -#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0 -#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040 -#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080 -#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0 -#define NV04_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8) -#define NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE (1 << 12) -#define NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE (1 << 16) -#define NV04_MULTITEX_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20) -#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000 -#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28 -#define NV04_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0 0x0000033c -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK 0x00000f00 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_ENABLE (1 << 12) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN (1 << 13) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE (1 << 14) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK 0x000f0000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT 20 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK 0x00300000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_BOTH 0x00000000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_NONE 0x00100000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CW 0x00200000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CCW 0x00300000 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE (1 << 22) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 23) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE (1 << 24) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE (1 << 25) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE (1 << 27) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE (1 << 28) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE (1 << 29) -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT 30 -#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK 0xc0000000 -#define NV04_MULTITEX_TRIANGLE_CONTROL1 0x00000340 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE (1 << 0) -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT 4 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK 0x000000f0 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK 0x0000ff00 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000 -#define NV04_MULTITEX_TRIANGLE_CONTROL2 0x00000344 -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK 0x0000000f -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT 4 -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK 0x000000f0 -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK 0x00000f00 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR 0x00000348 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK 0xff000000 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x) (0x00000400+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x) (0x00000404+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x) (0x00000408+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x) (0x0000040c+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x) (0x00000410+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK 0x0000ff00 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK 0xff000000 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x) (0x00000414+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK 0x000000ff -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK 0x0000ff00 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK 0x00ff0000 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT 24 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK 0xff000000 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x) (0x00000418+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x) (0x0000041c+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x) (0x00000420+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x) (0x00000424+((x)*40)) -#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE 0x00000008 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE(x) (0x00000540+((x)*4)) -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000030 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20 -#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000 - - -#define NV10_MULTITEX_TRIANGLE 0x00000095 - - - -#define NV10TCL 0x00000056 - -#define NV10TCL_NOP 0x00000100 -#define NV10TCL_NOTIFY 0x00000104 -#define NV10TCL_DMA_NOTIFY 0x00000180 -#define NV10TCL_DMA_IN_MEMORY0 0x00000184 -#define NV10TCL_DMA_IN_MEMORY1 0x00000188 -#define NV10TCL_DMA_VTXBUF0 0x0000018c -#define NV10TCL_DMA_IN_MEMORY2 0x00000194 -#define NV10TCL_DMA_IN_MEMORY3 0x00000198 -#define NV10TCL_RT_HORIZ 0x00000200 -#define NV10TCL_RT_HORIZ_X_SHIFT 0 -#define NV10TCL_RT_HORIZ_X_MASK 0x0000ffff -#define NV10TCL_RT_HORIZ_W_SHIFT 16 -#define NV10TCL_RT_HORIZ_W_MASK 0xffff0000 -#define NV10TCL_RT_VERT 0x00000204 -#define NV10TCL_RT_VERT_Y_SHIFT 0 -#define NV10TCL_RT_VERT_Y_MASK 0x0000ffff -#define NV10TCL_RT_VERT_H_SHIFT 16 -#define NV10TCL_RT_VERT_H_MASK 0xffff0000 -#define NV10TCL_RT_FORMAT 0x00000208 -#define NV10TCL_RT_FORMAT_TYPE_SHIFT 8 -#define NV10TCL_RT_FORMAT_TYPE_MASK 0x00000f00 -#define NV10TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 -#define NV10TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 -#define NV10TCL_RT_FORMAT_COLOR_SHIFT 0 -#define NV10TCL_RT_FORMAT_COLOR_MASK 0x0000001f -#define NV10TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 -#define NV10TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 -#define NV10TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 -#define NV10TCL_RT_FORMAT_COLOR_B8 0x00000009 -#define NV10TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d -#define NV10TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f -#define NV10TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 -#define NV10TCL_RT_PITCH 0x0000020c -#define NV10TCL_RT_PITCH_COLOR_PITCH_SHIFT 0 -#define NV10TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff -#define NV10TCL_RT_PITCH_ZETA_PITCH_SHIFT 16 -#define NV10TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000 -#define NV10TCL_COLOR_OFFSET 0x00000210 -#define NV10TCL_ZETA_OFFSET 0x00000214 -#define NV10TCL_TX_OFFSET(x) (0x00000218+((x)*4)) -#define NV10TCL_TX_OFFSET__SIZE 0x00000002 -#define NV10TCL_TX_FORMAT(x) (0x00000220+((x)*4)) -#define NV10TCL_TX_FORMAT__SIZE 0x00000002 -#define NV10TCL_TX_FORMAT_DMA0 (1 << 0) -#define NV10TCL_TX_FORMAT_DMA1 (1 << 1) -#define NV10TCL_TX_FORMAT_CUBE_MAP (1 << 2) -#define NV10TCL_TX_FORMAT_FORMAT_SHIFT 7 -#define NV10TCL_TX_FORMAT_FORMAT_MASK 0x00000f80 -#define NV10TCL_TX_FORMAT_FORMAT_L8 0x00000000 -#define NV10TCL_TX_FORMAT_FORMAT_A8 0x00000080 -#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000100 -#define NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000200 -#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000280 -#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000300 -#define NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000380 -#define NV10TCL_TX_FORMAT_FORMAT_INDEX8 0x00000580 -#define NV10TCL_TX_FORMAT_FORMAT_DXT1 0x00000600 -#define NV10TCL_TX_FORMAT_FORMAT_DXT3 0x00000700 -#define NV10TCL_TX_FORMAT_FORMAT_DXT5 0x00000780 -#define NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00000800 -#define NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00000880 -#define NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00000900 -#define NV10TCL_TX_FORMAT_FORMAT_A8_RECT 0x00000980 -#define NV10TCL_TX_FORMAT_MIPMAP (1 << 15) -#define NV10TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 16 -#define NV10TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x000f0000 -#define NV10TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 20 -#define NV10TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x00f00000 -#define NV10TCL_TX_FORMAT_WRAP_S_SHIFT 24 -#define NV10TCL_TX_FORMAT_WRAP_S_MASK 0x0f000000 -#define NV10TCL_TX_FORMAT_WRAP_S_REPEAT 0x01000000 -#define NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT 0x02000000 -#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE 0x03000000 -#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER 0x04000000 -#define NV10TCL_TX_FORMAT_WRAP_S_CLAMP 0x05000000 -#define NV10TCL_TX_FORMAT_WRAP_T_SHIFT 28 -#define NV10TCL_TX_FORMAT_WRAP_T_MASK 0xf0000000 -#define NV10TCL_TX_FORMAT_WRAP_T_REPEAT 0x10000000 -#define NV10TCL_TX_FORMAT_WRAP_T_MIRRORED_REPEAT 0x20000000 -#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE 0x30000000 -#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER 0x40000000 -#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP 0x50000000 -#define NV10TCL_TX_ENABLE(x) (0x00000228+((x)*4)) -#define NV10TCL_TX_ENABLE__SIZE 0x00000002 -#define NV10TCL_TX_ENABLE_CULL_SHIFT 0 -#define NV10TCL_TX_ENABLE_CULL_MASK 0x0000000f -#define NV10TCL_TX_ENABLE_CULL_DISABLED 0x00000000 -#define NV10TCL_TX_ENABLE_CULL_TEST_ALL 0x00000003 -#define NV10TCL_TX_ENABLE_CULL_TEST_ALPHA 0x00000004 -#define NV10TCL_TX_ENABLE_ANISOTROPY_SHIFT 4 -#define NV10TCL_TX_ENABLE_ANISOTROPY_MASK 0x00000030 -#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14 -#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000 -#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26 -#define NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000 -#define NV10TCL_TX_ENABLE_ENABLE (1 << 30) -#define NV10TCL_TX_NPOT_PITCH(x) (0x00000230+((x)*4)) -#define NV10TCL_TX_NPOT_PITCH__SIZE 0x00000002 -#define NV10TCL_TX_NPOT_PITCH_PITCH_SHIFT 16 -#define NV10TCL_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 -#define NV10TCL_TX_NPOT_SIZE(x) (0x00000240+((x)*4)) -#define NV10TCL_TX_NPOT_SIZE__SIZE 0x00000002 -#define NV10TCL_TX_NPOT_SIZE_H_SHIFT 0 -#define NV10TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff -#define NV10TCL_TX_NPOT_SIZE_W_SHIFT 16 -#define NV10TCL_TX_NPOT_SIZE_W_MASK 0xffff0000 -#define NV10TCL_TX_FILTER(x) (0x00000248+((x)*4)) -#define NV10TCL_TX_FILTER__SIZE 0x00000002 -#define NV10TCL_TX_FILTER_LOD_BIAS_SHIFT 8 -#define NV10TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00 -#define NV10TCL_TX_FILTER_MINIFY_SHIFT 24 -#define NV10TCL_TX_FILTER_MINIFY_MASK 0x0f000000 -#define NV10TCL_TX_FILTER_MINIFY_NEAREST 0x01000000 -#define NV10TCL_TX_FILTER_MINIFY_LINEAR 0x02000000 -#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000 -#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000 -#define NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000 -#define NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000 -#define NV10TCL_TX_FILTER_MAGNIFY_SHIFT 28 -#define NV10TCL_TX_FILTER_MAGNIFY_MASK 0xf0000000 -#define NV10TCL_TX_FILTER_MAGNIFY_NEAREST 0x10000000 -#define NV10TCL_TX_FILTER_MAGNIFY_LINEAR 0x20000000 -#define NV10TCL_TX_PALETTE_OFFSET(x) (0x00000250+((x)*4)) -#define NV10TCL_TX_PALETTE_OFFSET__SIZE 0x00000002 -#define NV10TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4)) -#define NV10TCL_RC_IN_ALPHA__SIZE 0x00000002 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f -#define NV10TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 -#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c -#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d -#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f -#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a -#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b -#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4) -#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 -#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12) -#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 -#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 -#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 -#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20) -#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 -#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 -#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 -#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28) -#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 -#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV10TCL_RC_IN_RGB(x) (0x00000268+((x)*4)) -#define NV10TCL_RC_IN_RGB__SIZE 0x00000002 -#define NV10TCL_RC_IN_RGB_D_INPUT_SHIFT 0 -#define NV10TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f -#define NV10TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV10TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003 -#define NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 -#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 -#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c -#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d -#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f -#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a -#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b -#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4) -#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV10TCL_RC_IN_RGB_D_MAPPING_SHIFT 5 -#define NV10TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0 -#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV10TCL_RC_IN_RGB_C_INPUT_SHIFT 8 -#define NV10TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00 -#define NV10TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300 -#define NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12) -#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_SHIFT 13 -#define NV10TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV10TCL_RC_IN_RGB_B_INPUT_SHIFT 16 -#define NV10TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV10TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000 -#define NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 -#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 -#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 -#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 -#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20) -#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_SHIFT 21 -#define NV10TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV10TCL_RC_IN_RGB_A_INPUT_SHIFT 24 -#define NV10TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 -#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 -#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28) -#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_SHIFT 29 -#define NV10TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV10TCL_RC_COLOR(x) (0x00000270+((x)*4)) -#define NV10TCL_RC_COLOR__SIZE 0x00000002 -#define NV10TCL_RC_COLOR_B_SHIFT 0 -#define NV10TCL_RC_COLOR_B_MASK 0x000000ff -#define NV10TCL_RC_COLOR_G_SHIFT 8 -#define NV10TCL_RC_COLOR_G_MASK 0x0000ff00 -#define NV10TCL_RC_COLOR_R_SHIFT 16 -#define NV10TCL_RC_COLOR_R_MASK 0x00ff0000 -#define NV10TCL_RC_COLOR_A_SHIFT 24 -#define NV10TCL_RC_COLOR_A_MASK 0xff000000 -#define NV10TCL_RC_OUT_ALPHA(x) (0x00000278+((x)*4)) -#define NV10TCL_RC_OUT_ALPHA__SIZE 0x00000002 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -#define NV10TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -#define NV10TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14) -#define NV10TCL_RC_OUT_ALPHA_BIAS (1 << 15) -#define NV10TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV10TCL_RC_OUT_ALPHA_SCALE_SHIFT 17 -#define NV10TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000 -#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000 -#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV10TCL_RC_OUT_RGB(x) (0x00000280+((x)*4)) -#define NV10TCL_RC_OUT_RGB__SIZE 0x00000002 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -#define NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -#define NV10TCL_RC_OUT_RGB_MUX_SUM (1 << 14) -#define NV10TCL_RC_OUT_RGB_BIAS (1 << 15) -#define NV10TCL_RC_OUT_RGB_BIAS_NONE 0x00000000 -#define NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV10TCL_RC_OUT_RGB_SCALE_SHIFT 17 -#define NV10TCL_RC_OUT_RGB_SCALE_MASK 0x00000000 -#define NV10TCL_RC_OUT_RGB_SCALE_NONE 0x00000000 -#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000 -#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV10TCL_RC_OUT_RGB_OPERATION_SHIFT 27 -#define NV10TCL_RC_OUT_RGB_OPERATION_MASK 0x38000000 -#define NV10TCL_RC_FINAL0 0x00000288 -#define NV10TCL_RC_FINAL0_D_INPUT_SHIFT 0 -#define NV10TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f -#define NV10TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV10TCL_RC_FINAL0_D_INPUT_FOG 0x00000003 -#define NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 -#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 -#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c -#define NV10TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d -#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f -#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a -#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b -#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4) -#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV10TCL_RC_FINAL0_D_MAPPING_SHIFT 5 -#define NV10TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0 -#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV10TCL_RC_FINAL0_C_INPUT_SHIFT 8 -#define NV10TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00 -#define NV10TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_FINAL0_C_INPUT_FOG 0x00000300 -#define NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12) -#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV10TCL_RC_FINAL0_C_MAPPING_SHIFT 13 -#define NV10TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000 -#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV10TCL_RC_FINAL0_B_INPUT_SHIFT 16 -#define NV10TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000 -#define NV10TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV10TCL_RC_FINAL0_B_INPUT_FOG 0x00030000 -#define NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 -#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 -#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 -#define NV10TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 -#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 -#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 -#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 -#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20) -#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV10TCL_RC_FINAL0_B_MAPPING_SHIFT 21 -#define NV10TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000 -#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV10TCL_RC_FINAL0_A_INPUT_SHIFT 24 -#define NV10TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000 -#define NV10TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV10TCL_RC_FINAL0_A_INPUT_FOG 0x03000000 -#define NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 -#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 -#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 -#define NV10TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 -#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 -#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 -#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 -#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28) -#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_SHIFT 29 -#define NV10TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV10TCL_RC_FINAL1 0x0000028c -#define NV10TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -#define NV10TCL_RC_FINAL1_G_INPUT_SHIFT 8 -#define NV10TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00 -#define NV10TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV10TCL_RC_FINAL1_G_INPUT_FOG 0x00000300 -#define NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 -#define NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 -#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 -#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 -#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 -#define NV10TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 -#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 -#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 -#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 -#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12) -#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV10TCL_RC_FINAL1_G_MAPPING_SHIFT 13 -#define NV10TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000 -#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV10TCL_RC_FINAL1_F_INPUT_SHIFT 16 -#define NV10TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000 -#define NV10TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV10TCL_RC_FINAL1_F_INPUT_FOG 0x00030000 -#define NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 -#define NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 -#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 -#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 -#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 -#define NV10TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 -#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 -#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 -#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 -#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20) -#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV10TCL_RC_FINAL1_F_MAPPING_SHIFT 21 -#define NV10TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000 -#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV10TCL_RC_FINAL1_E_INPUT_SHIFT 24 -#define NV10TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000 -#define NV10TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000 -#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV10TCL_RC_FINAL1_E_INPUT_FOG 0x03000000 -#define NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 -#define NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 -#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 -#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 -#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 -#define NV10TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 -#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 -#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 -#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 -#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28) -#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 -#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_SHIFT 29 -#define NV10TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV10TCL_LIGHT_MODEL 0x00000294 -#define NV10TCL_LIGHT_MODEL_VERTEX_SPECULAR (1 << 0) -#define NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 1) -#define NV10TCL_LIGHT_MODEL_LOCAL_VIEWER (1 << 16) -#define NV10TCL_COLOR_MATERIAL 0x00000298 -#define NV10TCL_COLOR_MATERIAL_EMISSION (1 << 0) -#define NV10TCL_COLOR_MATERIAL_AMBIENT (1 << 1) -#define NV10TCL_COLOR_MATERIAL_DIFFUSE (1 << 2) -#define NV10TCL_COLOR_MATERIAL_SPECULAR (1 << 3) -#define NV10TCL_FOG_MODE 0x0000029c -#define NV10TCL_FOG_MODE_LINEAR 0x00002601 -#define NV10TCL_FOG_MODE_EXP 0x00000800 -#define NV10TCL_FOG_MODE_EXP_ABS 0x00000802 -#define NV10TCL_FOG_MODE_EXP2 0x00000803 -#define NV10TCL_FOG_COORD 0x000002a0 -#define NV10TCL_FOG_COORD_FOG 0x00000000 -#define NV10TCL_FOG_COORD_DIST_RADIAL 0x00000001 -#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002 -#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003 -#define NV10TCL_FOG_ENABLE 0x000002a4 -#define NV10TCL_FOG_COLOR 0x000002a8 -#define NV10TCL_FOG_COLOR_R_SHIFT 0 -#define NV10TCL_FOG_COLOR_R_MASK 0x000000ff -#define NV10TCL_FOG_COLOR_G_SHIFT 8 -#define NV10TCL_FOG_COLOR_G_MASK 0x0000ff00 -#define NV10TCL_FOG_COLOR_B_SHIFT 16 -#define NV10TCL_FOG_COLOR_B_MASK 0x00ff0000 -#define NV10TCL_FOG_COLOR_A_SHIFT 24 -#define NV10TCL_FOG_COLOR_A_MASK 0xff000000 -#define NV10TCL_VIEWPORT_CLIP_MODE 0x000002b4 -#define NV10TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4)) -#define NV10TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_SHIFT 0 -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_MASK 0x000007ff -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE (1 << 11) -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_SHIFT 16 -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_MASK 0x07ff0000 -#define NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE (1 << 27) -#define NV10TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4)) -#define NV10TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_SHIFT 0 -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_MASK 0x000007ff -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE (1 << 11) -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_SHIFT 16 -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_MASK 0x07ff0000 -#define NV10TCL_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE (1 << 27) -#define NV10TCL_ALPHA_FUNC_ENABLE 0x00000300 -#define NV10TCL_BLEND_FUNC_ENABLE 0x00000304 -#define NV10TCL_CULL_FACE_ENABLE 0x00000308 -#define NV10TCL_DEPTH_TEST_ENABLE 0x0000030c -#define NV10TCL_DITHER_ENABLE 0x00000310 -#define NV10TCL_LIGHTING_ENABLE 0x00000314 -#define NV10TCL_POINT_PARAMETERS_ENABLE 0x00000318 -#define NV10TCL_POINT_SMOOTH_ENABLE 0x0000031c -#define NV10TCL_LINE_SMOOTH_ENABLE 0x00000320 -#define NV10TCL_POLYGON_SMOOTH_ENABLE 0x00000324 -#define NV10TCL_VERTEX_WEIGHT_ENABLE 0x00000328 -#define NV10TCL_STENCIL_ENABLE 0x0000032c -#define NV10TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330 -#define NV10TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334 -#define NV10TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338 -#define NV10TCL_ALPHA_FUNC_FUNC 0x0000033c -#define NV10TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200 -#define NV10TCL_ALPHA_FUNC_FUNC_LESS 0x00000201 -#define NV10TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202 -#define NV10TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 -#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204 -#define NV10TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV10TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 -#define NV10TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 -#define NV10TCL_ALPHA_FUNC_REF 0x00000340 -#define NV10TCL_BLEND_FUNC_SRC 0x00000344 -#define NV10TCL_BLEND_FUNC_SRC_ZERO 0x00000000 -#define NV10TCL_BLEND_FUNC_SRC_ONE 0x00000001 -#define NV10TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV10TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV10TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307 -#define NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308 -#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV10TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003 -#define NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV10TCL_BLEND_FUNC_DST 0x00000348 -#define NV10TCL_BLEND_FUNC_DST_ZERO 0x00000000 -#define NV10TCL_BLEND_FUNC_DST_ONE 0x00000001 -#define NV10TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV10TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV10TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307 -#define NV10TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308 -#define NV10TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV10TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003 -#define NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV10TCL_BLEND_COLOR 0x0000034c -#define NV10TCL_BLEND_COLOR_B_SHIFT 0 -#define NV10TCL_BLEND_COLOR_B_MASK 0x000000ff -#define NV10TCL_BLEND_COLOR_G_SHIFT 8 -#define NV10TCL_BLEND_COLOR_G_MASK 0x0000ff00 -#define NV10TCL_BLEND_COLOR_R_SHIFT 16 -#define NV10TCL_BLEND_COLOR_R_MASK 0x00ff0000 -#define NV10TCL_BLEND_COLOR_A_SHIFT 24 -#define NV10TCL_BLEND_COLOR_A_MASK 0xff000000 -#define NV10TCL_BLEND_EQUATION 0x00000350 -#define NV10TCL_BLEND_EQUATION_FUNC_ADD 0x00008006 -#define NV10TCL_BLEND_EQUATION_MIN 0x00008007 -#define NV10TCL_BLEND_EQUATION_MAX 0x00008008 -#define NV10TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a -#define NV10TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV10TCL_DEPTH_FUNC 0x00000354 -#define NV10TCL_DEPTH_FUNC_NEVER 0x00000200 -#define NV10TCL_DEPTH_FUNC_LESS 0x00000201 -#define NV10TCL_DEPTH_FUNC_EQUAL 0x00000202 -#define NV10TCL_DEPTH_FUNC_LEQUAL 0x00000203 -#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204 -#define NV10TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 -#define NV10TCL_DEPTH_FUNC_GEQUAL 0x00000206 -#define NV10TCL_DEPTH_FUNC_ALWAYS 0x00000207 -#define NV10TCL_COLOR_MASK 0x00000358 -#define NV10TCL_COLOR_MASK_B (1 << 0) -#define NV10TCL_COLOR_MASK_G (1 << 8) -#define NV10TCL_COLOR_MASK_R (1 << 16) -#define NV10TCL_COLOR_MASK_A (1 << 24) -#define NV10TCL_DEPTH_WRITE_ENABLE 0x0000035c -#define NV10TCL_STENCIL_MASK 0x00000360 -#define NV10TCL_STENCIL_FUNC_FUNC 0x00000364 -#define NV10TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200 -#define NV10TCL_STENCIL_FUNC_FUNC_LESS 0x00000201 -#define NV10TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202 -#define NV10TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 -#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204 -#define NV10TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV10TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 -#define NV10TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 -#define NV10TCL_STENCIL_FUNC_REF 0x00000368 -#define NV10TCL_STENCIL_FUNC_MASK 0x0000036c -#define NV10TCL_STENCIL_OP_FAIL 0x00000370 -#define NV10TCL_STENCIL_OP_FAIL_ZERO 0x00000000 -#define NV10TCL_STENCIL_OP_FAIL_INVERT 0x0000150a -#define NV10TCL_STENCIL_OP_FAIL_KEEP 0x00001e00 -#define NV10TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01 -#define NV10TCL_STENCIL_OP_FAIL_INCR 0x00001e02 -#define NV10TCL_STENCIL_OP_FAIL_DECR 0x00001e03 -#define NV10TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 -#define NV10TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 -#define NV10TCL_STENCIL_OP_ZFAIL 0x00000374 -#define NV10TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000 -#define NV10TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a -#define NV10TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00 -#define NV10TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 -#define NV10TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02 -#define NV10TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03 -#define NV10TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV10TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV10TCL_STENCIL_OP_ZPASS 0x00000378 -#define NV10TCL_STENCIL_OP_ZPASS_ZERO 0x00000000 -#define NV10TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a -#define NV10TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00 -#define NV10TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01 -#define NV10TCL_STENCIL_OP_ZPASS_INCR 0x00001e02 -#define NV10TCL_STENCIL_OP_ZPASS_DECR 0x00001e03 -#define NV10TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV10TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV10TCL_SHADE_MODEL 0x0000037c -#define NV10TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NV10TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NV10TCL_LINE_WIDTH 0x00000380 -#define NV10TCL_POLYGON_OFFSET_FACTOR 0x00000384 -#define NV10TCL_POLYGON_OFFSET_UNITS 0x00000388 -#define NV10TCL_POLYGON_MODE_FRONT 0x0000038c -#define NV10TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NV10TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NV10TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NV10TCL_POLYGON_MODE_BACK 0x00000390 -#define NV10TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NV10TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NV10TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NV10TCL_DEPTH_RANGE_NEAR 0x00000394 -#define NV10TCL_DEPTH_RANGE_FAR 0x00000398 -#define NV10TCL_CULL_FACE 0x0000039c -#define NV10TCL_CULL_FACE_FRONT 0x00000404 -#define NV10TCL_CULL_FACE_BACK 0x00000405 -#define NV10TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NV10TCL_FRONT_FACE 0x000003a0 -#define NV10TCL_FRONT_FACE_CW 0x00000900 -#define NV10TCL_FRONT_FACE_CCW 0x00000901 -#define NV10TCL_NORMALIZE_ENABLE 0x000003a4 -#define NV10TCL_MATERIAL_FACTOR_R 0x000003a8 -#define NV10TCL_MATERIAL_FACTOR_G 0x000003ac -#define NV10TCL_MATERIAL_FACTOR_B 0x000003b0 -#define NV10TCL_MATERIAL_FACTOR_A 0x000003b4 -#define NV10TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8 -#define NV10TCL_ENABLED_LIGHTS 0x000003bc -#define NV10TCL_ENABLED_LIGHTS_0_SHIFT 0 -#define NV10TCL_ENABLED_LIGHTS_0_MASK 0x00000003 -#define NV10TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001 -#define NV10TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002 -#define NV10TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003 -#define NV10TCL_ENABLED_LIGHTS_1_SHIFT 2 -#define NV10TCL_ENABLED_LIGHTS_1_MASK 0x0000000c -#define NV10TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004 -#define NV10TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008 -#define NV10TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c -#define NV10TCL_ENABLED_LIGHTS_2_SHIFT 4 -#define NV10TCL_ENABLED_LIGHTS_2_MASK 0x00000030 -#define NV10TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010 -#define NV10TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020 -#define NV10TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030 -#define NV10TCL_ENABLED_LIGHTS_3_SHIFT 6 -#define NV10TCL_ENABLED_LIGHTS_3_MASK 0x000000c0 -#define NV10TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040 -#define NV10TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080 -#define NV10TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0 -#define NV10TCL_ENABLED_LIGHTS_4_SHIFT 8 -#define NV10TCL_ENABLED_LIGHTS_4_MASK 0x00000300 -#define NV10TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100 -#define NV10TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200 -#define NV10TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300 -#define NV10TCL_ENABLED_LIGHTS_5_SHIFT 10 -#define NV10TCL_ENABLED_LIGHTS_5_MASK 0x00000c00 -#define NV10TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400 -#define NV10TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800 -#define NV10TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00 -#define NV10TCL_ENABLED_LIGHTS_6_SHIFT 12 -#define NV10TCL_ENABLED_LIGHTS_6_MASK 0x00003000 -#define NV10TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000 -#define NV10TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000 -#define NV10TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000 -#define NV10TCL_ENABLED_LIGHTS_7_SHIFT 14 -#define NV10TCL_ENABLED_LIGHTS_7_MASK 0x0000c000 -#define NV10TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000 -#define NV10TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000 -#define NV10TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000 -#define NV10TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000 -#define NV10TCL_TX_GEN_MODE_S(x) (0x000003c0+((x)*16)) -#define NV10TCL_TX_GEN_MODE_S__SIZE 0x00000002 -#define NV10TCL_TX_GEN_MODE_S_FALSE 0x00000000 -#define NV10TCL_TX_GEN_MODE_S_EYE_LINEAR 0x00002400 -#define NV10TCL_TX_GEN_MODE_S_OBJECT_LINEAR 0x00002401 -#define NV10TCL_TX_GEN_MODE_S_SPHERE_MAP 0x00002402 -#define NV10TCL_TX_GEN_MODE_S_NORMAL_MAP 0x00008511 -#define NV10TCL_TX_GEN_MODE_S_REFLECTION_MAP 0x00008512 -#define NV10TCL_TX_GEN_MODE_T(x) (0x000003c4+((x)*16)) -#define NV10TCL_TX_GEN_MODE_T__SIZE 0x00000002 -#define NV10TCL_TX_GEN_MODE_T_FALSE 0x00000000 -#define NV10TCL_TX_GEN_MODE_T_EYE_LINEAR 0x00002400 -#define NV10TCL_TX_GEN_MODE_T_OBJECT_LINEAR 0x00002401 -#define NV10TCL_TX_GEN_MODE_T_SPHERE_MAP 0x00002402 -#define NV10TCL_TX_GEN_MODE_T_NORMAL_MAP 0x00008511 -#define NV10TCL_TX_GEN_MODE_T_REFLECTION_MAP 0x00008512 -#define NV10TCL_TX_GEN_MODE_R(x) (0x000003c8+((x)*16)) -#define NV10TCL_TX_GEN_MODE_R__SIZE 0x00000002 -#define NV10TCL_TX_GEN_MODE_R_FALSE 0x00000000 -#define NV10TCL_TX_GEN_MODE_R_EYE_LINEAR 0x00002400 -#define NV10TCL_TX_GEN_MODE_R_OBJECT_LINEAR 0x00002401 -#define NV10TCL_TX_GEN_MODE_R_SPHERE_MAP 0x00002402 -#define NV10TCL_TX_GEN_MODE_R_NORMAL_MAP 0x00008511 -#define NV10TCL_TX_GEN_MODE_R_REFLECTION_MAP 0x00008512 -#define NV10TCL_TX_GEN_MODE_Q(x) (0x000003cc+((x)*16)) -#define NV10TCL_TX_GEN_MODE_Q__SIZE 0x00000002 -#define NV10TCL_TX_GEN_MODE_Q_FALSE 0x00000000 -#define NV10TCL_TX_GEN_MODE_Q_EYE_LINEAR 0x00002400 -#define NV10TCL_TX_GEN_MODE_Q_OBJECT_LINEAR 0x00002401 -#define NV10TCL_TX_GEN_MODE_Q_SPHERE_MAP 0x00002402 -#define NV10TCL_TX_GEN_MODE_Q_NORMAL_MAP 0x00008511 -#define NV10TCL_TX_GEN_MODE_Q_REFLECTION_MAP 0x00008512 -#define NV10TCL_TX_MATRIX_ENABLE(x) (0x000003e0+((x)*4)) -#define NV10TCL_TX_MATRIX_ENABLE__SIZE 0x00000002 -#define NV10TCL_VIEW_MATRIX_ENABLE 0x000003e8 -#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW1 (1 << 0) -#define NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW0 (1 << 1) -#define NV10TCL_VIEW_MATRIX_ENABLE_PROJECTION (1 << 2) -#define NV10TCL_POINT_SIZE 0x000003ec -#define NV10TCL_MODELVIEW0_MATRIX(x) (0x00000400+((x)*4)) -#define NV10TCL_MODELVIEW0_MATRIX__SIZE 0x00000010 -#define NV10TCL_MODELVIEW1_MATRIX(x) (0x00000440+((x)*4)) -#define NV10TCL_MODELVIEW1_MATRIX__SIZE 0x00000010 -#define NV10TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4)) -#define NV10TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010 -#define NV10TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4)) -#define NV10TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010 -#define NV10TCL_PROJECTION_MATRIX(x) (0x00000500+((x)*4)) -#define NV10TCL_PROJECTION_MATRIX__SIZE 0x00000010 -#define NV10TCL_TX0_MATRIX(x) (0x00000540+((x)*4)) -#define NV10TCL_TX0_MATRIX__SIZE 0x00000010 -#define NV10TCL_TX1_MATRIX(x) (0x00000580+((x)*4)) -#define NV10TCL_TX1_MATRIX__SIZE 0x00000010 -#define NV10TCL_TX_GEN_COEFF_S_A(x) (0x00000600+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_S_A__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_S_B(x) (0x00000604+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_S_B__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_S_C(x) (0x00000608+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_S_C__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_S_D(x) (0x0000060c+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_S_D__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_T_A(x) (0x00000610+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_T_A__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_T_B(x) (0x00000614+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_T_B__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_T_C(x) (0x00000618+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_T_C__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_T_D(x) (0x0000061c+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_T_D__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_R_A(x) (0x00000620+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_R_A__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_R_B(x) (0x00000624+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_R_B__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_R_C(x) (0x00000628+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_R_C__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_R_D(x) (0x0000062c+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_R_D__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_Q_A(x) (0x00000630+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_Q_A__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_Q_B(x) (0x00000634+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_Q_B__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_Q_C(x) (0x00000638+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_Q_C__SIZE 0x00000002 -#define NV10TCL_TX_GEN_COEFF_Q_D(x) (0x0000063c+((x)*64)) -#define NV10TCL_TX_GEN_COEFF_Q_D__SIZE 0x00000002 -#define NV10TCL_FOG_EQUATION_CONSTANT 0x00000680 -#define NV10TCL_FOG_EQUATION_LINEAR 0x00000684 -#define NV10TCL_FOG_EQUATION_QUADRATIC 0x00000688 -#define NV10TCL_MATERIAL_SHININESS(x) (0x000006a0+((x)*4)) -#define NV10TCL_MATERIAL_SHININESS__SIZE 0x00000006 -#define NV10TCL_LIGHT_MODEL_AMBIENT_R 0x000006c4 -#define NV10TCL_LIGHT_MODEL_AMBIENT_G 0x000006c8 -#define NV10TCL_LIGHT_MODEL_AMBIENT_B 0x000006cc -#define NV10TCL_VIEWPORT_TRANSLATE_X 0x000006e8 -#define NV10TCL_VIEWPORT_TRANSLATE_Y 0x000006ec -#define NV10TCL_VIEWPORT_TRANSLATE_Z 0x000006f0 -#define NV10TCL_VIEWPORT_TRANSLATE_W 0x000006f4 -#define NV10TCL_POINT_PARAMETER(x) (0x000006f8+((x)*4)) -#define NV10TCL_POINT_PARAMETER__SIZE 0x00000008 -#define NV10TCL_LIGHT_AMBIENT_R(x) (0x00000800+((x)*128)) -#define NV10TCL_LIGHT_AMBIENT_R__SIZE 0x00000008 -#define NV10TCL_LIGHT_AMBIENT_G(x) (0x00000804+((x)*128)) -#define NV10TCL_LIGHT_AMBIENT_G__SIZE 0x00000008 -#define NV10TCL_LIGHT_AMBIENT_B(x) (0x00000808+((x)*128)) -#define NV10TCL_LIGHT_AMBIENT_B__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIFFUSE_R(x) (0x0000080c+((x)*128)) -#define NV10TCL_LIGHT_DIFFUSE_R__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIFFUSE_G(x) (0x00000810+((x)*128)) -#define NV10TCL_LIGHT_DIFFUSE_G__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIFFUSE_B(x) (0x00000814+((x)*128)) -#define NV10TCL_LIGHT_DIFFUSE_B__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPECULAR_R(x) (0x00000818+((x)*128)) -#define NV10TCL_LIGHT_SPECULAR_R__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPECULAR_G(x) (0x0000081c+((x)*128)) -#define NV10TCL_LIGHT_SPECULAR_G__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPECULAR_B(x) (0x00000820+((x)*128)) -#define NV10TCL_LIGHT_SPECULAR_B__SIZE 0x00000008 -#define NV10TCL_LIGHT_HALF_VECTOR_X(x) (0x00000828+((x)*128)) -#define NV10TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008 -#define NV10TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000082c+((x)*128)) -#define NV10TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008 -#define NV10TCL_LIGHT_HALF_VECTOR_Z(x) (0x00000830+((x)*128)) -#define NV10TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIRECTION_X(x) (0x00000834+((x)*128)) -#define NV10TCL_LIGHT_DIRECTION_X__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIRECTION_Y(x) (0x00000838+((x)*128)) -#define NV10TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008 -#define NV10TCL_LIGHT_DIRECTION_Z(x) (0x0000083c+((x)*128)) -#define NV10TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00000840+((x)*128)) -#define NV10TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00000844+((x)*128)) -#define NV10TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00000848+((x)*128)) -#define NV10TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_DIR_X(x) (0x0000084c+((x)*128)) -#define NV10TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_DIR_Y(x) (0x00000850+((x)*128)) -#define NV10TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_DIR_Z(x) (0x00000854+((x)*128)) -#define NV10TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008 -#define NV10TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00000858+((x)*128)) -#define NV10TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008 -#define NV10TCL_LIGHT_POSITION_X(x) (0x0000085c+((x)*128)) -#define NV10TCL_LIGHT_POSITION_X__SIZE 0x00000008 -#define NV10TCL_LIGHT_POSITION_Y(x) (0x00000860+((x)*128)) -#define NV10TCL_LIGHT_POSITION_Y__SIZE 0x00000008 -#define NV10TCL_LIGHT_POSITION_Z(x) (0x00000864+((x)*128)) -#define NV10TCL_LIGHT_POSITION_Z__SIZE 0x00000008 -#define NV10TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00000868+((x)*128)) -#define NV10TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008 -#define NV10TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000086c+((x)*128)) -#define NV10TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008 -#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00000870+((x)*128)) -#define NV10TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008 -#define NV10TCL_VERTEX_POS_3F_X 0x00000c00 -#define NV10TCL_VERTEX_POS_3F_Y 0x00000c04 -#define NV10TCL_VERTEX_POS_3F_Z 0x00000c08 -#define NV10TCL_VERTEX_POS_4F_X 0x00000c18 -#define NV10TCL_VERTEX_POS_4F_Y 0x00000c1c -#define NV10TCL_VERTEX_POS_4F_Z 0x00000c20 -#define NV10TCL_VERTEX_POS_4F_W 0x00000c24 -#define NV10TCL_VERTEX_NOR_3F_X 0x00000c30 -#define NV10TCL_VERTEX_NOR_3F_Y 0x00000c34 -#define NV10TCL_VERTEX_NOR_3F_Z 0x00000c38 -#define NV10TCL_VERTEX_NOR_3I_XY 0x00000c40 -#define NV10TCL_VERTEX_NOR_3I_XY_X_SHIFT 0 -#define NV10TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -#define NV10TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16 -#define NV10TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -#define NV10TCL_VERTEX_NOR_3I_Z 0x00000c44 -#define NV10TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0 -#define NV10TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -#define NV10TCL_VERTEX_COL_4F_R 0x00000c50 -#define NV10TCL_VERTEX_COL_4F_G 0x00000c54 -#define NV10TCL_VERTEX_COL_4F_B 0x00000c58 -#define NV10TCL_VERTEX_COL_4F_A 0x00000c5c -#define NV10TCL_VERTEX_COL_3F_R 0x00000c60 -#define NV10TCL_VERTEX_COL_3F_G 0x00000c64 -#define NV10TCL_VERTEX_COL_3F_B 0x00000c68 -#define NV10TCL_VERTEX_COL_4I 0x00000c6c -#define NV10TCL_VERTEX_COL_4I_R_SHIFT 0 -#define NV10TCL_VERTEX_COL_4I_R_MASK 0x000000ff -#define NV10TCL_VERTEX_COL_4I_G_SHIFT 8 -#define NV10TCL_VERTEX_COL_4I_G_MASK 0x0000ff00 -#define NV10TCL_VERTEX_COL_4I_B_SHIFT 16 -#define NV10TCL_VERTEX_COL_4I_B_MASK 0x00ff0000 -#define NV10TCL_VERTEX_COL_4I_A_SHIFT 24 -#define NV10TCL_VERTEX_COL_4I_A_MASK 0xff000000 -#define NV10TCL_VERTEX_COL2_3F_R 0x00000c80 -#define NV10TCL_VERTEX_COL2_3F_G 0x00000c84 -#define NV10TCL_VERTEX_COL2_3F_B 0x00000c88 -#define NV10TCL_VERTEX_COL2_3I 0x00000c8c -#define NV10TCL_VERTEX_COL2_3I_R_SHIFT 0 -#define NV10TCL_VERTEX_COL2_3I_R_MASK 0x000000ff -#define NV10TCL_VERTEX_COL2_3I_G_SHIFT 8 -#define NV10TCL_VERTEX_COL2_3I_G_MASK 0x0000ff00 -#define NV10TCL_VERTEX_COL2_3I_B_SHIFT 16 -#define NV10TCL_VERTEX_COL2_3I_B_MASK 0x00ff0000 -#define NV10TCL_VERTEX_TX0_2F_S 0x00000c90 -#define NV10TCL_VERTEX_TX0_2F_T 0x00000c94 -#define NV10TCL_VERTEX_TX0_2I 0x00000c98 -#define NV10TCL_VERTEX_TX0_2I_S_SHIFT 0 -#define NV10TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX0_2I_T_SHIFT 16 -#define NV10TCL_VERTEX_TX0_2I_T_MASK 0xffff0000 -#define NV10TCL_VERTEX_TX0_4F_S 0x00000ca0 -#define NV10TCL_VERTEX_TX0_4F_T 0x00000ca4 -#define NV10TCL_VERTEX_TX0_4F_R 0x00000ca8 -#define NV10TCL_VERTEX_TX0_4F_Q 0x00000cac -#define NV10TCL_VERTEX_TX0_4I_ST 0x00000cb0 -#define NV10TCL_VERTEX_TX0_4I_ST_S_SHIFT 0 -#define NV10TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX0_4I_ST_T_SHIFT 16 -#define NV10TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -#define NV10TCL_VERTEX_TX0_4I_RQ 0x00000cb4 -#define NV10TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0 -#define NV10TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -#define NV10TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -#define NV10TCL_VERTEX_TX1_2F_S 0x00000cb8 -#define NV10TCL_VERTEX_TX1_2F_T 0x00000cbc -#define NV10TCL_VERTEX_TX1_2I 0x00000cc0 -#define NV10TCL_VERTEX_TX1_2I_S_SHIFT 0 -#define NV10TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX1_2I_T_SHIFT 16 -#define NV10TCL_VERTEX_TX1_2I_T_MASK 0xffff0000 -#define NV10TCL_VERTEX_TX1_4F_S 0x00000cc8 -#define NV10TCL_VERTEX_TX1_4F_T 0x00000ccc -#define NV10TCL_VERTEX_TX1_4F_R 0x00000cd0 -#define NV10TCL_VERTEX_TX1_4F_Q 0x00000cd4 -#define NV10TCL_VERTEX_TX1_4I_ST 0x00000cd8 -#define NV10TCL_VERTEX_TX1_4I_ST_S_SHIFT 0 -#define NV10TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX1_4I_ST_T_SHIFT 16 -#define NV10TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -#define NV10TCL_VERTEX_TX1_4I_RQ 0x00000cdc -#define NV10TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0 -#define NV10TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -#define NV10TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -#define NV10TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -#define NV10TCL_VERTEX_FOG_1F 0x00000ce0 -#define NV10TCL_VERTEX_WGH_1F 0x00000ce4 -#define NV10TCL_EDGEFLAG_ENABLE 0x00000cec -#define NV10TCL_VERTEX_ARRAY_VALIDATE 0x00000cf0 -#define NV10TCL_VTXBUF_ADDRESS(x) (0x00000d00+((x)*8)) -#define NV10TCL_VTXBUF_ADDRESS__SIZE 0x00000008 -#define NV10TCL_VTXFMT(x) (0x00000d04+((x)*8)) -#define NV10TCL_VTXFMT__SIZE 0x00000008 -#define NV10TCL_VTXFMT_TYPE_SHIFT 0 -#define NV10TCL_VTXFMT_TYPE_MASK 0x0000000f -#define NV10TCL_VTXFMT_TYPE_BYTE_BGRA 0x00000000 -#define NV10TCL_VTXFMT_TYPE_SHORT 0x00000001 -#define NV10TCL_VTXFMT_TYPE_FLOAT 0x00000002 -#define NV10TCL_VTXFMT_TYPE_BYTE_RGBA 0x00000004 -#define NV10TCL_VTXFMT_FIELDS_SHIFT 4 -#define NV10TCL_VTXFMT_FIELDS_MASK 0x000000f0 -#define NV10TCL_VTXFMT_STRIDE_SHIFT 8 -#define NV10TCL_VTXFMT_STRIDE_MASK 0x0000ff00 -#define NV10TCL_VTXFMT_POS_HOMOGENEOUS (1 << 24) -#define NV10TCL_VERTEX_BEGIN_END 0x00000dfc -#define NV10TCL_VERTEX_BEGIN_END_STOP 0x00000000 -#define NV10TCL_VERTEX_BEGIN_END_POINTS 0x00000001 -#define NV10TCL_VERTEX_BEGIN_END_LINES 0x00000002 -#define NV10TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 -#define NV10TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 -#define NV10TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005 -#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 -#define NV10TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 -#define NV10TCL_VERTEX_BEGIN_END_QUADS 0x00000008 -#define NV10TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 -#define NV10TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a -#define NV10TCL_VB_ELEMENT_U16 0x00000e00 -#define NV10TCL_VB_ELEMENT_U16_I0_SHIFT 0 -#define NV10TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff -#define NV10TCL_VB_ELEMENT_U16_I1_SHIFT 16 -#define NV10TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 -#define NV10TCL_VB_ELEMENT_U32 0x00001100 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END 0x000013fc -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_STOP 0x00000000 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POINTS 0x00000001 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINES 0x00000002 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_LOOP 0x00000003 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_STRIP 0x00000004 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLES 0x00000005 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_STRIP 0x00000006 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_FAN 0x00000007 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUADS 0x00000008 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_QUAD_STRIP 0x00000009 -#define NV10TCL_VERTEX_BUFFER_BEGIN_END_POLYGON 0x0000000a -#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS 0x00001400 -#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_SHIFT 0 -#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK 0x0000ffff -#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_SHIFT 24 -#define NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_MASK 0xff000000 -#define NV10TCL_VERTEX_ARRAY_DATA 0x00001800 - - -#define NV11TCL 0x00000096 - -#define NV11TCL_COLOR_LOGIC_OP_ENABLE 0x00000d40 -#define NV11TCL_COLOR_LOGIC_OP_OP 0x00000d44 -#define NV11TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 -#define NV11TCL_COLOR_LOGIC_OP_OP_AND 0x00001501 -#define NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 -#define NV11TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503 -#define NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 -#define NV11TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505 -#define NV11TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506 -#define NV11TCL_COLOR_LOGIC_OP_OP_OR 0x00001507 -#define NV11TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508 -#define NV11TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 -#define NV11TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a -#define NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b -#define NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c -#define NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d -#define NV11TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e -#define NV11TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f - - -#define NV17TCL 0x00000099 - -#define NV17TCL_DMA_IN_MEMORY4 0x000001ac -#define NV17TCL_DMA_IN_MEMORY5 0x000001b0 -#define NV17TCL_COLOR_MASK_ENABLE 0x000002bc -#define NV17TCL_LMA_DEPTH_BUFFER_PITCH 0x00000d5c -#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET 0x00000d60 -#define NV17TCL_LMA_DEPTH_FILL_VALUE 0x00000d68 -#define NV17TCL_LMA_DEPTH_BUFFER_CLEAR 0x00000d6c -#define NV17TCL_LMA_DEPTH_WINDOW_X 0x00001638 -#define NV17TCL_LMA_DEPTH_WINDOW_Y 0x0000163c -#define NV17TCL_LMA_DEPTH_WINDOW_Z 0x00001640 -#define NV17TCL_LMA_DEPTH_WINDOW_W 0x00001644 -#define NV17TCL_LMA_DEPTH_ENABLE 0x00001658 - - -#define NV03_CONTEXT_SURFACES_2D 0x00000058 - -#define NV03_CONTEXT_SURFACES_2D_SYNCHRONIZE 0x00000100 -#define NV03_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 -#define NV03_CONTEXT_SURFACES_2D_DMA_SOURCE 0x00000184 -#define NV03_CONTEXT_SURFACES_2D_DMA_DESTIN 0x00000188 -#define NV03_CONTEXT_SURFACES_2D_COLOR_FORMAT 0x00000300 -#define NV03_CONTEXT_SURFACES_2D_PITCH 0x00000304 -#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT 0 -#define NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK 0x0000ffff -#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT 16 -#define NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK 0xffff0000 -#define NV03_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 -#define NV03_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c - - -#define NV03_CONTEXT_SURFACES_3D 0x0000005a - -#define NV03_CONTEXT_SURFACES_3D_SYNCHRONIZE 0x00000100 -#define NV03_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180 -#define NV03_CONTEXT_SURFACES_3D_DMA_SURFACE 0x00000184 -#define NV03_CONTEXT_SURFACES_3D_PITCH 0x00000300 -#define NV03_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x00000304 -#define NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000308 - - -#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060 - -#define NV04_INDEXED_IMAGE_FROM_CPU_NOP 0x00000100 -#define NV04_INDEXED_IMAGE_FROM_CPU_NOTIFY 0x00000104 -#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c -#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 -#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184 -#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188 -#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c -#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190 -#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194 -#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198 -#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c -#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 -#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4 -#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8 -#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec -#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0 -#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4 -#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8 -#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc -#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) -#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000700 - - -#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064 - -#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0 - - -#define NV03_CHANNEL_PIO 0x0000006a - - - -#define NV03_CHANNEL_DMA 0x0000006b - - - -#define NV04_BETA_SOLID 0x00000072 - -#define NV04_BETA_SOLID_NOP 0x00000100 -#define NV04_BETA_SOLID_NOTIFY 0x00000104 -#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180 -#define NV04_BETA_SOLID_BETA_OUTPUT 0x00000200 -#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300 - - -#define NV10_TEXTURE_FROM_CPU 0x0000007b - -#define NV10_TEXTURE_FROM_CPU_NOP 0x00000100 -#define NV10_TEXTURE_FROM_CPU_NOTIFY 0x00000104 -#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 -#define NV10_TEXTURE_FROM_CPU_PM_TRIGGER 0x00000140 -#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180 -#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184 -#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300 -#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304 -#define NV10_TEXTURE_FROM_CPU_POINT_X_SHIFT 0 -#define NV10_TEXTURE_FROM_CPU_POINT_X_MASK 0x0000ffff -#define NV10_TEXTURE_FROM_CPU_POINT_Y_SHIFT 16 -#define NV10_TEXTURE_FROM_CPU_POINT_Y_MASK 0xffff0000 -#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308 -#define NV10_TEXTURE_FROM_CPU_SIZE_W_SHIFT 0 -#define NV10_TEXTURE_FROM_CPU_SIZE_W_MASK 0x0000ffff -#define NV10_TEXTURE_FROM_CPU_SIZE_H_SHIFT 16 -#define NV10_TEXTURE_FROM_CPU_SIZE_H_MASK 0xffff0000 -#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c -#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_SHIFT 0 -#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_MASK 0x0000ffff -#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_SHIFT 16 -#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_MASK 0xffff0000 -#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310 -#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_SHIFT 0 -#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_MASK 0x0000ffff -#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_SHIFT 16 -#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_MASK 0xffff0000 -#define NV10_TEXTURE_FROM_CPU_COLOR(x) (0x00000400+((x)*4)) -#define NV10_TEXTURE_FROM_CPU_COLOR__SIZE 0x00000700 - - -#define NV30_TEXTURE_FROM_CPU 0x0000037b - - - -#define NV40_TEXTURE_FROM_CPU 0x0000307b - - - -#define NV10_VIDEO_DISPLAY 0x0000007c - - - -#define NV20TCL 0x00000097 - -#define NV20TCL_NOP 0x00000100 -#define NV20TCL_NOTIFY 0x00000104 -#define NV20TCL_DMA_NOTIFY 0x00000180 -#define NV20TCL_DMA_TEXTURE0 0x00000184 -#define NV20TCL_DMA_TEXTURE1 0x00000188 -#define NV20TCL_DMA_COLOR 0x00000194 -#define NV20TCL_DMA_ZETA 0x00000198 -#define NV20TCL_DMA_VTXBUF0 0x0000019c -#define NV20TCL_DMA_VTXBUF1 0x000001a0 -#define NV20TCL_DMA_FENCE 0x000001a4 -#define NV20TCL_DMA_QUERY 0x000001a8 -#define NV20TCL_RT_HORIZ 0x00000200 -#define NV20TCL_RT_HORIZ_X_SHIFT 0 -#define NV20TCL_RT_HORIZ_X_MASK 0x0000ffff -#define NV20TCL_RT_HORIZ_W_SHIFT 16 -#define NV20TCL_RT_HORIZ_W_MASK 0xffff0000 -#define NV20TCL_RT_VERT 0x00000204 -#define NV20TCL_RT_VERT_Y_SHIFT 0 -#define NV20TCL_RT_VERT_Y_MASK 0x0000ffff -#define NV20TCL_RT_VERT_H_SHIFT 16 -#define NV20TCL_RT_VERT_H_MASK 0xffff0000 -#define NV20TCL_RT_FORMAT 0x00000208 -#define NV20TCL_RT_FORMAT_TYPE_SHIFT 8 -#define NV20TCL_RT_FORMAT_TYPE_MASK 0x00000f00 -#define NV20TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 -#define NV20TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 -#define NV20TCL_RT_FORMAT_COLOR_SHIFT 0 -#define NV20TCL_RT_FORMAT_COLOR_MASK 0x0000001f -#define NV20TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 -#define NV20TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 -#define NV20TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 -#define NV20TCL_RT_FORMAT_COLOR_B8 0x00000009 -#define NV20TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d -#define NV20TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f -#define NV20TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 -#define NV20TCL_RT_PITCH 0x0000020c -#define NV20TCL_RT_PITCH_COLOR_PITCH_SHIFT 0 -#define NV20TCL_RT_PITCH_COLOR_PITCH_MASK 0x0000ffff -#define NV20TCL_RT_PITCH_ZETA_PITCH_SHIFT 16 -#define NV20TCL_RT_PITCH_ZETA_PITCH_MASK 0xffff0000 -#define NV20TCL_COLOR_OFFSET 0x00000210 -#define NV20TCL_ZETA_OFFSET 0x00000214 -#define NV20TCL_RC_IN_ALPHA(x) (0x00000260+((x)*4)) -#define NV20TCL_RC_IN_ALPHA__SIZE 0x00000008 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f -#define NV20TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 -#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c -#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d -#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f -#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a -#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b -#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4) -#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 -#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12) -#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 -#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 -#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 -#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20) -#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 -#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 -#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 -#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28) -#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 -#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV20TCL_RC_FINAL0 0x00000288 -#define NV20TCL_RC_FINAL0_D_INPUT_SHIFT 0 -#define NV20TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f -#define NV20TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV20TCL_RC_FINAL0_D_INPUT_FOG 0x00000003 -#define NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 -#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 -#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c -#define NV20TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d -#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f -#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a -#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b -#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4) -#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV20TCL_RC_FINAL0_D_MAPPING_SHIFT 5 -#define NV20TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0 -#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV20TCL_RC_FINAL0_C_INPUT_SHIFT 8 -#define NV20TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00 -#define NV20TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_FINAL0_C_INPUT_FOG 0x00000300 -#define NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12) -#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV20TCL_RC_FINAL0_C_MAPPING_SHIFT 13 -#define NV20TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000 -#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV20TCL_RC_FINAL0_B_INPUT_SHIFT 16 -#define NV20TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000 -#define NV20TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV20TCL_RC_FINAL0_B_INPUT_FOG 0x00030000 -#define NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 -#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 -#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 -#define NV20TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 -#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 -#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 -#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 -#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20) -#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV20TCL_RC_FINAL0_B_MAPPING_SHIFT 21 -#define NV20TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000 -#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV20TCL_RC_FINAL0_A_INPUT_SHIFT 24 -#define NV20TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000 -#define NV20TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV20TCL_RC_FINAL0_A_INPUT_FOG 0x03000000 -#define NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 -#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 -#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 -#define NV20TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 -#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 -#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 -#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 -#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28) -#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_SHIFT 29 -#define NV20TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV20TCL_RC_FINAL1 0x0000028c -#define NV20TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -#define NV20TCL_RC_FINAL1_G_INPUT_SHIFT 8 -#define NV20TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00 -#define NV20TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_FINAL1_G_INPUT_FOG 0x00000300 -#define NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12) -#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV20TCL_RC_FINAL1_G_MAPPING_SHIFT 13 -#define NV20TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000 -#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV20TCL_RC_FINAL1_F_INPUT_SHIFT 16 -#define NV20TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000 -#define NV20TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV20TCL_RC_FINAL1_F_INPUT_FOG 0x00030000 -#define NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 -#define NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 -#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 -#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 -#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 -#define NV20TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 -#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 -#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 -#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 -#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20) -#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV20TCL_RC_FINAL1_F_MAPPING_SHIFT 21 -#define NV20TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000 -#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV20TCL_RC_FINAL1_E_INPUT_SHIFT 24 -#define NV20TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000 -#define NV20TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV20TCL_RC_FINAL1_E_INPUT_FOG 0x03000000 -#define NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 -#define NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 -#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 -#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 -#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 -#define NV20TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 -#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 -#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 -#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 -#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28) -#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_SHIFT 29 -#define NV20TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV20TCL_LIGHT_MODEL 0x00000294 -#define NV20TCL_LIGHT_MODEL_VIEWER_SHIFT 16 -#define NV20TCL_LIGHT_MODEL_VIEWER_MASK 0x00030000 -#define NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL 0x00020000 -#define NV20TCL_LIGHT_MODEL_VIEWER_LOCAL 0x00030000 -#define NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 0) -#define NV20TCL_COLOR_MATERIAL 0x00000298 -#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_SHIFT 0 -#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_MASK 0x00000003 -#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL1 0x00000001 -#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL2 0x00000002 -#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_SHIFT 2 -#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_MASK 0x0000000c -#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL1 0x00000004 -#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL2 0x00000008 -#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_SHIFT 4 -#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_MASK 0x00000030 -#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL1 0x00000010 -#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL2 0x00000020 -#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_SHIFT 6 -#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_MASK 0x000000c0 -#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL1 0x00000040 -#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL2 0x00000080 -#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_SHIFT 8 -#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_MASK 0x00000300 -#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL1 0x00000100 -#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL2 0x00000200 -#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_SHIFT 10 -#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_MASK 0x00000c00 -#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL1 0x00000400 -#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL2 0x00000800 -#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_SHIFT 12 -#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_MASK 0x00003000 -#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL1 0x00001000 -#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL2 0x00002000 -#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_SHIFT 14 -#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_MASK 0x0000c000 -#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_OFF 0x00000000 -#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL1 0x00004000 -#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL2 0x00008000 -#define NV20TCL_FOG_MODE 0x0000029c -#define NV20TCL_FOG_MODE_LINEAR_UNSIGNED 0x00000804 -#define NV20TCL_FOG_MODE_LINEAR_SIGNED 0x00002601 -#define NV20TCL_FOG_MODE_EXP_UNSIGNED 0x00000802 -#define NV20TCL_FOG_MODE_EXP_SIGNED 0x00000800 -#define NV20TCL_FOG_MODE_EXP2_UNSIGNED 0x00000803 -#define NV20TCL_FOG_MODE_EXP2_SIGNED 0x00000801 -#define NV20TCL_FOG_COORD 0x000002a0 -#define NV20TCL_FOG_COORD_DIST_RADIAL 0x00000001 -#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002 -#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003 -#define NV20TCL_FOG_COORD_FOG 0x00000006 -#define NV20TCL_FOG_ENABLE 0x000002a4 -#define NV20TCL_FOG_COLOR 0x000002a8 -#define NV20TCL_FOG_COLOR_R_SHIFT 0 -#define NV20TCL_FOG_COLOR_R_MASK 0x000000ff -#define NV20TCL_FOG_COLOR_G_SHIFT 8 -#define NV20TCL_FOG_COLOR_G_MASK 0x0000ff00 -#define NV20TCL_FOG_COLOR_B_SHIFT 16 -#define NV20TCL_FOG_COLOR_B_MASK 0x00ff0000 -#define NV20TCL_FOG_COLOR_A_SHIFT 24 -#define NV20TCL_FOG_COLOR_A_MASK 0xff000000 -#define NV20TCL_VIEWPORT_CLIP_MODE 0x000002b4 -#define NV20TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*4)) -#define NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NV20TCL_VIEWPORT_CLIP_VERT(x) (0x000002e0+((x)*4)) -#define NV20TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NV20TCL_ALPHA_FUNC_ENABLE 0x00000300 -#define NV20TCL_BLEND_FUNC_ENABLE 0x00000304 -#define NV20TCL_CULL_FACE_ENABLE 0x00000308 -#define NV20TCL_DEPTH_TEST_ENABLE 0x0000030c -#define NV20TCL_DITHER_ENABLE 0x00000310 -#define NV20TCL_LIGHTING_ENABLE 0x00000314 -#define NV20TCL_POINT_PARAMETERS_ENABLE 0x00000318 -#define NV20TCL_POINT_SMOOTH_ENABLE 0x0000031c -#define NV20TCL_LINE_SMOOTH_ENABLE 0x00000320 -#define NV20TCL_POLYGON_SMOOTH_ENABLE 0x00000324 -#define NV20TCL_STENCIL_ENABLE 0x0000032c -#define NV20TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000330 -#define NV20TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000334 -#define NV20TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000338 -#define NV20TCL_ALPHA_FUNC_FUNC 0x0000033c -#define NV20TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200 -#define NV20TCL_ALPHA_FUNC_FUNC_LESS 0x00000201 -#define NV20TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202 -#define NV20TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 -#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204 -#define NV20TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV20TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 -#define NV20TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 -#define NV20TCL_ALPHA_FUNC_REF 0x00000340 -#define NV20TCL_BLEND_FUNC_SRC 0x00000344 -#define NV20TCL_BLEND_FUNC_SRC_ZERO 0x00000000 -#define NV20TCL_BLEND_FUNC_SRC_ONE 0x00000001 -#define NV20TCL_BLEND_FUNC_SRC_SRC_COLOR 0x00000300 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA 0x00000302 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV20TCL_BLEND_FUNC_SRC_DST_ALPHA 0x00000304 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV20TCL_BLEND_FUNC_SRC_DST_COLOR 0x00000306 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR 0x00000307 -#define NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE 0x00000308 -#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_COLOR 0x00008001 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV20TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA 0x00008003 -#define NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV20TCL_BLEND_FUNC_DST 0x00000348 -#define NV20TCL_BLEND_FUNC_DST_ZERO 0x00000000 -#define NV20TCL_BLEND_FUNC_DST_ONE 0x00000001 -#define NV20TCL_BLEND_FUNC_DST_SRC_COLOR 0x00000300 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA 0x00000302 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV20TCL_BLEND_FUNC_DST_DST_ALPHA 0x00000304 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV20TCL_BLEND_FUNC_DST_DST_COLOR 0x00000306 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR 0x00000307 -#define NV20TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE 0x00000308 -#define NV20TCL_BLEND_FUNC_DST_CONSTANT_COLOR 0x00008001 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV20TCL_BLEND_FUNC_DST_CONSTANT_ALPHA 0x00008003 -#define NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV20TCL_BLEND_COLOR 0x0000034c -#define NV20TCL_BLEND_COLOR_B_SHIFT 0 -#define NV20TCL_BLEND_COLOR_B_MASK 0x000000ff -#define NV20TCL_BLEND_COLOR_G_SHIFT 8 -#define NV20TCL_BLEND_COLOR_G_MASK 0x0000ff00 -#define NV20TCL_BLEND_COLOR_R_SHIFT 16 -#define NV20TCL_BLEND_COLOR_R_MASK 0x00ff0000 -#define NV20TCL_BLEND_COLOR_A_SHIFT 24 -#define NV20TCL_BLEND_COLOR_A_MASK 0xff000000 -#define NV20TCL_BLEND_EQUATION 0x00000350 -#define NV20TCL_BLEND_EQUATION_FUNC_ADD 0x00008006 -#define NV20TCL_BLEND_EQUATION_MIN 0x00008007 -#define NV20TCL_BLEND_EQUATION_MAX 0x00008008 -#define NV20TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a -#define NV20TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV20TCL_DEPTH_FUNC 0x00000354 -#define NV20TCL_DEPTH_FUNC_NEVER 0x00000200 -#define NV20TCL_DEPTH_FUNC_LESS 0x00000201 -#define NV20TCL_DEPTH_FUNC_EQUAL 0x00000202 -#define NV20TCL_DEPTH_FUNC_LEQUAL 0x00000203 -#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204 -#define NV20TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 -#define NV20TCL_DEPTH_FUNC_GEQUAL 0x00000206 -#define NV20TCL_DEPTH_FUNC_ALWAYS 0x00000207 -#define NV20TCL_COLOR_MASK 0x00000358 -#define NV20TCL_COLOR_MASK_B (1 << 0) -#define NV20TCL_COLOR_MASK_G (1 << 8) -#define NV20TCL_COLOR_MASK_R (1 << 16) -#define NV20TCL_COLOR_MASK_A (1 << 24) -#define NV20TCL_DEPTH_WRITE_ENABLE 0x0000035c -#define NV20TCL_STENCIL_MASK 0x00000360 -#define NV20TCL_STENCIL_FUNC_FUNC 0x00000364 -#define NV20TCL_STENCIL_FUNC_FUNC_NEVER 0x00000200 -#define NV20TCL_STENCIL_FUNC_FUNC_LESS 0x00000201 -#define NV20TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202 -#define NV20TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 -#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204 -#define NV20TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV20TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 -#define NV20TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 -#define NV20TCL_STENCIL_FUNC_REF 0x00000368 -#define NV20TCL_STENCIL_FUNC_MASK 0x0000036c -#define NV20TCL_STENCIL_OP_FAIL 0x00000370 -#define NV20TCL_STENCIL_OP_FAIL_ZERO 0x00000000 -#define NV20TCL_STENCIL_OP_FAIL_INVERT 0x0000150a -#define NV20TCL_STENCIL_OP_FAIL_KEEP 0x00001e00 -#define NV20TCL_STENCIL_OP_FAIL_REPLACE 0x00001e01 -#define NV20TCL_STENCIL_OP_FAIL_INCR 0x00001e02 -#define NV20TCL_STENCIL_OP_FAIL_DECR 0x00001e03 -#define NV20TCL_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 -#define NV20TCL_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 -#define NV20TCL_STENCIL_OP_ZFAIL 0x00000374 -#define NV20TCL_STENCIL_OP_ZFAIL_ZERO 0x00000000 -#define NV20TCL_STENCIL_OP_ZFAIL_INVERT 0x0000150a -#define NV20TCL_STENCIL_OP_ZFAIL_KEEP 0x00001e00 -#define NV20TCL_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 -#define NV20TCL_STENCIL_OP_ZFAIL_INCR 0x00001e02 -#define NV20TCL_STENCIL_OP_ZFAIL_DECR 0x00001e03 -#define NV20TCL_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV20TCL_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV20TCL_STENCIL_OP_ZPASS 0x00000378 -#define NV20TCL_STENCIL_OP_ZPASS_ZERO 0x00000000 -#define NV20TCL_STENCIL_OP_ZPASS_INVERT 0x0000150a -#define NV20TCL_STENCIL_OP_ZPASS_KEEP 0x00001e00 -#define NV20TCL_STENCIL_OP_ZPASS_REPLACE 0x00001e01 -#define NV20TCL_STENCIL_OP_ZPASS_INCR 0x00001e02 -#define NV20TCL_STENCIL_OP_ZPASS_DECR 0x00001e03 -#define NV20TCL_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV20TCL_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV20TCL_SHADE_MODEL 0x0000037c -#define NV20TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NV20TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NV20TCL_LINE_WIDTH 0x00000380 -#define NV20TCL_POLYGON_OFFSET_FACTOR 0x00000384 -#define NV20TCL_POLYGON_OFFSET_UNITS 0x00000388 -#define NV20TCL_POLYGON_MODE_FRONT 0x0000038c -#define NV20TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NV20TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NV20TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NV20TCL_POLYGON_MODE_BACK 0x00000390 -#define NV20TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NV20TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NV20TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NV20TCL_DEPTH_RANGE_NEAR 0x00000394 -#define NV20TCL_DEPTH_RANGE_FAR 0x00000398 -#define NV20TCL_CULL_FACE 0x0000039c -#define NV20TCL_CULL_FACE_FRONT 0x00000404 -#define NV20TCL_CULL_FACE_BACK 0x00000405 -#define NV20TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NV20TCL_FRONT_FACE 0x000003a0 -#define NV20TCL_FRONT_FACE_CW 0x00000900 -#define NV20TCL_FRONT_FACE_CCW 0x00000901 -#define NV20TCL_NORMALIZE_ENABLE 0x000003a4 -#define NV20TCL_MATERIAL_FACTOR_FRONT_R 0x000003a8 -#define NV20TCL_MATERIAL_FACTOR_FRONT_G 0x000003ac -#define NV20TCL_MATERIAL_FACTOR_FRONT_B 0x000003b0 -#define NV20TCL_MATERIAL_FACTOR_FRONT_A 0x000003b4 -#define NV20TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8 -#define NV20TCL_ENABLED_LIGHTS 0x000003bc -#define NV20TCL_ENABLED_LIGHTS_0_SHIFT 0 -#define NV20TCL_ENABLED_LIGHTS_0_MASK 0x00000003 -#define NV20TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001 -#define NV20TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002 -#define NV20TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003 -#define NV20TCL_ENABLED_LIGHTS_1_SHIFT 2 -#define NV20TCL_ENABLED_LIGHTS_1_MASK 0x0000000c -#define NV20TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004 -#define NV20TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008 -#define NV20TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c -#define NV20TCL_ENABLED_LIGHTS_2_SHIFT 4 -#define NV20TCL_ENABLED_LIGHTS_2_MASK 0x00000030 -#define NV20TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010 -#define NV20TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020 -#define NV20TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030 -#define NV20TCL_ENABLED_LIGHTS_3_SHIFT 6 -#define NV20TCL_ENABLED_LIGHTS_3_MASK 0x000000c0 -#define NV20TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040 -#define NV20TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080 -#define NV20TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0 -#define NV20TCL_ENABLED_LIGHTS_4_SHIFT 8 -#define NV20TCL_ENABLED_LIGHTS_4_MASK 0x00000300 -#define NV20TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100 -#define NV20TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200 -#define NV20TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300 -#define NV20TCL_ENABLED_LIGHTS_5_SHIFT 10 -#define NV20TCL_ENABLED_LIGHTS_5_MASK 0x00000c00 -#define NV20TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400 -#define NV20TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800 -#define NV20TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00 -#define NV20TCL_ENABLED_LIGHTS_6_SHIFT 12 -#define NV20TCL_ENABLED_LIGHTS_6_MASK 0x00003000 -#define NV20TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000 -#define NV20TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000 -#define NV20TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000 -#define NV20TCL_ENABLED_LIGHTS_7_SHIFT 14 -#define NV20TCL_ENABLED_LIGHTS_7_MASK 0x0000c000 -#define NV20TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000 -#define NV20TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000 -#define NV20TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000 -#define NV20TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000 -#define NV20TCL_TX_GEN_MODE_S(x) (0x000003c0+((x)*16)) -#define NV20TCL_TX_GEN_MODE_S__SIZE 0x00000004 -#define NV20TCL_TX_GEN_MODE_S_FALSE 0x00000000 -#define NV20TCL_TX_GEN_MODE_S_EYE_LINEAR 0x00002400 -#define NV20TCL_TX_GEN_MODE_S_OBJECT_LINEAR 0x00002401 -#define NV20TCL_TX_GEN_MODE_S_SPHERE_MAP 0x00002402 -#define NV20TCL_TX_GEN_MODE_S_NORMAL_MAP 0x00008511 -#define NV20TCL_TX_GEN_MODE_S_REFLECTION_MAP 0x00008512 -#define NV20TCL_TX_GEN_MODE_T(x) (0x000003c4+((x)*16)) -#define NV20TCL_TX_GEN_MODE_T__SIZE 0x00000004 -#define NV20TCL_TX_GEN_MODE_T_FALSE 0x00000000 -#define NV20TCL_TX_GEN_MODE_T_EYE_LINEAR 0x00002400 -#define NV20TCL_TX_GEN_MODE_T_OBJECT_LINEAR 0x00002401 -#define NV20TCL_TX_GEN_MODE_T_SPHERE_MAP 0x00002402 -#define NV20TCL_TX_GEN_MODE_T_NORMAL_MAP 0x00008511 -#define NV20TCL_TX_GEN_MODE_T_REFLECTION_MAP 0x00008512 -#define NV20TCL_TX_GEN_MODE_R(x) (0x000003c8+((x)*16)) -#define NV20TCL_TX_GEN_MODE_R__SIZE 0x00000004 -#define NV20TCL_TX_GEN_MODE_R_FALSE 0x00000000 -#define NV20TCL_TX_GEN_MODE_R_EYE_LINEAR 0x00002400 -#define NV20TCL_TX_GEN_MODE_R_OBJECT_LINEAR 0x00002401 -#define NV20TCL_TX_GEN_MODE_R_SPHERE_MAP 0x00002402 -#define NV20TCL_TX_GEN_MODE_R_NORMAL_MAP 0x00008511 -#define NV20TCL_TX_GEN_MODE_R_REFLECTION_MAP 0x00008512 -#define NV20TCL_TX_GEN_MODE_Q(x) (0x000003cc+((x)*16)) -#define NV20TCL_TX_GEN_MODE_Q__SIZE 0x00000004 -#define NV20TCL_TX_GEN_MODE_Q_FALSE 0x00000000 -#define NV20TCL_TX_GEN_MODE_Q_EYE_LINEAR 0x00002400 -#define NV20TCL_TX_GEN_MODE_Q_OBJECT_LINEAR 0x00002401 -#define NV20TCL_TX_GEN_MODE_Q_SPHERE_MAP 0x00002402 -#define NV20TCL_TX_GEN_MODE_Q_NORMAL_MAP 0x00008511 -#define NV20TCL_TX_GEN_MODE_Q_REFLECTION_MAP 0x00008512 -#define NV20TCL_TX_MATRIX_ENABLE(x) (0x00000420+((x)*4)) -#define NV20TCL_TX_MATRIX_ENABLE__SIZE 0x00000004 -#define NV20TCL_POINT_SIZE 0x0000043c -#define NV20TCL_MODELVIEW0_MATRIX(x) (0x00000480+((x)*4)) -#define NV20TCL_MODELVIEW0_MATRIX__SIZE 0x00000010 -#define NV20TCL_MODELVIEW1_MATRIX(x) (0x000004c0+((x)*4)) -#define NV20TCL_MODELVIEW1_MATRIX__SIZE 0x00000010 -#define NV20TCL_MODELVIEW2_MATRIX(x) (0x00000500+((x)*4)) -#define NV20TCL_MODELVIEW2_MATRIX__SIZE 0x00000010 -#define NV20TCL_MODELVIEW3_MATRIX(x) (0x00000540+((x)*4)) -#define NV20TCL_MODELVIEW3_MATRIX__SIZE 0x00000010 -#define NV20TCL_INVERSE_MODELVIEW0_MATRIX(x) (0x00000580+((x)*4)) -#define NV20TCL_INVERSE_MODELVIEW0_MATRIX__SIZE 0x00000010 -#define NV20TCL_INVERSE_MODELVIEW1_MATRIX(x) (0x000005c0+((x)*4)) -#define NV20TCL_INVERSE_MODELVIEW1_MATRIX__SIZE 0x00000010 -#define NV20TCL_INVERSE_MODELVIEW2_MATRIX(x) (0x00000600+((x)*4)) -#define NV20TCL_INVERSE_MODELVIEW2_MATRIX__SIZE 0x00000010 -#define NV20TCL_INVERSE_MODELVIEW3_MATRIX(x) (0x00000640+((x)*4)) -#define NV20TCL_INVERSE_MODELVIEW3_MATRIX__SIZE 0x00000010 -#define NV20TCL_PROJECTION_MATRIX(x) (0x00000680+((x)*4)) -#define NV20TCL_PROJECTION_MATRIX__SIZE 0x00000010 -#define NV20TCL_TX0_MATRIX(x) (0x000006c0+((x)*4)) -#define NV20TCL_TX0_MATRIX__SIZE 0x00000010 -#define NV20TCL_TX1_MATRIX(x) (0x00000700+((x)*4)) -#define NV20TCL_TX1_MATRIX__SIZE 0x00000010 -#define NV20TCL_TX2_MATRIX(x) (0x00000740+((x)*4)) -#define NV20TCL_TX2_MATRIX__SIZE 0x00000010 -#define NV20TCL_TX3_MATRIX(x) (0x00000780+((x)*4)) -#define NV20TCL_TX3_MATRIX__SIZE 0x00000010 -#define NV20TCL_TX_GEN_COEFF_S_A(x) (0x00000840+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_S_A__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_S_B(x) (0x00000844+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_S_B__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_S_C(x) (0x00000848+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_S_C__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_S_D(x) (0x0000084c+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_S_D__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_T_A(x) (0x00000850+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_T_A__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_T_B(x) (0x00000854+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_T_B__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_T_C(x) (0x00000858+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_T_C__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_T_D(x) (0x0000085c+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_T_D__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_R_A(x) (0x00000860+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_R_A__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_R_B(x) (0x00000864+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_R_B__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_R_C(x) (0x00000868+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_R_C__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_R_D(x) (0x0000086c+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_R_D__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_Q_A(x) (0x00000870+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_Q_A__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_Q_B(x) (0x00000874+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_Q_B__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_Q_C(x) (0x00000878+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_Q_C__SIZE 0x00000004 -#define NV20TCL_TX_GEN_COEFF_Q_D(x) (0x0000087c+((x)*64)) -#define NV20TCL_TX_GEN_COEFF_Q_D__SIZE 0x00000004 -#define NV20TCL_FOG_EQUATION_CONSTANT 0x000009c0 -#define NV20TCL_FOG_EQUATION_LINEAR 0x000009c4 -#define NV20TCL_FOG_EQUATION_QUADRATIC 0x000009c8 -#define NV20TCL_FRONT_MATERIAL_SHININESS(x) (0x000009e0+((x)*4)) -#define NV20TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006 -#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R 0x00000a10 -#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_G 0x00000a14 -#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_B 0x00000a18 -#define NV20TCL_VIEWPORT_TRANSLATE_X 0x00000a20 -#define NV20TCL_VIEWPORT_TRANSLATE_Y 0x00000a24 -#define NV20TCL_VIEWPORT_TRANSLATE_Z 0x00000a28 -#define NV20TCL_VIEWPORT_TRANSLATE_W 0x00000a2c -#define NV20TCL_POINT_PARAMETER(x) (0x00000a30+((x)*4)) -#define NV20TCL_POINT_PARAMETER__SIZE 0x00000008 -#define NV20TCL_RC_CONSTANT_COLOR0(x) (0x00000a60+((x)*4)) -#define NV20TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008 -#define NV20TCL_RC_CONSTANT_COLOR0_B_SHIFT 0 -#define NV20TCL_RC_CONSTANT_COLOR0_B_MASK 0x000000ff -#define NV20TCL_RC_CONSTANT_COLOR0_G_SHIFT 8 -#define NV20TCL_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00 -#define NV20TCL_RC_CONSTANT_COLOR0_R_SHIFT 16 -#define NV20TCL_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000 -#define NV20TCL_RC_CONSTANT_COLOR0_A_SHIFT 24 -#define NV20TCL_RC_CONSTANT_COLOR0_A_MASK 0xff000000 -#define NV20TCL_RC_CONSTANT_COLOR1(x) (0x00000a80+((x)*4)) -#define NV20TCL_RC_CONSTANT_COLOR1__SIZE 0x00000008 -#define NV20TCL_RC_CONSTANT_COLOR1_B_SHIFT 0 -#define NV20TCL_RC_CONSTANT_COLOR1_B_MASK 0x000000ff -#define NV20TCL_RC_CONSTANT_COLOR1_G_SHIFT 8 -#define NV20TCL_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00 -#define NV20TCL_RC_CONSTANT_COLOR1_R_SHIFT 16 -#define NV20TCL_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000 -#define NV20TCL_RC_CONSTANT_COLOR1_A_SHIFT 24 -#define NV20TCL_RC_CONSTANT_COLOR1_A_MASK 0xff000000 -#define NV20TCL_RC_OUT_ALPHA(x) (0x00000aa0+((x)*4)) -#define NV20TCL_RC_OUT_ALPHA__SIZE 0x00000008 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -#define NV20TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -#define NV20TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14) -#define NV20TCL_RC_OUT_ALPHA_BIAS (1 << 15) -#define NV20TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV20TCL_RC_OUT_ALPHA_SCALE_SHIFT 17 -#define NV20TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000 -#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000 -#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV20TCL_RC_IN_RGB(x) (0x00000ac0+((x)*4)) -#define NV20TCL_RC_IN_RGB__SIZE 0x00000008 -#define NV20TCL_RC_IN_RGB_D_INPUT_SHIFT 0 -#define NV20TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f -#define NV20TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV20TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003 -#define NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 -#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 -#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c -#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d -#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f -#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a -#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b -#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4) -#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV20TCL_RC_IN_RGB_D_MAPPING_SHIFT 5 -#define NV20TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0 -#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV20TCL_RC_IN_RGB_C_INPUT_SHIFT 8 -#define NV20TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00 -#define NV20TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300 -#define NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12) -#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_SHIFT 13 -#define NV20TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV20TCL_RC_IN_RGB_B_INPUT_SHIFT 16 -#define NV20TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV20TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000 -#define NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 -#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 -#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 -#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 -#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20) -#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_SHIFT 21 -#define NV20TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV20TCL_RC_IN_RGB_A_INPUT_SHIFT 24 -#define NV20TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 -#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 -#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28) -#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_SHIFT 29 -#define NV20TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV20TCL_VIEWPORT_SCALE_X 0x00000af0 -#define NV20TCL_VIEWPORT_SCALE_Y 0x00000af4 -#define NV20TCL_VIEWPORT_SCALE_Z 0x00000af8 -#define NV20TCL_VIEWPORT_SCALE_W 0x00000afc -#define NV20TCL_VP_UPLOAD_INST(x) (0x00000b00+((x)*4)) -#define NV20TCL_VP_UPLOAD_INST__SIZE 0x00000004 -#define NV20TCL_VP_UPLOAD_CONST(x) (0x00000b80+((x)*4)) -#define NV20TCL_VP_UPLOAD_CONST__SIZE 0x00000004 -#define NV20TCL_LIGHT_BACK_AMBIENT_R(x) (0x00000c00+((x)*64)) -#define NV20TCL_LIGHT_BACK_AMBIENT_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_AMBIENT_G(x) (0x00000c04+((x)*64)) -#define NV20TCL_LIGHT_BACK_AMBIENT_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_AMBIENT_B(x) (0x00000c08+((x)*64)) -#define NV20TCL_LIGHT_BACK_AMBIENT_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_DIFFUSE_R(x) (0x00000c0c+((x)*64)) -#define NV20TCL_LIGHT_BACK_DIFFUSE_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_DIFFUSE_G(x) (0x00000c10+((x)*64)) -#define NV20TCL_LIGHT_BACK_DIFFUSE_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_DIFFUSE_B(x) (0x00000c14+((x)*64)) -#define NV20TCL_LIGHT_BACK_DIFFUSE_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_SPECULAR_R(x) (0x00000c18+((x)*64)) -#define NV20TCL_LIGHT_BACK_SPECULAR_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_SPECULAR_G(x) (0x00000c1c+((x)*64)) -#define NV20TCL_LIGHT_BACK_SPECULAR_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_BACK_SPECULAR_B(x) (0x00000c20+((x)*64)) -#define NV20TCL_LIGHT_BACK_SPECULAR_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_AMBIENT_R(x) (0x00001000+((x)*128)) -#define NV20TCL_LIGHT_FRONT_AMBIENT_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_AMBIENT_G(x) (0x00001004+((x)*128)) -#define NV20TCL_LIGHT_FRONT_AMBIENT_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_AMBIENT_B(x) (0x00001008+((x)*128)) -#define NV20TCL_LIGHT_FRONT_AMBIENT_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_DIFFUSE_R(x) (0x0000100c+((x)*128)) -#define NV20TCL_LIGHT_FRONT_DIFFUSE_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_DIFFUSE_G(x) (0x00001010+((x)*128)) -#define NV20TCL_LIGHT_FRONT_DIFFUSE_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_DIFFUSE_B(x) (0x00001014+((x)*128)) -#define NV20TCL_LIGHT_FRONT_DIFFUSE_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_SPECULAR_R(x) (0x00001018+((x)*128)) -#define NV20TCL_LIGHT_FRONT_SPECULAR_R__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_SPECULAR_G(x) (0x0000101c+((x)*128)) -#define NV20TCL_LIGHT_FRONT_SPECULAR_G__SIZE 0x00000008 -#define NV20TCL_LIGHT_FRONT_SPECULAR_B(x) (0x00001020+((x)*128)) -#define NV20TCL_LIGHT_FRONT_SPECULAR_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*128)) -#define NV20TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008 -#define NV20TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*128)) -#define NV20TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008 -#define NV20TCL_LIGHT_HALF_VECTOR_Z(x) (0x00001030+((x)*128)) -#define NV20TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008 -#define NV20TCL_LIGHT_DIRECTION_X(x) (0x00001034+((x)*128)) -#define NV20TCL_LIGHT_DIRECTION_X__SIZE 0x00000008 -#define NV20TCL_LIGHT_DIRECTION_Y(x) (0x00001038+((x)*128)) -#define NV20TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008 -#define NV20TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*128)) -#define NV20TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00001040+((x)*128)) -#define NV20TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00001044+((x)*128)) -#define NV20TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00001048+((x)*128)) -#define NV20TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_DIR_X(x) (0x0000104c+((x)*128)) -#define NV20TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_DIR_Y(x) (0x00001050+((x)*128)) -#define NV20TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_DIR_Z(x) (0x00001054+((x)*128)) -#define NV20TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008 -#define NV20TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00001058+((x)*128)) -#define NV20TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008 -#define NV20TCL_LIGHT_POSITION_X(x) (0x0000105c+((x)*128)) -#define NV20TCL_LIGHT_POSITION_X__SIZE 0x00000008 -#define NV20TCL_LIGHT_POSITION_Y(x) (0x00001060+((x)*128)) -#define NV20TCL_LIGHT_POSITION_Y__SIZE 0x00000008 -#define NV20TCL_LIGHT_POSITION_Z(x) (0x00001064+((x)*128)) -#define NV20TCL_LIGHT_POSITION_Z__SIZE 0x00000008 -#define NV20TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00001068+((x)*128)) -#define NV20TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008 -#define NV20TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000106c+((x)*128)) -#define NV20TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008 -#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00001070+((x)*128)) -#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008 -#define NV20TCL_POLYGON_STIPPLE_ENABLE 0x0000147c -#define NV20TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4)) -#define NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 -#define NV20TCL_VERTEX_POS_3F_X 0x00001500 -#define NV20TCL_VERTEX_POS_3F_Y 0x00001504 -#define NV20TCL_VERTEX_POS_3F_Z 0x00001508 -#define NV20TCL_VERTEX_POS_4F_X 0x00001518 -#define NV20TCL_VERTEX_POS_4F_Y 0x0000151c -#define NV20TCL_VERTEX_POS_4F_Z 0x00001520 -#define NV20TCL_VERTEX_POS_3I_XY 0x00001528 -#define NV20TCL_VERTEX_POS_3I_XY_X_SHIFT 0 -#define NV20TCL_VERTEX_POS_3I_XY_X_MASK 0x0000ffff -#define NV20TCL_VERTEX_POS_3I_XY_Y_SHIFT 16 -#define NV20TCL_VERTEX_POS_3I_XY_Y_MASK 0xffff0000 -#define NV20TCL_VERTEX_POS_3I_Z 0x0000152c -#define NV20TCL_VERTEX_POS_3I_Z_Z_SHIFT 0 -#define NV20TCL_VERTEX_POS_3I_Z_Z_MASK 0x0000ffff -#define NV20TCL_VERTEX_NOR_3F_X 0x00001530 -#define NV20TCL_VERTEX_NOR_3F_Y 0x00001534 -#define NV20TCL_VERTEX_NOR_3F_Z 0x00001538 -#define NV20TCL_VERTEX_NOR_3I_XY 0x00001540 -#define NV20TCL_VERTEX_NOR_3I_XY_X_SHIFT 0 -#define NV20TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -#define NV20TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16 -#define NV20TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -#define NV20TCL_VERTEX_NOR_3I_Z 0x00001544 -#define NV20TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0 -#define NV20TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -#define NV20TCL_VERTEX_COL_4F_X 0x00001550 -#define NV20TCL_VERTEX_COL_4F_Y 0x00001554 -#define NV20TCL_VERTEX_COL_4F_Z 0x00001558 -#define NV20TCL_VERTEX_COL_4F_W 0x0000155c -#define NV20TCL_VERTEX_COL_3F_X 0x00001560 -#define NV20TCL_VERTEX_COL_3F_Y 0x00001564 -#define NV20TCL_VERTEX_COL_3F_Z 0x00001568 -#define NV20TCL_VERTEX_COL_4I 0x0000156c -#define NV20TCL_VERTEX_COL_4I_R_SHIFT 0 -#define NV20TCL_VERTEX_COL_4I_R_MASK 0x000000ff -#define NV20TCL_VERTEX_COL_4I_G_SHIFT 8 -#define NV20TCL_VERTEX_COL_4I_G_MASK 0x0000ff00 -#define NV20TCL_VERTEX_COL_4I_B_SHIFT 16 -#define NV20TCL_VERTEX_COL_4I_B_MASK 0x00ff0000 -#define NV20TCL_VERTEX_COL_4I_A_SHIFT 24 -#define NV20TCL_VERTEX_COL_4I_A_MASK 0xff000000 -#define NV20TCL_VERTEX_COL2_3F_X 0x00001580 -#define NV20TCL_VERTEX_COL2_3F_Y 0x00001584 -#define NV20TCL_VERTEX_COL2_3F_Z 0x00001588 -#define NV20TCL_VERTEX_COL2_4I 0x0000158c -#define NV20TCL_VERTEX_COL2_4I_R_SHIFT 0 -#define NV20TCL_VERTEX_COL2_4I_R_MASK 0x000000ff -#define NV20TCL_VERTEX_COL2_4I_G_SHIFT 8 -#define NV20TCL_VERTEX_COL2_4I_G_MASK 0x0000ff00 -#define NV20TCL_VERTEX_COL2_4I_B_SHIFT 16 -#define NV20TCL_VERTEX_COL2_4I_B_MASK 0x00ff0000 -#define NV20TCL_VERTEX_COL2_4I_A_SHIFT 24 -#define NV20TCL_VERTEX_COL2_4I_A_MASK 0xff000000 -#define NV20TCL_VERTEX_TX0_2F_S 0x00001590 -#define NV20TCL_VERTEX_TX0_2F_T 0x00001594 -#define NV20TCL_VERTEX_TX0_2I 0x00001598 -#define NV20TCL_VERTEX_TX0_2I_S_SHIFT 0 -#define NV20TCL_VERTEX_TX0_2I_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX0_2I_T_SHIFT 16 -#define NV20TCL_VERTEX_TX0_2I_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX0_4F_S 0x000015a0 -#define NV20TCL_VERTEX_TX0_4F_T 0x000015a4 -#define NV20TCL_VERTEX_TX0_4F_R 0x000015a8 -#define NV20TCL_VERTEX_TX0_4F_Q 0x000015ac -#define NV20TCL_VERTEX_TX0_4I_ST 0x000015b0 -#define NV20TCL_VERTEX_TX0_4I_ST_S_SHIFT 0 -#define NV20TCL_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX0_4I_ST_T_SHIFT 16 -#define NV20TCL_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX0_4I_RQ 0x000015b4 -#define NV20TCL_VERTEX_TX0_4I_RQ_R_SHIFT 0 -#define NV20TCL_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -#define NV20TCL_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX1_2F_S 0x000015b8 -#define NV20TCL_VERTEX_TX1_2F_T 0x000015bc -#define NV20TCL_VERTEX_TX1_2I 0x000015c0 -#define NV20TCL_VERTEX_TX1_2I_S_SHIFT 0 -#define NV20TCL_VERTEX_TX1_2I_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX1_2I_T_SHIFT 16 -#define NV20TCL_VERTEX_TX1_2I_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX1_4F_S 0x000015c8 -#define NV20TCL_VERTEX_TX1_4F_T 0x000015cc -#define NV20TCL_VERTEX_TX1_4F_R 0x000015d0 -#define NV20TCL_VERTEX_TX1_4F_Q 0x000015d4 -#define NV20TCL_VERTEX_TX1_4I_ST 0x000015d8 -#define NV20TCL_VERTEX_TX1_4I_ST_S_SHIFT 0 -#define NV20TCL_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX1_4I_ST_T_SHIFT 16 -#define NV20TCL_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX1_4I_RQ 0x000015dc -#define NV20TCL_VERTEX_TX1_4I_RQ_R_SHIFT 0 -#define NV20TCL_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -#define NV20TCL_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX2_2F_S 0x000015e0 -#define NV20TCL_VERTEX_TX2_2F_T 0x000015e4 -#define NV20TCL_VERTEX_TX2_2I 0x000015e8 -#define NV20TCL_VERTEX_TX2_2I_S_SHIFT 0 -#define NV20TCL_VERTEX_TX2_2I_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX2_2I_T_SHIFT 16 -#define NV20TCL_VERTEX_TX2_2I_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX2_4F_S 0x000015f0 -#define NV20TCL_VERTEX_TX2_4F_T 0x000015f4 -#define NV20TCL_VERTEX_TX2_4F_R 0x000015f8 -#define NV20TCL_VERTEX_TX2_4F_Q 0x000015fc -#define NV20TCL_VERTEX_TX2_4I_ST 0x00001600 -#define NV20TCL_VERTEX_TX2_4I_ST_S_SHIFT 0 -#define NV20TCL_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX2_4I_ST_T_SHIFT 16 -#define NV20TCL_VERTEX_TX2_4I_ST_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX2_4I_RQ 0x00001604 -#define NV20TCL_VERTEX_TX2_4I_RQ_R_SHIFT 0 -#define NV20TCL_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX2_4I_RQ_Q_SHIFT 16 -#define NV20TCL_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX3_2F_S 0x00001608 -#define NV20TCL_VERTEX_TX3_2F_T 0x0000160c -#define NV20TCL_VERTEX_TX3_2I 0x00001610 -#define NV20TCL_VERTEX_TX3_2I_S_SHIFT 0 -#define NV20TCL_VERTEX_TX3_2I_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX3_2I_T_SHIFT 16 -#define NV20TCL_VERTEX_TX3_2I_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX3_4F_S 0x00001620 -#define NV20TCL_VERTEX_TX3_4F_T 0x00001624 -#define NV20TCL_VERTEX_TX3_4F_R 0x00001628 -#define NV20TCL_VERTEX_TX3_4F_Q 0x0000162c -#define NV20TCL_VERTEX_TX3_4I_ST 0x00001630 -#define NV20TCL_VERTEX_TX3_4I_ST_S_SHIFT 0 -#define NV20TCL_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX3_4I_ST_T_SHIFT 16 -#define NV20TCL_VERTEX_TX3_4I_ST_T_MASK 0xffff0000 -#define NV20TCL_VERTEX_TX3_4I_RQ 0x00001634 -#define NV20TCL_VERTEX_TX3_4I_RQ_R_SHIFT 0 -#define NV20TCL_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff -#define NV20TCL_VERTEX_TX3_4I_RQ_Q_SHIFT 16 -#define NV20TCL_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000 -#define NV20TCL_VERTEX_FOG_1F 0x00001698 -#define NV20TCL_EDGEFLAG_ENABLE 0x000016bc -#define NV20TCL_VTX_CACHE_INVALIDATE 0x00001710 -#define NV20TCL_VTXBUF_ADDRESS(x) (0x00001720+((x)*4)) -#define NV20TCL_VTXBUF_ADDRESS__SIZE 0x00000010 -#define NV20TCL_VTXBUF_ADDRESS_DMA1 (1 << 31) -#define NV20TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0 -#define NV20TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff -#define NV20TCL_VTXFMT(x) (0x00001760+((x)*4)) -#define NV20TCL_VTXFMT__SIZE 0x00000010 -#define NV20TCL_VTXFMT_TYPE_SHIFT 0 -#define NV20TCL_VTXFMT_TYPE_MASK 0x0000000f -#define NV20TCL_VTXFMT_TYPE_FLOAT 0x00000002 -#define NV20TCL_VTXFMT_TYPE_HALF 0x00000003 -#define NV20TCL_VTXFMT_TYPE_UBYTE 0x00000004 -#define NV20TCL_VTXFMT_TYPE_USHORT 0x00000005 -#define NV20TCL_VTXFMT_SIZE_SHIFT 4 -#define NV20TCL_VTXFMT_SIZE_MASK 0x000000f0 -#define NV20TCL_VTXFMT_STRIDE_SHIFT 8 -#define NV20TCL_VTXFMT_STRIDE_MASK 0x0000ff00 -#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R 0x000017a0 -#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_G 0x000017a4 -#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_B 0x000017a8 -#define NV20TCL_MATERIAL_FACTOR_BACK_A 0x000017ac -#define NV20TCL_MATERIAL_FACTOR_BACK_R 0x000017b0 -#define NV20TCL_MATERIAL_FACTOR_BACK_G 0x000017b4 -#define NV20TCL_MATERIAL_FACTOR_BACK_B 0x000017b8 -#define NV20TCL_COLOR_LOGIC_OP_ENABLE 0x000017bc -#define NV20TCL_COLOR_LOGIC_OP_OP 0x000017c0 -#define NV20TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 -#define NV20TCL_COLOR_LOGIC_OP_OP_AND 0x00001501 -#define NV20TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 -#define NV20TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503 -#define NV20TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 -#define NV20TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505 -#define NV20TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506 -#define NV20TCL_COLOR_LOGIC_OP_OP_OR 0x00001507 -#define NV20TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508 -#define NV20TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 -#define NV20TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a -#define NV20TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b -#define NV20TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c -#define NV20TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d -#define NV20TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e -#define NV20TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f -#define NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE 0x000017c4 -#define NV20TCL_TX_SHADER_CULL_MODE 0x000017f8 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S (1 << 0) -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_S_LESS 0x00000001 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T (1 << 1) -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_T_LESS 0x00000002 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R (1 << 2) -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_R_LESS 0x00000004 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q (1 << 3) -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_LESS 0x00000008 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S (1 << 4) -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_S_LESS 0x00000010 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T (1 << 5) -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_T_LESS 0x00000020 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R (1 << 6) -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_R_LESS 0x00000040 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q (1 << 7) -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_LESS 0x00000080 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S (1 << 8) -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_S_LESS 0x00000100 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T (1 << 9) -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_T_LESS 0x00000200 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R (1 << 10) -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_R_LESS 0x00000400 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q (1 << 11) -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_LESS 0x00000800 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S (1 << 12) -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_S_LESS 0x00001000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T (1 << 13) -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_T_LESS 0x00002000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R (1 << 14) -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_R_LESS 0x00004000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q (1 << 15) -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_GEQUAL 0x00000000 -#define NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_LESS 0x00008000 -#define NV20TCL_VERTEX_BEGIN_END 0x000017fc -#define NV20TCL_VERTEX_BEGIN_END_STOP 0x00000000 -#define NV20TCL_VERTEX_BEGIN_END_POINTS 0x00000001 -#define NV20TCL_VERTEX_BEGIN_END_LINES 0x00000002 -#define NV20TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 -#define NV20TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 -#define NV20TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005 -#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 -#define NV20TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 -#define NV20TCL_VERTEX_BEGIN_END_QUADS 0x00000008 -#define NV20TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 -#define NV20TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a -#define NV20TCL_VB_ELEMENT_U16 0x00001800 -#define NV20TCL_VB_ELEMENT_U16_I0_SHIFT 0 -#define NV20TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff -#define NV20TCL_VB_ELEMENT_U16_I1_SHIFT 16 -#define NV20TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 -#define NV20TCL_VB_ELEMENT_U32 0x00001808 -#define NV20TCL_VB_VERTEX_BATCH 0x00001810 -#define NV20TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0 -#define NV20TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff -#define NV20TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24 -#define NV20TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000 -#define NV20TCL_VERTEX_DATA 0x00001818 -#define NV20TCL_TX_SHADER_CONST_EYE_X 0x0000181c -#define NV20TCL_TX_SHADER_CONST_EYE_Y 0x00001820 -#define NV20TCL_TX_SHADER_CONST_EYE_Z 0x00001824 -#define NV20TCL_VTX_ATTR_4F_X(x) (0x00001a00+((x)*16)) -#define NV20TCL_VTX_ATTR_4F_X__SIZE 0x00000010 -#define NV20TCL_VTX_ATTR_4F_Y(x) (0x00001a04+((x)*16)) -#define NV20TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 -#define NV20TCL_VTX_ATTR_4F_Z(x) (0x00001a08+((x)*16)) -#define NV20TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 -#define NV20TCL_VTX_ATTR_4F_W(x) (0x00001a0c+((x)*16)) -#define NV20TCL_VTX_ATTR_4F_W__SIZE 0x00000010 -#define NV20TCL_TX_OFFSET(x) (0x00001b00+((x)*64)) -#define NV20TCL_TX_OFFSET__SIZE 0x00000004 -#define NV20TCL_TX_FORMAT(x) (0x00001b04+((x)*64)) -#define NV20TCL_TX_FORMAT__SIZE 0x00000004 -#define NV20TCL_TX_FORMAT_DMA0 (1 << 0) -#define NV20TCL_TX_FORMAT_DMA1 (1 << 1) -#define NV20TCL_TX_FORMAT_CUBIC (1 << 2) -#define NV20TCL_TX_FORMAT_NO_BORDER (1 << 3) -#define NV20TCL_TX_FORMAT_DIMS_SHIFT 4 -#define NV20TCL_TX_FORMAT_DIMS_MASK 0x000000f0 -#define NV20TCL_TX_FORMAT_DIMS_1D 0x00000010 -#define NV20TCL_TX_FORMAT_DIMS_2D 0x00000020 -#define NV20TCL_TX_FORMAT_DIMS_3D 0x00000030 -#define NV20TCL_TX_FORMAT_FORMAT_SHIFT 8 -#define NV20TCL_TX_FORMAT_FORMAT_MASK 0x0000ff00 -#define NV20TCL_TX_FORMAT_FORMAT_L8 0x00000000 -#define NV20TCL_TX_FORMAT_FORMAT_A8 0x00000100 -#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000200 -#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000400 -#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000500 -#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000600 -#define NV20TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000700 -#define NV20TCL_TX_FORMAT_FORMAT_INDEX8 0x00000b00 -#define NV20TCL_TX_FORMAT_FORMAT_DXT1 0x00000c00 -#define NV20TCL_TX_FORMAT_FORMAT_DXT3 0x00000e00 -#define NV20TCL_TX_FORMAT_FORMAT_DXT5 0x00000f00 -#define NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000 -#define NV20TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100 -#define NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200 -#define NV20TCL_TX_FORMAT_FORMAT_L8_RECT 0x00001300 -#define NV20TCL_TX_FORMAT_FORMAT_DSDT8_RECT 0x00001700 -#define NV20TCL_TX_FORMAT_FORMAT_A8L8 0x00001a00 -#define NV20TCL_TX_FORMAT_FORMAT_A8_RECT 0x00001b00 -#define NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00 -#define NV20TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00 -#define NV20TCL_TX_FORMAT_FORMAT_A8L8_RECT 0x00002000 -#define NV20TCL_TX_FORMAT_FORMAT_DSDT8 0x00002800 -#define NV20TCL_TX_FORMAT_FORMAT_HILO16 0x00003300 -#define NV20TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00003600 -#define NV20TCL_TX_FORMAT_FORMAT_HILO8 0x00004400 -#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500 -#define NV20TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00004600 -#define NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700 -#define NV20TCL_TX_FORMAT_FORMAT_A16 0x00003200 -#define NV20TCL_TX_FORMAT_FORMAT_A16_RECT 0x00003500 -#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00 -#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00 -#define NV20TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00 -#define NV20TCL_TX_FORMAT_MIPMAP (1 << 19) -#define NV20TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 20 -#define NV20TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x00f00000 -#define NV20TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 24 -#define NV20TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x0f000000 -#define NV20TCL_TX_FORMAT_BASE_SIZE_W_SHIFT 28 -#define NV20TCL_TX_FORMAT_BASE_SIZE_W_MASK 0xf0000000 -#define NV20TCL_TX_WRAP(x) (0x00001b08+((x)*64)) -#define NV20TCL_TX_WRAP__SIZE 0x00000004 -#define NV20TCL_TX_WRAP_S_SHIFT 0 -#define NV20TCL_TX_WRAP_S_MASK 0x000000ff -#define NV20TCL_TX_WRAP_S_REPEAT 0x00000001 -#define NV20TCL_TX_WRAP_S_MIRRORED_REPEAT 0x00000002 -#define NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE 0x00000003 -#define NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER 0x00000004 -#define NV20TCL_TX_WRAP_S_CLAMP 0x00000005 -#define NV20TCL_TX_WRAP_T_SHIFT 8 -#define NV20TCL_TX_WRAP_T_MASK 0x00000f00 -#define NV20TCL_TX_WRAP_T_REPEAT 0x00000100 -#define NV20TCL_TX_WRAP_T_MIRRORED_REPEAT 0x00000200 -#define NV20TCL_TX_WRAP_T_CLAMP_TO_EDGE 0x00000300 -#define NV20TCL_TX_WRAP_T_CLAMP_TO_BORDER 0x00000400 -#define NV20TCL_TX_WRAP_T_CLAMP 0x00000500 -#define NV20TCL_TX_WRAP_R_SHIFT 16 -#define NV20TCL_TX_WRAP_R_MASK 0x000f0000 -#define NV20TCL_TX_WRAP_R_REPEAT 0x00010000 -#define NV20TCL_TX_WRAP_R_MIRRORED_REPEAT 0x00020000 -#define NV20TCL_TX_WRAP_R_CLAMP_TO_EDGE 0x00030000 -#define NV20TCL_TX_WRAP_R_CLAMP_TO_BORDER 0x00040000 -#define NV20TCL_TX_WRAP_R_CLAMP 0x00050000 -#define NV20TCL_TX_ENABLE(x) (0x00001b0c+((x)*64)) -#define NV20TCL_TX_ENABLE__SIZE 0x00000004 -#define NV20TCL_TX_ENABLE_ANISO_SHIFT 4 -#define NV20TCL_TX_ENABLE_ANISO_MASK 0x00000030 -#define NV20TCL_TX_ENABLE_ANISO_NONE 0x00000000 -#define NV20TCL_TX_ENABLE_ANISO_2X 0x00000010 -#define NV20TCL_TX_ENABLE_ANISO_4X 0x00000020 -#define NV20TCL_TX_ENABLE_ANISO_8X 0x00000030 -#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14 -#define NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000 -#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26 -#define NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000 -#define NV20TCL_TX_ENABLE_ENABLE (1 << 30) -#define NV20TCL_TX_NPOT_PITCH(x) (0x00001b10+((x)*64)) -#define NV20TCL_TX_NPOT_PITCH__SIZE 0x00000004 -#define NV20TCL_TX_NPOT_PITCH_PITCH_SHIFT 16 -#define NV20TCL_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 -#define NV20TCL_TX_FILTER(x) (0x00001b14+((x)*64)) -#define NV20TCL_TX_FILTER__SIZE 0x00000004 -#define NV20TCL_TX_FILTER_LOD_BIAS_SHIFT 8 -#define NV20TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00 -#define NV20TCL_TX_FILTER_MINIFY_SHIFT 16 -#define NV20TCL_TX_FILTER_MINIFY_MASK 0x000f0000 -#define NV20TCL_TX_FILTER_MINIFY_NEAREST 0x00010000 -#define NV20TCL_TX_FILTER_MINIFY_LINEAR 0x00020000 -#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x00030000 -#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x00040000 -#define NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x00050000 -#define NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x00060000 -#define NV20TCL_TX_FILTER_MAGNIFY_SHIFT 24 -#define NV20TCL_TX_FILTER_MAGNIFY_MASK 0x0f000000 -#define NV20TCL_TX_FILTER_MAGNIFY_NEAREST 0x01000000 -#define NV20TCL_TX_FILTER_MAGNIFY_LINEAR 0x02000000 -#define NV20TCL_TX_NPOT_SIZE(x) (0x00001b1c+((x)*64)) -#define NV20TCL_TX_NPOT_SIZE__SIZE 0x00000004 -#define NV20TCL_TX_NPOT_SIZE_H_SHIFT 0 -#define NV20TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff -#define NV20TCL_TX_NPOT_SIZE_W_SHIFT 16 -#define NV20TCL_TX_NPOT_SIZE_W_MASK 0xffff0000 -#define NV20TCL_TX_PALETTE_OFFSET(x) (0x00001b20+((x)*64)) -#define NV20TCL_TX_PALETTE_OFFSET__SIZE 0x00000004 -#define NV20TCL_TX_BORDER_COLOR(x) (0x00001b24+((x)*64)) -#define NV20TCL_TX_BORDER_COLOR__SIZE 0x00000004 -#define NV20TCL_TX_BORDER_COLOR_B_SHIFT 0 -#define NV20TCL_TX_BORDER_COLOR_B_MASK 0x000000ff -#define NV20TCL_TX_BORDER_COLOR_G_SHIFT 8 -#define NV20TCL_TX_BORDER_COLOR_G_MASK 0x0000ff00 -#define NV20TCL_TX_BORDER_COLOR_R_SHIFT 16 -#define NV20TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000 -#define NV20TCL_TX_BORDER_COLOR_A_SHIFT 24 -#define NV20TCL_TX_BORDER_COLOR_A_MASK 0xff000000 -#define NV20TCL_TX_SHADER_OFFSET_MATRIX00(x) (0x00001b28+((x)*64)) -#define NV20TCL_TX_SHADER_OFFSET_MATRIX00__SIZE 0x00000004 -#define NV20TCL_TX_SHADER_OFFSET_MATRIX01(x) (0x00001b2c+((x)*64)) -#define NV20TCL_TX_SHADER_OFFSET_MATRIX01__SIZE 0x00000004 -#define NV20TCL_TX_SHADER_OFFSET_MATRIX11(x) (0x00001b30+((x)*64)) -#define NV20TCL_TX_SHADER_OFFSET_MATRIX11__SIZE 0x00000004 -#define NV20TCL_TX_SHADER_OFFSET_MATRIX10(x) (0x00001b34+((x)*64)) -#define NV20TCL_TX_SHADER_OFFSET_MATRIX10__SIZE 0x00000004 -#define NV20TCL_DEPTH_UNK17D8 0x00001d78 -#define NV20TCL_DEPTH_UNK17D8_CLAMP_SHIFT 4 -#define NV20TCL_DEPTH_UNK17D8_CLAMP_MASK 0x000000f0 -#define NV20TCL_MULTISAMPLE_CONTROL 0x00001d7c -#define NV20TCL_CLEAR_DEPTH_VALUE 0x00001d8c -#define NV20TCL_CLEAR_VALUE 0x00001d90 -#define NV20TCL_CLEAR_BUFFERS 0x00001d94 -#define NV20TCL_CLEAR_BUFFERS_COLOR_A (1 << 7) -#define NV20TCL_CLEAR_BUFFERS_COLOR_B (1 << 6) -#define NV20TCL_CLEAR_BUFFERS_COLOR_G (1 << 5) -#define NV20TCL_CLEAR_BUFFERS_COLOR_R (1 << 4) -#define NV20TCL_CLEAR_BUFFERS_STENCIL (1 << 1) -#define NV20TCL_CLEAR_BUFFERS_DEPTH (1 << 0) -#define NV20TCL_RC_COLOR0 0x00001e20 -#define NV20TCL_RC_COLOR0_B_SHIFT 0 -#define NV20TCL_RC_COLOR0_B_MASK 0x000000ff -#define NV20TCL_RC_COLOR0_G_SHIFT 8 -#define NV20TCL_RC_COLOR0_G_MASK 0x0000ff00 -#define NV20TCL_RC_COLOR0_R_SHIFT 16 -#define NV20TCL_RC_COLOR0_R_MASK 0x00ff0000 -#define NV20TCL_RC_COLOR0_A_SHIFT 24 -#define NV20TCL_RC_COLOR0_A_MASK 0xff000000 -#define NV20TCL_RC_COLOR1 0x00001e24 -#define NV20TCL_RC_COLOR1_B_SHIFT 0 -#define NV20TCL_RC_COLOR1_B_MASK 0x000000ff -#define NV20TCL_RC_COLOR1_G_SHIFT 8 -#define NV20TCL_RC_COLOR1_G_MASK 0x0000ff00 -#define NV20TCL_RC_COLOR1_R_SHIFT 16 -#define NV20TCL_RC_COLOR1_R_MASK 0x00ff0000 -#define NV20TCL_RC_COLOR1_A_SHIFT 24 -#define NV20TCL_RC_COLOR1_A_MASK 0xff000000 -#define NV20TCL_BACK_MATERIAL_SHININESS(x) (0x00001e28+((x)*4)) -#define NV20TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006 -#define NV20TCL_RC_OUT_RGB(x) (0x00001e40+((x)*4)) -#define NV20TCL_RC_OUT_RGB__SIZE 0x00000008 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV20TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -#define NV20TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -#define NV20TCL_RC_OUT_RGB_MUX_SUM (1 << 14) -#define NV20TCL_RC_OUT_RGB_BIAS (1 << 15) -#define NV20TCL_RC_OUT_RGB_BIAS_NONE 0x00000000 -#define NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV20TCL_RC_OUT_RGB_SCALE_SHIFT 17 -#define NV20TCL_RC_OUT_RGB_SCALE_MASK 0x00000000 -#define NV20TCL_RC_OUT_RGB_SCALE_NONE 0x00000000 -#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000 -#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV20TCL_RC_ENABLE 0x00001e60 -#define NV20TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0 -#define NV20TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f -#define NV20TCL_TX_RCOMP 0x00001e6c -#define NV20TCL_TX_RCOMP_NEVER 0x00000000 -#define NV20TCL_TX_RCOMP_GREATER 0x00000001 -#define NV20TCL_TX_RCOMP_EQUAL 0x00000002 -#define NV20TCL_TX_RCOMP_GEQUAL 0x00000003 -#define NV20TCL_TX_RCOMP_LESS 0x00000004 -#define NV20TCL_TX_RCOMP_NOTEQUAL 0x00000005 -#define NV20TCL_TX_RCOMP_LEQUAL 0x00000006 -#define NV20TCL_TX_RCOMP_ALWAYS 0x00000007 -#define NV20TCL_TX_SHADER_OP 0x00001e70 -#define NV20TCL_TX_SHADER_OP_TX0_SHIFT 0 -#define NV20TCL_TX_SHADER_OP_TX0_MASK 0x0000001f -#define NV20TCL_TX_SHADER_OP_TX0_NONE 0x00000000 -#define NV20TCL_TX_SHADER_OP_TX0_TEXTURE_2D 0x00000001 -#define NV20TCL_TX_SHADER_OP_TX0_PASS_THROUGH 0x00000004 -#define NV20TCL_TX_SHADER_OP_TX0_CULL_FRAGMENT 0x00000005 -#define NV20TCL_TX_SHADER_OP_TX0_OFFSET_TEXTURE_2D 0x00000006 -#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_TEXTURE_2D 0x00000009 -#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_DEPTH_REPLACE 0x0000000a -#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_AR_TEXTURE_2D 0x0000000f -#define NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_GB_TEXTURE_2D 0x00000010 -#define NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT 0x00000011 -#define NV20TCL_TX_SHADER_OP_TX1_SHIFT 5 -#define NV20TCL_TX_SHADER_OP_TX1_MASK 0x000003e0 -#define NV20TCL_TX_SHADER_OP_TX1_NONE 0x00000000 -#define NV20TCL_TX_SHADER_OP_TX1_TEXTURE_2D 0x00000020 -#define NV20TCL_TX_SHADER_OP_TX1_PASS_THROUGH 0x00000080 -#define NV20TCL_TX_SHADER_OP_TX1_CULL_FRAGMENT 0x000000a0 -#define NV20TCL_TX_SHADER_OP_TX1_OFFSET_TEXTURE_2D 0x000000c0 -#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_TEXTURE_2D 0x00000120 -#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_DEPTH_REPLACE 0x00000140 -#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_AR_TEXTURE_2D 0x000001e0 -#define NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_GB_TEXTURE_2D 0x00000200 -#define NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT 0x00000220 -#define NV20TCL_TX_SHADER_OP_TX2_SHIFT 10 -#define NV20TCL_TX_SHADER_OP_TX2_MASK 0x00007c00 -#define NV20TCL_TX_SHADER_OP_TX2_NONE 0x00000000 -#define NV20TCL_TX_SHADER_OP_TX2_TEXTURE_2D 0x00000400 -#define NV20TCL_TX_SHADER_OP_TX2_PASS_THROUGH 0x00001000 -#define NV20TCL_TX_SHADER_OP_TX2_CULL_FRAGMENT 0x00001400 -#define NV20TCL_TX_SHADER_OP_TX2_OFFSET_TEXTURE_2D 0x00001800 -#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_TEXTURE_2D 0x00002400 -#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_DEPTH_REPLACE 0x00002800 -#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_AR_TEXTURE_2D 0x00003c00 -#define NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_GB_TEXTURE_2D 0x00004000 -#define NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT 0x00004400 -#define NV20TCL_TX_SHADER_OP_TX3_SHIFT 15 -#define NV20TCL_TX_SHADER_OP_TX3_MASK 0x000f8000 -#define NV20TCL_TX_SHADER_OP_TX3_NONE 0x00000000 -#define NV20TCL_TX_SHADER_OP_TX3_TEXTURE_2D 0x00008000 -#define NV20TCL_TX_SHADER_OP_TX3_PASS_THROUGH 0x00020000 -#define NV20TCL_TX_SHADER_OP_TX3_CULL_FRAGMENT 0x00028000 -#define NV20TCL_TX_SHADER_OP_TX3_OFFSET_TEXTURE_2D 0x00030000 -#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_TEXTURE_2D 0x00048000 -#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_DEPTH_REPLACE 0x00050000 -#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_AR_TEXTURE_2D 0x00078000 -#define NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_GB_TEXTURE_2D 0x00080000 -#define NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT 0x00088000 -#define NV20TCL_TX_SHADER_DOTMAPPING 0x00001e74 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_SHIFT 0 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX0_MASK 0x0000000f -#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_SHIFT 4 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX1_MASK 0x000000f0 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_SHIFT 8 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX2_MASK 0x00000f00 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_SHIFT 12 -#define NV20TCL_TX_SHADER_DOTMAPPING_TX3_MASK 0x0000f000 -#define NV20TCL_TX_SHADER_PREVIOUS 0x00001e78 -#define NV20TCL_TX_SHADER_PREVIOUS_TX0_SHIFT 8 -#define NV20TCL_TX_SHADER_PREVIOUS_TX0_MASK 0x00000f00 -#define NV20TCL_TX_SHADER_PREVIOUS_TX1_SHIFT 12 -#define NV20TCL_TX_SHADER_PREVIOUS_TX1_MASK 0x0000f000 -#define NV20TCL_TX_SHADER_PREVIOUS_TX2_SHIFT 16 -#define NV20TCL_TX_SHADER_PREVIOUS_TX2_MASK 0x00030000 -#define NV20TCL_TX_SHADER_PREVIOUS_TX3_SHIFT 20 -#define NV20TCL_TX_SHADER_PREVIOUS_TX3_MASK 0x00300000 -#define NV20TCL_ENGINE 0x00001e94 -#define NV20TCL_ENGINE_VP (1 << 1) -#define NV20TCL_ENGINE_FIXED (1 << 2) -#define NV20TCL_VP_UPLOAD_FROM_ID 0x00001e9c -#define NV20TCL_VP_START_FROM_ID 0x00001ea0 -#define NV20TCL_VP_UPLOAD_CONST_ID 0x00001ea4 - - -#define NV25TCL 0x00000597 - -#define NV25TCL_DMA_IN_MEMORY4 0x0000019c -#define NV25TCL_DMA_IN_MEMORY5 0x000001a0 -#define NV25TCL_DMA_IN_MEMORY8 0x000001ac -#define NV25TCL_DMA_IN_MEMORY9 0x000001b0 - - -#define NV30TCL 0x00000397 - - - -#define NV35TCL 0x00000497 - - - -#define NV34TCL 0x00000697 - -#define NV34TCL_NOP 0x00000100 -#define NV34TCL_NOTIFY 0x00000104 -#define NV34TCL_DMA_NOTIFY 0x00000180 -#define NV34TCL_DMA_TEXTURE0 0x00000184 -#define NV34TCL_DMA_TEXTURE1 0x00000188 -#define NV34TCL_DMA_COLOR1 0x0000018c -#define NV34TCL_DMA_COLOR0 0x00000194 -#define NV34TCL_DMA_ZETA 0x00000198 -#define NV34TCL_DMA_VTXBUF0 0x0000019c -#define NV34TCL_DMA_VTXBUF1 0x000001a0 -#define NV34TCL_DMA_FENCE 0x000001a4 -#define NV34TCL_DMA_QUERY 0x000001a8 -#define NV34TCL_DMA_IN_MEMORY7 0x000001ac -#define NV34TCL_DMA_IN_MEMORY8 0x000001b0 -#define NV34TCL_RT_HORIZ 0x00000200 -#define NV34TCL_RT_HORIZ_X_SHIFT 0 -#define NV34TCL_RT_HORIZ_X_MASK 0x0000ffff -#define NV34TCL_RT_HORIZ_W_SHIFT 16 -#define NV34TCL_RT_HORIZ_W_MASK 0xffff0000 -#define NV34TCL_RT_VERT 0x00000204 -#define NV34TCL_RT_VERT_Y_SHIFT 0 -#define NV34TCL_RT_VERT_Y_MASK 0x0000ffff -#define NV34TCL_RT_VERT_H_SHIFT 16 -#define NV34TCL_RT_VERT_H_MASK 0xffff0000 -#define NV34TCL_RT_FORMAT 0x00000208 -#define NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT 24 -#define NV34TCL_RT_FORMAT_LOG2_HEIGHT_MASK 0xff000000 -#define NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT 16 -#define NV34TCL_RT_FORMAT_LOG2_WIDTH_MASK 0x00ff0000 -#define NV34TCL_RT_FORMAT_TYPE_SHIFT 8 -#define NV34TCL_RT_FORMAT_TYPE_MASK 0x00000f00 -#define NV34TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 -#define NV34TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 -#define NV34TCL_RT_FORMAT_ZETA_SHIFT 5 -#define NV34TCL_RT_FORMAT_ZETA_MASK 0x000000e0 -#define NV34TCL_RT_FORMAT_ZETA_Z16 0x00000020 -#define NV34TCL_RT_FORMAT_ZETA_Z24S8 0x00000040 -#define NV34TCL_RT_FORMAT_COLOR_SHIFT 0 -#define NV34TCL_RT_FORMAT_COLOR_MASK 0x0000001f -#define NV34TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 -#define NV34TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 -#define NV34TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 -#define NV34TCL_RT_FORMAT_COLOR_B8 0x00000009 -#define NV34TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d -#define NV34TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f -#define NV34TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 -#define NV34TCL_COLOR0_PITCH 0x0000020c -#define NV34TCL_COLOR0_PITCH_COLOR0_SHIFT 0 -#define NV34TCL_COLOR0_PITCH_COLOR0_MASK 0x0000ffff -#define NV34TCL_COLOR0_PITCH_ZETA_SHIFT 16 -#define NV34TCL_COLOR0_PITCH_ZETA_MASK 0xffff0000 -#define NV34TCL_COLOR0_OFFSET 0x00000210 -#define NV34TCL_ZETA_OFFSET 0x00000214 -#define NV34TCL_COLOR1_OFFSET 0x00000218 -#define NV34TCL_COLOR1_PITCH 0x0000021c -#define NV34TCL_RT_ENABLE 0x00000220 -#define NV34TCL_RT_ENABLE_MRT (1 << 4) -#define NV34TCL_RT_ENABLE_COLOR1 (1 << 1) -#define NV34TCL_RT_ENABLE_COLOR0 (1 << 0) -#define NV34TCL_LMA_DEPTH_PITCH 0x0000022c -#define NV34TCL_LMA_DEPTH_OFFSET 0x00000230 -#define NV34TCL_TX_UNITS_ENABLE 0x0000023c -#define NV34TCL_TX_UNITS_ENABLE_TX0 (1 << 0) -#define NV34TCL_TX_UNITS_ENABLE_TX1 (1 << 1) -#define NV34TCL_TX_UNITS_ENABLE_TX2 (1 << 2) -#define NV34TCL_TX_UNITS_ENABLE_TX3 (1 << 3) -#define NV34TCL_TX_UNITS_ENABLE_TX4 (1 << 4) -#define NV34TCL_TX_UNITS_ENABLE_TX5 (1 << 5) -#define NV34TCL_TX_UNITS_ENABLE_TX6 (1 << 6) -#define NV34TCL_TX_UNITS_ENABLE_TX7 (1 << 7) -#define NV34TCL_TX_MATRIX_ENABLE(x) (0x00000240+((x)*4)) -#define NV34TCL_TX_MATRIX_ENABLE__SIZE 0x00000008 -#define NV34TCL_VIEWPORT_TX_ORIGIN 0x000002b8 -#define NV34TCL_VIEWPORT_TX_ORIGIN_X_SHIFT 0 -#define NV34TCL_VIEWPORT_TX_ORIGIN_X_MASK 0x0000ffff -#define NV34TCL_VIEWPORT_TX_ORIGIN_Y_SHIFT 16 -#define NV34TCL_VIEWPORT_TX_ORIGIN_Y_MASK 0xffff0000 -#define NV34TCL_VIEWPORT_CLIP_MODE 0x000002bc -#define NV34TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*8)) -#define NV34TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NV34TCL_VIEWPORT_CLIP_HORIZ_L_SHIFT 0 -#define NV34TCL_VIEWPORT_CLIP_HORIZ_L_MASK 0x0000ffff -#define NV34TCL_VIEWPORT_CLIP_HORIZ_R_SHIFT 16 -#define NV34TCL_VIEWPORT_CLIP_HORIZ_R_MASK 0xffff0000 -#define NV34TCL_VIEWPORT_CLIP_VERT(x) (0x000002c4+((x)*8)) -#define NV34TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NV34TCL_VIEWPORT_CLIP_VERT_T_SHIFT 0 -#define NV34TCL_VIEWPORT_CLIP_VERT_T_MASK 0x0000ffff -#define NV34TCL_VIEWPORT_CLIP_VERT_D_SHIFT 16 -#define NV34TCL_VIEWPORT_CLIP_VERT_D_MASK 0xffff0000 -#define NV34TCL_DITHER_ENABLE 0x00000300 -#define NV34TCL_ALPHA_FUNC_ENABLE 0x00000304 -#define NV34TCL_ALPHA_FUNC_FUNC 0x00000308 -#define NV34TCL_ALPHA_FUNC_FUNC_NEVER 0x00000200 -#define NV34TCL_ALPHA_FUNC_FUNC_LESS 0x00000201 -#define NV34TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202 -#define NV34TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 -#define NV34TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204 -#define NV34TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV34TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 -#define NV34TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 -#define NV34TCL_ALPHA_FUNC_REF 0x0000030c -#define NV34TCL_BLEND_FUNC_ENABLE 0x00000310 -#define NV34TCL_BLEND_FUNC_SRC 0x00000314 -#define NV34TCL_BLEND_FUNC_SRC_RGB_SHIFT 0 -#define NV34TCL_BLEND_FUNC_SRC_RGB_MASK 0x0000ffff -#define NV34TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00000000 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE 0x00000001 -#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV34TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV34TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307 -#define NV34TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308 -#define NV34TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV34TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003 -#define NV34TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SHIFT 16 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_MASK 0xffff0000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000 -#define NV34TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 -#define NV34TCL_BLEND_FUNC_DST 0x00000318 -#define NV34TCL_BLEND_FUNC_DST_RGB_SHIFT 0 -#define NV34TCL_BLEND_FUNC_DST_RGB_MASK 0x0000ffff -#define NV34TCL_BLEND_FUNC_DST_RGB_ZERO 0x00000000 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE 0x00000001 -#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV34TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV34TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307 -#define NV34TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308 -#define NV34TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV34TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003 -#define NV34TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_SHIFT 16 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_MASK 0xffff0000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00010000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000 -#define NV34TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 -#define NV34TCL_BLEND_COLOR 0x0000031c -#define NV34TCL_BLEND_COLOR_B_SHIFT 0 -#define NV34TCL_BLEND_COLOR_B_MASK 0x000000ff -#define NV34TCL_BLEND_COLOR_G_SHIFT 8 -#define NV34TCL_BLEND_COLOR_G_MASK 0x0000ff00 -#define NV34TCL_BLEND_COLOR_R_SHIFT 16 -#define NV34TCL_BLEND_COLOR_R_MASK 0x00ff0000 -#define NV34TCL_BLEND_COLOR_A_SHIFT 24 -#define NV34TCL_BLEND_COLOR_A_MASK 0xff000000 -#define NV34TCL_BLEND_EQUATION 0x00000320 -#define NV34TCL_BLEND_EQUATION_FUNC_ADD 0x00008006 -#define NV34TCL_BLEND_EQUATION_MIN 0x00008007 -#define NV34TCL_BLEND_EQUATION_MAX 0x00008008 -#define NV34TCL_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a -#define NV34TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV34TCL_COLOR_MASK 0x00000324 -#define NV34TCL_COLOR_MASK_B_SHIFT 0 -#define NV34TCL_COLOR_MASK_B_MASK 0x000000ff -#define NV34TCL_COLOR_MASK_G_SHIFT 8 -#define NV34TCL_COLOR_MASK_G_MASK 0x0000ff00 -#define NV34TCL_COLOR_MASK_R_SHIFT 16 -#define NV34TCL_COLOR_MASK_R_MASK 0x00ff0000 -#define NV34TCL_COLOR_MASK_A_SHIFT 24 -#define NV34TCL_COLOR_MASK_A_MASK 0xff000000 -#define NV34TCL_STENCIL_FRONT_ENABLE 0x00000328 -#define NV34TCL_STENCIL_FRONT_MASK 0x0000032c -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC 0x00000330 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 -#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 -#define NV34TCL_STENCIL_FRONT_FUNC_REF 0x00000334 -#define NV34TCL_STENCIL_FRONT_FUNC_MASK 0x00000338 -#define NV34TCL_STENCIL_FRONT_OP_FAIL 0x0000033c -#define NV34TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a -#define NV34TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL 0x00000340 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS 0x00000344 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV34TCL_STENCIL_BACK_ENABLE 0x00000348 -#define NV34TCL_STENCIL_BACK_MASK 0x0000034c -#define NV34TCL_STENCIL_BACK_FUNC_FUNC 0x00000350 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 -#define NV34TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 -#define NV34TCL_STENCIL_BACK_FUNC_REF 0x00000354 -#define NV34TCL_STENCIL_BACK_FUNC_MASK 0x00000358 -#define NV34TCL_STENCIL_BACK_OP_FAIL 0x0000035c -#define NV34TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 -#define NV34TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a -#define NV34TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00 -#define NV34TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02 -#define NV34TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03 -#define NV34TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL 0x00000360 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV34TCL_STENCIL_BACK_OP_ZPASS 0x00000364 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a -#define NV34TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV34TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV34TCL_SHADE_MODEL 0x00000368 -#define NV34TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NV34TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NV34TCL_FOG_ENABLE 0x0000036c -#define NV34TCL_FOG_COLOR 0x00000370 -#define NV34TCL_FOG_COLOR_R_SHIFT 0 -#define NV34TCL_FOG_COLOR_R_MASK 0x000000ff -#define NV34TCL_FOG_COLOR_G_SHIFT 8 -#define NV34TCL_FOG_COLOR_G_MASK 0x0000ff00 -#define NV34TCL_FOG_COLOR_B_SHIFT 16 -#define NV34TCL_FOG_COLOR_B_MASK 0x00ff0000 -#define NV34TCL_FOG_COLOR_A_SHIFT 24 -#define NV34TCL_FOG_COLOR_A_MASK 0xff000000 -#define NV34TCL_COLOR_LOGIC_OP_ENABLE 0x00000374 -#define NV34TCL_COLOR_LOGIC_OP_OP 0x00000378 -#define NV34TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 -#define NV34TCL_COLOR_LOGIC_OP_OP_AND 0x00001501 -#define NV34TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 -#define NV34TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503 -#define NV34TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 -#define NV34TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505 -#define NV34TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506 -#define NV34TCL_COLOR_LOGIC_OP_OP_OR 0x00001507 -#define NV34TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508 -#define NV34TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 -#define NV34TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a -#define NV34TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b -#define NV34TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c -#define NV34TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d -#define NV34TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e -#define NV34TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f -#define NV34TCL_NORMALIZE_ENABLE 0x0000037c -#define NV34TCL_COLOR_MATERIAL 0x00000390 -#define NV34TCL_COLOR_MATERIAL_FRONT_EMISSION_ENABLE (1 << 0) -#define NV34TCL_COLOR_MATERIAL_FRONT_AMBIENT_ENABLE (1 << 2) -#define NV34TCL_COLOR_MATERIAL_FRONT_DIFFUSE_ENABLE (1 << 4) -#define NV34TCL_COLOR_MATERIAL_FRONT_SPECULAR_ENABLE (1 << 6) -#define NV34TCL_COLOR_MATERIAL_BACK_EMISSION_ENABLE (1 << 8) -#define NV34TCL_COLOR_MATERIAL_BACK_AMBIENT_ENABLE (1 << 10) -#define NV34TCL_COLOR_MATERIAL_BACK_DIFFUSE_ENABLE (1 << 12) -#define NV34TCL_COLOR_MATERIAL_BACK_SPECULAR_ENABLE (1 << 14) -#define NV34TCL_DEPTH_RANGE_NEAR 0x00000394 -#define NV34TCL_DEPTH_RANGE_FAR 0x00000398 -#define NV34TCL_COLOR_MATERIAL_FRONT_R 0x000003a0 -#define NV34TCL_COLOR_MATERIAL_FRONT_G 0x000003a4 -#define NV34TCL_COLOR_MATERIAL_FRONT_B 0x000003a8 -#define NV34TCL_COLOR_MATERIAL_FRONT_A 0x000003b4 -#define NV34TCL_LINE_WIDTH 0x000003b8 -#define NV34TCL_LINE_SMOOTH_ENABLE 0x000003bc -#define NV34TCL_TX_GEN_S(x) (0x00000400+((x)*16)) -#define NV34TCL_TX_GEN_S__SIZE 0x00000008 -#define NV34TCL_TX_GEN_S_FALSE 0x00000000 -#define NV34TCL_TX_GEN_S_EYE_LINEAR 0x00002400 -#define NV34TCL_TX_GEN_S_OBJECT_LINEAR 0x00002401 -#define NV34TCL_TX_GEN_S_SPHERE_MAP 0x00002402 -#define NV34TCL_TX_GEN_S_NORMAL_MAP 0x00008511 -#define NV34TCL_TX_GEN_S_REFLECTION_MAP 0x00008512 -#define NV34TCL_TX_GEN_T(x) (0x00000404+((x)*16)) -#define NV34TCL_TX_GEN_T__SIZE 0x00000008 -#define NV34TCL_TX_GEN_T_FALSE 0x00000000 -#define NV34TCL_TX_GEN_T_EYE_LINEAR 0x00002400 -#define NV34TCL_TX_GEN_T_OBJECT_LINEAR 0x00002401 -#define NV34TCL_TX_GEN_T_SPHERE_MAP 0x00002402 -#define NV34TCL_TX_GEN_T_NORMAL_MAP 0x00008511 -#define NV34TCL_TX_GEN_T_REFLECTION_MAP 0x00008512 -#define NV34TCL_TX_GEN_R(x) (0x00000408+((x)*16)) -#define NV34TCL_TX_GEN_R__SIZE 0x00000008 -#define NV34TCL_TX_GEN_R_FALSE 0x00000000 -#define NV34TCL_TX_GEN_R_EYE_LINEAR 0x00002400 -#define NV34TCL_TX_GEN_R_OBJECT_LINEAR 0x00002401 -#define NV34TCL_TX_GEN_R_SPHERE_MAP 0x00002402 -#define NV34TCL_TX_GEN_R_NORMAL_MAP 0x00008511 -#define NV34TCL_TX_GEN_R_REFLECTION_MAP 0x00008512 -#define NV34TCL_TX_GEN_Q(x) (0x0000040c+((x)*16)) -#define NV34TCL_TX_GEN_Q__SIZE 0x00000008 -#define NV34TCL_TX_GEN_Q_FALSE 0x00000000 -#define NV34TCL_TX_GEN_Q_EYE_LINEAR 0x00002400 -#define NV34TCL_TX_GEN_Q_OBJECT_LINEAR 0x00002401 -#define NV34TCL_TX_GEN_Q_SPHERE_MAP 0x00002402 -#define NV34TCL_TX_GEN_Q_NORMAL_MAP 0x00008511 -#define NV34TCL_TX_GEN_Q_REFLECTION_MAP 0x00008512 -#define NV34TCL_MODELVIEW_MATRIX(x) (0x00000480+((x)*4)) -#define NV34TCL_MODELVIEW_MATRIX__SIZE 0x00000010 -#define NV34TCL_INVERSE_MODELVIEW_MATRIX(x) (0x00000580+((x)*4)) -#define NV34TCL_INVERSE_MODELVIEW_MATRIX__SIZE 0x0000000c -#define NV34TCL_PROJECTION_MATRIX(x) (0x00000680+((x)*4)) -#define NV34TCL_PROJECTION_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX0_MATRIX(x) (0x000006c0+((x)*4)) -#define NV34TCL_TX0_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX1_MATRIX(x) (0x00000700+((x)*4)) -#define NV34TCL_TX1_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX2_MATRIX(x) (0x00000740+((x)*4)) -#define NV34TCL_TX2_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX3_MATRIX(x) (0x00000780+((x)*4)) -#define NV34TCL_TX3_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX4_MATRIX(x) (0x000007c0+((x)*4)) -#define NV34TCL_TX4_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX5_MATRIX(x) (0x00000800+((x)*4)) -#define NV34TCL_TX5_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX6_MATRIX(x) (0x00000840+((x)*4)) -#define NV34TCL_TX6_MATRIX__SIZE 0x00000010 -#define NV34TCL_TX7_MATRIX(x) (0x00000880+((x)*4)) -#define NV34TCL_TX7_MATRIX__SIZE 0x00000010 -#define NV34TCL_SCISSOR_HORIZ 0x000008c0 -#define NV34TCL_SCISSOR_HORIZ_X_SHIFT 0 -#define NV34TCL_SCISSOR_HORIZ_X_MASK 0x0000ffff -#define NV34TCL_SCISSOR_HORIZ_W_SHIFT 16 -#define NV34TCL_SCISSOR_HORIZ_W_MASK 0xffff0000 -#define NV34TCL_SCISSOR_VERT 0x000008c4 -#define NV34TCL_SCISSOR_VERT_Y_SHIFT 0 -#define NV34TCL_SCISSOR_VERT_Y_MASK 0x0000ffff -#define NV34TCL_SCISSOR_VERT_H_SHIFT 16 -#define NV34TCL_SCISSOR_VERT_H_MASK 0xffff0000 -#define NV34TCL_FOG_COORD_DIST 0x000008c8 -#define NV34TCL_FOG_MODE 0x000008cc -#define NV34TCL_FOG_EQUATION_CONSTANT 0x000008d0 -#define NV34TCL_FOG_EQUATION_LINEAR 0x000008d4 -#define NV34TCL_FOG_EQUATION_QUADRATIC 0x000008d8 -#define NV34TCL_FP_ACTIVE_PROGRAM 0x000008e4 -#define NV34TCL_FP_ACTIVE_PROGRAM_DMA0 (1 << 0) -#define NV34TCL_FP_ACTIVE_PROGRAM_DMA1 (1 << 1) -#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_SHIFT 2 -#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_MASK 0xfffffffc -#define NV34TCL_RC_COLOR0 0x000008ec -#define NV34TCL_RC_COLOR0_B_SHIFT 0 -#define NV34TCL_RC_COLOR0_B_MASK 0x000000ff -#define NV34TCL_RC_COLOR0_G_SHIFT 8 -#define NV34TCL_RC_COLOR0_G_MASK 0x0000ff00 -#define NV34TCL_RC_COLOR0_R_SHIFT 16 -#define NV34TCL_RC_COLOR0_R_MASK 0x00ff0000 -#define NV34TCL_RC_COLOR0_A_SHIFT 24 -#define NV34TCL_RC_COLOR0_A_MASK 0xff000000 -#define NV34TCL_RC_COLOR1 0x000008f0 -#define NV34TCL_RC_COLOR1_B_SHIFT 0 -#define NV34TCL_RC_COLOR1_B_MASK 0x000000ff -#define NV34TCL_RC_COLOR1_G_SHIFT 8 -#define NV34TCL_RC_COLOR1_G_MASK 0x0000ff00 -#define NV34TCL_RC_COLOR1_R_SHIFT 16 -#define NV34TCL_RC_COLOR1_R_MASK 0x00ff0000 -#define NV34TCL_RC_COLOR1_A_SHIFT 24 -#define NV34TCL_RC_COLOR1_A_MASK 0xff000000 -#define NV34TCL_RC_FINAL0 0x000008f4 -#define NV34TCL_RC_FINAL0_D_INPUT_SHIFT 0 -#define NV34TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f -#define NV34TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV34TCL_RC_FINAL0_D_INPUT_FOG 0x00000003 -#define NV34TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV34TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 -#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 -#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c -#define NV34TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d -#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV34TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f -#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a -#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b -#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4) -#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV34TCL_RC_FINAL0_D_MAPPING_SHIFT 5 -#define NV34TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0 -#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV34TCL_RC_FINAL0_C_INPUT_SHIFT 8 -#define NV34TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00 -#define NV34TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_FINAL0_C_INPUT_FOG 0x00000300 -#define NV34TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12) -#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV34TCL_RC_FINAL0_C_MAPPING_SHIFT 13 -#define NV34TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000 -#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV34TCL_RC_FINAL0_B_INPUT_SHIFT 16 -#define NV34TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000 -#define NV34TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV34TCL_RC_FINAL0_B_INPUT_FOG 0x00030000 -#define NV34TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV34TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 -#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 -#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 -#define NV34TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 -#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV34TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 -#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 -#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 -#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20) -#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV34TCL_RC_FINAL0_B_MAPPING_SHIFT 21 -#define NV34TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000 -#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV34TCL_RC_FINAL0_A_INPUT_SHIFT 24 -#define NV34TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000 -#define NV34TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV34TCL_RC_FINAL0_A_INPUT_FOG 0x03000000 -#define NV34TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV34TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 -#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 -#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 -#define NV34TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 -#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV34TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 -#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 -#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 -#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28) -#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_SHIFT 29 -#define NV34TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV34TCL_RC_FINAL1 0x000008f8 -#define NV34TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -#define NV34TCL_RC_FINAL1_G_INPUT_SHIFT 8 -#define NV34TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00 -#define NV34TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_FINAL1_G_INPUT_FOG 0x00000300 -#define NV34TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12) -#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV34TCL_RC_FINAL1_G_MAPPING_SHIFT 13 -#define NV34TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000 -#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV34TCL_RC_FINAL1_F_INPUT_SHIFT 16 -#define NV34TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000 -#define NV34TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV34TCL_RC_FINAL1_F_INPUT_FOG 0x00030000 -#define NV34TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 -#define NV34TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 -#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 -#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 -#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 -#define NV34TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 -#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV34TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 -#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 -#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 -#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20) -#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV34TCL_RC_FINAL1_F_MAPPING_SHIFT 21 -#define NV34TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000 -#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV34TCL_RC_FINAL1_E_INPUT_SHIFT 24 -#define NV34TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000 -#define NV34TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV34TCL_RC_FINAL1_E_INPUT_FOG 0x03000000 -#define NV34TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 -#define NV34TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 -#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 -#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 -#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 -#define NV34TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 -#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV34TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 -#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 -#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 -#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28) -#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_SHIFT 29 -#define NV34TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV34TCL_RC_ENABLE 0x000008fc -#define NV34TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0 -#define NV34TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f -#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR0_SHIFT 12 -#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR0_MASK 0x0000f000 -#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR1_SHIFT 16 -#define NV34TCL_RC_ENABLE_STAGE_CONSTANT_COLOR1_MASK 0x000f0000 -#define NV34TCL_RC_IN_ALPHA(x) (0x00000900+((x)*32)) -#define NV34TCL_RC_IN_ALPHA__SIZE 0x00000008 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f -#define NV34TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 -#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c -#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d -#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV34TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f -#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a -#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b -#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4) -#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 -#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12) -#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 -#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 -#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 -#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20) -#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 -#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 -#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 -#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28) -#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 -#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV34TCL_RC_IN_RGB(x) (0x00000904+((x)*32)) -#define NV34TCL_RC_IN_RGB__SIZE 0x00000008 -#define NV34TCL_RC_IN_RGB_D_INPUT_SHIFT 0 -#define NV34TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f -#define NV34TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 -#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 -#define NV34TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003 -#define NV34TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 -#define NV34TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 -#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 -#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 -#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c -#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d -#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV34TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f -#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a -#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b -#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4) -#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 -#define NV34TCL_RC_IN_RGB_D_MAPPING_SHIFT 5 -#define NV34TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0 -#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 -#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 -#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 -#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 -#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 -#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 -#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 -#define NV34TCL_RC_IN_RGB_C_INPUT_SHIFT 8 -#define NV34TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00 -#define NV34TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300 -#define NV34TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12) -#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_SHIFT 13 -#define NV34TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 -#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 -#define NV34TCL_RC_IN_RGB_B_INPUT_SHIFT 16 -#define NV34TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 -#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 -#define NV34TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000 -#define NV34TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 -#define NV34TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 -#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 -#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 -#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 -#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 -#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20) -#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_SHIFT 21 -#define NV34TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 -#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 -#define NV34TCL_RC_IN_RGB_A_INPUT_SHIFT 24 -#define NV34TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 -#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 -#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28) -#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 -#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_SHIFT 29 -#define NV34TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 -#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 -#define NV34TCL_RC_CONSTANT_COLOR0(x) (0x00000908+((x)*32)) -#define NV34TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008 -#define NV34TCL_RC_CONSTANT_COLOR0_B_SHIFT 0 -#define NV34TCL_RC_CONSTANT_COLOR0_B_MASK 0x000000ff -#define NV34TCL_RC_CONSTANT_COLOR0_G_SHIFT 8 -#define NV34TCL_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00 -#define NV34TCL_RC_CONSTANT_COLOR0_R_SHIFT 16 -#define NV34TCL_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000 -#define NV34TCL_RC_CONSTANT_COLOR0_A_SHIFT 24 -#define NV34TCL_RC_CONSTANT_COLOR0_A_MASK 0xff000000 -#define NV34TCL_RC_CONSTANT_COLOR1(x) (0x0000090c+((x)*32)) -#define NV34TCL_RC_CONSTANT_COLOR1__SIZE 0x00000008 -#define NV34TCL_RC_CONSTANT_COLOR1_B_SHIFT 0 -#define NV34TCL_RC_CONSTANT_COLOR1_B_MASK 0x000000ff -#define NV34TCL_RC_CONSTANT_COLOR1_G_SHIFT 8 -#define NV34TCL_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00 -#define NV34TCL_RC_CONSTANT_COLOR1_R_SHIFT 16 -#define NV34TCL_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000 -#define NV34TCL_RC_CONSTANT_COLOR1_A_SHIFT 24 -#define NV34TCL_RC_CONSTANT_COLOR1_A_MASK 0xff000000 -#define NV34TCL_RC_OUT_ALPHA(x) (0x00000910+((x)*32)) -#define NV34TCL_RC_OUT_ALPHA__SIZE 0x00000008 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -#define NV34TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -#define NV34TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14) -#define NV34TCL_RC_OUT_ALPHA_BIAS (1 << 15) -#define NV34TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV34TCL_RC_OUT_ALPHA_SCALE_SHIFT 17 -#define NV34TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000 -#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000 -#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV34TCL_RC_OUT_RGB(x) (0x00000914+((x)*32)) -#define NV34TCL_RC_OUT_RGB__SIZE 0x00000008 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a -#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 -#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 -#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 -#define NV34TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -#define NV34TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -#define NV34TCL_RC_OUT_RGB_MUX_SUM (1 << 14) -#define NV34TCL_RC_OUT_RGB_BIAS (1 << 15) -#define NV34TCL_RC_OUT_RGB_BIAS_NONE 0x00000000 -#define NV34TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 -#define NV34TCL_RC_OUT_RGB_SCALE_SHIFT 17 -#define NV34TCL_RC_OUT_RGB_SCALE_MASK 0x00000000 -#define NV34TCL_RC_OUT_RGB_SCALE_NONE 0x00000000 -#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000 -#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000 -#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000 -#define NV34TCL_VIEWPORT_HORIZ 0x00000a00 -#define NV34TCL_VIEWPORT_HORIZ_X_SHIFT 0 -#define NV34TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff -#define NV34TCL_VIEWPORT_HORIZ_W_SHIFT 16 -#define NV34TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000 -#define NV34TCL_VIEWPORT_VERT 0x00000a04 -#define NV34TCL_VIEWPORT_VERT_Y_SHIFT 0 -#define NV34TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff -#define NV34TCL_VIEWPORT_VERT_H_SHIFT 16 -#define NV34TCL_VIEWPORT_VERT_H_MASK 0xffff0000 -#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10 -#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14 -#define NV34TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18 -#define NV34TCL_VIEWPORT_TRANSLATE_X 0x00000a20 -#define NV34TCL_VIEWPORT_TRANSLATE_Y 0x00000a24 -#define NV34TCL_VIEWPORT_TRANSLATE_Z 0x00000a28 -#define NV34TCL_VIEWPORT_TRANSLATE_W 0x00000a2c -#define NV34TCL_VIEWPORT_SCALE_X 0x00000a30 -#define NV34TCL_VIEWPORT_SCALE_Y 0x00000a34 -#define NV34TCL_VIEWPORT_SCALE_Z 0x00000a38 -#define NV34TCL_VIEWPORT_SCALE_W 0x00000a3c -#define NV34TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000a60 -#define NV34TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000a64 -#define NV34TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000a68 -#define NV34TCL_DEPTH_FUNC 0x00000a6c -#define NV34TCL_DEPTH_FUNC_NEVER 0x00000200 -#define NV34TCL_DEPTH_FUNC_LESS 0x00000201 -#define NV34TCL_DEPTH_FUNC_EQUAL 0x00000202 -#define NV34TCL_DEPTH_FUNC_LEQUAL 0x00000203 -#define NV34TCL_DEPTH_FUNC_GREATER 0x00000204 -#define NV34TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 -#define NV34TCL_DEPTH_FUNC_GEQUAL 0x00000206 -#define NV34TCL_DEPTH_FUNC_ALWAYS 0x00000207 -#define NV34TCL_DEPTH_WRITE_ENABLE 0x00000a70 -#define NV34TCL_DEPTH_TEST_ENABLE 0x00000a74 -#define NV34TCL_POLYGON_OFFSET_FACTOR 0x00000a78 -#define NV34TCL_POLYGON_OFFSET_UNITS 0x00000a7c -#define NV34TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8)) -#define NV34TCL_VTX_ATTR_3I_XY__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_3I_XY_X_SHIFT 0 -#define NV34TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff -#define NV34TCL_VTX_ATTR_3I_XY_Y_SHIFT 16 -#define NV34TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000 -#define NV34TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8)) -#define NV34TCL_VTX_ATTR_3I_Z__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_3I_Z_Z_SHIFT 0 -#define NV34TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff -#define NV34TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4)) -#define NV34TCL_VP_UPLOAD_INST__SIZE 0x00000004 -#define NV34TCL_TX0_CLIP_PLANE_A(x) (0x00000e00+((x)*16)) -#define NV34TCL_TX0_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX0_CLIP_PLANE_B(x) (0x00000e04+((x)*16)) -#define NV34TCL_TX0_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX0_CLIP_PLANE_C(x) (0x00000e08+((x)*16)) -#define NV34TCL_TX0_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX0_CLIP_PLANE_D(x) (0x00000e0c+((x)*16)) -#define NV34TCL_TX0_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX1_CLIP_PLANE_A(x) (0x00000e40+((x)*16)) -#define NV34TCL_TX1_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX1_CLIP_PLANE_B(x) (0x00000e44+((x)*16)) -#define NV34TCL_TX1_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX1_CLIP_PLANE_C(x) (0x00000e48+((x)*16)) -#define NV34TCL_TX1_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX1_CLIP_PLANE_D(x) (0x00000e4c+((x)*16)) -#define NV34TCL_TX1_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX2_CLIP_PLANE_A(x) (0x00000e80+((x)*16)) -#define NV34TCL_TX2_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX2_CLIP_PLANE_B(x) (0x00000e84+((x)*16)) -#define NV34TCL_TX2_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX2_CLIP_PLANE_C(x) (0x00000e88+((x)*16)) -#define NV34TCL_TX2_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX2_CLIP_PLANE_D(x) (0x00000e8c+((x)*16)) -#define NV34TCL_TX2_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX3_CLIP_PLANE_A(x) (0x00000ec0+((x)*16)) -#define NV34TCL_TX3_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX3_CLIP_PLANE_B(x) (0x00000ec4+((x)*16)) -#define NV34TCL_TX3_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX3_CLIP_PLANE_C(x) (0x00000ec8+((x)*16)) -#define NV34TCL_TX3_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX3_CLIP_PLANE_D(x) (0x00000ecc+((x)*16)) -#define NV34TCL_TX3_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX4_CLIP_PLANE_A(x) (0x00000f00+((x)*16)) -#define NV34TCL_TX4_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX4_CLIP_PLANE_B(x) (0x00000f04+((x)*16)) -#define NV34TCL_TX4_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX4_CLIP_PLANE_C(x) (0x00000f08+((x)*16)) -#define NV34TCL_TX4_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX4_CLIP_PLANE_D(x) (0x00000f0c+((x)*16)) -#define NV34TCL_TX4_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX5_CLIP_PLANE_A(x) (0x00000f40+((x)*16)) -#define NV34TCL_TX5_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX5_CLIP_PLANE_B(x) (0x00000f44+((x)*16)) -#define NV34TCL_TX5_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX5_CLIP_PLANE_C(x) (0x00000f48+((x)*16)) -#define NV34TCL_TX5_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX5_CLIP_PLANE_D(x) (0x00000f4c+((x)*16)) -#define NV34TCL_TX5_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX6_CLIP_PLANE_A(x) (0x00000f80+((x)*16)) -#define NV34TCL_TX6_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX6_CLIP_PLANE_B(x) (0x00000f84+((x)*16)) -#define NV34TCL_TX6_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX6_CLIP_PLANE_C(x) (0x00000f88+((x)*16)) -#define NV34TCL_TX6_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX6_CLIP_PLANE_D(x) (0x00000f8c+((x)*16)) -#define NV34TCL_TX6_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_TX7_CLIP_PLANE_A(x) (0x00000fc0+((x)*16)) -#define NV34TCL_TX7_CLIP_PLANE_A__SIZE 0x00000004 -#define NV34TCL_TX7_CLIP_PLANE_B(x) (0x00000fc4+((x)*16)) -#define NV34TCL_TX7_CLIP_PLANE_B__SIZE 0x00000004 -#define NV34TCL_TX7_CLIP_PLANE_C(x) (0x00000fc8+((x)*16)) -#define NV34TCL_TX7_CLIP_PLANE_C__SIZE 0x00000004 -#define NV34TCL_TX7_CLIP_PLANE_D(x) (0x00000fcc+((x)*16)) -#define NV34TCL_TX7_CLIP_PLANE_D__SIZE 0x00000004 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00001000+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00001004+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00001008+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000100c+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00001010+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00001014+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00001018+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000101c+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008 -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00001020+((x)*64)) -#define NV34TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008 -#define NV34TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*64)) -#define NV34TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008 -#define NV34TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*64)) -#define NV34TCL_LIGHT_HALF_VECTOR_Y__SIZE 0x00000008 -#define NV34TCL_LIGHT_HALF_VECTOR_Z(x) (0x00001030+((x)*64)) -#define NV34TCL_LIGHT_HALF_VECTOR_Z__SIZE 0x00000008 -#define NV34TCL_LIGHT_DIRECTION_X(x) (0x00001034+((x)*64)) -#define NV34TCL_LIGHT_DIRECTION_X__SIZE 0x00000008 -#define NV34TCL_LIGHT_DIRECTION_Y(x) (0x00001038+((x)*64)) -#define NV34TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008 -#define NV34TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*64)) -#define NV34TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00001200+((x)*64)) -#define NV34TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00001204+((x)*64)) -#define NV34TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00001208+((x)*64)) -#define NV34TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_DIR_X(x) (0x0000120c+((x)*64)) -#define NV34TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_DIR_Y(x) (0x00001210+((x)*64)) -#define NV34TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_DIR_Z(x) (0x00001214+((x)*64)) -#define NV34TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008 -#define NV34TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00001218+((x)*64)) -#define NV34TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008 -#define NV34TCL_LIGHT_POSITION_X(x) (0x0000121c+((x)*64)) -#define NV34TCL_LIGHT_POSITION_X__SIZE 0x00000008 -#define NV34TCL_LIGHT_POSITION_Y(x) (0x00001220+((x)*64)) -#define NV34TCL_LIGHT_POSITION_Y__SIZE 0x00000008 -#define NV34TCL_LIGHT_POSITION_Z(x) (0x00001224+((x)*64)) -#define NV34TCL_LIGHT_POSITION_Z__SIZE 0x00000008 -#define NV34TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00001228+((x)*64)) -#define NV34TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008 -#define NV34TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000122c+((x)*64)) -#define NV34TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008 -#define NV34TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00001230+((x)*64)) -#define NV34TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008 -#define NV34TCL_FRONT_MATERIAL_SHININESS(x) (0x00001400+((x)*4)) -#define NV34TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006 -#define NV34TCL_ENABLED_LIGHTS 0x00001420 -#define NV34TCL_VERTEX_TWO_SIDE_ENABLE 0x0000142c -#define NV34TCL_FP_REG_CONTROL 0x00001450 -#define NV34TCL_FP_REG_CONTROL_UNK1_SHIFT 16 -#define NV34TCL_FP_REG_CONTROL_UNK1_MASK 0xffff0000 -#define NV34TCL_FP_REG_CONTROL_UNK0_SHIFT 0 -#define NV34TCL_FP_REG_CONTROL_UNK0_MASK 0x0000ffff -#define NV34TCL_FLATSHADE_FIRST 0x00001454 -#define NV34TCL_EDGEFLAG_ENABLE 0x0000145c -#define NV34TCL_VP_CLIP_PLANES_ENABLE 0x00001478 -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 (1 << 1) -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 (1 << 5) -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 (1 << 9) -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 (1 << 13) -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 (1 << 17) -#define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5 (1 << 21) -#define NV34TCL_POLYGON_STIPPLE_ENABLE 0x0000147c -#define NV34TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4)) -#define NV34TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 -#define NV34TCL_VTX_ATTR_3F_X(x) (0x00001500+((x)*16)) -#define NV34TCL_VTX_ATTR_3F_X__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_3F_Y(x) (0x00001504+((x)*16)) -#define NV34TCL_VTX_ATTR_3F_Y__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_3F_Z(x) (0x00001508+((x)*16)) -#define NV34TCL_VTX_ATTR_3F_Z__SIZE 0x00000010 -#define NV34TCL_VP_CLIP_PLANE_A(x) (0x00001600+((x)*16)) -#define NV34TCL_VP_CLIP_PLANE_A__SIZE 0x00000006 -#define NV34TCL_VP_CLIP_PLANE_B(x) (0x00001604+((x)*16)) -#define NV34TCL_VP_CLIP_PLANE_B__SIZE 0x00000006 -#define NV34TCL_VP_CLIP_PLANE_C(x) (0x00001608+((x)*16)) -#define NV34TCL_VP_CLIP_PLANE_C__SIZE 0x00000006 -#define NV34TCL_VP_CLIP_PLANE_D(x) (0x0000160c+((x)*16)) -#define NV34TCL_VP_CLIP_PLANE_D__SIZE 0x00000006 -#define NV34TCL_VTXBUF_ADDRESS(x) (0x00001680+((x)*4)) -#define NV34TCL_VTXBUF_ADDRESS__SIZE 0x00000010 -#define NV34TCL_VTXBUF_ADDRESS_DMA1 (1 << 31) -#define NV34TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0 -#define NV34TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff -#define NV34TCL_VTXFMT(x) (0x00001740+((x)*4)) -#define NV34TCL_VTXFMT__SIZE 0x00000010 -#define NV34TCL_VTXFMT_TYPE_SHIFT 0 -#define NV34TCL_VTXFMT_TYPE_MASK 0x0000000f -#define NV34TCL_VTXFMT_TYPE_16_SNORM 0x00000001 -#define NV34TCL_VTXFMT_TYPE_32_FLOAT 0x00000002 -#define NV34TCL_VTXFMT_TYPE_16_FLOAT 0x00000003 -#define NV34TCL_VTXFMT_TYPE_8_UNORM 0x00000004 -#define NV34TCL_VTXFMT_TYPE_16_SSCALED 0x00000005 -#define NV34TCL_VTXFMT_TYPE_11_11_10_SNORM 0x00000006 -#define NV34TCL_VTXFMT_TYPE_8_USCALED 0x00000007 -#define NV34TCL_VTXFMT_SIZE_SHIFT 4 -#define NV34TCL_VTXFMT_SIZE_MASK 0x000000f0 -#define NV34TCL_VTXFMT_STRIDE_SHIFT 8 -#define NV34TCL_VTXFMT_STRIDE_MASK 0x0000ff00 -#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0 -#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4 -#define NV34TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8 -#define NV34TCL_COLOR_MATERIAL_BACK_R 0x000017b0 -#define NV34TCL_COLOR_MATERIAL_BACK_G 0x000017b4 -#define NV34TCL_COLOR_MATERIAL_BACK_B 0x000017b8 -#define NV34TCL_COLOR_MATERIAL_BACK_A 0x000017c0 -#define NV34TCL_QUERY_RESET 0x000017c8 -#define NV34TCL_QUERY_UNK17CC 0x000017cc -#define NV34TCL_QUERY_GET 0x00001800 -#define NV34TCL_QUERY_GET_UNK24_SHIFT 24 -#define NV34TCL_QUERY_GET_UNK24_MASK 0xff000000 -#define NV34TCL_QUERY_GET_OFFSET_SHIFT 0 -#define NV34TCL_QUERY_GET_OFFSET_MASK 0x00ffffff -#define NV34TCL_VERTEX_BEGIN_END 0x00001808 -#define NV34TCL_VERTEX_BEGIN_END_STOP 0x00000000 -#define NV34TCL_VERTEX_BEGIN_END_POINTS 0x00000001 -#define NV34TCL_VERTEX_BEGIN_END_LINES 0x00000002 -#define NV34TCL_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 -#define NV34TCL_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 -#define NV34TCL_VERTEX_BEGIN_END_TRIANGLES 0x00000005 -#define NV34TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 -#define NV34TCL_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 -#define NV34TCL_VERTEX_BEGIN_END_QUADS 0x00000008 -#define NV34TCL_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 -#define NV34TCL_VERTEX_BEGIN_END_POLYGON 0x0000000a -#define NV34TCL_VB_ELEMENT_U16 0x0000180c -#define NV34TCL_VB_ELEMENT_U16_I0_SHIFT 0 -#define NV34TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff -#define NV34TCL_VB_ELEMENT_U16_I1_SHIFT 16 -#define NV34TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 -#define NV34TCL_VB_ELEMENT_U32 0x00001810 -#define NV34TCL_VB_VERTEX_BATCH 0x00001814 -#define NV34TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0 -#define NV34TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff -#define NV34TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24 -#define NV34TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000 -#define NV34TCL_VERTEX_DATA 0x00001818 -#define NV34TCL_IDXBUF_ADDRESS 0x0000181c -#define NV34TCL_IDXBUF_FORMAT 0x00001820 -#define NV34TCL_IDXBUF_FORMAT_TYPE_SHIFT 4 -#define NV34TCL_IDXBUF_FORMAT_TYPE_MASK 0x000000f0 -#define NV34TCL_IDXBUF_FORMAT_TYPE_U32 0x00000000 -#define NV34TCL_IDXBUF_FORMAT_TYPE_U16 0x00000010 -#define NV34TCL_IDXBUF_FORMAT_DMA1 (1 << 0) -#define NV34TCL_VB_INDEX_BATCH 0x00001824 -#define NV34TCL_VB_INDEX_BATCH_COUNT_SHIFT 24 -#define NV34TCL_VB_INDEX_BATCH_COUNT_MASK 0xff000000 -#define NV34TCL_VB_INDEX_BATCH_START_SHIFT 0 -#define NV34TCL_VB_INDEX_BATCH_START_MASK 0x00ffffff -#define NV34TCL_POLYGON_MODE_FRONT 0x00001828 -#define NV34TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NV34TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NV34TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NV34TCL_POLYGON_MODE_BACK 0x0000182c -#define NV34TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NV34TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NV34TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NV34TCL_CULL_FACE 0x00001830 -#define NV34TCL_CULL_FACE_FRONT 0x00000404 -#define NV34TCL_CULL_FACE_BACK 0x00000405 -#define NV34TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NV34TCL_FRONT_FACE 0x00001834 -#define NV34TCL_FRONT_FACE_CW 0x00000900 -#define NV34TCL_FRONT_FACE_CCW 0x00000901 -#define NV34TCL_POLYGON_SMOOTH_ENABLE 0x00001838 -#define NV34TCL_CULL_FACE_ENABLE 0x0000183c -#define NV34TCL_TX_PALETTE_OFFSET(x) (0x00001840+((x)*4)) -#define NV34TCL_TX_PALETTE_OFFSET__SIZE 0x00000008 -#define NV34TCL_VTX_ATTR_2F_X(x) (0x00001880+((x)*8)) -#define NV34TCL_VTX_ATTR_2F_X__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_2F_Y(x) (0x00001884+((x)*8)) -#define NV34TCL_VTX_ATTR_2F_Y__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4)) -#define NV34TCL_VTX_ATTR_2I__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_2I_X_SHIFT 0 -#define NV34TCL_VTX_ATTR_2I_X_MASK 0x0000ffff -#define NV34TCL_VTX_ATTR_2I_Y_SHIFT 16 -#define NV34TCL_VTX_ATTR_2I_Y_MASK 0xffff0000 -#define NV34TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4)) -#define NV34TCL_VTX_ATTR_4UB__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4UB_X_SHIFT 0 -#define NV34TCL_VTX_ATTR_4UB_X_MASK 0x000000ff -#define NV34TCL_VTX_ATTR_4UB_Y_SHIFT 8 -#define NV34TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00 -#define NV34TCL_VTX_ATTR_4UB_Z_SHIFT 16 -#define NV34TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000 -#define NV34TCL_VTX_ATTR_4UB_W_SHIFT 24 -#define NV34TCL_VTX_ATTR_4UB_W_MASK 0xff000000 -#define NV34TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8)) -#define NV34TCL_VTX_ATTR_4I_XY__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4I_XY_X_SHIFT 0 -#define NV34TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff -#define NV34TCL_VTX_ATTR_4I_XY_Y_SHIFT 16 -#define NV34TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000 -#define NV34TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8)) -#define NV34TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0 -#define NV34TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff -#define NV34TCL_VTX_ATTR_4I_ZW_W_SHIFT 16 -#define NV34TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000 -#define NV34TCL_TX_OFFSET(x) (0x00001a00+((x)*32)) -#define NV34TCL_TX_OFFSET__SIZE 0x00000008 -#define NV34TCL_TX_FORMAT(x) (0x00001a04+((x)*32)) -#define NV34TCL_TX_FORMAT__SIZE 0x00000008 -#define NV34TCL_TX_FORMAT_DMA0 (1 << 0) -#define NV34TCL_TX_FORMAT_DMA1 (1 << 1) -#define NV34TCL_TX_FORMAT_CUBIC (1 << 2) -#define NV34TCL_TX_FORMAT_NO_BORDER (1 << 3) -#define NV34TCL_TX_FORMAT_DIMS_SHIFT 4 -#define NV34TCL_TX_FORMAT_DIMS_MASK 0x000000f0 -#define NV34TCL_TX_FORMAT_DIMS_1D 0x00000010 -#define NV34TCL_TX_FORMAT_DIMS_2D 0x00000020 -#define NV34TCL_TX_FORMAT_DIMS_3D 0x00000030 -#define NV34TCL_TX_FORMAT_FORMAT_SHIFT 8 -#define NV34TCL_TX_FORMAT_FORMAT_MASK 0x0000ff00 -#define NV34TCL_TX_FORMAT_FORMAT_L8 0x00000000 -#define NV34TCL_TX_FORMAT_FORMAT_A8 0x00000100 -#define NV34TCL_TX_FORMAT_FORMAT_A1R5G5B5 0x00000200 -#define NV34TCL_TX_FORMAT_FORMAT_A4R4G4B4 0x00000400 -#define NV34TCL_TX_FORMAT_FORMAT_R5G6B5 0x00000500 -#define NV34TCL_TX_FORMAT_FORMAT_A8R8G8B8 0x00000600 -#define NV34TCL_TX_FORMAT_FORMAT_X8R8G8B8 0x00000700 -#define NV34TCL_TX_FORMAT_FORMAT_INDEX8 0x00000b00 -#define NV34TCL_TX_FORMAT_FORMAT_DXT1 0x00000c00 -#define NV34TCL_TX_FORMAT_FORMAT_DXT3 0x00000e00 -#define NV34TCL_TX_FORMAT_FORMAT_DXT5 0x00000f00 -#define NV34TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000 -#define NV34TCL_TX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100 -#define NV34TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200 -#define NV34TCL_TX_FORMAT_FORMAT_L8_RECT 0x00001300 -#define NV34TCL_TX_FORMAT_FORMAT_DSDT8_RECT 0x00001700 -#define NV34TCL_TX_FORMAT_FORMAT_A8L8 0x00001a00 -#define NV34TCL_TX_FORMAT_FORMAT_A8_RECT 0x00001b00 -#define NV34TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00 -#define NV34TCL_TX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00 -#define NV34TCL_TX_FORMAT_FORMAT_A8L8_RECT 0x00002000 -#define NV34TCL_TX_FORMAT_FORMAT_DSDT8 0x00002800 -#define NV34TCL_TX_FORMAT_FORMAT_Z24 0x2a00 -#define NV34TCL_TX_FORMAT_FORMAT_Z24_RECT 0x2b00 /* XXX: guess! */ -#define NV34TCL_TX_FORMAT_FORMAT_Z16 0x2c00 -#define NV34TCL_TX_FORMAT_FORMAT_Z16_RECT 0x2d00 /* XXX: guess! */ -#define NV34TCL_TX_FORMAT_FORMAT_HILO16 0x00003300 -#define NV34TCL_TX_FORMAT_FORMAT_HILO16_RECT 0x00003600 -#define NV34TCL_TX_FORMAT_FORMAT_HILO8 0x00004400 -#define NV34TCL_TX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500 -#define NV34TCL_TX_FORMAT_FORMAT_HILO8_RECT 0x00004600 -#define NV34TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700 -#define NV34TCL_TX_FORMAT_FORMAT_A16 0x00003200 -#define NV34TCL_TX_FORMAT_FORMAT_A16_RECT 0x00003500 -#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00 -#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00 -#define NV34TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00 -#define NV34TCL_TX_FORMAT_MIPMAP (1 << 19) -#define NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT 20 -#define NV34TCL_TX_FORMAT_BASE_SIZE_U_MASK 0x00f00000 -#define NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT 24 -#define NV34TCL_TX_FORMAT_BASE_SIZE_V_MASK 0x0f000000 -#define NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT 28 -#define NV34TCL_TX_FORMAT_BASE_SIZE_W_MASK 0xf0000000 -#define NV34TCL_TX_WRAP(x) (0x00001a08+((x)*32)) -#define NV34TCL_TX_WRAP__SIZE 0x00000008 -#define NV34TCL_TX_WRAP_S_SHIFT 0 -#define NV34TCL_TX_WRAP_S_MASK 0x000000ff -#define NV34TCL_TX_WRAP_S_REPEAT 0x00000001 -#define NV34TCL_TX_WRAP_S_MIRRORED_REPEAT 0x00000002 -#define NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE 0x00000003 -#define NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER 0x00000004 -#define NV34TCL_TX_WRAP_S_CLAMP 0x00000005 -#define NV34TCL_TX_WRAP_T_SHIFT 8 -#define NV34TCL_TX_WRAP_T_MASK 0x00000f00 -#define NV34TCL_TX_WRAP_T_REPEAT 0x00000100 -#define NV34TCL_TX_WRAP_T_MIRRORED_REPEAT 0x00000200 -#define NV34TCL_TX_WRAP_T_CLAMP_TO_EDGE 0x00000300 -#define NV34TCL_TX_WRAP_T_CLAMP_TO_BORDER 0x00000400 -#define NV34TCL_TX_WRAP_T_CLAMP 0x00000500 -#define NV34TCL_TX_WRAP_EXPAND_NORMAL_SHIFT 12 -#define NV34TCL_TX_WRAP_EXPAND_NORMAL_MASK 0x0000f000 -#define NV34TCL_TX_WRAP_R_SHIFT 16 -#define NV34TCL_TX_WRAP_R_MASK 0x000f0000 -#define NV34TCL_TX_WRAP_R_REPEAT 0x00010000 -#define NV34TCL_TX_WRAP_R_MIRRORED_REPEAT 0x00020000 -#define NV34TCL_TX_WRAP_R_CLAMP_TO_EDGE 0x00030000 -#define NV34TCL_TX_WRAP_R_CLAMP_TO_BORDER 0x00040000 -#define NV34TCL_TX_WRAP_R_CLAMP 0x00050000 -#define NV34TCL_TX_WRAP_RCOMP_SHIFT 28 -#define NV34TCL_TX_WRAP_RCOMP_MASK 0xf0000000 -#define NV34TCL_TX_WRAP_RCOMP_NEVER 0x00000000 -#define NV34TCL_TX_WRAP_RCOMP_GREATER 0x10000000 -#define NV34TCL_TX_WRAP_RCOMP_EQUAL 0x20000000 -#define NV34TCL_TX_WRAP_RCOMP_GEQUAL 0x30000000 -#define NV34TCL_TX_WRAP_RCOMP_LESS 0x40000000 -#define NV34TCL_TX_WRAP_RCOMP_NOTEQUAL 0x50000000 -#define NV34TCL_TX_WRAP_RCOMP_LEQUAL 0x60000000 -#define NV34TCL_TX_WRAP_RCOMP_ALWAYS 0x70000000 -#define NV34TCL_TX_ENABLE(x) (0x00001a0c+((x)*32)) -#define NV34TCL_TX_ENABLE__SIZE 0x00000008 -#define NV34TCL_TX_ENABLE_ANISO_SHIFT 4 -#define NV34TCL_TX_ENABLE_ANISO_MASK 0x00000030 -#define NV34TCL_TX_ENABLE_ANISO_NONE 0x00000000 -#define NV34TCL_TX_ENABLE_ANISO_2X 0x00000010 -#define NV34TCL_TX_ENABLE_ANISO_4X 0x00000020 -#define NV34TCL_TX_ENABLE_ANISO_8X 0x00000030 -#define NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14 -#define NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK 0x0003c000 -#define NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT 26 -#define NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK 0x3c000000 -#define NV34TCL_TX_ENABLE_ENABLE (1 << 30) -#define NV34TCL_TX_SWIZZLE(x) (0x00001a10+((x)*32)) -#define NV34TCL_TX_SWIZZLE__SIZE 0x00000008 -#define NV34TCL_TX_SWIZZLE_S0_X_SHIFT 14 -#define NV34TCL_TX_SWIZZLE_S0_X_MASK 0x0000c000 -#define NV34TCL_TX_SWIZZLE_S0_X_ZERO 0x00000000 -#define NV34TCL_TX_SWIZZLE_S0_X_ONE 0x00004000 -#define NV34TCL_TX_SWIZZLE_S0_X_S1 0x00008000 -#define NV34TCL_TX_SWIZZLE_S0_Y_SHIFT 12 -#define NV34TCL_TX_SWIZZLE_S0_Y_MASK 0x00003000 -#define NV34TCL_TX_SWIZZLE_S0_Y_ZERO 0x00000000 -#define NV34TCL_TX_SWIZZLE_S0_Y_ONE 0x00001000 -#define NV34TCL_TX_SWIZZLE_S0_Y_S1 0x00002000 -#define NV34TCL_TX_SWIZZLE_S0_Z_SHIFT 10 -#define NV34TCL_TX_SWIZZLE_S0_Z_MASK 0x00000c00 -#define NV34TCL_TX_SWIZZLE_S0_Z_ZERO 0x00000000 -#define NV34TCL_TX_SWIZZLE_S0_Z_ONE 0x00000400 -#define NV34TCL_TX_SWIZZLE_S0_Z_S1 0x00000800 -#define NV34TCL_TX_SWIZZLE_S0_W_SHIFT 8 -#define NV34TCL_TX_SWIZZLE_S0_W_MASK 0x00000300 -#define NV34TCL_TX_SWIZZLE_S0_W_ZERO 0x00000000 -#define NV34TCL_TX_SWIZZLE_S0_W_ONE 0x00000100 -#define NV34TCL_TX_SWIZZLE_S0_W_S1 0x00000200 -#define NV34TCL_TX_SWIZZLE_S1_X_SHIFT 6 -#define NV34TCL_TX_SWIZZLE_S1_X_MASK 0x000000c0 -#define NV34TCL_TX_SWIZZLE_S1_X_W 0x00000000 -#define NV34TCL_TX_SWIZZLE_S1_X_Z 0x00000040 -#define NV34TCL_TX_SWIZZLE_S1_X_Y 0x00000080 -#define NV34TCL_TX_SWIZZLE_S1_X_X 0x000000c0 -#define NV34TCL_TX_SWIZZLE_S1_Y_SHIFT 4 -#define NV34TCL_TX_SWIZZLE_S1_Y_MASK 0x00000030 -#define NV34TCL_TX_SWIZZLE_S1_Y_W 0x00000000 -#define NV34TCL_TX_SWIZZLE_S1_Y_Z 0x00000010 -#define NV34TCL_TX_SWIZZLE_S1_Y_Y 0x00000020 -#define NV34TCL_TX_SWIZZLE_S1_Y_X 0x00000030 -#define NV34TCL_TX_SWIZZLE_S1_Z_SHIFT 2 -#define NV34TCL_TX_SWIZZLE_S1_Z_MASK 0x0000000c -#define NV34TCL_TX_SWIZZLE_S1_Z_W 0x00000000 -#define NV34TCL_TX_SWIZZLE_S1_Z_Z 0x00000004 -#define NV34TCL_TX_SWIZZLE_S1_Z_Y 0x00000008 -#define NV34TCL_TX_SWIZZLE_S1_Z_X 0x0000000c -#define NV34TCL_TX_SWIZZLE_S1_W_SHIFT 0 -#define NV34TCL_TX_SWIZZLE_S1_W_MASK 0x00000003 -#define NV34TCL_TX_SWIZZLE_S1_W_W 0x00000000 -#define NV34TCL_TX_SWIZZLE_S1_W_Z 0x00000001 -#define NV34TCL_TX_SWIZZLE_S1_W_Y 0x00000002 -#define NV34TCL_TX_SWIZZLE_S1_W_X 0x00000003 -#define NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT 16 -#define NV34TCL_TX_SWIZZLE_RECT_PITCH_MASK 0xffff0000 -#define NV34TCL_TX_FILTER(x) (0x00001a14+((x)*32)) -#define NV34TCL_TX_FILTER__SIZE 0x00000008 -#define NV34TCL_TX_FILTER_LOD_BIAS_SHIFT 8 -#define NV34TCL_TX_FILTER_LOD_BIAS_MASK 0x00000f00 -#define NV34TCL_TX_FILTER_MINIFY_SHIFT 16 -#define NV34TCL_TX_FILTER_MINIFY_MASK 0x000f0000 -#define NV34TCL_TX_FILTER_MINIFY_NEAREST 0x00010000 -#define NV34TCL_TX_FILTER_MINIFY_LINEAR 0x00020000 -#define NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x00030000 -#define NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x00040000 -#define NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x00050000 -#define NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x00060000 -#define NV34TCL_TX_FILTER_MAGNIFY_SHIFT 24 -#define NV34TCL_TX_FILTER_MAGNIFY_MASK 0x0f000000 -#define NV34TCL_TX_FILTER_MAGNIFY_NEAREST 0x01000000 -#define NV34TCL_TX_FILTER_MAGNIFY_LINEAR 0x02000000 -#define NV34TCL_TX_FILTER_SIGNED_BLUE (1 << 28) -#define NV34TCL_TX_FILTER_SIGNED_GREEN (1 << 29) -#define NV34TCL_TX_FILTER_SIGNED_RED (1 << 30) -#define NV34TCL_TX_FILTER_SIGNED_ALPHA (1 << 31) -#define NV34TCL_TX_NPOT_SIZE(x) (0x00001a18+((x)*32)) -#define NV34TCL_TX_NPOT_SIZE__SIZE 0x00000008 -#define NV34TCL_TX_NPOT_SIZE_H_SHIFT 0 -#define NV34TCL_TX_NPOT_SIZE_H_MASK 0x0000ffff -#define NV34TCL_TX_NPOT_SIZE_W_SHIFT 16 -#define NV34TCL_TX_NPOT_SIZE_W_MASK 0xffff0000 -#define NV34TCL_TX_BORDER_COLOR(x) (0x00001a1c+((x)*32)) -#define NV34TCL_TX_BORDER_COLOR__SIZE 0x00000008 -#define NV34TCL_TX_BORDER_COLOR_B_SHIFT 0 -#define NV34TCL_TX_BORDER_COLOR_B_MASK 0x000000ff -#define NV34TCL_TX_BORDER_COLOR_G_SHIFT 8 -#define NV34TCL_TX_BORDER_COLOR_G_MASK 0x0000ff00 -#define NV34TCL_TX_BORDER_COLOR_R_SHIFT 16 -#define NV34TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000 -#define NV34TCL_TX_BORDER_COLOR_A_SHIFT 24 -#define NV34TCL_TX_BORDER_COLOR_A_MASK 0xff000000 -#define NV34TCL_VTX_ATTR_4F_X(x) (0x00001c00+((x)*16)) -#define NV34TCL_VTX_ATTR_4F_X__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4F_Y(x) (0x00001c04+((x)*16)) -#define NV34TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4F_Z(x) (0x00001c08+((x)*16)) -#define NV34TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 -#define NV34TCL_VTX_ATTR_4F_W(x) (0x00001c0c+((x)*16)) -#define NV34TCL_VTX_ATTR_4F_W__SIZE 0x00000010 -#define NV34TCL_FP_CONTROL 0x00001d60 -#define NV34TCL_FP_CONTROL_USES_KIL (1 << 7) -#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_SHIFT 0 -#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_MASK 0x0000000f -#define NV34TCL_DEPTH_UNK17D8 0x00001d78 -#define NV34TCL_DEPTH_UNK17D8_CLAMP_SHIFT 4 -#define NV34TCL_DEPTH_UNK17D8_CLAMP_MASK 0x000000f0 -#define NV34TCL_MULTISAMPLE_CONTROL 0x00001d7c -#define NV34TCL_MULTISAMPLE_CONTROL_ENABLE (1 << 0) -#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_COVERAGE (1 << 4) -#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_ONE (1 << 8) -#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE_SHIFT 16 -#define NV34TCL_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE_MASK 0xffff0000 -#define NV34TCL_CLEAR_DEPTH_VALUE 0x00001d8c -#define NV34TCL_CLEAR_COLOR_VALUE 0x00001d90 -#define NV34TCL_CLEAR_COLOR_VALUE_B_SHIFT 0 -#define NV34TCL_CLEAR_COLOR_VALUE_B_MASK 0x000000ff -#define NV34TCL_CLEAR_COLOR_VALUE_G_SHIFT 8 -#define NV34TCL_CLEAR_COLOR_VALUE_G_MASK 0x0000ff00 -#define NV34TCL_CLEAR_COLOR_VALUE_R_SHIFT 16 -#define NV34TCL_CLEAR_COLOR_VALUE_R_MASK 0x00ff0000 -#define NV34TCL_CLEAR_COLOR_VALUE_A_SHIFT 24 -#define NV34TCL_CLEAR_COLOR_VALUE_A_MASK 0xff000000 -#define NV34TCL_CLEAR_BUFFERS 0x00001d94 -#define NV34TCL_CLEAR_BUFFERS_COLOR_A (1 << 7) -#define NV34TCL_CLEAR_BUFFERS_COLOR_B (1 << 6) -#define NV34TCL_CLEAR_BUFFERS_COLOR_G (1 << 5) -#define NV34TCL_CLEAR_BUFFERS_COLOR_R (1 << 4) -#define NV34TCL_CLEAR_BUFFERS_STENCIL (1 << 1) -#define NV34TCL_CLEAR_BUFFERS_DEPTH (1 << 0) -#define NV34TCL_DO_VERTICES 0x00001dac -#define NV34TCL_LINE_STIPPLE_ENABLE 0x00001db4 -#define NV34TCL_LINE_STIPPLE_PATTERN 0x00001db8 -#define NV34TCL_LINE_STIPPLE_PATTERN_FACTOR_SHIFT 0 -#define NV34TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff -#define NV34TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16 -#define NV34TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000 -#define NV34TCL_BACK_MATERIAL_SHININESS(x) (0x00001e20+((x)*4)) -#define NV34TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006 -#define NV34TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4)) -#define NV34TCL_VTX_ATTR_1F__SIZE 0x00000010 -#define NV34TCL_ENGINE 0x00001e94 -#define NV34TCL_ENGINE_FP (1 << 0) -#define NV34TCL_ENGINE_VP (1 << 1) -#define NV34TCL_ENGINE_FIXED (1 << 2) -#define NV34TCL_VP_UPLOAD_FROM_ID 0x00001e9c -#define NV34TCL_VP_START_FROM_ID 0x00001ea0 -#define NV34TCL_POINT_PARAMETERS(x) (0x00001ec0+((x)*4)) -#define NV34TCL_POINT_PARAMETERS__SIZE 0x00000008 -#define NV34TCL_POINT_SIZE 0x00001ee0 -#define NV34TCL_POINT_PARAMETERS_ENABLE 0x00001ee4 -#define NV34TCL_POINT_SPRITE 0x00001ee8 -#define NV34TCL_POINT_SPRITE_ENABLE (1 << 0) -#define NV34TCL_POINT_SPRITE_R_MODE_SHIFT 1 -#define NV34TCL_POINT_SPRITE_R_MODE_MASK 0x00000006 -#define NV34TCL_POINT_SPRITE_R_MODE_ZERO 0x00000000 -#define NV34TCL_POINT_SPRITE_R_MODE_R 0x00000002 -#define NV34TCL_POINT_SPRITE_R_MODE_S 0x00000004 -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_0 (1 << 8) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_1 (1 << 9) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_2 (1 << 10) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_3 (1 << 11) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_4 (1 << 12) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_5 (1 << 13) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_6 (1 << 14) -#define NV34TCL_POINT_SPRITE_COORD_REPLACE_7 (1 << 15) -#define NV34TCL_VP_UPLOAD_CONST_ID 0x00001efc -#define NV34TCL_VP_UPLOAD_CONST_X(x) (0x00001f00+((x)*16)) -#define NV34TCL_VP_UPLOAD_CONST_X__SIZE 0x00000004 -#define NV34TCL_VP_UPLOAD_CONST_Y(x) (0x00001f04+((x)*16)) -#define NV34TCL_VP_UPLOAD_CONST_Y__SIZE 0x00000004 -#define NV34TCL_VP_UPLOAD_CONST_Z(x) (0x00001f08+((x)*16)) -#define NV34TCL_VP_UPLOAD_CONST_Z__SIZE 0x00000004 -#define NV34TCL_VP_UPLOAD_CONST_W(x) (0x00001f0c+((x)*16)) -#define NV34TCL_VP_UPLOAD_CONST_W__SIZE 0x00000004 -#define NV34TCL_UNK1f80(x) (0x00001f80+((x)*4)) -#define NV34TCL_UNK1f80__SIZE 0x00000010 - - -#define NV40TCL 0x00004097 - -#define NV40TCL_REF_CNT 0x00000050 -#define NV40TCL_NOP 0x00000100 -#define NV40TCL_NOTIFY 0x00000104 -#define NV40TCL_DMA_NOTIFY 0x00000180 -#define NV40TCL_DMA_TEXTURE0 0x00000184 -#define NV40TCL_DMA_TEXTURE1 0x00000188 -#define NV40TCL_DMA_COLOR1 0x0000018c -#define NV40TCL_DMA_COLOR0 0x00000194 -#define NV40TCL_DMA_ZETA 0x00000198 -#define NV40TCL_DMA_VTXBUF0 0x0000019c -#define NV40TCL_DMA_VTXBUF1 0x000001a0 -#define NV40TCL_DMA_FENCE 0x000001a4 -#define NV40TCL_DMA_QUERY 0x000001a8 -#define NV40TCL_DMA_UNK01AC 0x000001ac -#define NV40TCL_DMA_UNK01B0 0x000001b0 -#define NV40TCL_DMA_COLOR2 0x000001b4 -#define NV40TCL_DMA_COLOR3 0x000001b8 -#define NV40TCL_RT_HORIZ 0x00000200 -#define NV40TCL_RT_HORIZ_W_SHIFT 16 -#define NV40TCL_RT_HORIZ_W_MASK 0xffff0000 -#define NV40TCL_RT_HORIZ_X_SHIFT 0 -#define NV40TCL_RT_HORIZ_X_MASK 0x0000ffff -#define NV40TCL_RT_VERT 0x00000204 -#define NV40TCL_RT_VERT_H_SHIFT 16 -#define NV40TCL_RT_VERT_H_MASK 0xffff0000 -#define NV40TCL_RT_VERT_Y_SHIFT 0 -#define NV40TCL_RT_VERT_Y_MASK 0x0000ffff -#define NV40TCL_RT_FORMAT 0x00000208 -#define NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT 24 -#define NV40TCL_RT_FORMAT_LOG2_HEIGHT_MASK 0xff000000 -#define NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT 16 -#define NV40TCL_RT_FORMAT_LOG2_WIDTH_MASK 0x00ff0000 -#define NV40TCL_RT_FORMAT_TYPE_SHIFT 8 -#define NV40TCL_RT_FORMAT_TYPE_MASK 0x00000f00 -#define NV40TCL_RT_FORMAT_TYPE_LINEAR 0x00000100 -#define NV40TCL_RT_FORMAT_TYPE_SWIZZLED 0x00000200 -#define NV40TCL_RT_FORMAT_ZETA_SHIFT 5 -#define NV40TCL_RT_FORMAT_ZETA_MASK 0x000000e0 -#define NV40TCL_RT_FORMAT_ZETA_Z16 0x00000020 -#define NV40TCL_RT_FORMAT_ZETA_Z24S8 0x00000040 -#define NV40TCL_RT_FORMAT_COLOR_SHIFT 0 -#define NV40TCL_RT_FORMAT_COLOR_MASK 0x0000001f -#define NV40TCL_RT_FORMAT_COLOR_R5G6B5 0x00000003 -#define NV40TCL_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 -#define NV40TCL_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 -#define NV40TCL_RT_FORMAT_COLOR_B8 0x00000009 -#define NV40TCL_RT_FORMAT_COLOR_UNKNOWN 0x0000000d -#define NV40TCL_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f -#define NV40TCL_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 -#define NV40TCL_COLOR0_PITCH 0x0000020c -#define NV40TCL_COLOR0_OFFSET 0x00000210 -#define NV40TCL_ZETA_OFFSET 0x00000214 -#define NV40TCL_COLOR1_OFFSET 0x00000218 -#define NV40TCL_COLOR1_PITCH 0x0000021c -#define NV40TCL_RT_ENABLE 0x00000220 -#define NV40TCL_RT_ENABLE_MRT (1 << 4) -#define NV40TCL_RT_ENABLE_COLOR3 (1 << 3) -#define NV40TCL_RT_ENABLE_COLOR2 (1 << 2) -#define NV40TCL_RT_ENABLE_COLOR1 (1 << 1) -#define NV40TCL_RT_ENABLE_COLOR0 (1 << 0) -#define NV40TCL_ZETA_PITCH 0x0000022c -#define NV40TCL_COLOR2_PITCH 0x00000280 -#define NV40TCL_COLOR3_PITCH 0x00000284 -#define NV40TCL_COLOR2_OFFSET 0x00000288 -#define NV40TCL_COLOR3_OFFSET 0x0000028c -#define NV40TCL_VIEWPORT_CLIP_HORIZ(x) (0x000002c0+((x)*8)) -#define NV40TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NV40TCL_VIEWPORT_CLIP_VERT(x) (0x000002c4+((x)*8)) -#define NV40TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NV40TCL_DITHER_ENABLE 0x00000300 -#define NV40TCL_ALPHA_TEST_ENABLE 0x00000304 -#define NV40TCL_ALPHA_TEST_FUNC 0x00000308 -#define NV40TCL_ALPHA_TEST_FUNC_NEVER 0x00000200 -#define NV40TCL_ALPHA_TEST_FUNC_LESS 0x00000201 -#define NV40TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202 -#define NV40TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203 -#define NV40TCL_ALPHA_TEST_FUNC_GREATER 0x00000204 -#define NV40TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205 -#define NV40TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206 -#define NV40TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NV40TCL_ALPHA_TEST_REF 0x0000030c -#define NV40TCL_BLEND_ENABLE 0x00000310 -#define NV40TCL_BLEND_FUNC_SRC 0x00000314 -#define NV40TCL_BLEND_FUNC_SRC_RGB_SHIFT 0 -#define NV40TCL_BLEND_FUNC_SRC_RGB_MASK 0x0000ffff -#define NV40TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00000000 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE 0x00000001 -#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV40TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV40TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307 -#define NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308 -#define NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003 -#define NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SHIFT 16 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_MASK 0xffff0000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000 -#define NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 -#define NV40TCL_BLEND_FUNC_DST 0x00000318 -#define NV40TCL_BLEND_FUNC_DST_RGB_SHIFT 0 -#define NV40TCL_BLEND_FUNC_DST_RGB_MASK 0x0000ffff -#define NV40TCL_BLEND_FUNC_DST_RGB_ZERO 0x00000000 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE 0x00000001 -#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301 -#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 -#define NV40TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305 -#define NV40TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307 -#define NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308 -#define NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 -#define NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003 -#define NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_SHIFT 16 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_MASK 0xffff0000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00010000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000 -#define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 -#define NV40TCL_BLEND_COLOR 0x0000031c -#define NV40TCL_BLEND_COLOR_B_SHIFT 0 -#define NV40TCL_BLEND_COLOR_B_MASK 0x000000ff -#define NV40TCL_BLEND_COLOR_G_SHIFT 8 -#define NV40TCL_BLEND_COLOR_G_MASK 0x0000ff00 -#define NV40TCL_BLEND_COLOR_R_SHIFT 16 -#define NV40TCL_BLEND_COLOR_R_MASK 0x00ff0000 -#define NV40TCL_BLEND_COLOR_A_SHIFT 24 -#define NV40TCL_BLEND_COLOR_A_MASK 0xff000000 -#define NV40TCL_BLEND_EQUATION 0x00000320 -#define NV40TCL_BLEND_EQUATION_RGB_SHIFT 0 -#define NV40TCL_BLEND_EQUATION_RGB_MASK 0x0000ffff -#define NV40TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 -#define NV40TCL_BLEND_EQUATION_RGB_MIN 0x00008007 -#define NV40TCL_BLEND_EQUATION_RGB_MAX 0x00008008 -#define NV40TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a -#define NV40TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV40TCL_BLEND_EQUATION_ALPHA_SHIFT 16 -#define NV40TCL_BLEND_EQUATION_ALPHA_MASK 0xffff0000 -#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x80060000 -#define NV40TCL_BLEND_EQUATION_ALPHA_MIN 0x80070000 -#define NV40TCL_BLEND_EQUATION_ALPHA_MAX 0x80080000 -#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x800a0000 -#define NV40TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x800b0000 -#define NV40TCL_COLOR_MASK 0x00000324 -#define NV40TCL_COLOR_MASK_BUFFER0_B_SHIFT 0 -#define NV40TCL_COLOR_MASK_BUFFER0_B_MASK 0x000000ff -#define NV40TCL_COLOR_MASK_BUFFER0_G_SHIFT 8 -#define NV40TCL_COLOR_MASK_BUFFER0_G_MASK 0x0000ff00 -#define NV40TCL_COLOR_MASK_BUFFER0_R_SHIFT 16 -#define NV40TCL_COLOR_MASK_BUFFER0_R_MASK 0x00ff0000 -#define NV40TCL_COLOR_MASK_BUFFER0_A_SHIFT 24 -#define NV40TCL_COLOR_MASK_BUFFER0_A_MASK 0xff000000 -#define NV40TCL_STENCIL_FRONT_ENABLE 0x00000328 -#define NV40TCL_STENCIL_FRONT_MASK 0x0000032c -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC 0x00000330 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 -#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 -#define NV40TCL_STENCIL_FRONT_FUNC_REF 0x00000334 -#define NV40TCL_STENCIL_FRONT_FUNC_MASK 0x00000338 -#define NV40TCL_STENCIL_FRONT_OP_FAIL 0x0000033c -#define NV40TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a -#define NV40TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL 0x00000340 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS 0x00000344 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV40TCL_STENCIL_BACK_ENABLE 0x00000348 -#define NV40TCL_STENCIL_BACK_MASK 0x0000034c -#define NV40TCL_STENCIL_BACK_FUNC_FUNC 0x00000350 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 -#define NV40TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 -#define NV40TCL_STENCIL_BACK_FUNC_REF 0x00000354 -#define NV40TCL_STENCIL_BACK_FUNC_MASK 0x00000358 -#define NV40TCL_STENCIL_BACK_OP_FAIL 0x0000035c -#define NV40TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 -#define NV40TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a -#define NV40TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00 -#define NV40TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02 -#define NV40TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03 -#define NV40TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL 0x00000360 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV40TCL_STENCIL_BACK_OP_ZPASS 0x00000364 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a -#define NV40TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV40TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV40TCL_SHADE_MODEL 0x00000368 -#define NV40TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NV40TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NV40TCL_MRT_COLOR_MASK 0x00000370 -#define NV40TCL_MRT_COLOR_MASK_BUFFER1_A (1 << 4) -#define NV40TCL_MRT_COLOR_MASK_BUFFER1_R (1 << 5) -#define NV40TCL_MRT_COLOR_MASK_BUFFER1_G (1 << 6) -#define NV40TCL_MRT_COLOR_MASK_BUFFER1_B (1 << 7) -#define NV40TCL_MRT_COLOR_MASK_BUFFER2_A (1 << 8) -#define NV40TCL_MRT_COLOR_MASK_BUFFER2_R (1 << 9) -#define NV40TCL_MRT_COLOR_MASK_BUFFER2_G (1 << 10) -#define NV40TCL_MRT_COLOR_MASK_BUFFER2_B (1 << 11) -#define NV40TCL_MRT_COLOR_MASK_BUFFER3_A (1 << 12) -#define NV40TCL_MRT_COLOR_MASK_BUFFER3_R (1 << 13) -#define NV40TCL_MRT_COLOR_MASK_BUFFER3_G (1 << 14) -#define NV40TCL_MRT_COLOR_MASK_BUFFER3_B (1 << 15) -#define NV40TCL_COLOR_LOGIC_OP_ENABLE 0x00000374 -#define NV40TCL_COLOR_LOGIC_OP 0x00000378 -#define NV40TCL_COLOR_LOGIC_OP_CLEAR 0x00001500 -#define NV40TCL_COLOR_LOGIC_OP_AND 0x00001501 -#define NV40TCL_COLOR_LOGIC_OP_AND_REVERSE 0x00001502 -#define NV40TCL_COLOR_LOGIC_OP_COPY 0x00001503 -#define NV40TCL_COLOR_LOGIC_OP_AND_INVERTED 0x00001504 -#define NV40TCL_COLOR_LOGIC_OP_NOOP 0x00001505 -#define NV40TCL_COLOR_LOGIC_OP_XOR 0x00001506 -#define NV40TCL_COLOR_LOGIC_OP_OR 0x00001507 -#define NV40TCL_COLOR_LOGIC_OP_NOR 0x00001508 -#define NV40TCL_COLOR_LOGIC_OP_EQUIV 0x00001509 -#define NV40TCL_COLOR_LOGIC_OP_INVERT 0x0000150a -#define NV40TCL_COLOR_LOGIC_OP_OR_REVERSE 0x0000150b -#define NV40TCL_COLOR_LOGIC_OP_COPY_INVERTED 0x0000150c -#define NV40TCL_COLOR_LOGIC_OP_OR_INVERTED 0x0000150d -#define NV40TCL_COLOR_LOGIC_OP_NAND 0x0000150e -#define NV40TCL_COLOR_LOGIC_OP_SET 0x0000150f -#define NV40TCL_DEPTH_RANGE_NEAR 0x00000394 -#define NV40TCL_DEPTH_RANGE_FAR 0x00000398 -#define NV40TCL_LINE_WIDTH 0x000003b8 -#define NV40TCL_LINE_SMOOTH_ENABLE 0x000003bc -#define NV40TCL_UNK03C0(x) (0x000003c0+((x)*4)) -#define NV40TCL_UNK03C0__SIZE 0x00000010 -#define NV40TCL_UNK0400(x) (0x00000400+((x)*4)) -#define NV40TCL_UNK0400__SIZE 0x00000010 -#define NV40TCL_UNK0440(x) (0x00000440+((x)*4)) -#define NV40TCL_UNK0440__SIZE 0x00000020 -#define NV40TCL_SCISSOR_HORIZ 0x000008c0 -#define NV40TCL_SCISSOR_HORIZ_X_SHIFT 0 -#define NV40TCL_SCISSOR_HORIZ_X_MASK 0x0000ffff -#define NV40TCL_SCISSOR_HORIZ_W_SHIFT 16 -#define NV40TCL_SCISSOR_HORIZ_W_MASK 0xffff0000 -#define NV40TCL_SCISSOR_VERT 0x000008c4 -#define NV40TCL_SCISSOR_VERT_Y_SHIFT 0 -#define NV40TCL_SCISSOR_VERT_Y_MASK 0x0000ffff -#define NV40TCL_SCISSOR_VERT_H_SHIFT 16 -#define NV40TCL_SCISSOR_VERT_H_MASK 0xffff0000 -#define NV40TCL_FOG_MODE 0x000008cc -#define NV40TCL_FOG_EQUATION_CONSTANT 0x000008d0 -#define NV40TCL_FOG_EQUATION_LINEAR 0x000008d4 -#define NV40TCL_FOG_EQUATION_QUADRATIC 0x000008d8 -#define NV40TCL_FP_ADDRESS 0x000008e4 -#define NV40TCL_FP_ADDRESS_OFFSET_SHIFT 8 -#define NV40TCL_FP_ADDRESS_OFFSET_MASK 0xffffff00 -#define NV40TCL_FP_ADDRESS_DMA1 (1 << 1) -#define NV40TCL_FP_ADDRESS_DMA0 (1 << 0) -#define NV40TCL_VIEWPORT_HORIZ 0x00000a00 -#define NV40TCL_VIEWPORT_HORIZ_W_SHIFT 16 -#define NV40TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000 -#define NV40TCL_VIEWPORT_HORIZ_X_SHIFT 0 -#define NV40TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff -#define NV40TCL_VIEWPORT_VERT 0x00000a04 -#define NV40TCL_VIEWPORT_VERT_H_SHIFT 16 -#define NV40TCL_VIEWPORT_VERT_H_MASK 0xffff0000 -#define NV40TCL_VIEWPORT_VERT_Y_SHIFT 0 -#define NV40TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff -#define NV40TCL_VIEWPORT_TRANSLATE_X 0x00000a20 -#define NV40TCL_VIEWPORT_TRANSLATE_Y 0x00000a24 -#define NV40TCL_VIEWPORT_TRANSLATE_Z 0x00000a28 -#define NV40TCL_VIEWPORT_TRANSLATE_W 0x00000a2c -#define NV40TCL_VIEWPORT_SCALE_X 0x00000a30 -#define NV40TCL_VIEWPORT_SCALE_Y 0x00000a34 -#define NV40TCL_VIEWPORT_SCALE_Z 0x00000a38 -#define NV40TCL_VIEWPORT_SCALE_W 0x00000a3c -#define NV40TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000a60 -#define NV40TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000a64 -#define NV40TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000a68 -#define NV40TCL_DEPTH_FUNC 0x00000a6c -#define NV40TCL_DEPTH_FUNC_NEVER 0x00000200 -#define NV40TCL_DEPTH_FUNC_LESS 0x00000201 -#define NV40TCL_DEPTH_FUNC_EQUAL 0x00000202 -#define NV40TCL_DEPTH_FUNC_LEQUAL 0x00000203 -#define NV40TCL_DEPTH_FUNC_GREATER 0x00000204 -#define NV40TCL_DEPTH_FUNC_NOTEQUAL 0x00000205 -#define NV40TCL_DEPTH_FUNC_GEQUAL 0x00000206 -#define NV40TCL_DEPTH_FUNC_ALWAYS 0x00000207 -#define NV40TCL_DEPTH_WRITE_ENABLE 0x00000a70 -#define NV40TCL_DEPTH_TEST_ENABLE 0x00000a74 -#define NV40TCL_POLYGON_OFFSET_FACTOR 0x00000a78 -#define NV40TCL_POLYGON_OFFSET_UNITS 0x00000a7c -#define NV40TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8)) -#define NV40TCL_VTX_ATTR_3I_XY__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_3I_XY_X_SHIFT 0 -#define NV40TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff -#define NV40TCL_VTX_ATTR_3I_XY_Y_SHIFT 16 -#define NV40TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000 -#define NV40TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8)) -#define NV40TCL_VTX_ATTR_3I_Z__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_3I_Z_Z_SHIFT 0 -#define NV40TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff -#define NV40TCL_TEX_FILTER_OPTIMIZATION 0x00000b00 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_SHIFT 0 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_MASK 0x0000001f -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_SHIFT 6 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_MASK 0x000001c0 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_SHIFT 10 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_MASK 0x00007c00 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00 -#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00 -#define NV40TCL_UNK0B40(x) (0x00000b40+((x)*4)) -#define NV40TCL_UNK0B40__SIZE 0x00000008 -#define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4)) -#define NV40TCL_VP_UPLOAD_INST__SIZE 0x00000004 -#define NV40TCL_VERTEX_TWO_SIDE_ENABLE 0x0000142c -#define NV40TCL_CLIP_PLANE_ENABLE 0x00001478 -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE0 (1 << 1) -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE1 (1 << 5) -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE2 (1 << 9) -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE3 (1 << 13) -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE4 (1 << 17) -#define NV40TCL_CLIP_PLANE_ENABLE_PLANE5 (1 << 21) -#define NV40TCL_POLYGON_STIPPLE_ENABLE 0x0000147c -#define NV40TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4)) -#define NV40TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 -#define NV40TCL_VTX_ATTR_3F_X(x) (0x00001500+((x)*16)) -#define NV40TCL_VTX_ATTR_3F_X__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_3F_Y(x) (0x00001504+((x)*16)) -#define NV40TCL_VTX_ATTR_3F_Y__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_3F_Z(x) (0x00001508+((x)*16)) -#define NV40TCL_VTX_ATTR_3F_Z__SIZE 0x00000010 -#define NV40TCL_VTXBUF_ADDRESS(x) (0x00001680+((x)*4)) -#define NV40TCL_VTXBUF_ADDRESS__SIZE 0x00000010 -#define NV40TCL_VTXBUF_ADDRESS_DMA1 (1 << 31) -#define NV40TCL_VTXBUF_ADDRESS_OFFSET_SHIFT 0 -#define NV40TCL_VTXBUF_ADDRESS_OFFSET_MASK 0x0fffffff -#define NV40TCL_VTX_CACHE_INVALIDATE 0x00001714 -#define NV40TCL_VTXFMT(x) (0x00001740+((x)*4)) -#define NV40TCL_VTXFMT__SIZE 0x00000010 -#define NV40TCL_VTXFMT_TYPE_SHIFT 0 -#define NV40TCL_VTXFMT_TYPE_MASK 0x0000000f -#define NV40TCL_VTXFMT_TYPE_FLOAT 0x00000002 -#define NV40TCL_VTXFMT_TYPE_HALF 0x00000003 -#define NV40TCL_VTXFMT_TYPE_UBYTE 0x00000004 -#define NV40TCL_VTXFMT_TYPE_USHORT 0x00000005 -#define NV40TCL_VTXFMT_SIZE_SHIFT 4 -#define NV40TCL_VTXFMT_SIZE_MASK 0x000000f0 -#define NV40TCL_VTXFMT_STRIDE_SHIFT 8 -#define NV40TCL_VTXFMT_STRIDE_MASK 0x0000ff00 -#define NV40TCL_QUERY_RESET 0x000017c8 -#define NV40TCL_QUERY_UNK17CC 0x000017cc -#define NV40TCL_QUERY_GET 0x00001800 -#define NV40TCL_QUERY_GET_UNK24_SHIFT 24 -#define NV40TCL_QUERY_GET_UNK24_MASK 0xff000000 -#define NV40TCL_QUERY_GET_OFFSET_SHIFT 0 -#define NV40TCL_QUERY_GET_OFFSET_MASK 0x00ffffff -#define NV40TCL_BEGIN_END 0x00001808 -#define NV40TCL_BEGIN_END_STOP 0x00000000 -#define NV40TCL_BEGIN_END_POINTS 0x00000001 -#define NV40TCL_BEGIN_END_LINES 0x00000002 -#define NV40TCL_BEGIN_END_LINE_LOOP 0x00000003 -#define NV40TCL_BEGIN_END_LINE_STRIP 0x00000004 -#define NV40TCL_BEGIN_END_TRIANGLES 0x00000005 -#define NV40TCL_BEGIN_END_TRIANGLE_STRIP 0x00000006 -#define NV40TCL_BEGIN_END_TRIANGLE_FAN 0x00000007 -#define NV40TCL_BEGIN_END_QUADS 0x00000008 -#define NV40TCL_BEGIN_END_QUAD_STRIP 0x00000009 -#define NV40TCL_BEGIN_END_POLYGON 0x0000000a -#define NV40TCL_VB_ELEMENT_U16 0x0000180c -#define NV40TCL_VB_ELEMENT_U16_1_SHIFT 16 -#define NV40TCL_VB_ELEMENT_U16_1_MASK 0xffff0000 -#define NV40TCL_VB_ELEMENT_U16_0_SHIFT 0 -#define NV40TCL_VB_ELEMENT_U16_0_MASK 0x0000ffff -#define NV40TCL_VB_ELEMENT_U32 0x00001810 -#define NV40TCL_VB_VERTEX_BATCH 0x00001814 -#define NV40TCL_VB_VERTEX_BATCH_COUNT_SHIFT 24 -#define NV40TCL_VB_VERTEX_BATCH_COUNT_MASK 0xff000000 -#define NV40TCL_VB_VERTEX_BATCH_START_SHIFT 0 -#define NV40TCL_VB_VERTEX_BATCH_START_MASK 0x00ffffff -#define NV40TCL_VERTEX_DATA 0x00001818 -#define NV40TCL_IDXBUF_ADDRESS 0x0000181c -#define NV40TCL_IDXBUF_FORMAT 0x00001820 -#define NV40TCL_IDXBUF_FORMAT_TYPE_SHIFT 4 -#define NV40TCL_IDXBUF_FORMAT_TYPE_MASK 0x000000f0 -#define NV40TCL_IDXBUF_FORMAT_TYPE_U32 0x00000000 -#define NV40TCL_IDXBUF_FORMAT_TYPE_U16 0x00000010 -#define NV40TCL_IDXBUF_FORMAT_DMA1 (1 << 0) -#define NV40TCL_VB_INDEX_BATCH 0x00001824 -#define NV40TCL_VB_INDEX_BATCH_COUNT_SHIFT 24 -#define NV40TCL_VB_INDEX_BATCH_COUNT_MASK 0xff000000 -#define NV40TCL_VB_INDEX_BATCH_START_SHIFT 0 -#define NV40TCL_VB_INDEX_BATCH_START_MASK 0x00ffffff -#define NV40TCL_POLYGON_MODE_FRONT 0x00001828 -#define NV40TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NV40TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NV40TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NV40TCL_POLYGON_MODE_BACK 0x0000182c -#define NV40TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NV40TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NV40TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NV40TCL_CULL_FACE 0x00001830 -#define NV40TCL_CULL_FACE_FRONT 0x00000404 -#define NV40TCL_CULL_FACE_BACK 0x00000405 -#define NV40TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NV40TCL_FRONT_FACE 0x00001834 -#define NV40TCL_FRONT_FACE_CW 0x00000900 -#define NV40TCL_FRONT_FACE_CCW 0x00000901 -#define NV40TCL_POLYGON_SMOOTH_ENABLE 0x00001838 -#define NV40TCL_CULL_FACE_ENABLE 0x0000183c -#define NV40TCL_TEX_SIZE1(x) (0x00001840+((x)*4)) -#define NV40TCL_TEX_SIZE1__SIZE 0x00000008 -#define NV40TCL_TEX_SIZE1_DEPTH_SHIFT 20 -#define NV40TCL_TEX_SIZE1_DEPTH_MASK 0xfff00000 -#define NV40TCL_TEX_SIZE1_PITCH_SHIFT 0 -#define NV40TCL_TEX_SIZE1_PITCH_MASK 0x0000ffff -#define NV40TCL_VTX_ATTR_2F_X(x) (0x00001880+((x)*8)) -#define NV40TCL_VTX_ATTR_2F_X__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_2F_Y(x) (0x00001884+((x)*8)) -#define NV40TCL_VTX_ATTR_2F_Y__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4)) -#define NV40TCL_VTX_ATTR_2I__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_2I_X_SHIFT 0 -#define NV40TCL_VTX_ATTR_2I_X_MASK 0x0000ffff -#define NV40TCL_VTX_ATTR_2I_Y_SHIFT 16 -#define NV40TCL_VTX_ATTR_2I_Y_MASK 0xffff0000 -#define NV40TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4)) -#define NV40TCL_VTX_ATTR_4UB__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4UB_X_SHIFT 0 -#define NV40TCL_VTX_ATTR_4UB_X_MASK 0x000000ff -#define NV40TCL_VTX_ATTR_4UB_Y_SHIFT 8 -#define NV40TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00 -#define NV40TCL_VTX_ATTR_4UB_Z_SHIFT 16 -#define NV40TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000 -#define NV40TCL_VTX_ATTR_4UB_W_SHIFT 24 -#define NV40TCL_VTX_ATTR_4UB_W_MASK 0xff000000 -#define NV40TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8)) -#define NV40TCL_VTX_ATTR_4I_XY__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4I_XY_X_SHIFT 0 -#define NV40TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff -#define NV40TCL_VTX_ATTR_4I_XY_Y_SHIFT 16 -#define NV40TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000 -#define NV40TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8)) -#define NV40TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0 -#define NV40TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff -#define NV40TCL_VTX_ATTR_4I_ZW_W_SHIFT 16 -#define NV40TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000 -#define NV40TCL_TEX_OFFSET(x) (0x00001a00+((x)*32)) -#define NV40TCL_TEX_OFFSET__SIZE 0x00000010 -#define NV40TCL_TEX_FORMAT(x) (0x00001a04+((x)*32)) -#define NV40TCL_TEX_FORMAT__SIZE 0x00000010 -#define NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT 16 -#define NV40TCL_TEX_FORMAT_MIPMAP_COUNT_MASK 0x000f0000 -#define NV40TCL_TEX_FORMAT_RECT (1 << 14) -#define NV40TCL_TEX_FORMAT_LINEAR (1 << 13) -#define NV40TCL_TEX_FORMAT_FORMAT_SHIFT 8 -#define NV40TCL_TEX_FORMAT_FORMAT_MASK 0x00001f00 -#define NV40TCL_TEX_FORMAT_FORMAT_L8 0x00000100 -#define NV40TCL_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200 -#define NV40TCL_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000300 -#define NV40TCL_TEX_FORMAT_FORMAT_R5G6B5 0x00000400 -#define NV40TCL_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000500 -#define NV40TCL_TEX_FORMAT_FORMAT_DXT1 0x00000600 -#define NV40TCL_TEX_FORMAT_FORMAT_DXT3 0x00000700 -#define NV40TCL_TEX_FORMAT_FORMAT_DXT5 0x00000800 -#define NV40TCL_TEX_FORMAT_FORMAT_A8L8 0x00000b00 -#define NV40TCL_TEX_FORMAT_FORMAT_Z24 0x00001000 -#define NV40TCL_TEX_FORMAT_FORMAT_Z16 0x00001200 -#define NV40TCL_TEX_FORMAT_FORMAT_A16 0x00001400 -#define NV40TCL_TEX_FORMAT_FORMAT_A16L16 0x00001500 -#define NV40TCL_TEX_FORMAT_FORMAT_HILO8 0x00001800 -#define NV40TCL_TEX_FORMAT_FORMAT_RGBA16F 0x00001a00 -#define NV40TCL_TEX_FORMAT_FORMAT_RGBA32F 0x00001b00 -#define NV40TCL_TEX_FORMAT_DIMS_SHIFT 4 -#define NV40TCL_TEX_FORMAT_DIMS_MASK 0x000000f0 -#define NV40TCL_TEX_FORMAT_DIMS_1D 0x00000010 -#define NV40TCL_TEX_FORMAT_DIMS_2D 0x00000020 -#define NV40TCL_TEX_FORMAT_DIMS_3D 0x00000030 -#define NV40TCL_TEX_FORMAT_NO_BORDER (1 << 3) -#define NV40TCL_TEX_FORMAT_CUBIC (1 << 2) -#define NV40TCL_TEX_FORMAT_DMA1 (1 << 1) -#define NV40TCL_TEX_FORMAT_DMA0 (1 << 0) -#define NV40TCL_TEX_WRAP(x) (0x00001a08+((x)*32)) -#define NV40TCL_TEX_WRAP__SIZE 0x00000010 -#define NV40TCL_TEX_WRAP_S_SHIFT 0 -#define NV40TCL_TEX_WRAP_S_MASK 0x0000000f -#define NV40TCL_TEX_WRAP_S_REPEAT 0x00000001 -#define NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002 -#define NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003 -#define NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER 0x00000004 -#define NV40TCL_TEX_WRAP_S_CLAMP 0x00000005 -#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006 -#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007 -#define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP 0x00000008 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_SHIFT 4 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_MASK 0x00000070 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030 -#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070 -#define NV40TCL_TEX_WRAP_T_SHIFT 8 -#define NV40TCL_TEX_WRAP_T_MASK 0x00000f00 -#define NV40TCL_TEX_WRAP_T_REPEAT 0x00000100 -#define NV40TCL_TEX_WRAP_T_MIRRORED_REPEAT 0x00000200 -#define NV40TCL_TEX_WRAP_T_CLAMP_TO_EDGE 0x00000300 -#define NV40TCL_TEX_WRAP_T_CLAMP_TO_BORDER 0x00000400 -#define NV40TCL_TEX_WRAP_T_CLAMP 0x00000500 -#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE 0x00000600 -#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER 0x00000700 -#define NV40TCL_TEX_WRAP_T_MIRROR_CLAMP 0x00000800 -#define NV40TCL_TEX_WRAP_EXPAND_NORMAL_SHIFT 12 -#define NV40TCL_TEX_WRAP_EXPAND_NORMAL_MASK 0x0000f000 -#define NV40TCL_TEX_WRAP_R_SHIFT 16 -#define NV40TCL_TEX_WRAP_R_MASK 0x000f0000 -#define NV40TCL_TEX_WRAP_R_REPEAT 0x00010000 -#define NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000 -#define NV40TCL_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000 -#define NV40TCL_TEX_WRAP_R_CLAMP_TO_BORDER 0x00040000 -#define NV40TCL_TEX_WRAP_R_CLAMP 0x00050000 -#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000 -#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000 -#define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP 0x00080000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_SHIFT 20 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_MASK 0x00f00000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000 -#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000 -#define NV40TCL_TEX_WRAP_RCOMP_SHIFT 28 -#define NV40TCL_TEX_WRAP_RCOMP_MASK 0xf0000000 -#define NV40TCL_TEX_WRAP_RCOMP_NEVER 0x00000000 -#define NV40TCL_TEX_WRAP_RCOMP_GREATER 0x10000000 -#define NV40TCL_TEX_WRAP_RCOMP_EQUAL 0x20000000 -#define NV40TCL_TEX_WRAP_RCOMP_GEQUAL 0x30000000 -#define NV40TCL_TEX_WRAP_RCOMP_LESS 0x40000000 -#define NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL 0x50000000 -#define NV40TCL_TEX_WRAP_RCOMP_LEQUAL 0x60000000 -#define NV40TCL_TEX_WRAP_RCOMP_ALWAYS 0x70000000 -#define NV40TCL_TEX_ENABLE(x) (0x00001a0c+((x)*32)) -#define NV40TCL_TEX_ENABLE__SIZE 0x00000010 -#define NV40TCL_TEX_ENABLE_ENABLE (1 << 31) -#define NV40TCL_TEX_ENABLE_MIPMAP_MIN_LOD_SHIFT 27 -#define NV40TCL_TEX_ENABLE_MIPMAP_MIN_LOD_MASK 0x38000000 -#define NV40TCL_TEX_ENABLE_MIPMAP_MAX_LOD_SHIFT 15 -#define NV40TCL_TEX_ENABLE_MIPMAP_MAX_LOD_MASK 0x00038000 -#define NV40TCL_TEX_ENABLE_ANISO_SHIFT 4 -#define NV40TCL_TEX_ENABLE_ANISO_MASK 0x000000f0 -#define NV40TCL_TEX_ENABLE_ANISO_NONE 0x00000000 -#define NV40TCL_TEX_ENABLE_ANISO_2X 0x00000010 -#define NV40TCL_TEX_ENABLE_ANISO_4X 0x00000020 -#define NV40TCL_TEX_ENABLE_ANISO_6X 0x00000030 -#define NV40TCL_TEX_ENABLE_ANISO_8X 0x00000040 -#define NV40TCL_TEX_ENABLE_ANISO_10X 0x00000050 -#define NV40TCL_TEX_ENABLE_ANISO_12X 0x00000060 -#define NV40TCL_TEX_ENABLE_ANISO_16X 0x00000070 -#define NV40TCL_TEX_SWIZZLE(x) (0x00001a10+((x)*32)) -#define NV40TCL_TEX_SWIZZLE__SIZE 0x00000010 -#define NV40TCL_TEX_SWIZZLE_S0_X_SHIFT 14 -#define NV40TCL_TEX_SWIZZLE_S0_X_MASK 0x0000c000 -#define NV40TCL_TEX_SWIZZLE_S0_X_ZERO 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S0_X_ONE 0x00004000 -#define NV40TCL_TEX_SWIZZLE_S0_X_S1 0x00008000 -#define NV40TCL_TEX_SWIZZLE_S0_Y_SHIFT 12 -#define NV40TCL_TEX_SWIZZLE_S0_Y_MASK 0x00003000 -#define NV40TCL_TEX_SWIZZLE_S0_Y_ZERO 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S0_Y_ONE 0x00001000 -#define NV40TCL_TEX_SWIZZLE_S0_Y_S1 0x00002000 -#define NV40TCL_TEX_SWIZZLE_S0_Z_SHIFT 10 -#define NV40TCL_TEX_SWIZZLE_S0_Z_MASK 0x00000c00 -#define NV40TCL_TEX_SWIZZLE_S0_Z_ZERO 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S0_Z_ONE 0x00000400 -#define NV40TCL_TEX_SWIZZLE_S0_Z_S1 0x00000800 -#define NV40TCL_TEX_SWIZZLE_S0_W_SHIFT 8 -#define NV40TCL_TEX_SWIZZLE_S0_W_MASK 0x00000300 -#define NV40TCL_TEX_SWIZZLE_S0_W_ZERO 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S0_W_ONE 0x00000100 -#define NV40TCL_TEX_SWIZZLE_S0_W_S1 0x00000200 -#define NV40TCL_TEX_SWIZZLE_S1_X_SHIFT 6 -#define NV40TCL_TEX_SWIZZLE_S1_X_MASK 0x000000c0 -#define NV40TCL_TEX_SWIZZLE_S1_X_W 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S1_X_Z 0x00000040 -#define NV40TCL_TEX_SWIZZLE_S1_X_Y 0x00000080 -#define NV40TCL_TEX_SWIZZLE_S1_X_X 0x000000c0 -#define NV40TCL_TEX_SWIZZLE_S1_Y_SHIFT 4 -#define NV40TCL_TEX_SWIZZLE_S1_Y_MASK 0x00000030 -#define NV40TCL_TEX_SWIZZLE_S1_Y_W 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S1_Y_Z 0x00000010 -#define NV40TCL_TEX_SWIZZLE_S1_Y_Y 0x00000020 -#define NV40TCL_TEX_SWIZZLE_S1_Y_X 0x00000030 -#define NV40TCL_TEX_SWIZZLE_S1_Z_SHIFT 2 -#define NV40TCL_TEX_SWIZZLE_S1_Z_MASK 0x0000000c -#define NV40TCL_TEX_SWIZZLE_S1_Z_W 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S1_Z_Z 0x00000004 -#define NV40TCL_TEX_SWIZZLE_S1_Z_Y 0x00000008 -#define NV40TCL_TEX_SWIZZLE_S1_Z_X 0x0000000c -#define NV40TCL_TEX_SWIZZLE_S1_W_SHIFT 0 -#define NV40TCL_TEX_SWIZZLE_S1_W_MASK 0x00000003 -#define NV40TCL_TEX_SWIZZLE_S1_W_W 0x00000000 -#define NV40TCL_TEX_SWIZZLE_S1_W_Z 0x00000001 -#define NV40TCL_TEX_SWIZZLE_S1_W_Y 0x00000002 -#define NV40TCL_TEX_SWIZZLE_S1_W_X 0x00000003 -#define NV40TCL_TEX_FILTER(x) (0x00001a14+((x)*32)) -#define NV40TCL_TEX_FILTER__SIZE 0x00000010 -#define NV40TCL_TEX_FILTER_SIGNED_ALPHA (1 << 31) -#define NV40TCL_TEX_FILTER_SIGNED_RED (1 << 30) -#define NV40TCL_TEX_FILTER_SIGNED_GREEN (1 << 29) -#define NV40TCL_TEX_FILTER_SIGNED_BLUE (1 << 28) -#define NV40TCL_TEX_FILTER_MIN_SHIFT 16 -#define NV40TCL_TEX_FILTER_MIN_MASK 0x000f0000 -#define NV40TCL_TEX_FILTER_MIN_NEAREST 0x00010000 -#define NV40TCL_TEX_FILTER_MIN_LINEAR 0x00020000 -#define NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x00030000 -#define NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x00040000 -#define NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x00050000 -#define NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x00060000 -#define NV40TCL_TEX_FILTER_MAG_SHIFT 24 -#define NV40TCL_TEX_FILTER_MAG_MASK 0x0f000000 -#define NV40TCL_TEX_FILTER_MAG_NEAREST 0x01000000 -#define NV40TCL_TEX_FILTER_MAG_LINEAR 0x02000000 -#define NV40TCL_TEX_SIZE0(x) (0x00001a18+((x)*32)) -#define NV40TCL_TEX_SIZE0__SIZE 0x00000010 -#define NV40TCL_TEX_SIZE0_H_SHIFT 0 -#define NV40TCL_TEX_SIZE0_H_MASK 0x0000ffff -#define NV40TCL_TEX_SIZE0_W_SHIFT 16 -#define NV40TCL_TEX_SIZE0_W_MASK 0xffff0000 -#define NV40TCL_TEX_BORDER_COLOR(x) (0x00001a1c+((x)*32)) -#define NV40TCL_TEX_BORDER_COLOR__SIZE 0x00000010 -#define NV40TCL_TEX_BORDER_COLOR_B_SHIFT 0 -#define NV40TCL_TEX_BORDER_COLOR_B_MASK 0x000000ff -#define NV40TCL_TEX_BORDER_COLOR_G_SHIFT 8 -#define NV40TCL_TEX_BORDER_COLOR_G_MASK 0x0000ff00 -#define NV40TCL_TEX_BORDER_COLOR_R_SHIFT 16 -#define NV40TCL_TEX_BORDER_COLOR_R_MASK 0x00ff0000 -#define NV40TCL_TEX_BORDER_COLOR_A_SHIFT 24 -#define NV40TCL_TEX_BORDER_COLOR_A_MASK 0xff000000 -#define NV40TCL_VTX_ATTR_4F_X(x) (0x00001c00+((x)*16)) -#define NV40TCL_VTX_ATTR_4F_X__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4F_Y(x) (0x00001c04+((x)*16)) -#define NV40TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4F_Z(x) (0x00001c08+((x)*16)) -#define NV40TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 -#define NV40TCL_VTX_ATTR_4F_W(x) (0x00001c0c+((x)*16)) -#define NV40TCL_VTX_ATTR_4F_W__SIZE 0x00000010 -#define NV40TCL_FP_CONTROL 0x00001d60 -#define NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT 24 -#define NV40TCL_FP_CONTROL_TEMP_COUNT_MASK 0xff000000 -#define NV40TCL_FP_CONTROL_KIL (1 << 7) -#define NV40TCL_MULTISAMPLE_CONTROL 0x00001d7c -#define NV40TCL_CLEAR_VALUE_DEPTH 0x00001d8c -#define NV40TCL_CLEAR_VALUE_COLOR 0x00001d90 -#define NV40TCL_CLEAR_VALUE_COLOR_B_SHIFT 0 -#define NV40TCL_CLEAR_VALUE_COLOR_B_MASK 0x000000ff -#define NV40TCL_CLEAR_VALUE_COLOR_G_SHIFT 8 -#define NV40TCL_CLEAR_VALUE_COLOR_G_MASK 0x0000ff00 -#define NV40TCL_CLEAR_VALUE_COLOR_R_SHIFT 16 -#define NV40TCL_CLEAR_VALUE_COLOR_R_MASK 0x00ff0000 -#define NV40TCL_CLEAR_VALUE_COLOR_A_SHIFT 24 -#define NV40TCL_CLEAR_VALUE_COLOR_A_MASK 0xff000000 -#define NV40TCL_CLEAR_BUFFERS 0x00001d94 -#define NV40TCL_CLEAR_BUFFERS_COLOR_A (1 << 7) -#define NV40TCL_CLEAR_BUFFERS_COLOR_B (1 << 6) -#define NV40TCL_CLEAR_BUFFERS_COLOR_G (1 << 5) -#define NV40TCL_CLEAR_BUFFERS_COLOR_R (1 << 4) -#define NV40TCL_CLEAR_BUFFERS_STENCIL (1 << 1) -#define NV40TCL_CLEAR_BUFFERS_DEPTH (1 << 0) -#define NV40TCL_LINE_STIPPLE_ENABLE 0x00001db4 -#define NV40TCL_LINE_STIPPLE_PATTERN 0x00001db8 -#define NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_SHIFT 0 -#define NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff -#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16 -#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000 -#define NV40TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4)) -#define NV40TCL_VTX_ATTR_1F__SIZE 0x00000010 -#define NV40TCL_VP_UPLOAD_FROM_ID 0x00001e9c -#define NV40TCL_VP_START_FROM_ID 0x00001ea0 -#define NV40TCL_POINT_SIZE 0x00001ee0 -#define NV40TCL_POINT_SPRITE 0x00001ee8 -#define NV40TCL_POINT_SPRITE_ENABLE (1 << 0) -#define NV40TCL_POINT_SPRITE_R_MODE_SHIFT 1 -#define NV40TCL_POINT_SPRITE_R_MODE_MASK 0x00000006 -#define NV40TCL_POINT_SPRITE_R_MODE_ZERO 0x00000000 -#define NV40TCL_POINT_SPRITE_R_MODE_R 0x00000002 -#define NV40TCL_POINT_SPRITE_R_MODE_S 0x00000004 -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_0 (1 << 8) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_1 (1 << 9) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_2 (1 << 10) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_3 (1 << 11) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_4 (1 << 12) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_5 (1 << 13) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_6 (1 << 14) -#define NV40TCL_POINT_SPRITE_COORD_REPLACE_7 (1 << 15) -#define NV40TCL_VP_UPLOAD_CONST_ID 0x00001efc -#define NV40TCL_VP_UPLOAD_CONST_X(x) (0x00001f00+((x)*16)) -#define NV40TCL_VP_UPLOAD_CONST_X__SIZE 0x00000004 -#define NV40TCL_VP_UPLOAD_CONST_Y(x) (0x00001f04+((x)*16)) -#define NV40TCL_VP_UPLOAD_CONST_Y__SIZE 0x00000004 -#define NV40TCL_VP_UPLOAD_CONST_Z(x) (0x00001f08+((x)*16)) -#define NV40TCL_VP_UPLOAD_CONST_Z__SIZE 0x00000004 -#define NV40TCL_VP_UPLOAD_CONST_W(x) (0x00001f0c+((x)*16)) -#define NV40TCL_VP_UPLOAD_CONST_W__SIZE 0x00000004 -#define NV40TCL_TEX_CACHE_CTL 0x00001fd8 -#define NV40TCL_VP_ATTRIB_EN 0x00001ff0 -#define NV40TCL_VP_RESULT_EN 0x00001ff4 - - -#define NV44TCL 0x00004497 - - - -#define NV50_2D 0x0000502d - -#define NV50_2D_NOP 0x00000100 -#define NV50_2D_NOTIFY 0x00000104 -#define NV50_2D_SERIALIZE 0x00000110 -#define NV50_2D_DMA_NOTIFY 0x00000180 -#define NV50_2D_DMA_DST 0x00000184 -#define NV50_2D_DMA_SRC 0x00000188 -#define NV50_2D_DMA_COND 0x0000018c -#define NV50_2D_DST_FORMAT 0x00000200 -#define NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NV50_2D_DST_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NV50_2D_DST_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NV50_2D_DST_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NV50_2D_DST_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NV50_2D_DST_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NV50_2D_DST_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NV50_2D_DST_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NV50_2D_DST_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NV50_2D_DST_FORMAT_R32G32_FLOAT 0x000000cb -#define NV50_2D_DST_FORMAT_R32G32_SINT 0x000000cc -#define NV50_2D_DST_FORMAT_R32G32_UINT 0x000000cd -#define NV50_2D_DST_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NV50_2D_DST_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NV50_2D_DST_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NV50_2D_DST_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NV50_2D_DST_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NV50_2D_DST_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NV50_2D_DST_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NV50_2D_DST_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NV50_2D_DST_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NV50_2D_DST_FORMAT_R16G16_UNORM 0x000000da -#define NV50_2D_DST_FORMAT_R16G16_SNORM 0x000000db -#define NV50_2D_DST_FORMAT_R16G16_SINT 0x000000dc -#define NV50_2D_DST_FORMAT_R16G16_UINT 0x000000dd -#define NV50_2D_DST_FORMAT_R16G16_FLOAT 0x000000de -#define NV50_2D_DST_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NV50_2D_DST_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NV50_2D_DST_FORMAT_R32_FLOAT 0x000000e5 -#define NV50_2D_DST_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NV50_2D_DST_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NV50_2D_DST_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NV50_2D_DST_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NV50_2D_DST_FORMAT_R8G8_UNORM 0x000000ea -#define NV50_2D_DST_FORMAT_R8G8_SNORM 0x000000eb -#define NV50_2D_DST_FORMAT_R8G8_SINT 0x000000ec -#define NV50_2D_DST_FORMAT_R8G8_UINT 0x000000ed -#define NV50_2D_DST_FORMAT_R16_UNORM 0x000000ee -#define NV50_2D_DST_FORMAT_R16_SNORM 0x000000ef -#define NV50_2D_DST_FORMAT_R16_SINT 0x000000f0 -#define NV50_2D_DST_FORMAT_R16_UINT 0x000000f1 -#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000f2 -#define NV50_2D_DST_FORMAT_R8_UNORM 0x000000f3 -#define NV50_2D_DST_FORMAT_R8_SNORM 0x000000f4 -#define NV50_2D_DST_FORMAT_R8_SINT 0x000000f5 -#define NV50_2D_DST_FORMAT_R8_UINT 0x000000f6 -#define NV50_2D_DST_FORMAT_A8_UNORM 0x000000f7 -#define NV50_2D_DST_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NV50_2D_DST_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NV50_2D_DST_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NV50_2D_DST_LINEAR 0x00000204 -#define NV50_2D_DST_TILE_MODE 0x00000208 -#define NV50_2D_DST_DEPTH 0x0000020c -#define NV50_2D_DST_LAYER 0x00000210 -#define NV50_2D_DST_PITCH 0x00000214 -#define NV50_2D_DST_WIDTH 0x00000218 -#define NV50_2D_DST_HEIGHT 0x0000021c -#define NV50_2D_DST_ADDRESS_HIGH 0x00000220 -#define NV50_2D_DST_ADDRESS_LOW 0x00000224 -#define NV50_2D_SRC_FORMAT 0x00000230 -#define NV50_2D_SRC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NV50_2D_SRC_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NV50_2D_SRC_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NV50_2D_SRC_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NV50_2D_SRC_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NV50_2D_SRC_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NV50_2D_SRC_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NV50_2D_SRC_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NV50_2D_SRC_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NV50_2D_SRC_FORMAT_R32G32_FLOAT 0x000000cb -#define NV50_2D_SRC_FORMAT_R32G32_SINT 0x000000cc -#define NV50_2D_SRC_FORMAT_R32G32_UINT 0x000000cd -#define NV50_2D_SRC_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NV50_2D_SRC_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NV50_2D_SRC_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NV50_2D_SRC_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NV50_2D_SRC_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NV50_2D_SRC_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NV50_2D_SRC_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NV50_2D_SRC_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NV50_2D_SRC_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NV50_2D_SRC_FORMAT_R16G16_UNORM 0x000000da -#define NV50_2D_SRC_FORMAT_R16G16_SNORM 0x000000db -#define NV50_2D_SRC_FORMAT_R16G16_SINT 0x000000dc -#define NV50_2D_SRC_FORMAT_R16G16_UINT 0x000000dd -#define NV50_2D_SRC_FORMAT_R16G16_FLOAT 0x000000de -#define NV50_2D_SRC_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NV50_2D_SRC_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NV50_2D_SRC_FORMAT_R32_FLOAT 0x000000e5 -#define NV50_2D_SRC_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NV50_2D_SRC_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NV50_2D_SRC_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NV50_2D_SRC_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NV50_2D_SRC_FORMAT_R8G8_UNORM 0x000000ea -#define NV50_2D_SRC_FORMAT_R8G8_SNORM 0x000000eb -#define NV50_2D_SRC_FORMAT_R8G8_SINT 0x000000ec -#define NV50_2D_SRC_FORMAT_R8G8_UINT 0x000000ed -#define NV50_2D_SRC_FORMAT_R16_UNORM 0x000000ee -#define NV50_2D_SRC_FORMAT_R16_SNORM 0x000000ef -#define NV50_2D_SRC_FORMAT_R16_SINT 0x000000f0 -#define NV50_2D_SRC_FORMAT_R16_UINT 0x000000f1 -#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000f2 -#define NV50_2D_SRC_FORMAT_R8_UNORM 0x000000f3 -#define NV50_2D_SRC_FORMAT_R8_SNORM 0x000000f4 -#define NV50_2D_SRC_FORMAT_R8_SINT 0x000000f5 -#define NV50_2D_SRC_FORMAT_R8_UINT 0x000000f6 -#define NV50_2D_SRC_FORMAT_A8_UNORM 0x000000f7 -#define NV50_2D_SRC_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NV50_2D_SRC_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NV50_2D_SRC_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NV50_2D_SRC_LINEAR 0x00000234 -#define NV50_2D_SRC_TILE_MODE 0x00000238 -#define NV50_2D_SRC_DEPTH 0x0000023c -#define NV50_2D_SRC_LAYER 0x00000240 -#define NV50_2D_SRC_PITCH 0x00000244 -#define NV50_2D_SRC_WIDTH 0x00000248 -#define NV50_2D_SRC_HEIGHT 0x0000024c -#define NV50_2D_SRC_ADDRESS_HIGH 0x00000250 -#define NV50_2D_SRC_ADDRESS_LOW 0x00000254 -#define NV50_2D_COND_ADDRESS_HIGH 0x00000264 -#define NV50_2D_COND_ADDRESS_LOW 0x00000268 -#define NV50_2D_COND_MODE 0x0000026c -#define NV50_2D_COND_MODE_NEVER 0x00000000 -#define NV50_2D_COND_MODE_ALWAYS 0x00000001 -#define NV50_2D_COND_MODE_RES 0x00000002 -#define NV50_2D_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 -#define NV50_2D_COND_MODE_RES_OR_ID 0x00000004 -#define NV50_2D_CLIP_X 0x00000280 -#define NV50_2D_CLIP_Y 0x00000284 -#define NV50_2D_CLIP_W 0x00000288 -#define NV50_2D_CLIP_H 0x0000028c -#define NV50_2D_CLIP_ENABLE 0x00000290 -#define NV50_2D_COLOR_KEY_FORMAT 0x00000294 -#define NV50_2D_COLOR_KEY_FORMAT_16BPP 0x00000000 -#define NV50_2D_COLOR_KEY_FORMAT_15BPP 0x00000001 -#define NV50_2D_COLOR_KEY_FORMAT_24BPP 0x00000002 -#define NV50_2D_COLOR_KEY_FORMAT_30BPP 0x00000003 -#define NV50_2D_COLOR_KEY_FORMAT_8BPP 0x00000004 -#define NV50_2D_COLOR_KEY_FORMAT_16BPP2 0x00000005 -#define NV50_2D_COLOR_KEY_FORMAT_32BPP 0x00000006 -#define NV50_2D_COLOR_KEY 0x00000298 -#define NV50_2D_COLOR_KEY_ENABLE 0x0000029c -#define NV50_2D_ROP 0x000002a0 -#define NV50_2D_OPERATION 0x000002ac -#define NV50_2D_OPERATION_SRCCOPY_AND 0x00000000 -#define NV50_2D_OPERATION_ROP_AND 0x00000001 -#define NV50_2D_OPERATION_BLEND_AND 0x00000002 -#define NV50_2D_OPERATION_SRCCOPY 0x00000003 -#define NV50_2D_OPERATION_SRCCOPY_PREMULT 0x00000004 -#define NV50_2D_OPERATION_BLEND_PREMULT 0x00000005 -#define NV50_2D_PATTERN_FORMAT 0x000002e8 -#define NV50_2D_PATTERN_FORMAT_16BPP 0x00000000 -#define NV50_2D_PATTERN_FORMAT_15BPP 0x00000001 -#define NV50_2D_PATTERN_FORMAT_32BPP 0x00000002 -#define NV50_2D_PATTERN_FORMAT_8BPP 0x00000003 -#define NV50_2D_PATTERN_COLOR(x) (0x000002f0+((x)*4)) -#define NV50_2D_PATTERN_COLOR__SIZE 0x00000002 -#define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4)) -#define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002 -#define NV50_2D_DRAW_SHAPE 0x00000580 -#define NV50_2D_DRAW_SHAPE_POINTS 0x00000000 -#define NV50_2D_DRAW_SHAPE_LINES 0x00000001 -#define NV50_2D_DRAW_SHAPE_LINE_STRIP 0x00000002 -#define NV50_2D_DRAW_SHAPE_TRIANGLES 0x00000003 -#define NV50_2D_DRAW_SHAPE_RECTANGLES 0x00000004 -#define NV50_2D_DRAW_COLOR_FORMAT 0x00000584 -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_FLOAT 0x000000cb -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_SINT 0x000000cc -#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_UINT 0x000000cd -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UNORM 0x000000da -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SNORM 0x000000db -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SINT 0x000000dc -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UINT 0x000000dd -#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_FLOAT 0x000000de -#define NV50_2D_DRAW_COLOR_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NV50_2D_DRAW_COLOR_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NV50_2D_DRAW_COLOR_FORMAT_R32_FLOAT 0x000000e5 -#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NV50_2D_DRAW_COLOR_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NV50_2D_DRAW_COLOR_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UNORM 0x000000ea -#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SNORM 0x000000eb -#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SINT 0x000000ec -#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UINT 0x000000ed -#define NV50_2D_DRAW_COLOR_FORMAT_R16_UNORM 0x000000ee -#define NV50_2D_DRAW_COLOR_FORMAT_R16_SNORM 0x000000ef -#define NV50_2D_DRAW_COLOR_FORMAT_R16_SINT 0x000000f0 -#define NV50_2D_DRAW_COLOR_FORMAT_R16_UINT 0x000000f1 -#define NV50_2D_DRAW_COLOR_FORMAT_R16_FLOAT 0x000000f2 -#define NV50_2D_DRAW_COLOR_FORMAT_R8_UNORM 0x000000f3 -#define NV50_2D_DRAW_COLOR_FORMAT_R8_SNORM 0x000000f4 -#define NV50_2D_DRAW_COLOR_FORMAT_R8_SINT 0x000000f5 -#define NV50_2D_DRAW_COLOR_FORMAT_R8_UINT 0x000000f6 -#define NV50_2D_DRAW_COLOR_FORMAT_A8_UNORM 0x000000f7 -#define NV50_2D_DRAW_COLOR_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NV50_2D_DRAW_COLOR 0x00000588 -#define NV50_2D_DRAW_POINT16 0x000005e0 -#define NV50_2D_DRAW_POINT16_X_SHIFT 0 -#define NV50_2D_DRAW_POINT16_X_MASK 0x0000ffff -#define NV50_2D_DRAW_POINT16_Y_SHIFT 16 -#define NV50_2D_DRAW_POINT16_Y_MASK 0xffff0000 -#define NV50_2D_DRAW_POINT32_X(x) (0x00000600+((x)*8)) -#define NV50_2D_DRAW_POINT32_X__SIZE 0x00000040 -#define NV50_2D_DRAW_POINT32_Y(x) (0x00000604+((x)*8)) -#define NV50_2D_DRAW_POINT32_Y__SIZE 0x00000040 -#define NV50_2D_SIFC_BITMAP_ENABLE 0x00000800 -#define NV50_2D_SIFC_FORMAT 0x00000804 -#define NV50_2D_SIFC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NV50_2D_SIFC_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NV50_2D_SIFC_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NV50_2D_SIFC_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NV50_2D_SIFC_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NV50_2D_SIFC_FORMAT_R32G32_FLOAT 0x000000cb -#define NV50_2D_SIFC_FORMAT_R32G32_SINT 0x000000cc -#define NV50_2D_SIFC_FORMAT_R32G32_UINT 0x000000cd -#define NV50_2D_SIFC_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NV50_2D_SIFC_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NV50_2D_SIFC_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NV50_2D_SIFC_FORMAT_R16G16_UNORM 0x000000da -#define NV50_2D_SIFC_FORMAT_R16G16_SNORM 0x000000db -#define NV50_2D_SIFC_FORMAT_R16G16_SINT 0x000000dc -#define NV50_2D_SIFC_FORMAT_R16G16_UINT 0x000000dd -#define NV50_2D_SIFC_FORMAT_R16G16_FLOAT 0x000000de -#define NV50_2D_SIFC_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NV50_2D_SIFC_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NV50_2D_SIFC_FORMAT_R32_FLOAT 0x000000e5 -#define NV50_2D_SIFC_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NV50_2D_SIFC_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NV50_2D_SIFC_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NV50_2D_SIFC_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NV50_2D_SIFC_FORMAT_R8G8_UNORM 0x000000ea -#define NV50_2D_SIFC_FORMAT_R8G8_SNORM 0x000000eb -#define NV50_2D_SIFC_FORMAT_R8G8_SINT 0x000000ec -#define NV50_2D_SIFC_FORMAT_R8G8_UINT 0x000000ed -#define NV50_2D_SIFC_FORMAT_R16_UNORM 0x000000ee -#define NV50_2D_SIFC_FORMAT_R16_SNORM 0x000000ef -#define NV50_2D_SIFC_FORMAT_R16_SINT 0x000000f0 -#define NV50_2D_SIFC_FORMAT_R16_UINT 0x000000f1 -#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000f2 -#define NV50_2D_SIFC_FORMAT_R8_UNORM 0x000000f3 -#define NV50_2D_SIFC_FORMAT_R8_SNORM 0x000000f4 -#define NV50_2D_SIFC_FORMAT_R8_SINT 0x000000f5 -#define NV50_2D_SIFC_FORMAT_R8_UINT 0x000000f6 -#define NV50_2D_SIFC_FORMAT_A8_UNORM 0x000000f7 -#define NV50_2D_SIFC_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NV50_2D_SIFC_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NV50_2D_SIFC_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NV50_2D_SIFC_BITMAP_UNK808 0x00000808 -#define NV50_2D_SIFC_BITMAP_LSB_FIRST 0x0000080c -#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE 0x00000810 -#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_PACKED 0x00000000 -#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_BYTE 0x00000001 -#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_WORD 0x00000002 -#define NV50_2D_SIFC_BITMAP_COLOR_BIT0 0x00000814 -#define NV50_2D_SIFC_BITMAP_COLOR_BIT1 0x00000818 -#define NV50_2D_SIFC_BITMAP_WRITE_BIT0_ENABLE 0x0000081c -#define NV50_2D_SIFC_WIDTH 0x00000838 -#define NV50_2D_SIFC_HEIGHT 0x0000083c -#define NV50_2D_SIFC_DX_DU_FRACT 0x00000840 -#define NV50_2D_SIFC_DX_DU_INT 0x00000844 -#define NV50_2D_SIFC_DY_DV_FRACT 0x00000848 -#define NV50_2D_SIFC_DY_DV_INT 0x0000084c -#define NV50_2D_SIFC_DST_X_FRACT 0x00000850 -#define NV50_2D_SIFC_DST_X_INT 0x00000854 -#define NV50_2D_SIFC_DST_Y_FRACT 0x00000858 -#define NV50_2D_SIFC_DST_Y_INT 0x0000085c -#define NV50_2D_SIFC_DATA 0x00000860 -#define NV50_2D_BLIT_DST_X 0x000008b0 -#define NV50_2D_BLIT_DST_Y 0x000008b4 -#define NV50_2D_BLIT_DST_W 0x000008b8 -#define NV50_2D_BLIT_DST_H 0x000008bc -#define NV50_2D_BLIT_DU_DX_FRACT 0x000008c0 -#define NV50_2D_BLIT_DU_DX_INT 0x000008c4 -#define NV50_2D_BLIT_DV_DY_FRACT 0x000008c8 -#define NV50_2D_BLIT_DV_DY_INT 0x000008cc -#define NV50_2D_BLIT_SRC_X_FRACT 0x000008d0 -#define NV50_2D_BLIT_SRC_X_INT 0x000008d4 -#define NV50_2D_BLIT_SRC_Y_FRACT 0x000008d8 -#define NV50_2D_BLIT_SRC_Y_INT 0x000008dc - - -#define NV50TCL 0x00005097 - -#define NV50TCL_NOP 0x00000100 -#define NV50TCL_NOTIFY 0x00000104 -#define NV50TCL_SERIALIZE 0x00000110 -#define NV50TCL_DMA_NOTIFY 0x00000180 -#define NV50TCL_DMA_ZETA 0x00000184 -#define NV50TCL_DMA_QUERY 0x00000188 -#define NV50TCL_DMA_VTXBUF0 0x0000018c -#define NV50TCL_DMA_LOCAL 0x00000190 -#define NV50TCL_DMA_STACK 0x00000194 -#define NV50TCL_DMA_CODE_CB 0x00000198 -#define NV50TCL_DMA_TSC 0x0000019c -#define NV50TCL_DMA_TIC 0x000001a0 -#define NV50TCL_DMA_TEXTURE 0x000001a4 -#define NV50TCL_DMA_STRMOUT 0x000001a8 -#define NV50TCL_DMA_CLIPID 0x000001ac -#define NV50TCL_DMA_COLOR(x) (0x000001c0+((x)*4)) -#define NV50TCL_DMA_COLOR__SIZE 0x00000008 -#define NV50TCL_RT_ADDRESS_HIGH(x) (0x00000200+((x)*32)) -#define NV50TCL_RT_ADDRESS_HIGH__SIZE 0x00000008 -#define NV50TCL_RT_ADDRESS_LOW(x) (0x00000204+((x)*32)) -#define NV50TCL_RT_ADDRESS_LOW__SIZE 0x00000008 -#define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32)) -#define NV50TCL_RT_FORMAT__SIZE 0x00000008 -#define NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NV50TCL_RT_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NV50TCL_RT_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NV50TCL_RT_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NV50TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NV50TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NV50TCL_RT_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NV50TCL_RT_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NV50TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NV50TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb -#define NV50TCL_RT_FORMAT_R32G32_SINT 0x000000cc -#define NV50TCL_RT_FORMAT_R32G32_UINT 0x000000cd -#define NV50TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NV50TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NV50TCL_RT_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NV50TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NV50TCL_RT_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NV50TCL_RT_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NV50TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NV50TCL_RT_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NV50TCL_RT_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NV50TCL_RT_FORMAT_R16G16_UNORM 0x000000da -#define NV50TCL_RT_FORMAT_R16G16_SNORM 0x000000db -#define NV50TCL_RT_FORMAT_R16G16_SINT 0x000000dc -#define NV50TCL_RT_FORMAT_R16G16_UINT 0x000000dd -#define NV50TCL_RT_FORMAT_R16G16_FLOAT 0x000000de -#define NV50TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NV50TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NV50TCL_RT_FORMAT_R32_FLOAT 0x000000e5 -#define NV50TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NV50TCL_RT_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NV50TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NV50TCL_RT_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NV50TCL_RT_FORMAT_R8G8_UNORM 0x000000ea -#define NV50TCL_RT_FORMAT_R8G8_SNORM 0x000000eb -#define NV50TCL_RT_FORMAT_R8G8_SINT 0x000000ec -#define NV50TCL_RT_FORMAT_R8G8_UINT 0x000000ed -#define NV50TCL_RT_FORMAT_R16_UNORM 0x000000ee -#define NV50TCL_RT_FORMAT_R16_SNORM 0x000000ef -#define NV50TCL_RT_FORMAT_R16_SINT 0x000000f0 -#define NV50TCL_RT_FORMAT_R16_UINT 0x000000f1 -#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000f2 -#define NV50TCL_RT_FORMAT_R8_UNORM 0x000000f3 -#define NV50TCL_RT_FORMAT_R8_SNORM 0x000000f4 -#define NV50TCL_RT_FORMAT_R8_SINT 0x000000f5 -#define NV50TCL_RT_FORMAT_R8_UINT 0x000000f6 -#define NV50TCL_RT_FORMAT_A8_UNORM 0x000000f7 -#define NV50TCL_RT_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NV50TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NV50TCL_RT_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NV50TCL_RT_TILE_MODE(x) (0x0000020c+((x)*32)) -#define NV50TCL_RT_TILE_MODE__SIZE 0x00000008 -#define NV50TCL_RT_LAYER_STRIDE(x) (0x00000210+((x)*32)) -#define NV50TCL_RT_LAYER_STRIDE__SIZE 0x00000008 -#define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4)) -#define NV50TCL_VTX_ATTR_1F__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_2H(x) (0x00000340+((x)*4)) -#define NV50TCL_VTX_ATTR_2H__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_2H_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_2H_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_2H_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_2H_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_2F_X(x) (0x00000380+((x)*8)) -#define NV50TCL_VTX_ATTR_2F_X__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_2F_Y(x) (0x00000384+((x)*8)) -#define NV50TCL_VTX_ATTR_2F_Y__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_3F_X(x) (0x00000400+((x)*16)) -#define NV50TCL_VTX_ATTR_3F_X__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_3F_Y(x) (0x00000404+((x)*16)) -#define NV50TCL_VTX_ATTR_3F_Y__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_3F_Z(x) (0x00000408+((x)*16)) -#define NV50TCL_VTX_ATTR_3F_Z__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4F_X(x) (0x00000500+((x)*16)) -#define NV50TCL_VTX_ATTR_4F_X__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4F_Y(x) (0x00000504+((x)*16)) -#define NV50TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4F_Z(x) (0x00000508+((x)*16)) -#define NV50TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4F_W(x) (0x0000050c+((x)*16)) -#define NV50TCL_VTX_ATTR_4F_W__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4H_0(x) (0x00000600+((x)*8)) -#define NV50TCL_VTX_ATTR_4H_0__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4H_0_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4H_0_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4H_0_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_4H_0_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4H_1(x) (0x00000604+((x)*8)) -#define NV50TCL_VTX_ATTR_4H_1__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4H_1_Z_SHIFT 0 -#define NV50TCL_VTX_ATTR_4H_1_Z_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4H_1_W_SHIFT 16 -#define NV50TCL_VTX_ATTR_4H_1_W_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_2I(x) (0x00000680+((x)*4)) -#define NV50TCL_VTX_ATTR_2I__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_2I_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_2I_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_2I_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_2I_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_2NI(x) (0x000006c0+((x)*4)) -#define NV50TCL_VTX_ATTR_2NI__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_2NI_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_2NI_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_2NI_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_2NI_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4I_0(x) (0x00000700+((x)*8)) -#define NV50TCL_VTX_ATTR_4I_0__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4I_0_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4I_0_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4I_0_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_4I_0_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4I_1(x) (0x00000704+((x)*8)) -#define NV50TCL_VTX_ATTR_4I_1__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4I_1_Z_SHIFT 0 -#define NV50TCL_VTX_ATTR_4I_1_Z_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4I_1_W_SHIFT 16 -#define NV50TCL_VTX_ATTR_4I_1_W_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4NI_0(x) (0x00000780+((x)*8)) -#define NV50TCL_VTX_ATTR_4NI_0__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4NI_0_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4NI_0_X_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4NI_0_Y_SHIFT 16 -#define NV50TCL_VTX_ATTR_4NI_0_Y_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4NI_1(x) (0x00000784+((x)*8)) -#define NV50TCL_VTX_ATTR_4NI_1__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4NI_1_Z_SHIFT 0 -#define NV50TCL_VTX_ATTR_4NI_1_Z_MASK 0x0000ffff -#define NV50TCL_VTX_ATTR_4NI_1_W_SHIFT 16 -#define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000 -#define NV50TCL_VTX_ATTR_4UB(x) (0x00000800+((x)*4)) -#define NV50TCL_VTX_ATTR_4UB__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4UB_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4UB_X_MASK 0x000000ff -#define NV50TCL_VTX_ATTR_4UB_Y_SHIFT 8 -#define NV50TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00 -#define NV50TCL_VTX_ATTR_4UB_Z_SHIFT 16 -#define NV50TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000 -#define NV50TCL_VTX_ATTR_4UB_W_SHIFT 24 -#define NV50TCL_VTX_ATTR_4UB_W_MASK 0xff000000 -#define NV50TCL_VTX_ATTR_4B(x) (0x00000840+((x)*4)) -#define NV50TCL_VTX_ATTR_4B__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4B_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4B_X_MASK 0x000000ff -#define NV50TCL_VTX_ATTR_4B_Y_SHIFT 8 -#define NV50TCL_VTX_ATTR_4B_Y_MASK 0x0000ff00 -#define NV50TCL_VTX_ATTR_4B_Z_SHIFT 16 -#define NV50TCL_VTX_ATTR_4B_Z_MASK 0x00ff0000 -#define NV50TCL_VTX_ATTR_4B_W_SHIFT 24 -#define NV50TCL_VTX_ATTR_4B_W_MASK 0xff000000 -#define NV50TCL_VTX_ATTR_4NUB(x) (0x00000880+((x)*4)) -#define NV50TCL_VTX_ATTR_4NUB__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4NUB_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4NUB_X_MASK 0x000000ff -#define NV50TCL_VTX_ATTR_4NUB_Y_SHIFT 8 -#define NV50TCL_VTX_ATTR_4NUB_Y_MASK 0x0000ff00 -#define NV50TCL_VTX_ATTR_4NUB_Z_SHIFT 16 -#define NV50TCL_VTX_ATTR_4NUB_Z_MASK 0x00ff0000 -#define NV50TCL_VTX_ATTR_4NUB_W_SHIFT 24 -#define NV50TCL_VTX_ATTR_4NUB_W_MASK 0xff000000 -#define NV50TCL_VTX_ATTR_4NB(x) (0x000008c0+((x)*4)) -#define NV50TCL_VTX_ATTR_4NB__SIZE 0x00000010 -#define NV50TCL_VTX_ATTR_4NB_X_SHIFT 0 -#define NV50TCL_VTX_ATTR_4NB_X_MASK 0x000000ff -#define NV50TCL_VTX_ATTR_4NB_Y_SHIFT 8 -#define NV50TCL_VTX_ATTR_4NB_Y_MASK 0x0000ff00 -#define NV50TCL_VTX_ATTR_4NB_Z_SHIFT 16 -#define NV50TCL_VTX_ATTR_4NB_Z_MASK 0x00ff0000 -#define NV50TCL_VTX_ATTR_4NB_W_SHIFT 24 -#define NV50TCL_VTX_ATTR_4NB_W_MASK 0xff000000 -#define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16)) -#define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010 -#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT 0 -#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x00000fff -#define NV50TCL_VERTEX_ARRAY_FORMAT_ENABLE (1 << 29) -#define NV50TCL_VERTEX_ARRAY_START_HIGH(x) (0x00000904+((x)*16)) -#define NV50TCL_VERTEX_ARRAY_START_HIGH__SIZE 0x00000010 -#define NV50TCL_VERTEX_ARRAY_START_LOW(x) (0x00000908+((x)*16)) -#define NV50TCL_VERTEX_ARRAY_START_LOW__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_SCALE_X(x) (0x00000a00+((x)*32)) -#define NV50TCL_VIEWPORT_SCALE_X__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_SCALE_Y(x) (0x00000a04+((x)*32)) -#define NV50TCL_VIEWPORT_SCALE_Y__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_SCALE_Z(x) (0x00000a08+((x)*32)) -#define NV50TCL_VIEWPORT_SCALE_Z__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_TRANSLATE_X(x) (0x00000a0c+((x)*32)) -#define NV50TCL_VIEWPORT_TRANSLATE_X__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_TRANSLATE_Y(x) (0x00000a10+((x)*32)) -#define NV50TCL_VIEWPORT_TRANSLATE_Y__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_TRANSLATE_Z(x) (0x00000a14+((x)*32)) -#define NV50TCL_VIEWPORT_TRANSLATE_Z__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_HORIZ(x) (0x00000c00+((x)*16)) -#define NV50TCL_VIEWPORT_HORIZ__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0 -#define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff -#define NV50TCL_VIEWPORT_HORIZ_W_SHIFT 16 -#define NV50TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000 -#define NV50TCL_VIEWPORT_VERT(x) (0x00000c04+((x)*16)) -#define NV50TCL_VIEWPORT_VERT__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_VERT_Y_SHIFT 0 -#define NV50TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff -#define NV50TCL_VIEWPORT_VERT_H_SHIFT 16 -#define NV50TCL_VIEWPORT_VERT_H_MASK 0xffff0000 -#define NV50TCL_DEPTH_RANGE_NEAR(x) (0x00000c08+((x)*16)) -#define NV50TCL_DEPTH_RANGE_NEAR__SIZE 0x00000010 -#define NV50TCL_DEPTH_RANGE_FAR(x) (0x00000c0c+((x)*16)) -#define NV50TCL_DEPTH_RANGE_FAR__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_CLIP_HORIZ(x) (0x00000d00+((x)*8)) -#define NV50TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NV50TCL_VIEWPORT_CLIP_HORIZ_MIN_SHIFT 0 -#define NV50TCL_VIEWPORT_CLIP_HORIZ_MIN_MASK 0x0000ffff -#define NV50TCL_VIEWPORT_CLIP_HORIZ_MAX_SHIFT 16 -#define NV50TCL_VIEWPORT_CLIP_HORIZ_MAX_MASK 0xffff0000 -#define NV50TCL_VIEWPORT_CLIP_VERT(x) (0x00000d04+((x)*8)) -#define NV50TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NV50TCL_VIEWPORT_CLIP_VERT_MIN_SHIFT 0 -#define NV50TCL_VIEWPORT_CLIP_VERT_MIN_MASK 0x0000ffff -#define NV50TCL_VIEWPORT_CLIP_VERT_MAX_SHIFT 16 -#define NV50TCL_VIEWPORT_CLIP_VERT_MAX_MASK 0xffff0000 -#define NV50TCL_CLIPID_REGION_HORIZ(x) (0x00000d40+((x)*8)) -#define NV50TCL_CLIPID_REGION_HORIZ__SIZE 0x00000004 -#define NV50TCL_CLIPID_REGION_VERT(x) (0x00000d44+((x)*8)) -#define NV50TCL_CLIPID_REGION_VERT__SIZE 0x00000004 -#define NV50TCL_VERTEX_BUFFER_FIRST 0x00000d74 -#define NV50TCL_VERTEX_BUFFER_COUNT 0x00000d78 -#define NV50TCL_CLEAR_COLOR(x) (0x00000d80+((x)*4)) -#define NV50TCL_CLEAR_COLOR__SIZE 0x00000004 -#define NV50TCL_CLEAR_DEPTH 0x00000d90 -#define NV50TCL_STACK_ADDRESS_HIGH 0x00000d94 -#define NV50TCL_STACK_ADDRESS_LOW 0x00000d98 -#define NV50TCL_STACK_SIZE_LOG 0x00000d9c -#define NV50TCL_CLEAR_STENCIL 0x00000da0 -#define NV50TCL_STRMOUT_PRIMITIVE_COUNT 0x00000da8 -#define NV50TCL_POLYGON_MODE_FRONT 0x00000dac -#define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NV50TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NV50TCL_POLYGON_MODE_BACK 0x00000db0 -#define NV50TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NV50TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NV50TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NV50TCL_POLYGON_SMOOTH_ENABLE 0x00000db4 -#define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0 -#define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4 -#define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8 -#define NV50TCL_WATCHDOG_TIMER 0x00000de4 -#define NV50TCL_WINDOW_OFFSET_X 0x00000df8 -#define NV50TCL_WINDOW_OFFSET_Y 0x00000dfc -#define NV50TCL_SCISSOR_ENABLE(x) (0x00000e00+((x)*16)) -#define NV50TCL_SCISSOR_ENABLE__SIZE 0x00000010 -#define NV50TCL_SCISSOR_HORIZ(x) (0x00000e04+((x)*16)) -#define NV50TCL_SCISSOR_HORIZ__SIZE 0x00000010 -#define NV50TCL_SCISSOR_HORIZ_MIN_SHIFT 0 -#define NV50TCL_SCISSOR_HORIZ_MIN_MASK 0x0000ffff -#define NV50TCL_SCISSOR_HORIZ_MAX_SHIFT 16 -#define NV50TCL_SCISSOR_HORIZ_MAX_MASK 0xffff0000 -#define NV50TCL_SCISSOR_VERT(x) (0x00000e08+((x)*16)) -#define NV50TCL_SCISSOR_VERT__SIZE 0x00000010 -#define NV50TCL_SCISSOR_VERT_MIN_SHIFT 0 -#define NV50TCL_SCISSOR_VERT_MIN_MASK 0x0000ffff -#define NV50TCL_SCISSOR_VERT_MAX_SHIFT 16 -#define NV50TCL_SCISSOR_VERT_MAX_MASK 0xffff0000 -#define NV50TCL_CB_ADDR 0x00000f00 -#define NV50TCL_CB_ADDR_ID_SHIFT 8 -#define NV50TCL_CB_ADDR_ID_MASK 0x003fff00 -#define NV50TCL_CB_ADDR_BUFFER_SHIFT 0 -#define NV50TCL_CB_ADDR_BUFFER_MASK 0x0000007f -#define NV50TCL_CB_DATA(x) (0x00000f04+((x)*4)) -#define NV50TCL_CB_DATA__SIZE 0x00000010 -#define NV50TCL_LOCAL_WARPS_LOG_ALLOC 0x00000f44 -#define NV50TCL_LOCAL_WARPS_NO_CLAMP 0x00000f48 -#define NV50TCL_STACK_WARPS_LOG_ALLOC 0x00000f4c -#define NV50TCL_STACK_WARPS_NO_CLAMP 0x00000f50 -#define NV50TCL_STENCIL_BACK_FUNC_REF 0x00000f54 -#define NV50TCL_STENCIL_BACK_MASK 0x00000f58 -#define NV50TCL_STENCIL_BACK_FUNC_MASK 0x00000f5c -#define NV50TCL_GP_ADDRESS_HIGH 0x00000f70 -#define NV50TCL_GP_ADDRESS_LOW 0x00000f74 -#define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c -#define NV50TCL_VP_ADDRESS_LOW 0x00000f80 -#define NV50TCL_VERTEX_RUNOUT_HIGH 0x00000f84 -#define NV50TCL_VERTEX_RUNOUT_LOW 0x00000f88 -#define NV50TCL_DEPTH_BOUNDS(x) (0x00000f9c+((x)*4)) -#define NV50TCL_DEPTH_BOUNDS__SIZE 0x00000002 -#define NV50TCL_FP_ADDRESS_HIGH 0x00000fa4 -#define NV50TCL_FP_ADDRESS_LOW 0x00000fa8 -#define NV50TCL_MSAA_MASK(x) (0x00000fbc+((x)*4)) -#define NV50TCL_MSAA_MASK__SIZE 0x00000004 -#define NV50TCL_CLIPID_ADDRESS_HIGH 0x00000fcc -#define NV50TCL_CLIPID_ADDRESS_LOW 0x00000fd0 -#define NV50TCL_ZETA_ADDRESS_HIGH 0x00000fe0 -#define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4 -#define NV50TCL_ZETA_FORMAT 0x00000fe8 -#define NV50TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a -#define NV50TCL_ZETA_FORMAT_Z16_UNORM 0x00000013 -#define NV50TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014 -#define NV50TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015 -#define NV50TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016 -#define NV50TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019 -#define NV50TCL_ZETA_TILE_MODE 0x00000fec -#define NV50TCL_ZETA_LAYER_STRIDE 0x00000ff0 -#define NV50TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4 -#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16 -#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000 -#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_SHIFT 0 -#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_MASK 0x0000ffff -#define NV50TCL_SCREEN_SCISSOR_VERT 0x00000ff8 -#define NV50TCL_SCREEN_SCISSOR_VERT_H_SHIFT 16 -#define NV50TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000 -#define NV50TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0 -#define NV50TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff -#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(x) (0x00001080+((x)*8)) -#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH__SIZE 0x00000010 -#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW(x) (0x00001084+((x)*8)) -#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW__SIZE 0x00000010 -#define NV50TCL_RT_CONTROL 0x0000121c -#define NV50TCL_RT_CONTROL_COUNT_SHIFT 0 -#define NV50TCL_RT_CONTROL_COUNT_MASK 0x0000000f -#define NV50TCL_RT_CONTROL_MAP0_SHIFT 4 -#define NV50TCL_RT_CONTROL_MAP0_MASK 0x00000070 -#define NV50TCL_RT_CONTROL_MAP1_SHIFT 7 -#define NV50TCL_RT_CONTROL_MAP1_MASK 0x00000380 -#define NV50TCL_RT_CONTROL_MAP2_SHIFT 10 -#define NV50TCL_RT_CONTROL_MAP2_MASK 0x00001c00 -#define NV50TCL_RT_CONTROL_MAP3_SHIFT 13 -#define NV50TCL_RT_CONTROL_MAP3_MASK 0x0000e000 -#define NV50TCL_RT_CONTROL_MAP4_SHIFT 16 -#define NV50TCL_RT_CONTROL_MAP4_MASK 0x00070000 -#define NV50TCL_RT_CONTROL_MAP5_SHIFT 19 -#define NV50TCL_RT_CONTROL_MAP5_MASK 0x00380000 -#define NV50TCL_RT_CONTROL_MAP6_SHIFT 22 -#define NV50TCL_RT_CONTROL_MAP6_MASK 0x01c00000 -#define NV50TCL_RT_CONTROL_MAP7_SHIFT 25 -#define NV50TCL_RT_CONTROL_MAP7_MASK 0x0e000000 -#define NV50TCL_RT_ARRAY_MODE 0x00001224 -#define NV50TCL_RT_ARRAY_MODE_LAYERS_SHIFT 0 -#define NV50TCL_RT_ARRAY_MODE_LAYERS_MASK 0x0000ffff -#define NV50TCL_RT_ARRAY_MODE_VOLUME (1 << 16) -#define NV50TCL_ZETA_HORIZ 0x00001228 -#define NV50TCL_ZETA_VERT 0x0000122c -#define NV50TCL_ZETA_ARRAY_MODE 0x00001230 -#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_SHIFT 0 -#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_MASK 0x0000ffff -#define NV50TCL_ZETA_ARRAY_MODE_UNK (1 << 16) -#define NV50TCL_LINKED_TSC 0x00001234 -#define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8)) -#define NV50TCL_RT_HORIZ__SIZE 0x00000008 -#define NV50TCL_RT_VERT(x) (0x00001244+((x)*8)) -#define NV50TCL_RT_VERT__SIZE 0x00000008 -#define NV50TCL_CB_DEF_ADDRESS_HIGH 0x00001280 -#define NV50TCL_CB_DEF_ADDRESS_LOW 0x00001284 -#define NV50TCL_CB_DEF_SET 0x00001288 -#define NV50TCL_CB_DEF_SET_SIZE_SHIFT 0 -#define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff -#define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16 -#define NV50TCL_CB_DEF_SET_BUFFER_MASK 0x007f0000 -#define NV50TCL_STRMOUT_BUFFERS_CTRL 0x00001294 -#define NV50TCL_STRMOUT_BUFFERS_CTRL_INTERLEAVED (1 << 0) -#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_SHIFT 4 -#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_MASK 0x000000f0 -#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_SHIFT 8 -#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_MASK 0x0000ff00 -#define NV50TCL_FP_RESULT_COUNT 0x00001298 -#define NV50TCL_DEPTH_TEST_ENABLE 0x000012cc -#define NV50TCL_SHADE_MODEL 0x000012d4 -#define NV50TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NV50TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NV50TCL_LOCAL_ADDRESS_HIGH 0x000012d8 -#define NV50TCL_LOCAL_ADDRESS_LOW 0x000012dc -#define NV50TCL_LOCAL_SIZE_LOG 0x000012e0 -#define NV50TCL_DEPTH_WRITE_ENABLE 0x000012e8 -#define NV50TCL_ALPHA_TEST_ENABLE 0x000012ec -#define NV50TCL_PM_SET(x) (0x000012f0+((x)*4)) -#define NV50TCL_PM_SET__SIZE 0x00000004 -#define NV50TCL_VB_ELEMENT_U8_SETUP 0x00001300 -#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_SHIFT 30 -#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_MASK 0xc0000000 -#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_SHIFT 0 -#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_MASK 0x3fffffff -#define NV50TCL_VB_ELEMENT_U8 0x00001304 -#define NV50TCL_VB_ELEMENT_U8_I0_SHIFT 0 -#define NV50TCL_VB_ELEMENT_U8_I0_MASK 0x000000ff -#define NV50TCL_VB_ELEMENT_U8_I1_SHIFT 8 -#define NV50TCL_VB_ELEMENT_U8_I1_MASK 0x0000ff00 -#define NV50TCL_VB_ELEMENT_U8_I2_SHIFT 16 -#define NV50TCL_VB_ELEMENT_U8_I2_MASK 0x00ff0000 -#define NV50TCL_VB_ELEMENT_U8_I3_SHIFT 24 -#define NV50TCL_VB_ELEMENT_U8_I3_MASK 0xff000000 -#define NV50TCL_DEPTH_TEST_FUNC 0x0000130c -#define NV50TCL_DEPTH_TEST_FUNC_NEVER 0x00000200 -#define NV50TCL_DEPTH_TEST_FUNC_LESS 0x00000201 -#define NV50TCL_DEPTH_TEST_FUNC_EQUAL 0x00000202 -#define NV50TCL_DEPTH_TEST_FUNC_LEQUAL 0x00000203 -#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204 -#define NV50TCL_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205 -#define NV50TCL_DEPTH_TEST_FUNC_GEQUAL 0x00000206 -#define NV50TCL_DEPTH_TEST_FUNC_ALWAYS 0x00000207 -#define NV50TCL_ALPHA_TEST_REF 0x00001310 -#define NV50TCL_ALPHA_TEST_FUNC 0x00001314 -#define NV50TCL_ALPHA_TEST_FUNC_NEVER 0x00000200 -#define NV50TCL_ALPHA_TEST_FUNC_LESS 0x00000201 -#define NV50TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202 -#define NV50TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203 -#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204 -#define NV50TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205 -#define NV50TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206 -#define NV50TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NV50TCL_BLEND_COLOR(x) (0x0000131c+((x)*4)) -#define NV50TCL_BLEND_COLOR__SIZE 0x00000004 -#define NV50TCL_TIC_FLUSH 0x00001330 -#define NV50TCL_TSC_FLUSH 0x00001334 -#define NV50TCL_TEX_CACHE_CTL 0x00001338 -#define NV50TCL_BLEND_EQUATION_RGB 0x00001340 -#define NV50TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 -#define NV50TCL_BLEND_EQUATION_RGB_MIN 0x00008007 -#define NV50TCL_BLEND_EQUATION_RGB_MAX 0x00008008 -#define NV50TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a -#define NV50TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV50TCL_BLEND_FUNC_SRC_RGB 0x00001344 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00004000 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE 0x00004001 -#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00004300 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00004302 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00004304 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00004306 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x0000c001 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x0000c003 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC1_COLOR 0x0000c900 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC1_ALPHA 0x0000c902 -#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NV50TCL_BLEND_FUNC_DST_RGB 0x00001348 -#define NV50TCL_BLEND_FUNC_DST_RGB_ZERO 0x00004000 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE 0x00004001 -#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00004300 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00004302 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NV50TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00004304 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NV50TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00004306 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x0000c001 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x0000c003 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NV50TCL_BLEND_FUNC_DST_RGB_SRC1_COLOR 0x0000c900 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NV50TCL_BLEND_FUNC_DST_RGB_SRC1_ALPHA 0x0000c902 -#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NV50TCL_BLEND_EQUATION_ALPHA 0x0000134c -#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x00008006 -#define NV50TCL_BLEND_EQUATION_ALPHA_MIN 0x00008007 -#define NV50TCL_BLEND_EQUATION_ALPHA_MAX 0x00008008 -#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x0000800a -#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NV50TCL_BLEND_FUNC_SRC_ALPHA 0x00001350 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00004000 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00004001 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x00004300 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x00004302 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x00004304 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x00004306 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC1_COLOR 0x0000c900 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC1_ALPHA 0x0000c902 -#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NV50TCL_BLEND_FUNC_DST_ALPHA 0x00001358 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00004000 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00004001 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x00004300 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x00004302 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x00004304 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x00004306 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC1_COLOR 0x0000c900 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC1_ALPHA 0x0000c902 -#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NV50TCL_BLEND_ENABLE(x) (0x00001360+((x)*4)) -#define NV50TCL_BLEND_ENABLE__SIZE 0x00000008 -#define NV50TCL_STENCIL_FRONT_ENABLE 0x00001380 -#define NV50TCL_STENCIL_FRONT_OP_FAIL 0x00001384 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a -#define NV50TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL 0x00001388 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS 0x0000138c -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC 0x00001390 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 -#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 -#define NV50TCL_STENCIL_FRONT_FUNC_REF 0x00001394 -#define NV50TCL_STENCIL_FRONT_MASK 0x00001398 -#define NV50TCL_STENCIL_FRONT_FUNC_MASK 0x0000139c -#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8 -#define NV50TCL_Y_ORIGIN_BOTTOM 0x000013ac -#define NV50TCL_LINE_WIDTH 0x000013b0 -#define NV50TCL_TEX_LIMITS(x) (0x000013b4+((x)*4)) -#define NV50TCL_TEX_LIMITS__SIZE 0x00000003 -#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0 -#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f -#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4 -#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0 -#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4)) -#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008 -#define NV50TCL_VP_START_ID 0x0000140c -#define NV50TCL_GP_START_ID 0x00001410 -#define NV50TCL_FP_START_ID 0x00001414 -#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420 -#define NV50TCL_VB_ELEMENT_BASE 0x00001434 -#define NV50TCL_INSTANCE_BASE 0x00001438 -#define NV50TCL_CODE_CB_FLUSH 0x00001440 -#define NV50TCL_BIND_TSC(x) (0x00001444+((x)*8)) -#define NV50TCL_BIND_TSC__SIZE 0x00000003 -#define NV50TCL_BIND_TSC_VALID (1 << 0) -#define NV50TCL_BIND_TSC_SAMPLER_SHIFT 4 -#define NV50TCL_BIND_TSC_SAMPLER_MASK 0x000000f0 -#define NV50TCL_BIND_TSC_TSC_SHIFT 12 -#define NV50TCL_BIND_TSC_TSC_MASK 0x001ff000 -#define NV50TCL_BIND_TIC(x) (0x00001448+((x)*8)) -#define NV50TCL_BIND_TIC__SIZE 0x00000003 -#define NV50TCL_BIND_TIC_VALID (1 << 0) -#define NV50TCL_BIND_TIC_TEXTURE_SHIFT 1 -#define NV50TCL_BIND_TIC_TEXTURE_MASK 0x000001fe -#define NV50TCL_BIND_TIC_TIC_SHIFT 9 -#define NV50TCL_BIND_TIC_TIC_MASK 0x7ffffe00 -#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4)) -#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020 -#define NV50TCL_CLIPID_HEIGHT 0x00001504 -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510 -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_6 (1 << 6) -#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_7 (1 << 7) -#define NV50TCL_SAMPLECNT_ENABLE 0x00001514 -#define NV50TCL_POINT_SIZE 0x00001518 -#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520 -#define NV50TCL_SAMPLECNT_RESET 0x00001530 -#define NV50TCL_ZETA_ENABLE 0x00001538 -#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c -#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0) -#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4) -#define NV50TCL_NOPERSPECTIVE_BITMAP(x) (0x00001540+((x)*4)) -#define NV50TCL_NOPERSPECTIVE_BITMAP__SIZE 0x00000004 -#define NV50TCL_COND_ADDRESS_HIGH 0x00001550 -#define NV50TCL_COND_ADDRESS_LOW 0x00001554 -#define NV50TCL_COND_MODE 0x00001558 -#define NV50TCL_COND_MODE_NEVER 0x00000000 -#define NV50TCL_COND_MODE_ALWAYS 0x00000001 -#define NV50TCL_COND_MODE_RES 0x00000002 -#define NV50TCL_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 -#define NV50TCL_COND_MODE_RES_OR_ID 0x00000004 -#define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c -#define NV50TCL_TSC_ADDRESS_LOW 0x00001560 -#define NV50TCL_TSC_LIMIT 0x00001564 -#define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c -#define NV50TCL_LINE_SMOOTH_ENABLE 0x00001570 -#define NV50TCL_TIC_ADDRESS_HIGH 0x00001574 -#define NV50TCL_TIC_ADDRESS_LOW 0x00001578 -#define NV50TCL_TIC_LIMIT 0x0000157c -#define NV50TCL_PM_CONTROL(x) (0x00001580+((x)*4)) -#define NV50TCL_PM_CONTROL__SIZE 0x00000004 -#define NV50TCL_PM_CONTROL_UNK0 (1 << 0) -#define NV50TCL_PM_CONTROL_UNK1_SHIFT 4 -#define NV50TCL_PM_CONTROL_UNK1_MASK 0x00000070 -#define NV50TCL_PM_CONTROL_UNK2_SHIFT 8 -#define NV50TCL_PM_CONTROL_UNK2_MASK 0xffffff00 -#define NV50TCL_STENCIL_BACK_ENABLE 0x00001594 -#define NV50TCL_STENCIL_BACK_OP_FAIL 0x00001598 -#define NV50TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 -#define NV50TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a -#define NV50TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00 -#define NV50TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02 -#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03 -#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL 0x0000159c -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_BACK_OP_ZPASS 0x000015a0 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a -#define NV50TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 -#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC 0x000015a4 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 -#define NV50TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 -#define NV50TCL_FRAMEBUFFER_SRGB 0x000015b8 -#define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc -#define NV50TCL_GP_BUILTIN_RESULT_EN 0x000015cc -#define NV50TCL_GP_BUILTIN_RESULT_EN_VPORT_IDX (1 << 0) -#define NV50TCL_GP_BUILTIN_RESULT_EN_LAYER_IDX (1 << 16) -#define NV50TCL_MULTISAMPLE_MODE 0x000015d0 -#define NV50TCL_MULTISAMPLE_MODE_1X 0x00000000 -#define NV50TCL_MULTISAMPLE_MODE_2XMS 0x00000001 -#define NV50TCL_MULTISAMPLE_MODE_4XMS 0x00000002 -#define NV50TCL_MULTISAMPLE_MODE_8XMS 0x00000004 -#define NV50TCL_MULTISAMPLE_MODE_4XMS_4XCS 0x00000008 -#define NV50TCL_MULTISAMPLE_MODE_4XMS_12XCS 0x00000009 -#define NV50TCL_MULTISAMPLE_MODE_8XMS_8XCS 0x0000000a -#define NV50TCL_VERTEX_BEGIN 0x000015dc -#define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000 -#define NV50TCL_VERTEX_BEGIN_LINES 0x00000001 -#define NV50TCL_VERTEX_BEGIN_LINE_LOOP 0x00000002 -#define NV50TCL_VERTEX_BEGIN_LINE_STRIP 0x00000003 -#define NV50TCL_VERTEX_BEGIN_TRIANGLES 0x00000004 -#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP 0x00000005 -#define NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN 0x00000006 -#define NV50TCL_VERTEX_BEGIN_QUADS 0x00000007 -#define NV50TCL_VERTEX_BEGIN_QUAD_STRIP 0x00000008 -#define NV50TCL_VERTEX_BEGIN_POLYGON 0x00000009 -#define NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY 0x0000000a -#define NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY 0x0000000b -#define NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY 0x0000000c -#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY 0x0000000d -#define NV50TCL_VERTEX_BEGIN_PATCHES 0x0000000e -#define NV50TCL_VERTEX_END 0x000015e0 -#define NV50TCL_EDGEFLAG_ENABLE 0x000015e4 -#define NV50TCL_VB_ELEMENT_U32 0x000015e8 -#define NV50TCL_VB_ELEMENT_U16_SETUP 0x000015ec -#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_SHIFT 30 -#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_MASK 0xc0000000 -#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_SHIFT 0 -#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_MASK 0x3fffffff -#define NV50TCL_VB_ELEMENT_U16 0x000015f0 -#define NV50TCL_VB_ELEMENT_U16_I0_SHIFT 0 -#define NV50TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff -#define NV50TCL_VB_ELEMENT_U16_I1_SHIFT 16 -#define NV50TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 -#define NV50TCL_VERTEX_BASE_HIGH 0x000015f4 -#define NV50TCL_VERTEX_BASE_LOW 0x000015f8 -#define NV50TCL_VERTEX_DATA 0x00001640 -#define NV50TCL_PRIM_RESTART_ENABLE 0x00001644 -#define NV50TCL_PRIM_RESTART_INDEX 0x00001648 -#define NV50TCL_VP_GP_BUILTIN_ATTR_EN 0x0000164c -#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID (1 << 0) -#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID (1 << 4) -#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID (1 << 8) -#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_UNK12 (1 << 12) -#define NV50TCL_VP_ATTR_EN_0 0x00001650 -#define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28 -#define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000 -#define NV50TCL_VP_ATTR_EN_0_7_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_7_XNNN 0x10000000 -#define NV50TCL_VP_ATTR_EN_0_7_NYNN 0x20000000 -#define NV50TCL_VP_ATTR_EN_0_7_XYNN 0x30000000 -#define NV50TCL_VP_ATTR_EN_0_7_NNZN 0x40000000 -#define NV50TCL_VP_ATTR_EN_0_7_XNZN 0x50000000 -#define NV50TCL_VP_ATTR_EN_0_7_NYZN 0x60000000 -#define NV50TCL_VP_ATTR_EN_0_7_XYZN 0x70000000 -#define NV50TCL_VP_ATTR_EN_0_7_NNNW 0x80000000 -#define NV50TCL_VP_ATTR_EN_0_7_XNNW 0x90000000 -#define NV50TCL_VP_ATTR_EN_0_7_NYNW 0xa0000000 -#define NV50TCL_VP_ATTR_EN_0_7_XYNW 0xb0000000 -#define NV50TCL_VP_ATTR_EN_0_7_NNZW 0xc0000000 -#define NV50TCL_VP_ATTR_EN_0_7_XNZW 0xd0000000 -#define NV50TCL_VP_ATTR_EN_0_7_NYZW 0xe0000000 -#define NV50TCL_VP_ATTR_EN_0_7_XYZW 0xf0000000 -#define NV50TCL_VP_ATTR_EN_0_6_SHIFT 24 -#define NV50TCL_VP_ATTR_EN_0_6_MASK 0x0f000000 -#define NV50TCL_VP_ATTR_EN_0_6_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_6_XNNN 0x01000000 -#define NV50TCL_VP_ATTR_EN_0_6_NYNN 0x02000000 -#define NV50TCL_VP_ATTR_EN_0_6_XYNN 0x03000000 -#define NV50TCL_VP_ATTR_EN_0_6_NNZN 0x04000000 -#define NV50TCL_VP_ATTR_EN_0_6_XNZN 0x05000000 -#define NV50TCL_VP_ATTR_EN_0_6_NYZN 0x06000000 -#define NV50TCL_VP_ATTR_EN_0_6_XYZN 0x07000000 -#define NV50TCL_VP_ATTR_EN_0_6_NNNW 0x08000000 -#define NV50TCL_VP_ATTR_EN_0_6_XNNW 0x09000000 -#define NV50TCL_VP_ATTR_EN_0_6_NYNW 0x0a000000 -#define NV50TCL_VP_ATTR_EN_0_6_XYNW 0x0b000000 -#define NV50TCL_VP_ATTR_EN_0_6_NNZW 0x0c000000 -#define NV50TCL_VP_ATTR_EN_0_6_XNZW 0x0d000000 -#define NV50TCL_VP_ATTR_EN_0_6_NYZW 0x0e000000 -#define NV50TCL_VP_ATTR_EN_0_6_XYZW 0x0f000000 -#define NV50TCL_VP_ATTR_EN_0_5_SHIFT 20 -#define NV50TCL_VP_ATTR_EN_0_5_MASK 0x00f00000 -#define NV50TCL_VP_ATTR_EN_0_5_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_5_XNNN 0x00100000 -#define NV50TCL_VP_ATTR_EN_0_5_NYNN 0x00200000 -#define NV50TCL_VP_ATTR_EN_0_5_XYNN 0x00300000 -#define NV50TCL_VP_ATTR_EN_0_5_NNZN 0x00400000 -#define NV50TCL_VP_ATTR_EN_0_5_XNZN 0x00500000 -#define NV50TCL_VP_ATTR_EN_0_5_NYZN 0x00600000 -#define NV50TCL_VP_ATTR_EN_0_5_XYZN 0x00700000 -#define NV50TCL_VP_ATTR_EN_0_5_NNNW 0x00800000 -#define NV50TCL_VP_ATTR_EN_0_5_XNNW 0x00900000 -#define NV50TCL_VP_ATTR_EN_0_5_NYNW 0x00a00000 -#define NV50TCL_VP_ATTR_EN_0_5_XYNW 0x00b00000 -#define NV50TCL_VP_ATTR_EN_0_5_NNZW 0x00c00000 -#define NV50TCL_VP_ATTR_EN_0_5_XNZW 0x00d00000 -#define NV50TCL_VP_ATTR_EN_0_5_NYZW 0x00e00000 -#define NV50TCL_VP_ATTR_EN_0_5_XYZW 0x00f00000 -#define NV50TCL_VP_ATTR_EN_0_4_SHIFT 16 -#define NV50TCL_VP_ATTR_EN_0_4_MASK 0x000f0000 -#define NV50TCL_VP_ATTR_EN_0_4_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_4_XNNN 0x00010000 -#define NV50TCL_VP_ATTR_EN_0_4_NYNN 0x00020000 -#define NV50TCL_VP_ATTR_EN_0_4_XYNN 0x00030000 -#define NV50TCL_VP_ATTR_EN_0_4_NNZN 0x00040000 -#define NV50TCL_VP_ATTR_EN_0_4_XNZN 0x00050000 -#define NV50TCL_VP_ATTR_EN_0_4_NYZN 0x00060000 -#define NV50TCL_VP_ATTR_EN_0_4_XYZN 0x00070000 -#define NV50TCL_VP_ATTR_EN_0_4_NNNW 0x00080000 -#define NV50TCL_VP_ATTR_EN_0_4_XNNW 0x00090000 -#define NV50TCL_VP_ATTR_EN_0_4_NYNW 0x000a0000 -#define NV50TCL_VP_ATTR_EN_0_4_XYNW 0x000b0000 -#define NV50TCL_VP_ATTR_EN_0_4_NNZW 0x000c0000 -#define NV50TCL_VP_ATTR_EN_0_4_XNZW 0x000d0000 -#define NV50TCL_VP_ATTR_EN_0_4_NYZW 0x000e0000 -#define NV50TCL_VP_ATTR_EN_0_4_XYZW 0x000f0000 -#define NV50TCL_VP_ATTR_EN_0_3_SHIFT 12 -#define NV50TCL_VP_ATTR_EN_0_3_MASK 0x0000f000 -#define NV50TCL_VP_ATTR_EN_0_3_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_3_XNNN 0x00001000 -#define NV50TCL_VP_ATTR_EN_0_3_NYNN 0x00002000 -#define NV50TCL_VP_ATTR_EN_0_3_XYNN 0x00003000 -#define NV50TCL_VP_ATTR_EN_0_3_NNZN 0x00004000 -#define NV50TCL_VP_ATTR_EN_0_3_XNZN 0x00005000 -#define NV50TCL_VP_ATTR_EN_0_3_NYZN 0x00006000 -#define NV50TCL_VP_ATTR_EN_0_3_XYZN 0x00007000 -#define NV50TCL_VP_ATTR_EN_0_3_NNNW 0x00008000 -#define NV50TCL_VP_ATTR_EN_0_3_XNNW 0x00009000 -#define NV50TCL_VP_ATTR_EN_0_3_NYNW 0x0000a000 -#define NV50TCL_VP_ATTR_EN_0_3_XYNW 0x0000b000 -#define NV50TCL_VP_ATTR_EN_0_3_NNZW 0x0000c000 -#define NV50TCL_VP_ATTR_EN_0_3_XNZW 0x0000d000 -#define NV50TCL_VP_ATTR_EN_0_3_NYZW 0x0000e000 -#define NV50TCL_VP_ATTR_EN_0_3_XYZW 0x0000f000 -#define NV50TCL_VP_ATTR_EN_0_2_SHIFT 8 -#define NV50TCL_VP_ATTR_EN_0_2_MASK 0x00000f00 -#define NV50TCL_VP_ATTR_EN_0_2_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_2_XNNN 0x00000100 -#define NV50TCL_VP_ATTR_EN_0_2_NYNN 0x00000200 -#define NV50TCL_VP_ATTR_EN_0_2_XYNN 0x00000300 -#define NV50TCL_VP_ATTR_EN_0_2_NNZN 0x00000400 -#define NV50TCL_VP_ATTR_EN_0_2_XNZN 0x00000500 -#define NV50TCL_VP_ATTR_EN_0_2_NYZN 0x00000600 -#define NV50TCL_VP_ATTR_EN_0_2_XYZN 0x00000700 -#define NV50TCL_VP_ATTR_EN_0_2_NNNW 0x00000800 -#define NV50TCL_VP_ATTR_EN_0_2_XNNW 0x00000900 -#define NV50TCL_VP_ATTR_EN_0_2_NYNW 0x00000a00 -#define NV50TCL_VP_ATTR_EN_0_2_XYNW 0x00000b00 -#define NV50TCL_VP_ATTR_EN_0_2_NNZW 0x00000c00 -#define NV50TCL_VP_ATTR_EN_0_2_XNZW 0x00000d00 -#define NV50TCL_VP_ATTR_EN_0_2_NYZW 0x00000e00 -#define NV50TCL_VP_ATTR_EN_0_2_XYZW 0x00000f00 -#define NV50TCL_VP_ATTR_EN_0_1_SHIFT 4 -#define NV50TCL_VP_ATTR_EN_0_1_MASK 0x000000f0 -#define NV50TCL_VP_ATTR_EN_0_1_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_1_XNNN 0x00000010 -#define NV50TCL_VP_ATTR_EN_0_1_NYNN 0x00000020 -#define NV50TCL_VP_ATTR_EN_0_1_XYNN 0x00000030 -#define NV50TCL_VP_ATTR_EN_0_1_NNZN 0x00000040 -#define NV50TCL_VP_ATTR_EN_0_1_XNZN 0x00000050 -#define NV50TCL_VP_ATTR_EN_0_1_NYZN 0x00000060 -#define NV50TCL_VP_ATTR_EN_0_1_XYZN 0x00000070 -#define NV50TCL_VP_ATTR_EN_0_1_NNNW 0x00000080 -#define NV50TCL_VP_ATTR_EN_0_1_XNNW 0x00000090 -#define NV50TCL_VP_ATTR_EN_0_1_NYNW 0x000000a0 -#define NV50TCL_VP_ATTR_EN_0_1_XYNW 0x000000b0 -#define NV50TCL_VP_ATTR_EN_0_1_NNZW 0x000000c0 -#define NV50TCL_VP_ATTR_EN_0_1_XNZW 0x000000d0 -#define NV50TCL_VP_ATTR_EN_0_1_NYZW 0x000000e0 -#define NV50TCL_VP_ATTR_EN_0_1_XYZW 0x000000f0 -#define NV50TCL_VP_ATTR_EN_0_0_SHIFT 0 -#define NV50TCL_VP_ATTR_EN_0_0_MASK 0x0000000f -#define NV50TCL_VP_ATTR_EN_0_0_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_0_0_XNNN 0x00000001 -#define NV50TCL_VP_ATTR_EN_0_0_NYNN 0x00000002 -#define NV50TCL_VP_ATTR_EN_0_0_XYNN 0x00000003 -#define NV50TCL_VP_ATTR_EN_0_0_NNZN 0x00000004 -#define NV50TCL_VP_ATTR_EN_0_0_XNZN 0x00000005 -#define NV50TCL_VP_ATTR_EN_0_0_NYZN 0x00000006 -#define NV50TCL_VP_ATTR_EN_0_0_XYZN 0x00000007 -#define NV50TCL_VP_ATTR_EN_0_0_NNNW 0x00000008 -#define NV50TCL_VP_ATTR_EN_0_0_XNNW 0x00000009 -#define NV50TCL_VP_ATTR_EN_0_0_NYNW 0x0000000a -#define NV50TCL_VP_ATTR_EN_0_0_XYNW 0x0000000b -#define NV50TCL_VP_ATTR_EN_0_0_NNZW 0x0000000c -#define NV50TCL_VP_ATTR_EN_0_0_XNZW 0x0000000d -#define NV50TCL_VP_ATTR_EN_0_0_NYZW 0x0000000e -#define NV50TCL_VP_ATTR_EN_0_0_XYZW 0x0000000f -#define NV50TCL_VP_ATTR_EN_1 0x00001654 -#define NV50TCL_VP_ATTR_EN_1_15_SHIFT 28 -#define NV50TCL_VP_ATTR_EN_1_15_MASK 0xf0000000 -#define NV50TCL_VP_ATTR_EN_1_15_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_15_XNNN 0x10000000 -#define NV50TCL_VP_ATTR_EN_1_15_NYNN 0x20000000 -#define NV50TCL_VP_ATTR_EN_1_15_XYNN 0x30000000 -#define NV50TCL_VP_ATTR_EN_1_15_NNZN 0x40000000 -#define NV50TCL_VP_ATTR_EN_1_15_XNZN 0x50000000 -#define NV50TCL_VP_ATTR_EN_1_15_NYZN 0x60000000 -#define NV50TCL_VP_ATTR_EN_1_15_XYZN 0x70000000 -#define NV50TCL_VP_ATTR_EN_1_15_NNNW 0x80000000 -#define NV50TCL_VP_ATTR_EN_1_15_XNNW 0x90000000 -#define NV50TCL_VP_ATTR_EN_1_15_NYNW 0xa0000000 -#define NV50TCL_VP_ATTR_EN_1_15_XYNW 0xb0000000 -#define NV50TCL_VP_ATTR_EN_1_15_NNZW 0xc0000000 -#define NV50TCL_VP_ATTR_EN_1_15_XNZW 0xd0000000 -#define NV50TCL_VP_ATTR_EN_1_15_NYZW 0xe0000000 -#define NV50TCL_VP_ATTR_EN_1_15_XYZW 0xf0000000 -#define NV50TCL_VP_ATTR_EN_1_14_SHIFT 24 -#define NV50TCL_VP_ATTR_EN_1_14_MASK 0x0f000000 -#define NV50TCL_VP_ATTR_EN_1_14_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_14_XNNN 0x01000000 -#define NV50TCL_VP_ATTR_EN_1_14_NYNN 0x02000000 -#define NV50TCL_VP_ATTR_EN_1_14_XYNN 0x03000000 -#define NV50TCL_VP_ATTR_EN_1_14_NNZN 0x04000000 -#define NV50TCL_VP_ATTR_EN_1_14_XNZN 0x05000000 -#define NV50TCL_VP_ATTR_EN_1_14_NYZN 0x06000000 -#define NV50TCL_VP_ATTR_EN_1_14_XYZN 0x07000000 -#define NV50TCL_VP_ATTR_EN_1_14_NNNW 0x08000000 -#define NV50TCL_VP_ATTR_EN_1_14_XNNW 0x09000000 -#define NV50TCL_VP_ATTR_EN_1_14_NYNW 0x0a000000 -#define NV50TCL_VP_ATTR_EN_1_14_XYNW 0x0b000000 -#define NV50TCL_VP_ATTR_EN_1_14_NNZW 0x0c000000 -#define NV50TCL_VP_ATTR_EN_1_14_XNZW 0x0d000000 -#define NV50TCL_VP_ATTR_EN_1_14_NYZW 0x0e000000 -#define NV50TCL_VP_ATTR_EN_1_14_XYZW 0x0f000000 -#define NV50TCL_VP_ATTR_EN_1_13_SHIFT 20 -#define NV50TCL_VP_ATTR_EN_1_13_MASK 0x00f00000 -#define NV50TCL_VP_ATTR_EN_1_13_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_13_XNNN 0x00100000 -#define NV50TCL_VP_ATTR_EN_1_13_NYNN 0x00200000 -#define NV50TCL_VP_ATTR_EN_1_13_XYNN 0x00300000 -#define NV50TCL_VP_ATTR_EN_1_13_NNZN 0x00400000 -#define NV50TCL_VP_ATTR_EN_1_13_XNZN 0x00500000 -#define NV50TCL_VP_ATTR_EN_1_13_NYZN 0x00600000 -#define NV50TCL_VP_ATTR_EN_1_13_XYZN 0x00700000 -#define NV50TCL_VP_ATTR_EN_1_13_NNNW 0x00800000 -#define NV50TCL_VP_ATTR_EN_1_13_XNNW 0x00900000 -#define NV50TCL_VP_ATTR_EN_1_13_NYNW 0x00a00000 -#define NV50TCL_VP_ATTR_EN_1_13_XYNW 0x00b00000 -#define NV50TCL_VP_ATTR_EN_1_13_NNZW 0x00c00000 -#define NV50TCL_VP_ATTR_EN_1_13_XNZW 0x00d00000 -#define NV50TCL_VP_ATTR_EN_1_13_NYZW 0x00e00000 -#define NV50TCL_VP_ATTR_EN_1_13_XYZW 0x00f00000 -#define NV50TCL_VP_ATTR_EN_1_12_SHIFT 16 -#define NV50TCL_VP_ATTR_EN_1_12_MASK 0x000f0000 -#define NV50TCL_VP_ATTR_EN_1_12_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_12_XNNN 0x00010000 -#define NV50TCL_VP_ATTR_EN_1_12_NYNN 0x00020000 -#define NV50TCL_VP_ATTR_EN_1_12_XYNN 0x00030000 -#define NV50TCL_VP_ATTR_EN_1_12_NNZN 0x00040000 -#define NV50TCL_VP_ATTR_EN_1_12_XNZN 0x00050000 -#define NV50TCL_VP_ATTR_EN_1_12_NYZN 0x00060000 -#define NV50TCL_VP_ATTR_EN_1_12_XYZN 0x00070000 -#define NV50TCL_VP_ATTR_EN_1_12_NNNW 0x00080000 -#define NV50TCL_VP_ATTR_EN_1_12_XNNW 0x00090000 -#define NV50TCL_VP_ATTR_EN_1_12_NYNW 0x000a0000 -#define NV50TCL_VP_ATTR_EN_1_12_XYNW 0x000b0000 -#define NV50TCL_VP_ATTR_EN_1_12_NNZW 0x000c0000 -#define NV50TCL_VP_ATTR_EN_1_12_XNZW 0x000d0000 -#define NV50TCL_VP_ATTR_EN_1_12_NYZW 0x000e0000 -#define NV50TCL_VP_ATTR_EN_1_12_XYZW 0x000f0000 -#define NV50TCL_VP_ATTR_EN_1_11_SHIFT 12 -#define NV50TCL_VP_ATTR_EN_1_11_MASK 0x0000f000 -#define NV50TCL_VP_ATTR_EN_1_11_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_11_XNNN 0x00001000 -#define NV50TCL_VP_ATTR_EN_1_11_NYNN 0x00002000 -#define NV50TCL_VP_ATTR_EN_1_11_XYNN 0x00003000 -#define NV50TCL_VP_ATTR_EN_1_11_NNZN 0x00004000 -#define NV50TCL_VP_ATTR_EN_1_11_XNZN 0x00005000 -#define NV50TCL_VP_ATTR_EN_1_11_NYZN 0x00006000 -#define NV50TCL_VP_ATTR_EN_1_11_XYZN 0x00007000 -#define NV50TCL_VP_ATTR_EN_1_11_NNNW 0x00008000 -#define NV50TCL_VP_ATTR_EN_1_11_XNNW 0x00009000 -#define NV50TCL_VP_ATTR_EN_1_11_NYNW 0x0000a000 -#define NV50TCL_VP_ATTR_EN_1_11_XYNW 0x0000b000 -#define NV50TCL_VP_ATTR_EN_1_11_NNZW 0x0000c000 -#define NV50TCL_VP_ATTR_EN_1_11_XNZW 0x0000d000 -#define NV50TCL_VP_ATTR_EN_1_11_NYZW 0x0000e000 -#define NV50TCL_VP_ATTR_EN_1_11_XYZW 0x0000f000 -#define NV50TCL_VP_ATTR_EN_1_10_SHIFT 8 -#define NV50TCL_VP_ATTR_EN_1_10_MASK 0x00000f00 -#define NV50TCL_VP_ATTR_EN_1_10_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_10_XNNN 0x00000100 -#define NV50TCL_VP_ATTR_EN_1_10_NYNN 0x00000200 -#define NV50TCL_VP_ATTR_EN_1_10_XYNN 0x00000300 -#define NV50TCL_VP_ATTR_EN_1_10_NNZN 0x00000400 -#define NV50TCL_VP_ATTR_EN_1_10_XNZN 0x00000500 -#define NV50TCL_VP_ATTR_EN_1_10_NYZN 0x00000600 -#define NV50TCL_VP_ATTR_EN_1_10_XYZN 0x00000700 -#define NV50TCL_VP_ATTR_EN_1_10_NNNW 0x00000800 -#define NV50TCL_VP_ATTR_EN_1_10_XNNW 0x00000900 -#define NV50TCL_VP_ATTR_EN_1_10_NYNW 0x00000a00 -#define NV50TCL_VP_ATTR_EN_1_10_XYNW 0x00000b00 -#define NV50TCL_VP_ATTR_EN_1_10_NNZW 0x00000c00 -#define NV50TCL_VP_ATTR_EN_1_10_XNZW 0x00000d00 -#define NV50TCL_VP_ATTR_EN_1_10_NYZW 0x00000e00 -#define NV50TCL_VP_ATTR_EN_1_10_XYZW 0x00000f00 -#define NV50TCL_VP_ATTR_EN_1_9_SHIFT 4 -#define NV50TCL_VP_ATTR_EN_1_9_MASK 0x000000f0 -#define NV50TCL_VP_ATTR_EN_1_9_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_9_XNNN 0x00000010 -#define NV50TCL_VP_ATTR_EN_1_9_NYNN 0x00000020 -#define NV50TCL_VP_ATTR_EN_1_9_XYNN 0x00000030 -#define NV50TCL_VP_ATTR_EN_1_9_NNZN 0x00000040 -#define NV50TCL_VP_ATTR_EN_1_9_XNZN 0x00000050 -#define NV50TCL_VP_ATTR_EN_1_9_NYZN 0x00000060 -#define NV50TCL_VP_ATTR_EN_1_9_XYZN 0x00000070 -#define NV50TCL_VP_ATTR_EN_1_9_NNNW 0x00000080 -#define NV50TCL_VP_ATTR_EN_1_9_XNNW 0x00000090 -#define NV50TCL_VP_ATTR_EN_1_9_NYNW 0x000000a0 -#define NV50TCL_VP_ATTR_EN_1_9_XYNW 0x000000b0 -#define NV50TCL_VP_ATTR_EN_1_9_NNZW 0x000000c0 -#define NV50TCL_VP_ATTR_EN_1_9_XNZW 0x000000d0 -#define NV50TCL_VP_ATTR_EN_1_9_NYZW 0x000000e0 -#define NV50TCL_VP_ATTR_EN_1_9_XYZW 0x000000f0 -#define NV50TCL_VP_ATTR_EN_1_8_SHIFT 0 -#define NV50TCL_VP_ATTR_EN_1_8_MASK 0x0000000f -#define NV50TCL_VP_ATTR_EN_1_8_NONE 0x00000000 -#define NV50TCL_VP_ATTR_EN_1_8_XNNN 0x00000001 -#define NV50TCL_VP_ATTR_EN_1_8_NYNN 0x00000002 -#define NV50TCL_VP_ATTR_EN_1_8_XYNN 0x00000003 -#define NV50TCL_VP_ATTR_EN_1_8_NNZN 0x00000004 -#define NV50TCL_VP_ATTR_EN_1_8_XNZN 0x00000005 -#define NV50TCL_VP_ATTR_EN_1_8_NYZN 0x00000006 -#define NV50TCL_VP_ATTR_EN_1_8_XYZN 0x00000007 -#define NV50TCL_VP_ATTR_EN_1_8_NNNW 0x00000008 -#define NV50TCL_VP_ATTR_EN_1_8_XNNW 0x00000009 -#define NV50TCL_VP_ATTR_EN_1_8_NYNW 0x0000000a -#define NV50TCL_VP_ATTR_EN_1_8_XYNW 0x0000000b -#define NV50TCL_VP_ATTR_EN_1_8_NNZW 0x0000000c -#define NV50TCL_VP_ATTR_EN_1_8_XNZW 0x0000000d -#define NV50TCL_VP_ATTR_EN_1_8_NYZW 0x0000000e -#define NV50TCL_VP_ATTR_EN_1_8_XYZW 0x0000000f -#define NV50TCL_POINT_SPRITE_CTRL 0x00001660 -#define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c -#define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680 -#define NV50TCL_PROVOKING_VERTEX_LAST 0x00001684 -#define NV50TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688 -#define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c -#define NV50TCL_SET_PROGRAM_CB 0x00001694 -#define NV50TCL_SET_PROGRAM_CB_PROGRAM_SHIFT 4 -#define NV50TCL_SET_PROGRAM_CB_PROGRAM_MASK 0x000000f0 -#define NV50TCL_SET_PROGRAM_CB_PROGRAM_VERTEX 0x00000000 -#define NV50TCL_SET_PROGRAM_CB_PROGRAM_GEOMETRY 0x00000020 -#define NV50TCL_SET_PROGRAM_CB_PROGRAM_FRAGMENT 0x00000030 -#define NV50TCL_SET_PROGRAM_CB_INDEX_SHIFT 8 -#define NV50TCL_SET_PROGRAM_CB_INDEX_MASK 0x00000f00 -#define NV50TCL_SET_PROGRAM_CB_BUFFER_SHIFT 12 -#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000 -#define NV50TCL_SET_PROGRAM_CB_VALID (1 << 0) -#define NV50TCL_VP_RESULT_MAP_SIZE 0x000016ac -#define NV50TCL_VP_REG_ALLOC_TEMP 0x000016b0 -#define NV50TCL_VP_REG_ALLOC_RESULT 0x000016b8 -#define NV50TCL_VP_RESULT_MAP(x) (0x000016bc+((x)*4)) -#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000010 -#define NV50TCL_VP_RESULT_MAP_0_SHIFT 0 -#define NV50TCL_VP_RESULT_MAP_0_MASK 0x000000ff -#define NV50TCL_VP_RESULT_MAP_1_SHIFT 8 -#define NV50TCL_VP_RESULT_MAP_1_MASK 0x0000ff00 -#define NV50TCL_VP_RESULT_MAP_2_SHIFT 16 -#define NV50TCL_VP_RESULT_MAP_2_MASK 0x00ff0000 -#define NV50TCL_VP_RESULT_MAP_3_SHIFT 24 -#define NV50TCL_VP_RESULT_MAP_3_MASK 0xff000000 -#define NV50TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4)) -#define NV50TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 -#define NV50TCL_GP_ENABLE 0x00001798 -#define NV50TCL_GP_REG_ALLOC_TEMP 0x000017a0 -#define NV50TCL_GP_REG_ALLOC_RESULT 0x000017a8 -#define NV50TCL_GP_RESULT_MAP_SIZE 0x000017ac -#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE 0x000017b0 -#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS 0x00000001 -#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP 0x00000002 -#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000003 -#define NV50TCL_RASTERIZE_ENABLE 0x000017b4 -#define NV50TCL_STRMOUT_ENABLE 0x000017b8 -#define NV50TCL_GP_RESULT_MAP(x) (0x000017fc+((x)*4)) -#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000020 -#define NV50TCL_GP_RESULT_MAP_0_SHIFT 0 -#define NV50TCL_GP_RESULT_MAP_0_MASK 0x000000ff -#define NV50TCL_GP_RESULT_MAP_1_SHIFT 8 -#define NV50TCL_GP_RESULT_MAP_1_MASK 0x0000ff00 -#define NV50TCL_GP_RESULT_MAP_2_SHIFT 16 -#define NV50TCL_GP_RESULT_MAP_2_MASK 0x00ff0000 -#define NV50TCL_GP_RESULT_MAP_3_SHIFT 24 -#define NV50TCL_GP_RESULT_MAP_3_MASK 0xff000000 -#define NV50TCL_MAP_SEMANTIC_0 0x00001904 -#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_SHIFT 0 -#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_MASK 0x000000ff -#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_SHIFT 8 -#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_MASK 0x0000ff00 -#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_SHIFT 16 -#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_MASK 0x00ff0000 -#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_SHIFT 24 -#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_MASK 0xff000000 -#define NV50TCL_MAP_SEMANTIC_1 0x00001908 -#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_SHIFT 0 -#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_MASK 0x000000ff -#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_SHIFT 8 -#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_MASK 0x0000ff00 -#define NV50TCL_MAP_SEMANTIC_2 0x0000190c -#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_SHIFT 0 -#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_MASK 0x000000ff -#define NV50TCL_MAP_SEMANTIC_3 0x00001910 -#define NV50TCL_MAP_SEMANTIC_3_PTSZ_EN (1 << 0) -#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_SHIFT 4 -#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_MASK 0x00000ff0 -#define NV50TCL_MAP_SEMANTIC_4 0x00001914 -#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_SHIFT 0 -#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_MASK 0x000000ff -#define NV50TCL_CULL_FACE_ENABLE 0x00001918 -#define NV50TCL_FRONT_FACE 0x0000191c -#define NV50TCL_FRONT_FACE_CW 0x00000900 -#define NV50TCL_FRONT_FACE_CCW 0x00000901 -#define NV50TCL_CULL_FACE 0x00001920 -#define NV50TCL_CULL_FACE_FRONT 0x00000404 -#define NV50TCL_CULL_FACE_BACK 0x00000405 -#define NV50TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NV50TCL_VIEWPORT_TRANSFORM_EN 0x0000192c -#define NV50TCL_VIEW_VOLUME_CLIP_CTRL 0x0000193c -#define NV50TCL_VIEWPORT_CLIP_RECTS_EN 0x0000194c -#define NV50TCL_VIEWPORT_CLIP_MODE 0x00001950 -#define NV50TCL_VIEWPORT_CLIP_MODE_INCLUDE 0x00000000 -#define NV50TCL_VIEWPORT_CLIP_MODE_EXCLUDE 0x00000001 -#define NV50TCL_VIEWPORT_CLIP_MODE_UNKNOWN 0x00000002 -#define NV50TCL_FP_CTRL_UNK196C 0x0000196c -#define NV50TCL_CLIPID_ENABLE 0x0000197c -#define NV50TCL_CLIPID_WIDTH 0x00001980 -#define NV50TCL_CLIPID_ID 0x00001984 -#define NV50TCL_FP_INTERPOLANT_CTRL 0x00001988 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_SHIFT 24 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_MASK 0xff000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NONE 0x00000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNN 0x01000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNN 0x02000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNN 0x03000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZN 0x04000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZN 0x05000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZN 0x06000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZN 0x07000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNNW 0x08000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNW 0x09000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNW 0x0a000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNW 0x0b000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZW 0x0c000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZW 0x0d000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZW 0x0e000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZW 0x0f000000 -#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_SHIFT 16 -#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_MASK 0x00ff0000 -#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_SHIFT 8 -#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_MASK 0x0000ff00 -#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 0 -#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x000000ff -#define NV50TCL_FP_REG_ALLOC_TEMP 0x0000198c -#define NV50TCL_REG_MODE 0x000019a0 -#define NV50TCL_REG_MODE_PACKED 0x00000001 -#define NV50TCL_REG_MODE_STRIPED 0x00000002 -#define NV50TCL_FP_CONTROL 0x000019a8 -#define NV50TCL_FP_CONTROL_MULTIPLE_RESULTS (1 << 0) -#define NV50TCL_FP_CONTROL_EXPORTS_Z (1 << 8) -#define NV50TCL_FP_CONTROL_USES_KIL (1 << 20) -#define NV50TCL_DEPTH_BOUNDS_EN 0x000019bc -#define NV50TCL_LOGIC_OP_ENABLE 0x000019c4 -#define NV50TCL_LOGIC_OP 0x000019c8 -#define NV50TCL_LOGIC_OP_CLEAR 0x00001500 -#define NV50TCL_LOGIC_OP_AND 0x00001501 -#define NV50TCL_LOGIC_OP_AND_REVERSE 0x00001502 -#define NV50TCL_LOGIC_OP_COPY 0x00001503 -#define NV50TCL_LOGIC_OP_AND_INVERTED 0x00001504 -#define NV50TCL_LOGIC_OP_NOOP 0x00001505 -#define NV50TCL_LOGIC_OP_XOR 0x00001506 -#define NV50TCL_LOGIC_OP_OR 0x00001507 -#define NV50TCL_LOGIC_OP_NOR 0x00001508 -#define NV50TCL_LOGIC_OP_EQUIV 0x00001509 -#define NV50TCL_LOGIC_OP_INVERT 0x0000150a -#define NV50TCL_LOGIC_OP_OR_REVERSE 0x0000150b -#define NV50TCL_LOGIC_OP_COPY_INVERTED 0x0000150c -#define NV50TCL_LOGIC_OP_OR_INVERTED 0x0000150d -#define NV50TCL_LOGIC_OP_NAND 0x0000150e -#define NV50TCL_LOGIC_OP_SET 0x0000150f -#define NV50TCL_CLEAR_BUFFERS 0x000019d0 -#define NV50TCL_CLEAR_BUFFERS_Z (1 << 0) -#define NV50TCL_CLEAR_BUFFERS_S (1 << 1) -#define NV50TCL_CLEAR_BUFFERS_R (1 << 2) -#define NV50TCL_CLEAR_BUFFERS_G (1 << 3) -#define NV50TCL_CLEAR_BUFFERS_B (1 << 4) -#define NV50TCL_CLEAR_BUFFERS_A (1 << 5) -#define NV50TCL_CLEAR_BUFFERS_RT_SHIFT 6 -#define NV50TCL_CLEAR_BUFFERS_RT_MASK 0x000003c0 -#define NV50TCL_CLEAR_BUFFERS_LAYER_SHIFT 10 -#define NV50TCL_CLEAR_BUFFERS_LAYER_MASK 0x0007fc00 -#define NV50TCL_COLOR_MASK(x) (0x00001a00+((x)*4)) -#define NV50TCL_COLOR_MASK__SIZE 0x00000008 -#define NV50TCL_COLOR_MASK_R_SHIFT 0 -#define NV50TCL_COLOR_MASK_R_MASK 0x0000000f -#define NV50TCL_COLOR_MASK_G_SHIFT 4 -#define NV50TCL_COLOR_MASK_G_MASK 0x000000f0 -#define NV50TCL_COLOR_MASK_B_SHIFT 8 -#define NV50TCL_COLOR_MASK_B_MASK 0x00000f00 -#define NV50TCL_COLOR_MASK_A_SHIFT 12 -#define NV50TCL_COLOR_MASK_A_MASK 0x0000f000 -#define NV50TCL_STRMOUT_ADDRESS_HIGH(x) (0x00001a80+((x)*16)) -#define NV50TCL_STRMOUT_ADDRESS_HIGH__SIZE 0x00000004 -#define NV50TCL_STRMOUT_ADDRESS_LOW(x) (0x00001a84+((x)*16)) -#define NV50TCL_STRMOUT_ADDRESS_LOW__SIZE 0x00000004 -#define NV50TCL_STRMOUT_NUM_ATTRIBS(x) (0x00001a88+((x)*16)) -#define NV50TCL_STRMOUT_NUM_ATTRIBS__SIZE 0x00000004 -#define NV50TCL_VERTEX_ARRAY_ATTRIB(x) (0x00001ac0+((x)*4)) -#define NV50TCL_VERTEX_ARRAY_ATTRIB__SIZE 0x00000010 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_SHIFT 0 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x0000000f -#define NV50TCL_VERTEX_ARRAY_ATTRIB_CONST (1 << 4) -#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_SHIFT 5 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_MASK 0x0007ffe0 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_SHIFT 19 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_MASK 0x01f80000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 0x00080000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32 0x00100000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16 0x00180000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32 0x00200000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16 0x00280000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8 0x00500000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16 0x00780000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32 0x00900000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8 0x00980000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8 0x00c00000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16 0x00d80000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8 0x00e80000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_2_10_10_10 0x01800000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SHIFT 25 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_MASK 0x0e000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT 0x0e000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM 0x02000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM 0x04000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED 0x0a000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED 0x0c000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT 0x08000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT 0x06000000 -#define NV50TCL_VERTEX_ARRAY_ATTRIB_BGRA (1 << 31) -#define NV50TCL_QUERY_ADDRESS_HIGH 0x00001b00 -#define NV50TCL_QUERY_ADDRESS_LOW 0x00001b04 -#define NV50TCL_QUERY_SEQUENCE 0x00001b08 -#define NV50TCL_QUERY_GET 0x00001b0c - - -#define NV84TCL 0x00008297 - - - -#define NVA0TCL 0x00008397 - - - -#define NVA8TCL 0x00008597 - - - -#define NV50_COMPUTE 0x000050c0 - -#define NV50_COMPUTE_NOP 0x00000100 -#define NV50_COMPUTE_NOTIFY 0x00000104 -#define NV50_COMPUTE_SERIALIZE 0x00000110 -#define NV50_COMPUTE_DMA_NOTIFY 0x00000180 -#define NV50_COMPUTE_DMA_GLOBAL 0x000001a0 -#define NV50_COMPUTE_DMA_QUERY 0x000001a4 -#define NV50_COMPUTE_DMA_LOCAL 0x000001b8 -#define NV50_COMPUTE_DMA_STACK 0x000001bc -#define NV50_COMPUTE_DMA_CODE_CB 0x000001c0 -#define NV50_COMPUTE_DMA_TSC 0x000001c4 -#define NV50_COMPUTE_DMA_TIC 0x000001c8 -#define NV50_COMPUTE_DMA_TEXTURE 0x000001cc -#define NV50_COMPUTE_CP_ADDRESS_HIGH 0x00000210 -#define NV50_COMPUTE_CP_ADDRESS_LOW 0x00000214 -#define NV50_COMPUTE_STACK_ADDRESS_HIGH 0x00000218 -#define NV50_COMPUTE_STACK_ADDRESS_LOW 0x0000021c -#define NV50_COMPUTE_STACK_SIZE_LOG 0x00000220 -#define NV50_COMPUTE_TSC_ADDRESS_HIGH 0x0000022c -#define NV50_COMPUTE_TSC_ADDRESS_LOW 0x00000230 -#define NV50_COMPUTE_TSC_LIMIT 0x00000234 -#define NV50_COMPUTE_CB_ADDR 0x00000238 -#define NV50_COMPUTE_CB_ADDR_ID_SHIFT 8 -#define NV50_COMPUTE_CB_ADDR_ID_MASK 0x003fff00 -#define NV50_COMPUTE_CB_ADDR_BUFFER_SHIFT 0 -#define NV50_COMPUTE_CB_ADDR_BUFFER_MASK 0x0000007f -#define NV50_COMPUTE_CB_DATA(x) (0x0000023c+((x)*4)) -#define NV50_COMPUTE_CB_DATA__SIZE 0x00000010 -#define NV50_COMPUTE_DELAY1 0x00000284 -#define NV50_COMPUTE_WATCHDOG_TIMER 0x00000288 -#define NV50_COMPUTE_DELAY2 0x0000028c -#define NV50_COMPUTE_LOCAL_ADDRESS_HIGH 0x00000294 -#define NV50_COMPUTE_LOCAL_ADDRESS_LOW 0x00000298 -#define NV50_COMPUTE_LOCAL_SIZE_LOG 0x0000029c -#define NV50_COMPUTE_CB_DEF_ADDRESS_HIGH 0x000002a4 -#define NV50_COMPUTE_CB_DEF_ADDRESS_LOW 0x000002a8 -#define NV50_COMPUTE_CB_DEF_SET 0x000002ac -#define NV50_COMPUTE_CB_DEF_SET_SIZE_SHIFT 0 -#define NV50_COMPUTE_CB_DEF_SET_SIZE_MASK 0x0000ffff -#define NV50_COMPUTE_CB_DEF_SET_BUFFER_SHIFT 16 -#define NV50_COMPUTE_CB_DEF_SET_BUFFER_MASK 0x007f0000 -#define NV50_COMPUTE_BLOCK_ALLOC 0x000002b4 -#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_SHIFT 0 -#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_MASK 0x0000ffff -#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_SHIFT 16 -#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_MASK 0xffff0000 -#define NV50_COMPUTE_LANES32_ENABLE 0x000002b8 -#define NV50_COMPUTE_CP_REG_ALLOC_TEMP 0x000002c0 -#define NV50_COMPUTE_TIC_ADDRESS_HIGH 0x000002c4 -#define NV50_COMPUTE_TIC_ADDRESS_LOW 0x000002c8 -#define NV50_COMPUTE_TIC_LIMIT 0x000002cc -#define NV50_COMPUTE_PM_SET(x) (0x000002d0+((x)*4)) -#define NV50_COMPUTE_PM_SET__SIZE 0x00000004 -#define NV50_COMPUTE_PM_CONTROL(x) (0x000002e0+((x)*4)) -#define NV50_COMPUTE_PM_CONTROL__SIZE 0x00000004 -#define NV50_COMPUTE_PM_CONTROL_UNK0 (1 << 0) -#define NV50_COMPUTE_PM_CONTROL_UNK1_SHIFT 4 -#define NV50_COMPUTE_PM_CONTROL_UNK1_MASK 0x00000070 -#define NV50_COMPUTE_PM_CONTROL_UNK2_SHIFT 8 -#define NV50_COMPUTE_PM_CONTROL_UNK2_MASK 0xffffff00 -#define NV50_COMPUTE_LOCAL_WARPS_LOG_ALLOC 0x000002fc -#define NV50_COMPUTE_LOCAL_WARPS_NO_CLAMP 0x00000300 -#define NV50_COMPUTE_STACK_WARPS_LOG_ALLOC 0x00000304 -#define NV50_COMPUTE_STACK_WARPS_NO_CLAMP 0x00000308 -#define NV50_COMPUTE_QUERY_ADDRESS_HIGH 0x00000310 -#define NV50_COMPUTE_QUERY_ADDRESS_LOW 0x00000314 -#define NV50_COMPUTE_QUERY_COUNTER 0x00000318 -#define NV50_COMPUTE_QUERY_GET 0x0000031c -#define NV50_COMPUTE_COND_ADDRESS_HIGH 0x00000320 -#define NV50_COMPUTE_COND_ADDRESS_LOW 0x00000324 -#define NV50_COMPUTE_COND_MODE 0x00000328 -#define NV50_COMPUTE_COND_MODE_NEVER 0x00000000 -#define NV50_COMPUTE_COND_MODE_ALWAYS 0x00000001 -#define NV50_COMPUTE_COND_MODE_RES 0x00000002 -#define NV50_COMPUTE_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 -#define NV50_COMPUTE_COND_MODE_RES_OR_ID 0x00000004 -#define NV50_COMPUTE_LAUNCH 0x00000368 -#define NV50_COMPUTE_USER_PARAM_COUNT 0x00000374 -#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_SHIFT 8 -#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_MASK 0x0000ff00 -#define NV50_COMPUTE_LINKED_TSC 0x00000378 -#define NV50_COMPUTE_CODE_CB_FLUSH 0x00000380 -#define NV50_COMPUTE_GRIDDIM 0x000003a4 -#define NV50_COMPUTE_GRIDDIM_X_SHIFT 0 -#define NV50_COMPUTE_GRIDDIM_X_MASK 0x0000ffff -#define NV50_COMPUTE_GRIDDIM_Y_SHIFT 16 -#define NV50_COMPUTE_GRIDDIM_Y_MASK 0xffff0000 -#define NV50_COMPUTE_SHARED_SIZE 0x000003a8 -#define NV50_COMPUTE_BLOCKDIM_YX 0x000003ac -#define NV50_COMPUTE_BLOCKDIM_YX_X_SHIFT 0 -#define NV50_COMPUTE_BLOCKDIM_YX_X_MASK 0x0000ffff -#define NV50_COMPUTE_BLOCKDIM_YX_Y_SHIFT 16 -#define NV50_COMPUTE_BLOCKDIM_YX_Y_MASK 0xffff0000 -#define NV50_COMPUTE_BLOCKDIM_Z 0x000003b0 -#define NV50_COMPUTE_CP_START_ID 0x000003b4 -#define NV50_COMPUTE_REG_MODE 0x000003b8 -#define NV50_COMPUTE_REG_MODE_PACKED 0x00000001 -#define NV50_COMPUTE_REG_MODE_STRIPED 0x00000002 -#define NV50_COMPUTE_TEX_LIMITS 0x000003bc -#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0 -#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f -#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4 -#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0 -#define NV50_COMPUTE_BIND_TSC 0x000003c0 -#define NV50_COMPUTE_BIND_TSC_VALID (1 << 0) -#define NV50_COMPUTE_BIND_TSC_SAMPLER_SHIFT 4 -#define NV50_COMPUTE_BIND_TSC_SAMPLER_MASK 0x000000f0 -#define NV50_COMPUTE_BIND_TSC_TSC_SHIFT 12 -#define NV50_COMPUTE_BIND_TSC_TSC_MASK 0x001ff000 -#define NV50_COMPUTE_BIND_TIC 0x000003c4 -#define NV50_COMPUTE_BIND_TIC_VALID (1 << 0) -#define NV50_COMPUTE_BIND_TIC_TEXTURE_SHIFT 1 -#define NV50_COMPUTE_BIND_TIC_TEXTURE_MASK 0x000001fe -#define NV50_COMPUTE_BIND_TIC_TIC_SHIFT 9 -#define NV50_COMPUTE_BIND_TIC_TIC_MASK 0x7ffffe00 -#define NV50_COMPUTE_SET_PROGRAM_CB 0x000003c8 -#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_SHIFT 8 -#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_MASK 0x00000f00 -#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_SHIFT 12 -#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000 -#define NV50_COMPUTE_SET_PROGRAM_CB_VALID (1 << 0) -#define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH(x) (0x00000400+((x)*32)) -#define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH__SIZE 0x00000010 -#define NV50_COMPUTE_GLOBAL_ADDRESS_LOW(x) (0x00000404+((x)*32)) -#define NV50_COMPUTE_GLOBAL_ADDRESS_LOW__SIZE 0x00000010 -#define NV50_COMPUTE_GLOBAL_PITCH(x) (0x00000408+((x)*32)) -#define NV50_COMPUTE_GLOBAL_PITCH__SIZE 0x00000010 -#define NV50_COMPUTE_GLOBAL_LIMIT(x) (0x0000040c+((x)*32)) -#define NV50_COMPUTE_GLOBAL_LIMIT__SIZE 0x00000010 -#define NV50_COMPUTE_GLOBAL_MODE(x) (0x00000410+((x)*32)) -#define NV50_COMPUTE_GLOBAL_MODE__SIZE 0x00000010 -#define NV50_COMPUTE_GLOBAL_MODE_LINEAR (1 << 0) -#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_SHIFT 8 -#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_MASK 0x00000f00 -#define NV50_COMPUTE_USER_PARAM(x) (0x00000600+((x)*4)) -#define NV50_COMPUTE_USER_PARAM__SIZE 0x00000040 - - -#define NVC0TCL 0x00009097 - -#define NVC0TCL_SEMAPHORE_ADDRESS_HIGH 0x00000010 -#define NVC0TCL_SEMAPHORE_ADDRESS_LOW 0x00000014 -#define NVC0TCL_NOP 0x00000100 -#define NVC0TCL_NOTIFY_ADDRESS_HIGH 0x00000104 -#define NVC0TCL_NOTIFY_ADDRESS_LOW 0x00000108 -#define NVC0TCL_NOTIFY 0x0000010c -#define NVC0TCL_SERIALIZE 0x00000110 -#define NVC0TCL_EARLY_FRAGMENT_TESTS 0x00000210 -#define NVC0TCL_TESS_MODE 0x00000320 -#define NVC0TCL_TESS_MODE_PRIM_SHIFT 0 -#define NVC0TCL_TESS_MODE_PRIM_MASK 0x0000000f -#define NVC0TCL_TESS_MODE_PRIM_ISOLINES 0x00000000 -#define NVC0TCL_TESS_MODE_PRIM_TRIANGLES 0x00000001 -#define NVC0TCL_TESS_MODE_PRIM_QUADS 0x00000002 -#define NVC0TCL_TESS_MODE_SPACING_SHIFT 4 -#define NVC0TCL_TESS_MODE_SPACING_MASK 0x000000f0 -#define NVC0TCL_TESS_MODE_SPACING_EQUAL 0x00000000 -#define NVC0TCL_TESS_MODE_SPACING_FRACTIONAL_ODD 0x00000010 -#define NVC0TCL_TESS_MODE_SPACING_FRACTIONAL_EVEN 0x00000020 -#define NVC0TCL_TESS_MODE_CW (1 << 8) -#define NVC0TCL_TESS_MODE_CONNECTED (1 << 9) -#define NVC0TCL_TESS_LEVEL_OUTER(x) (0x00000324+((x)*4)) -#define NVC0TCL_TESS_LEVEL_OUTER__SIZE 0x00000004 -#define NVC0TCL_TESS_LEVEL_INNER(x) (0x00000334+((x)*4)) -#define NVC0TCL_TESS_LEVEL_INNER__SIZE 0x00000002 -#define NVC0TCL_RASTERIZE_ENABLE 0x0000037c -#define NVC0TCL_TFB_BUFFER_ENABLE(x) (0x00000380+((x)*32)) -#define NVC0TCL_TFB_BUFFER_ENABLE__SIZE 0x00000004 -#define NVC0TCL_TFB_ADDRESS_HIGH(x) (0x00000384+((x)*32)) -#define NVC0TCL_TFB_ADDRESS_HIGH__SIZE 0x00000004 -#define NVC0TCL_TFB_ADDRESS_LOW(x) (0x00000388+((x)*32)) -#define NVC0TCL_TFB_ADDRESS_LOW__SIZE 0x00000004 -#define NVC0TCL_TFB_BUFFER_SIZE(x) (0x0000038c+((x)*32)) -#define NVC0TCL_TFB_BUFFER_SIZE__SIZE 0x00000004 -#define NVC0TCL_TFB_PRIMITIVE_ID(x) (0x00000390+((x)*32)) -#define NVC0TCL_TFB_PRIMITIVE_ID__SIZE 0x00000004 -#define NVC0TCL_TFB_UNK0700(x) (0x00000700+((x)*16)) -#define NVC0TCL_TFB_UNK0700__SIZE 0x00000004 -#define NVC0TCL_TFB_VARYING_COUNT(x) (0x00000704+((x)*16)) -#define NVC0TCL_TFB_VARYING_COUNT__SIZE 0x00000004 -#define NVC0TCL_TFB_BUFFER_STRIDE(x) (0x00000708+((x)*16)) -#define NVC0TCL_TFB_BUFFER_STRIDE__SIZE 0x00000004 -#define NVC0TCL_TFB_ENABLE 0x00000744 -#define NVC0TCL_LOCAL_BASE 0x0000077c -#define NVC0TCL_UNK0790_ADDRESS_HIGH 0x00000790 -#define NVC0TCL_UNK0790_ADDRESS_LOW 0x00000794 -#define NVC0TCL_RT_ADDRESS_HIGH(x) (0x00000800+((x)*32)) -#define NVC0TCL_RT_ADDRESS_HIGH__SIZE 0x00000008 -#define NVC0TCL_RT_ADDRESS_LOW(x) (0x00000804+((x)*32)) -#define NVC0TCL_RT_ADDRESS_LOW__SIZE 0x00000008 -#define NVC0TCL_RT_HORIZ(x) (0x00000808+((x)*32)) -#define NVC0TCL_RT_HORIZ__SIZE 0x00000008 -#define NVC0TCL_RT_VERT(x) (0x0000080c+((x)*32)) -#define NVC0TCL_RT_VERT__SIZE 0x00000008 -#define NVC0TCL_RT_FORMAT(x) (0x00000810+((x)*32)) -#define NVC0TCL_RT_FORMAT__SIZE 0x00000008 -#define NVC0TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0 -#define NVC0TCL_RT_FORMAT_R32G32B32A32_SINT 0x000000c1 -#define NVC0TCL_RT_FORMAT_R32G32B32A32_UINT 0x000000c2 -#define NVC0TCL_RT_FORMAT_R32G32B32X32_FLOAT 0x000000c3 -#define NVC0TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6 -#define NVC0TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7 -#define NVC0TCL_RT_FORMAT_R16G16B16A16_SINT 0x000000c8 -#define NVC0TCL_RT_FORMAT_R16G16B16A16_UINT 0x000000c9 -#define NVC0TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca -#define NVC0TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb -#define NVC0TCL_RT_FORMAT_R32G32_SINT 0x000000cc -#define NVC0TCL_RT_FORMAT_R32G32_UINT 0x000000cd -#define NVC0TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce -#define NVC0TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf -#define NVC0TCL_RT_FORMAT_A8R8G8B8_SRGB 0x000000d0 -#define NVC0TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1 -#define NVC0TCL_RT_FORMAT_A2B10G10R10_UINT 0x000000d2 -#define NVC0TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d5 -#define NVC0TCL_RT_FORMAT_A8B8G8R8_SRGB 0x000000d6 -#define NVC0TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7 -#define NVC0TCL_RT_FORMAT_A8B8G8R8_SINT 0x000000d8 -#define NVC0TCL_RT_FORMAT_A8B8G8R8_UINT 0x000000d9 -#define NVC0TCL_RT_FORMAT_R16G16_UNORM 0x000000da -#define NVC0TCL_RT_FORMAT_R16G16_SNORM 0x000000db -#define NVC0TCL_RT_FORMAT_R16G16_SINT 0x000000dc -#define NVC0TCL_RT_FORMAT_R16G16_UINT 0x000000dd -#define NVC0TCL_RT_FORMAT_R16G16_FLOAT 0x000000de -#define NVC0TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df -#define NVC0TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0 -#define NVC0TCL_RT_FORMAT_R32_FLOAT 0x000000e5 -#define NVC0TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6 -#define NVC0TCL_RT_FORMAT_X8R8G8B8_SRGB 0x000000e7 -#define NVC0TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8 -#define NVC0TCL_RT_FORMAT_A1R5G5B5_UNORM 0x000000e9 -#define NVC0TCL_RT_FORMAT_R8G8_UNORM 0x000000ea -#define NVC0TCL_RT_FORMAT_R8G8_SNORM 0x000000eb -#define NVC0TCL_RT_FORMAT_R8G8_SINT 0x000000ec -#define NVC0TCL_RT_FORMAT_R8G8_UINT 0x000000ed -#define NVC0TCL_RT_FORMAT_R16_UNORM 0x000000ee -#define NVC0TCL_RT_FORMAT_R16_SNORM 0x000000ef -#define NVC0TCL_RT_FORMAT_R16_SINT 0x000000f0 -#define NVC0TCL_RT_FORMAT_R16_UINT 0x000000f1 -#define NVC0TCL_RT_FORMAT_R16_FLOAT 0x000000f2 -#define NVC0TCL_RT_FORMAT_R8_UNORM 0x000000f3 -#define NVC0TCL_RT_FORMAT_R8_SNORM 0x000000f4 -#define NVC0TCL_RT_FORMAT_R8_SINT 0x000000f5 -#define NVC0TCL_RT_FORMAT_R8_UINT 0x000000f6 -#define NVC0TCL_RT_FORMAT_A8_UNORM 0x000000f7 -#define NVC0TCL_RT_FORMAT_X1R5G5B5_UNORM 0x000000f8 -#define NVC0TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9 -#define NVC0TCL_RT_FORMAT_X8B8G8R8_SRGB 0x000000fa -#define NVC0TCL_RT_TILE_MODE(x) (0x00000814+((x)*32)) -#define NVC0TCL_RT_TILE_MODE__SIZE 0x00000008 -#define NVC0TCL_RT_ARRAY_MODE(x) (0x00000818+((x)*32)) -#define NVC0TCL_RT_ARRAY_MODE__SIZE 0x00000008 -#define NVC0TCL_RT_ARRAY_MODE_LAYERS_SHIFT 0 -#define NVC0TCL_RT_ARRAY_MODE_LAYERS_MASK 0x0000ffff -#define NVC0TCL_RT_ARRAY_MODE_VOLUME (1 << 16) -#define NVC0TCL_RT_LAYER_STRIDE(x) (0x0000081c+((x)*32)) -#define NVC0TCL_RT_LAYER_STRIDE__SIZE 0x00000008 -#define NVC0TCL_VIEWPORT_SCALE_X(x) (0x00000a00+((x)*32)) -#define NVC0TCL_VIEWPORT_SCALE_X__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_SCALE_Y(x) (0x00000a04+((x)*32)) -#define NVC0TCL_VIEWPORT_SCALE_Y__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_SCALE_Z(x) (0x00000a08+((x)*32)) -#define NVC0TCL_VIEWPORT_SCALE_Z__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_TRANSLATE_X(x) (0x00000a0c+((x)*32)) -#define NVC0TCL_VIEWPORT_TRANSLATE_X__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_TRANSLATE_Y(x) (0x00000a10+((x)*32)) -#define NVC0TCL_VIEWPORT_TRANSLATE_Y__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_TRANSLATE_Z(x) (0x00000a14+((x)*32)) -#define NVC0TCL_VIEWPORT_TRANSLATE_Z__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_HORIZ(x) (0x00000c00+((x)*16)) -#define NVC0TCL_VIEWPORT_HORIZ__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_HORIZ_X_SHIFT 0 -#define NVC0TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff -#define NVC0TCL_VIEWPORT_HORIZ_W_SHIFT 16 -#define NVC0TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000 -#define NVC0TCL_VIEWPORT_VERT(x) (0x00000c04+((x)*16)) -#define NVC0TCL_VIEWPORT_VERT__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_VERT_Y_SHIFT 0 -#define NVC0TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff -#define NVC0TCL_VIEWPORT_VERT_H_SHIFT 16 -#define NVC0TCL_VIEWPORT_VERT_H_MASK 0xffff0000 -#define NVC0TCL_DEPTH_RANGE_NEAR(x) (0x00000c08+((x)*16)) -#define NVC0TCL_DEPTH_RANGE_NEAR__SIZE 0x00000010 -#define NVC0TCL_DEPTH_RANGE_FAR(x) (0x00000c0c+((x)*16)) -#define NVC0TCL_DEPTH_RANGE_FAR__SIZE 0x00000010 -#define NVC0TCL_VIEWPORT_CLIP_HORIZ(x) (0x00000d00+((x)*8)) -#define NVC0TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 -#define NVC0TCL_VIEWPORT_CLIP_HORIZ_MIN_SHIFT 0 -#define NVC0TCL_VIEWPORT_CLIP_HORIZ_MIN_MASK 0x0000ffff -#define NVC0TCL_VIEWPORT_CLIP_HORIZ_MAX_SHIFT 16 -#define NVC0TCL_VIEWPORT_CLIP_HORIZ_MAX_MASK 0xffff0000 -#define NVC0TCL_VIEWPORT_CLIP_VERT(x) (0x00000d04+((x)*8)) -#define NVC0TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 -#define NVC0TCL_VIEWPORT_CLIP_VERT_MIN_SHIFT 0 -#define NVC0TCL_VIEWPORT_CLIP_VERT_MIN_MASK 0x0000ffff -#define NVC0TCL_VIEWPORT_CLIP_VERT_MAX_SHIFT 16 -#define NVC0TCL_VIEWPORT_CLIP_VERT_MAX_MASK 0xffff0000 -#define NVC0TCL_CLIPID_REGION_HORIZ(x) (0x00000d40+((x)*8)) -#define NVC0TCL_CLIPID_REGION_HORIZ__SIZE 0x00000004 -#define NVC0TCL_CLIPID_REGION_VERT(x) (0x00000d44+((x)*8)) -#define NVC0TCL_CLIPID_REGION_VERT__SIZE 0x00000004 -#define NVC0TCL_VERTEX_BUFFER_FIRST 0x00000d74 -#define NVC0TCL_VERTEX_BUFFER_COUNT 0x00000d78 -#define NVC0TCL_CLEAR_COLOR(x) (0x00000d80+((x)*4)) -#define NVC0TCL_CLEAR_COLOR__SIZE 0x00000004 -#define NVC0TCL_CLEAR_DEPTH 0x00000d90 -#define NVC0TCL_STACK_ADDRESS_HIGH 0x00000d94 -#define NVC0TCL_STACK_ADDRESS_LOW 0x00000d98 -#define NVC0TCL_STACK_SIZE_LOG 0x00000d9c -#define NVC0TCL_CLEAR_STENCIL 0x00000da0 -#define NVC0TCL_POLYGON_SMOOTH_ENABLE 0x00000db4 -#define NVC0TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0 -#define NVC0TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4 -#define NVC0TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8 -#define NVC0TCL_PATCH_VERTICES 0x00000dcc -#define NVC0TCL_WATCHDOG_TIMER 0x00000de4 -#define NVC0TCL_WINDOW_OFFSET_X 0x00000df8 -#define NVC0TCL_WINDOW_OFFSET_Y 0x00000dfc -#define NVC0TCL_SCISSOR_ENABLE(x) (0x00000e00+((x)*16)) -#define NVC0TCL_SCISSOR_ENABLE__SIZE 0x00000010 -#define NVC0TCL_SCISSOR_HORIZ(x) (0x00000e04+((x)*16)) -#define NVC0TCL_SCISSOR_HORIZ__SIZE 0x00000010 -#define NVC0TCL_SCISSOR_HORIZ_MIN_SHIFT 0 -#define NVC0TCL_SCISSOR_HORIZ_MIN_MASK 0x0000ffff -#define NVC0TCL_SCISSOR_HORIZ_MAX_SHIFT 16 -#define NVC0TCL_SCISSOR_HORIZ_MAX_MASK 0xffff0000 -#define NVC0TCL_SCISSOR_VERT(x) (0x00000e08+((x)*16)) -#define NVC0TCL_SCISSOR_VERT__SIZE 0x00000010 -#define NVC0TCL_SCISSOR_VERT_MIN_SHIFT 0 -#define NVC0TCL_SCISSOR_VERT_MIN_MASK 0x0000ffff -#define NVC0TCL_SCISSOR_VERT_MAX_SHIFT 16 -#define NVC0TCL_SCISSOR_VERT_MAX_MASK 0xffff0000 -#define NVC0TCL_LOCAL_WARPS_LOG_ALLOC 0x00000f44 -#define NVC0TCL_LOCAL_WARPS_NO_CLAMP 0x00000f48 -#define NVC0TCL_STACK_WARPS_LOG_ALLOC 0x00000f4c -#define NVC0TCL_STACK_WARPS_NO_CLAMP 0x00000f50 -#define NVC0TCL_STENCIL_BACK_FUNC_REF 0x00000f54 -#define NVC0TCL_STENCIL_BACK_MASK 0x00000f58 -#define NVC0TCL_STENCIL_BACK_FUNC_MASK 0x00000f5c -#define NVC0TCL_VERTEX_RUNOUT_HIGH 0x00000f84 -#define NVC0TCL_VERTEX_RUNOUT_LOW 0x00000f88 -#define NVC0TCL_DEPTH_BOUNDS(x) (0x00000f9c+((x)*4)) -#define NVC0TCL_DEPTH_BOUNDS__SIZE 0x00000002 -#define NVC0TCL_MSAA_MASK(x) (0x00000fbc+((x)*4)) -#define NVC0TCL_MSAA_MASK__SIZE 0x00000004 -#define NVC0TCL_CLIPID_ADDRESS_HIGH 0x00000fcc -#define NVC0TCL_CLIPID_ADDRESS_LOW 0x00000fd0 -#define NVC0TCL_ZETA_ADDRESS_HIGH 0x00000fe0 -#define NVC0TCL_ZETA_ADDRESS_LOW 0x00000fe4 -#define NVC0TCL_ZETA_FORMAT 0x00000fe8 -#define NVC0TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a -#define NVC0TCL_ZETA_FORMAT_Z16_UNORM 0x00000013 -#define NVC0TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014 -#define NVC0TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015 -#define NVC0TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016 -#define NVC0TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019 -#define NVC0TCL_ZETA_TILE_MODE 0x00000fec -#define NVC0TCL_ZETA_LAYER_STRIDE 0x00000ff0 -#define NVC0TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4 -#define NVC0TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16 -#define NVC0TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000 -#define NVC0TCL_SCREEN_SCISSOR_HORIZ_X_SHIFT 0 -#define NVC0TCL_SCREEN_SCISSOR_HORIZ_X_MASK 0x0000ffff -#define NVC0TCL_SCREEN_SCISSOR_VERT 0x00000ff8 -#define NVC0TCL_SCREEN_SCISSOR_VERT_H_SHIFT 16 -#define NVC0TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000 -#define NVC0TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0 -#define NVC0TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff -#define NVC0TCL_VTX_ATTR_DEFINE 0x0000114c -#define NVC0TCL_VTX_ATTR_DEFINE_ATTR_SHIFT 0 -#define NVC0TCL_VTX_ATTR_DEFINE_ATTR_MASK 0x0000003f -#define NVC0TCL_VTX_ATTR_DEFINE_COMP_SHIFT 8 -#define NVC0TCL_VTX_ATTR_DEFINE_COMP_MASK 0x00000f00 -#define NVC0TCL_VTX_ATTR_DEFINE_SIZE_SHIFT 12 -#define NVC0TCL_VTX_ATTR_DEFINE_SIZE_MASK 0x0000f000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_SHIFT 16 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_MASK 0x000f0000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_FLOAT 0x00070000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_SNORM 0x00010000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_UNORM 0x00020000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_USCALED 0x00050000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_SSCALED 0x00060000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_UINT 0x00040000 -#define NVC0TCL_VTX_ATTR_DEFINE_TYPE_SINT 0x00030000 -#define NVC0TCL_VTX_ATTR_DATA(x) (0x00001150+((x)*4)) -#define NVC0TCL_VTX_ATTR_DATA__SIZE 0x00000004 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT(x) (0x00001160+((x)*4)) -#define NVC0TCL_VERTEX_ATTRIB_FORMAT__SIZE 0x00000020 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_BUFFER_SHIFT 0 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_BUFFER_MASK 0x0000003f -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_CONST (1 << 6) -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_OFFSET_SHIFT 7 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_OFFSET_MASK 0x001fff80 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_SHIFT 21 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_MASK 0x07e00000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_32_32_32_32 0x00200000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_32_32_32 0x00400000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_16_16_16_16 0x00600000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_32_32 0x00800000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_16_16_16 0x00a00000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_8_8_8_8 0x01400000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_16_16 0x01e00000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_32 0x02400000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_8_8_8 0x02600000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_8_8 0x03000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_16 0x03600000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_8 0x03a00000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_FORMAT_2_10_10_10 0x06000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_SHIFT 27 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_MASK 0x78000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT 0x38000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_SNORM 0x08000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_UNORM 0x10000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_USCALED 0x28000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_SSCALED 0x30000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_UINT 0x20000000 -#define NVC0TCL_VERTEX_ATTRIB_FORMAT_TYPE_SINT 0x18000000 -#define NVC0TCL_RT_CONTROL 0x0000121c -#define NVC0TCL_RT_CONTROL_COUNT_SHIFT 0 -#define NVC0TCL_RT_CONTROL_COUNT_MASK 0x0000000f -#define NVC0TCL_RT_CONTROL_MAP0_SHIFT 4 -#define NVC0TCL_RT_CONTROL_MAP0_MASK 0x00000070 -#define NVC0TCL_RT_CONTROL_MAP1_SHIFT 7 -#define NVC0TCL_RT_CONTROL_MAP1_MASK 0x00000380 -#define NVC0TCL_RT_CONTROL_MAP2_SHIFT 10 -#define NVC0TCL_RT_CONTROL_MAP2_MASK 0x00001c00 -#define NVC0TCL_RT_CONTROL_MAP3_SHIFT 13 -#define NVC0TCL_RT_CONTROL_MAP3_MASK 0x0000e000 -#define NVC0TCL_RT_CONTROL_MAP4_SHIFT 16 -#define NVC0TCL_RT_CONTROL_MAP4_MASK 0x00070000 -#define NVC0TCL_RT_CONTROL_MAP5_SHIFT 19 -#define NVC0TCL_RT_CONTROL_MAP5_MASK 0x00380000 -#define NVC0TCL_RT_CONTROL_MAP6_SHIFT 22 -#define NVC0TCL_RT_CONTROL_MAP6_MASK 0x01c00000 -#define NVC0TCL_RT_CONTROL_MAP7_SHIFT 25 -#define NVC0TCL_RT_CONTROL_MAP7_MASK 0x0e000000 -#define NVC0TCL_ZETA_HORIZ 0x00001228 -#define NVC0TCL_ZETA_VERT 0x0000122c -#define NVC0TCL_ZETA_ARRAY_MODE 0x00001230 -#define NVC0TCL_ZETA_ARRAY_MODE_LAYERS_SHIFT 0 -#define NVC0TCL_ZETA_ARRAY_MODE_LAYERS_MASK 0x0000ffff -#define NVC0TCL_ZETA_ARRAY_MODE_UNK (1 << 16) -#define NVC0TCL_LINKED_TSC 0x00001234 -#define NVC0TCL_FP_RESULT_COUNT 0x00001298 -#define NVC0TCL_DEPTH_TEST_ENABLE 0x000012cc -#define NVC0TCL_SHADE_MODEL 0x000012d4 -#define NVC0TCL_SHADE_MODEL_FLAT 0x00001d00 -#define NVC0TCL_SHADE_MODEL_SMOOTH 0x00001d01 -#define NVC0TCL_BLEND_INDEPENDENT 0x000012e4 -#define NVC0TCL_DEPTH_WRITE_ENABLE 0x000012e8 -#define NVC0TCL_ALPHA_TEST_ENABLE 0x000012ec -#define NVC0TCL_PM_SET(x) (0x000012f0+((x)*4)) -#define NVC0TCL_PM_SET__SIZE 0x00000004 -#define NVC0TCL_VB_ELEMENT_U8_SETUP 0x00001300 -#define NVC0TCL_VB_ELEMENT_U8_SETUP_OFFSET_SHIFT 30 -#define NVC0TCL_VB_ELEMENT_U8_SETUP_OFFSET_MASK 0xc0000000 -#define NVC0TCL_VB_ELEMENT_U8_SETUP_COUNT_SHIFT 0 -#define NVC0TCL_VB_ELEMENT_U8_SETUP_COUNT_MASK 0x3fffffff -#define NVC0TCL_VB_ELEMENT_U8 0x00001304 -#define NVC0TCL_VB_ELEMENT_U8_I0_SHIFT 0 -#define NVC0TCL_VB_ELEMENT_U8_I0_MASK 0x000000ff -#define NVC0TCL_VB_ELEMENT_U8_I1_SHIFT 8 -#define NVC0TCL_VB_ELEMENT_U8_I1_MASK 0x0000ff00 -#define NVC0TCL_VB_ELEMENT_U8_I2_SHIFT 16 -#define NVC0TCL_VB_ELEMENT_U8_I2_MASK 0x00ff0000 -#define NVC0TCL_VB_ELEMENT_U8_I3_SHIFT 24 -#define NVC0TCL_VB_ELEMENT_U8_I3_MASK 0xff000000 -#define NVC0TCL_DEPTH_TEST_FUNC 0x0000130c -#define NVC0TCL_DEPTH_TEST_FUNC_NEVER 0x00000200 -#define NVC0TCL_DEPTH_TEST_FUNC_LESS 0x00000201 -#define NVC0TCL_DEPTH_TEST_FUNC_EQUAL 0x00000202 -#define NVC0TCL_DEPTH_TEST_FUNC_LEQUAL 0x00000203 -#define NVC0TCL_DEPTH_TEST_FUNC_GREATER 0x00000204 -#define NVC0TCL_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205 -#define NVC0TCL_DEPTH_TEST_FUNC_GEQUAL 0x00000206 -#define NVC0TCL_DEPTH_TEST_FUNC_ALWAYS 0x00000207 -#define NVC0TCL_ALPHA_TEST_REF 0x00001310 -#define NVC0TCL_ALPHA_TEST_FUNC 0x00001314 -#define NVC0TCL_ALPHA_TEST_FUNC_NEVER 0x00000200 -#define NVC0TCL_ALPHA_TEST_FUNC_LESS 0x00000201 -#define NVC0TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202 -#define NVC0TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203 -#define NVC0TCL_ALPHA_TEST_FUNC_GREATER 0x00000204 -#define NVC0TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205 -#define NVC0TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206 -#define NVC0TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NVC0TCL_BLEND_COLOR(x) (0x0000131c+((x)*4)) -#define NVC0TCL_BLEND_COLOR__SIZE 0x00000004 -#define NVC0TCL_TIC_FLUSH 0x00001330 -#define NVC0TCL_TSC_FLUSH 0x00001334 -#define NVC0TCL_TEX_CACHE_CTL 0x00001338 -#define NVC0TCL_BLEND_EQUATION_RGB 0x00001340 -#define NVC0TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 -#define NVC0TCL_BLEND_EQUATION_RGB_MIN 0x00008007 -#define NVC0TCL_BLEND_EQUATION_RGB_MAX 0x00008008 -#define NVC0TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a -#define NVC0TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NVC0TCL_BLEND_FUNC_SRC_RGB 0x00001344 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_FUNC_DST_RGB 0x00001348 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNC_DST_RGB_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNC_DST_RGB_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_EQUATION_ALPHA 0x0000134c -#define NVC0TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x00008006 -#define NVC0TCL_BLEND_EQUATION_ALPHA_MIN 0x00008007 -#define NVC0TCL_BLEND_EQUATION_ALPHA_MAX 0x00008008 -#define NVC0TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x0000800a -#define NVC0TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA 0x00001350 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA 0x00001358 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_STENCIL_ENABLE 0x00001380 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL 0x00001384 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL 0x00001388 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS 0x0000138c -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC 0x00001390 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 -#define NVC0TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 -#define NVC0TCL_STENCIL_FRONT_FUNC_REF 0x00001394 -#define NVC0TCL_STENCIL_FRONT_MASK 0x00001398 -#define NVC0TCL_STENCIL_FRONT_FUNC_MASK 0x0000139c -#define NVC0TCL_FRAG_COLOR_CLAMP_EN 0x000013a8 -#define NVC0TCL_Y_ORIGIN_BOTTOM 0x000013ac -#define NVC0TCL_LINE_WIDTH(x) (0x000013b0+((x)*4)) -#define NVC0TCL_LINE_WIDTH__SIZE 0x00000002 -#define NVC0TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4)) -#define NVC0TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008 -#define NVC0TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420 -#define NVC0TCL_FENCE 0x0000142c -#define NVC0TCL_VB_ELEMENT_BASE 0x00001434 -#define NVC0TCL_INSTANCE_BASE 0x00001438 -#define NVC0TCL_CODE_CB_FLUSH 0x00001440 -#define NVC0TCL_CLIPID_HEIGHT 0x00001504 -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510 -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_6 (1 << 6) -#define NVC0TCL_VP_CLIP_DISTANCE_ENABLE_7 (1 << 7) -#define NVC0TCL_SAMPLECNT_ENABLE 0x00001514 -#define NVC0TCL_POINT_SIZE 0x00001518 -#define NVC0TCL_POINT_SPRITE_ENABLE 0x00001520 -#define NVC0TCL_SAMPLECNT_RESET 0x00001530 -#define NVC0TCL_MULTISAMPLE_ZETA_ENABLE 0x00001534 -#define NVC0TCL_ZETA_ENABLE 0x00001538 -#define NVC0TCL_MULTISAMPLE_CTRL 0x0000153c -#define NVC0TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0) -#define NVC0TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4) -#define NVC0TCL_NOPERSPECTIVE_BITMAP(x) (0x00001540+((x)*4)) -#define NVC0TCL_NOPERSPECTIVE_BITMAP__SIZE 0x00000004 -#define NVC0TCL_COND_ADDRESS_HIGH 0x00001550 -#define NVC0TCL_COND_ADDRESS_LOW 0x00001554 -#define NVC0TCL_COND_MODE 0x00001558 -#define NVC0TCL_COND_MODE_NEVER 0x00000000 -#define NVC0TCL_COND_MODE_ALWAYS 0x00000001 -#define NVC0TCL_COND_MODE_RES 0x00000002 -#define NVC0TCL_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 -#define NVC0TCL_COND_MODE_RES_OR_ID 0x00000004 -#define NVC0TCL_TSC_ADDRESS_HIGH 0x0000155c -#define NVC0TCL_TSC_ADDRESS_LOW 0x00001560 -#define NVC0TCL_TSC_LIMIT 0x00001564 -#define NVC0TCL_POLYGON_OFFSET_FACTOR 0x0000156c -#define NVC0TCL_LINE_SMOOTH_ENABLE 0x00001570 -#define NVC0TCL_TIC_ADDRESS_HIGH 0x00001574 -#define NVC0TCL_TIC_ADDRESS_LOW 0x00001578 -#define NVC0TCL_TIC_LIMIT 0x0000157c -#define NVC0TCL_PM_CONTROL(x) (0x00001580+((x)*4)) -#define NVC0TCL_PM_CONTROL__SIZE 0x00000004 -#define NVC0TCL_PM_CONTROL_UNK0 (1 << 0) -#define NVC0TCL_PM_CONTROL_UNK1_SHIFT 4 -#define NVC0TCL_PM_CONTROL_UNK1_MASK 0x00000070 -#define NVC0TCL_PM_CONTROL_UNK2_SHIFT 8 -#define NVC0TCL_PM_CONTROL_UNK2_MASK 0xffffff00 -#define NVC0TCL_STENCIL_TWO_SIDE_ENABLE 0x00001594 -#define NVC0TCL_STENCIL_BACK_OP_FAIL 0x00001598 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a -#define NVC0TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL 0x0000159c -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS 0x000015a0 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 -#define NVC0TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC 0x000015a4 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 -#define NVC0TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 -#define NVC0TCL_MULTISAMPLE_COLOR_ENABLE 0x000015b4 -#define NVC0TCL_FRAMEBUFFER_SRGB 0x000015b8 -#define NVC0TCL_POLYGON_OFFSET_UNITS 0x000015bc -#define NVC0TCL_GP_BUILTIN_RESULT_EN 0x000015cc -#define NVC0TCL_GP_BUILTIN_RESULT_EN_VPORT (1 << 0) -#define NVC0TCL_GP_BUILTIN_RESULT_EN_LAYER (1 << 16) -#define NVC0TCL_MULTISAMPLE_MODE 0x000015d0 -#define NVC0TCL_MULTISAMPLE_MODE_1X 0x00000000 -#define NVC0TCL_MULTISAMPLE_MODE_2XMS 0x00000001 -#define NVC0TCL_MULTISAMPLE_MODE_4XMS 0x00000002 -#define NVC0TCL_MULTISAMPLE_MODE_8XMS 0x00000004 -#define NVC0TCL_MULTISAMPLE_MODE_4XMS_4XCS 0x00000008 -#define NVC0TCL_MULTISAMPLE_MODE_4XMS_12XCS 0x00000009 -#define NVC0TCL_MULTISAMPLE_MODE_8XMS_8XCS 0x0000000a -#define NVC0TCL_EDGEFLAG_ENABLE 0x000015e4 -#define NVC0TCL_VB_ELEMENT_U32 0x000015e8 -#define NVC0TCL_VB_ELEMENT_U16_SETUP 0x000015ec -#define NVC0TCL_VB_ELEMENT_U16_SETUP_OFFSET_SHIFT 30 -#define NVC0TCL_VB_ELEMENT_U16_SETUP_OFFSET_MASK 0xc0000000 -#define NVC0TCL_VB_ELEMENT_U16_SETUP_COUNT_SHIFT 0 -#define NVC0TCL_VB_ELEMENT_U16_SETUP_COUNT_MASK 0x3fffffff -#define NVC0TCL_VB_ELEMENT_U16 0x000015f0 -#define NVC0TCL_VB_ELEMENT_U16_I0_SHIFT 0 -#define NVC0TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff -#define NVC0TCL_VB_ELEMENT_U16_I1_SHIFT 16 -#define NVC0TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 -#define NVC0TCL_VERTEX_BASE_HIGH 0x000015f4 -#define NVC0TCL_VERTEX_BASE_LOW 0x000015f8 -#define NVC0TCL_CODE_ADDRESS_HIGH 0x00001608 -#define NVC0TCL_CODE_ADDRESS_LOW 0x0000160c -#define NVC0TCL_VERTEX_BEGIN 0x00001618 -#define NVC0TCL_VERTEX_BEGIN_MODE_SHIFT 0 -#define NVC0TCL_VERTEX_BEGIN_MODE_MASK 0x0000000f -#define NVC0TCL_VERTEX_BEGIN_MODE_POINTS 0x00000000 -#define NVC0TCL_VERTEX_BEGIN_MODE_LINES 0x00000001 -#define NVC0TCL_VERTEX_BEGIN_MODE_LINE_LOOP 0x00000002 -#define NVC0TCL_VERTEX_BEGIN_MODE_LINE_STRIP 0x00000003 -#define NVC0TCL_VERTEX_BEGIN_MODE_TRIANGLES 0x00000004 -#define NVC0TCL_VERTEX_BEGIN_MODE_TRIANGLE_STRIP 0x00000005 -#define NVC0TCL_VERTEX_BEGIN_MODE_TRIANGLE_FAN 0x00000006 -#define NVC0TCL_VERTEX_BEGIN_MODE_QUADS 0x00000007 -#define NVC0TCL_VERTEX_BEGIN_MODE_QUAD_STRIP 0x00000008 -#define NVC0TCL_VERTEX_BEGIN_MODE_POLYGON 0x00000009 -#define NVC0TCL_VERTEX_BEGIN_MODE_LINES_ADJACENCY 0x0000000a -#define NVC0TCL_VERTEX_BEGIN_MODE_LINE_STRIP_ADJACENCY 0x0000000b -#define NVC0TCL_VERTEX_BEGIN_MODE_TRIANGLES_ADJACENCY 0x0000000c -#define NVC0TCL_VERTEX_BEGIN_MODE_TRIANGLE_STRIP_ADJACENCY 0x0000000d -#define NVC0TCL_VERTEX_BEGIN_MODE_PATCHES 0x0000000e -#define NVC0TCL_VERTEX_BEGIN_INSTANCE (1 << 26) -#define NVC0TCL_VERTEX_END 0x00001614 -#define NVC0TCL_VERTEX_DATA 0x00001640 -#define NVC0TCL_PRIM_RESTART_ENABLE 0x00001644 -#define NVC0TCL_PRIM_RESTART_INDEX 0x00001648 -#define NVC0TCL_POINT_SMOOTH_ENABLE 0x00001658 -#define NVC0TCL_POINT_SPRITE_CTRL 0x00001660 -#define NVC0TCL_LINE_STIPPLE_ENABLE 0x0000166c -#define NVC0TCL_LINE_STIPPLE_PATTERN 0x00001680 -#define NVC0TCL_PROVOKING_VERTEX_LAST 0x00001684 -#define NVC0TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688 -#define NVC0TCL_POLYGON_STIPPLE_ENABLE 0x0000168c -#define NVC0TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4)) -#define NVC0TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 -#define NVC0TCL_UNK17BC_ADDRESS_HIGH 0x000017bc -#define NVC0TCL_UNK17BC_ADDRESS_LOW 0x000017c0 -#define NVC0TCL_UNK17BC_LIMIT 0x000017c4 -#define NVC0TCL_VP_POINT_SIZE_EN 0x00001910 -#define NVC0TCL_CULL_FACE_ENABLE 0x00001918 -#define NVC0TCL_FRONT_FACE 0x0000191c -#define NVC0TCL_FRONT_FACE_CW 0x00000900 -#define NVC0TCL_FRONT_FACE_CCW 0x00000901 -#define NVC0TCL_CULL_FACE 0x00001920 -#define NVC0TCL_CULL_FACE_FRONT 0x00000404 -#define NVC0TCL_CULL_FACE_BACK 0x00000405 -#define NVC0TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NVC0TCL_VIEWPORT_TRANSFORM_EN 0x0000192c -#define NVC0TCL_VIEW_VOLUME_CLIP_CTRL 0x0000193c -#define NVC0TCL_VIEWPORT_CLIP_RECTS_EN 0x0000194c -#define NVC0TCL_VIEWPORT_CLIP_MODE 0x00001950 -#define NVC0TCL_VIEWPORT_CLIP_MODE_INCLUDE 0x00000000 -#define NVC0TCL_VIEWPORT_CLIP_MODE_EXCLUDE 0x00000001 -#define NVC0TCL_VIEWPORT_CLIP_MODE_UNKNOWN 0x00000002 -#define NVC0TCL_FP_ZORDER_CTRL 0x0000196c -#define NVC0TCL_CLIPID_ENABLE 0x0000197c -#define NVC0TCL_CLIPID_WIDTH 0x00001980 -#define NVC0TCL_CLIPID_ID 0x00001984 -#define NVC0TCL_REG_MODE 0x000019a0 -#define NVC0TCL_REG_MODE_PACKED 0x00000001 -#define NVC0TCL_REG_MODE_STRIPED 0x00000002 -#define NVC0TCL_FP_CONTROL 0x000019a8 -#define NVC0TCL_FP_CONTROL_MULTIPLE_RESULTS (1 << 0) -#define NVC0TCL_FP_CONTROL_EXPORTS_Z (1 << 8) -#define NVC0TCL_FP_CONTROL_USES_KIL (1 << 20) -#define NVC0TCL_DEPTH_BOUNDS_EN 0x000019bc -#define NVC0TCL_LOGIC_OP_ENABLE 0x000019c4 -#define NVC0TCL_LOGIC_OP 0x000019c8 -#define NVC0TCL_LOGIC_OP_CLEAR 0x00001500 -#define NVC0TCL_LOGIC_OP_AND 0x00001501 -#define NVC0TCL_LOGIC_OP_AND_REVERSE 0x00001502 -#define NVC0TCL_LOGIC_OP_COPY 0x00001503 -#define NVC0TCL_LOGIC_OP_AND_INVERTED 0x00001504 -#define NVC0TCL_LOGIC_OP_NOOP 0x00001505 -#define NVC0TCL_LOGIC_OP_XOR 0x00001506 -#define NVC0TCL_LOGIC_OP_OR 0x00001507 -#define NVC0TCL_LOGIC_OP_NOR 0x00001508 -#define NVC0TCL_LOGIC_OP_EQUIV 0x00001509 -#define NVC0TCL_LOGIC_OP_INVERT 0x0000150a -#define NVC0TCL_LOGIC_OP_OR_REVERSE 0x0000150b -#define NVC0TCL_LOGIC_OP_COPY_INVERTED 0x0000150c -#define NVC0TCL_LOGIC_OP_OR_INVERTED 0x0000150d -#define NVC0TCL_LOGIC_OP_NAND 0x0000150e -#define NVC0TCL_LOGIC_OP_SET 0x0000150f -#define NVC0TCL_CLEAR_BUFFERS 0x000019d0 -#define NVC0TCL_CLEAR_BUFFERS_Z (1 << 0) -#define NVC0TCL_CLEAR_BUFFERS_S (1 << 1) -#define NVC0TCL_CLEAR_BUFFERS_R (1 << 2) -#define NVC0TCL_CLEAR_BUFFERS_G (1 << 3) -#define NVC0TCL_CLEAR_BUFFERS_B (1 << 4) -#define NVC0TCL_CLEAR_BUFFERS_A (1 << 5) -#define NVC0TCL_CLEAR_BUFFERS_RT_SHIFT 6 -#define NVC0TCL_CLEAR_BUFFERS_RT_MASK 0x000003c0 -#define NVC0TCL_CLEAR_BUFFERS_LAYER_SHIFT 10 -#define NVC0TCL_CLEAR_BUFFERS_LAYER_MASK 0x0007fc00 -#define NVC0TCL_COLOR_MASK(x) (0x00001a00+((x)*4)) -#define NVC0TCL_COLOR_MASK__SIZE 0x00000008 -#define NVC0TCL_COLOR_MASK_R_SHIFT 0 -#define NVC0TCL_COLOR_MASK_R_MASK 0x0000000f -#define NVC0TCL_COLOR_MASK_G_SHIFT 4 -#define NVC0TCL_COLOR_MASK_G_MASK 0x000000f0 -#define NVC0TCL_COLOR_MASK_B_SHIFT 8 -#define NVC0TCL_COLOR_MASK_B_MASK 0x00000f00 -#define NVC0TCL_COLOR_MASK_A_SHIFT 12 -#define NVC0TCL_COLOR_MASK_A_MASK 0x0000f000 -#define NVC0TCL_QUERY_ADDRESS_HIGH 0x00001b00 -#define NVC0TCL_QUERY_ADDRESS_LOW 0x00001b04 -#define NVC0TCL_QUERY_SEQUENCE 0x00001b08 -#define NVC0TCL_QUERY_GET 0x00001b0c -#define NVC0TCL_VERTEX_ARRAY_FETCH(x) (0x00001c00+((x)*16)) -#define NVC0TCL_VERTEX_ARRAY_FETCH__SIZE 0x00000020 -#define NVC0TCL_VERTEX_ARRAY_FETCH_STRIDE_SHIFT 0 -#define NVC0TCL_VERTEX_ARRAY_FETCH_STRIDE_MASK 0x00000fff -#define NVC0TCL_VERTEX_ARRAY_FETCH_ENABLE (1 << 12) -#define NVC0TCL_BLEND_EQUATIONI_RGB(x) (0x00001e04+((x)*32)) -#define NVC0TCL_BLEND_EQUATIONI_RGB__SIZE 0x00000008 -#define NVC0TCL_BLEND_EQUATIONI_RGB_FUNC_ADD 0x00008006 -#define NVC0TCL_BLEND_EQUATIONI_RGB_MIN 0x00008007 -#define NVC0TCL_BLEND_EQUATIONI_RGB_MAX 0x00008008 -#define NVC0TCL_BLEND_EQUATIONI_RGB_FUNC_SUBTRACT 0x0000800a -#define NVC0TCL_BLEND_EQUATIONI_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NVC0TCL_BLEND_FUNCI_SRC_RGB(x) (0x00001e08+((x)*32)) -#define NVC0TCL_BLEND_FUNCI_SRC_RGB__SIZE 0x00000008 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNCI_SRC_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_FUNCI_DST_RGB(x) (0x00001e0c+((x)*32)) -#define NVC0TCL_BLEND_FUNCI_DST_RGB__SIZE 0x00000008 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNCI_DST_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_EQUATIONI_ALPHA(x) (0x00001e10+((x)*32)) -#define NVC0TCL_BLEND_EQUATIONI_ALPHA__SIZE 0x00000008 -#define NVC0TCL_BLEND_EQUATIONI_ALPHA_FUNC_ADD 0x00008006 -#define NVC0TCL_BLEND_EQUATIONI_ALPHA_MIN 0x00008007 -#define NVC0TCL_BLEND_EQUATIONI_ALPHA_MAX 0x00008008 -#define NVC0TCL_BLEND_EQUATIONI_ALPHA_FUNC_SUBTRACT 0x0000800a -#define NVC0TCL_BLEND_EQUATIONI_ALPHA_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA(x) (0x00001e14+((x)*32)) -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA__SIZE 0x00000008 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNCI_SRC_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA(x) (0x00001e18+((x)*32)) -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA__SIZE 0x00000008 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ZERO 0x00004000 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE 0x00004001 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_SRC_COLOR 0x00004300 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_SRC_ALPHA 0x00004302 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_DST_ALPHA 0x00004304 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_DST_COLOR 0x00004306 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_SRC_ALPHA_SATURATE 0x00004308 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_CONSTANT_COLOR 0x0000c001 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_CONSTANT_ALPHA 0x0000c003 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_SRC1_COLOR 0x0000c900 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_SRC1_ALPHA 0x0000c902 -#define NVC0TCL_BLEND_FUNCI_DST_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 -#define NVC0TCL_SP_SELECT(x) (0x00002000+((x)*64)) -#define NVC0TCL_SP_SELECT__SIZE 0x00000006 -#define NVC0TCL_SP_SELECT_ENABLE (1 << 0) -#define NVC0TCL_SP_SELECT_PROGRAM_SHIFT 4 -#define NVC0TCL_SP_SELECT_PROGRAM_MASK 0x000000f0 -#define NVC0TCL_SP_START_ID(x) (0x00002004+((x)*64)) -#define NVC0TCL_SP_START_ID__SIZE 0x00000006 -#define NVC0TCL_SP_GPR_ALLOC(x) (0x0000200c+((x)*64)) -#define NVC0TCL_SP_GPR_ALLOC__SIZE 0x00000006 -#define NVC0TCL_CB_SIZE 0x00002380 -#define NVC0TCL_CB_BIND(x) (0x00002410+((x)*32)) -#define NVC0TCL_CB_BIND__SIZE 0x00000005 -#define NVC0TCL_CB_BIND_VALID (1 << 0) -#define NVC0TCL_CB_BIND_INDEX_SHIFT 4 -#define NVC0TCL_CB_BIND_INDEX_MASK 0x000000f0 -#define NVC0TCL_BIND_TIC(x) (0x00002404+((x)*32)) -#define NVC0TCL_BIND_TIC__SIZE 0x00000005 -#define NVC0TCL_BIND_TIC_ACTIVE (1 << 0) -#define NVC0TCL_BIND_TIC_TEXTURE_SHIFT 1 -#define NVC0TCL_BIND_TIC_TEXTURE_MASK 0x000001fe -#define NVC0TCL_BIND_TIC_TIC_SHIFT 9 -#define NVC0TCL_BIND_TIC_TIC_MASK 0x7ffffe00 -#define NVC0TCL_TEX_LIMITS(x) (0x00002200+((x)*16)) -#define NVC0TCL_TEX_LIMITS__SIZE 0x00000005 -#define NVC0TCL_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0 -#define NVC0TCL_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f -#define NVC0TCL_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4 -#define NVC0TCL_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0 -#define NVC0TCL_CB_ADDR_HIGH 0x00002384 -#define NVC0TCL_CB_ADDR_LOW 0x00002388 -#define NVC0TCL_CB_POS 0x0000238c -#define NVC0TCL_CB_DATA(x) (0x00002390+((x)*4)) -#define NVC0TCL_CB_DATA__SIZE 0x00000010 -#define NVC0TCL_TFB_VARYING_LOCS(x) (0x00002800+((x)*4)) -#define NVC0TCL_TFB_VARYING_LOCS__SIZE 0x00000080 -#define NVC0TCL_UNK_UPLOAD_POS 0x00003800 -#define NVC0TCL_UNK_UPLOAD_DATA 0x00003804 -#define NVC0TCL_VERTEX_ARRAY_SELECT 0x00003820 -#define NVC0TCL_VERTEX_ARRAY_ADDRESS 0x00003824 -#define NVC0TCL_BLEND_ENABLEI 0x00003858 -#define NVC0TCL_POLYGON_MODE_FRONT 0x00003868 -#define NVC0TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NVC0TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NVC0TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 -#define NVC0TCL_POLYGON_MODE_BACK 0x00003870 -#define NVC0TCL_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NVC0TCL_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NVC0TCL_POLYGON_MODE_BACK_FILL 0x00001b02 -#define NVC0TCL_GP_SELECT 0x00003878 -#define NVC0TCL_GP_SELECT_ENABLE (1 << 0) -#define NVC0TCL_GP_SELECT_PROGRAM_SHIFT 4 -#define NVC0TCL_GP_SELECT_PROGRAM_MASK 0x000000f0 -#define NVC0TCL_TEP_SELECT 0x00003880 -#define NVC0TCL_TEP_SELECT_ENABLE (1 << 0) -#define NVC0TCL_TEP_SELECT_PROGRAM_SHIFT 4 -#define NVC0TCL_TEP_SELECT_PROGRAM_MASK 0x000000f0 - - -#define NVC0_COMPUTE 0x000090c0 - -#define NVC0_COMPUTE_NOP 0x00000100 -#define NVC0_COMPUTE_NOTIFY 0x00000104 -#define NVC0_COMPUTE_SERIALIZE 0x00000110 -#define NVC0_COMPUTE_LOCAL_SIZE 0x00000204 -#define NVC0_COMPUTE_SHARED_BASE 0x00000214 -#define NVC0_COMPUTE_GRIDDIM_YX 0x00000238 -#define NVC0_COMPUTE_GRIDDIM_YX_X_SHIFT 0 -#define NVC0_COMPUTE_GRIDDIM_YX_X_MASK 0x0000ffff -#define NVC0_COMPUTE_GRIDDIM_YX_Y_SHIFT 16 -#define NVC0_COMPUTE_GRIDDIM_YX_Y_MASK 0xffff0000 -#define NVC0_COMPUTE_GRIDDIM_Z 0x0000023c -#define NVC0_COMPUTE_SHARED_SIZE 0x0000024c -#define NVC0_COMPUTE_BLOCK_ALLOC 0x00000250 -#define NVC0_COMPUTE_BLOCK_ALLOC_THREADS_SHIFT 0 -#define NVC0_COMPUTE_BLOCK_ALLOC_THREADS_MASK 0x0000ffff -#define NVC0_COMPUTE_BLOCK_ALLOC_BARRIERS_SHIFT 16 -#define NVC0_COMPUTE_BLOCK_ALLOC_BARRIERS_MASK 0xffff0000 -#define NVC0_COMPUTE_CP_GPR_ALLOC 0x000002c0 -#define NVC0_COMPUTE_GLOBAL_BASE 0x000002c8 -#define NVC0_COMPUTE_GLOBAL_BASE_HIGH_SHIFT 0 -#define NVC0_COMPUTE_GLOBAL_BASE_HIGH_MASK 0x000000ff -#define NVC0_COMPUTE_GLOBAL_BASE_INDEX_SHIFT 16 -#define NVC0_COMPUTE_GLOBAL_BASE_INDEX_MASK 0x00ff0000 -#define NVC0_COMPUTE_GLOBAL_BASE_FLAGS_SHIFT 28 -#define NVC0_COMPUTE_GLOBAL_BASE_FLAGS_MASK 0xf0000000 -#define NVC0_COMPUTE_LAUNCH 0x00000368 -#define NVC0_COMPUTE_BLOCKDIM_YX 0x000003ac -#define NVC0_COMPUTE_BLOCKDIM_YX_X_SHIFT 0 -#define NVC0_COMPUTE_BLOCKDIM_YX_X_MASK 0x0000ffff -#define NVC0_COMPUTE_BLOCKDIM_YX_Y_SHIFT 16 -#define NVC0_COMPUTE_BLOCKDIM_YX_Y_MASK 0xffff0000 -#define NVC0_COMPUTE_BLOCKDIM_Z 0x000003b0 -#define NVC0_COMPUTE_CP_START_ID 0x000003b4 -#define NVC0_COMPUTE_LOCAL_BASE 0x0000077c -#define NVC0_COMPUTE_UNK0790_ADDRESS_HIGH 0x00000790 -#define NVC0_COMPUTE_UNK0790_ADDRESS_LOW 0x00000794 -#define NVC0_COMPUTE_LINKED_TSC 0x00001234 -#define NVC0_COMPUTE_TSC_ADDRESS_HIGH 0x0000155c -#define NVC0_COMPUTE_TSC_ADDRESS_LOW 0x00001560 -#define NVC0_COMPUTE_TSC_LIMIT 0x00001564 -#define NVC0_COMPUTE_TIC_ADDRESS_HIGH 0x00001574 -#define NVC0_COMPUTE_TIC_ADDRESS_LOW 0x00001578 -#define NVC0_COMPUTE_TIC_LIMIT 0x0000157c -#define NVC0_COMPUTE_CODE_ADDRESS_HIGH 0x00001608 -#define NVC0_COMPUTE_CODE_ADDRESS_LOW 0x0000160c -#define NVC0_COMPUTE_CB_BIND 0x00001694 -#define NVC0_COMPUTE_CB_BIND_INDEX_SHIFT 1 -#define NVC0_COMPUTE_CB_BIND_INDEX_MASK 0xfffffffe -#define NVC0_COMPUTE_CB_BIND_VALID (1 << 0) -#define NVC0_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00 -#define NVC0_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04 -#define NVC0_COMPUTE_QUERY_SEQUENCE 0x00001b08 -#define NVC0_COMPUTE_QUERY_GET 0x00001b0c -#define NVC0_COMPUTE_CB_ADDRESS_HIGH 0x00002384 -#define NVC0_COMPUTE_CB_ADDRESS_LOW 0x00002388 -#define NVC0_COMPUTE_CB_POS 0x0000238c -#define NVC0_COMPUTE_CB_DATA 0x00002390 - - -#endif /* NOUVEAU_REG_H */ diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h index c6c93d40b8f..c9003c97f5d 100644 --- a/src/gallium/drivers/nouveau/nouveau_winsys.h +++ b/src/gallium/drivers/nouveau/nouveau_winsys.h @@ -6,7 +6,6 @@ #include "nouveau/nouveau_bo.h" #include "nouveau/nouveau_channel.h" -#include "nouveau/nouveau_class.h" #include "nouveau/nouveau_device.h" #include "nouveau/nouveau_grobj.h" #include "nouveau/nouveau_notifier.h" diff --git a/src/gallium/drivers/nouveau/nv_m2mf.xml.h b/src/gallium/drivers/nouveau/nv_m2mf.xml.h new file mode 100644 index 00000000000..ffdaf95de62 --- /dev/null +++ b/src/gallium/drivers/nouveau/nv_m2mf.xml.h @@ -0,0 +1,155 @@ +#ifndef NV_M2MF_XML +#define NV_M2MF_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv_m2mf.xml ( 2710 bytes, from 2010-08-05 19:38:53) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <[email protected]> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <[email protected]> (koala_br) +- Carlos Martin <[email protected]> (carlosmn) +- Christoph Bumiller <[email protected]> (calim, chrisbmr) +- Dawid Gajownik <[email protected]> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <[email protected]> (lumag) +- EdB <[email protected]> (edb_) +- Erik Waling <[email protected]> (erikwaling) +- Francisco Jerez <[email protected]> (curro, curro_, currojerez) +- imirkin <[email protected]> (imirkin) +- jb17bsome <[email protected]> (jb17bsome) +- Jeremy Kolb <[email protected]> (kjeremy) +- Laurent Carlier <[email protected]> (lordheavy) +- Luca Barbieri <[email protected]> (lb, lb1) +- Maarten Maathuis <[email protected]> (stillunknown) +- Marcin Kościelnicki <[email protected]> (mwk, koriakin) +- Mark Carey <[email protected]> (careym) +- Matthieu Castet <[email protected]> (mat-c) +- nvidiaman <[email protected]> (nvidiaman) +- Patrice Mandin <[email protected]> (pmandin, pmdata) +- Pekka Paalanen <[email protected]> (pq, ppaalanen) +- Peter Popov <[email protected]> (ironpeter) +- Richard Hughes <[email protected]> (hughsient) +- Rudi Cilibrasi <[email protected]> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <[email protected]> (leroutier) +- Stephane Marchesin <[email protected]> (marcheu) +- sturmflut <[email protected]> (sturmflut) +- Sylvain Munaut <[email protected]> +- Victor Stinner <[email protected]> (haypo) +- Wladmir van der Laan <[email protected]> (miathan6) +- Younes Manton <[email protected]> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + + +#define NV04_M2MF_DMA_NOTIFY 0x00000180 + +#define NV04_M2MF_DMA_BUFFER_IN 0x00000184 + +#define NV04_M2MF_DMA_BUFFER_OUT 0x00000188 + + +#define NV50_M2MF_LINEAR_IN 0x00000200 + +#define NV50_M2MF_TILING_MODE_IN 0x00000204 + +#define NV50_M2MF_TILING_PITCH_IN 0x00000208 + +#define NV50_M2MF_TILING_HEIGHT_IN 0x0000020c + +#define NV50_M2MF_TILING_DEPTH_IN 0x00000210 + +#define NV50_M2MF_TILING_POSITION_IN_Z 0x00000214 + +#define NV50_M2MF_TILING_POSITION_IN 0x00000218 +#define NV50_M2MF_TILING_POSITION_IN_X__MASK 0x0000ffff +#define NV50_M2MF_TILING_POSITION_IN_X__SHIFT 0 +#define NV50_M2MF_TILING_POSITION_IN_Y__MASK 0xffff0000 +#define NV50_M2MF_TILING_POSITION_IN_Y__SHIFT 16 + +#define NV50_M2MF_LINEAR_OUT 0x0000021c + +#define NV50_M2MF_TILING_MODE_OUT 0x00000220 + +#define NV50_M2MF_TILING_PITCH_OUT 0x00000224 + +#define NV50_M2MF_TILING_HEIGHT_OUT 0x00000228 + +#define NV50_M2MF_TILING_DEPTH_OUT 0x0000022c + +#define NV50_M2MF_TILING_POSITION_OUT_Z 0x00000230 + +#define NV50_M2MF_TILING_POSITION_OUT 0x00000234 +#define NV50_M2MF_TILING_POSITION_OUT_X__MASK 0x0000ffff +#define NV50_M2MF_TILING_POSITION_OUT_X__SHIFT 0 +#define NV50_M2MF_TILING_POSITION_OUT_Y__MASK 0xffff0000 +#define NV50_M2MF_TILING_POSITION_OUT_Y__SHIFT 16 + +#define NV50_M2MF_OFFSET_IN_HIGH 0x00000238 + +#define NV50_M2MF_OFFSET_OUT_HIGH 0x0000023c + +#define NV04_M2MF_OFFSET_IN 0x0000030c + +#define NV04_M2MF_OFFSET_OUT 0x00000310 + +#define NV04_M2MF_PITCH_IN 0x00000314 + +#define NV04_M2MF_PITCH_OUT 0x00000318 + +#define NV04_M2MF_LINE_LENGTH_IN 0x0000031c + +#define NV04_M2MF_LINE_COUNT 0x00000320 + +#define NV04_M2MF_FORMAT 0x00000324 +#define NV04_M2MF_FORMAT_INPUT_INC__MASK 0x000000ff +#define NV04_M2MF_FORMAT_INPUT_INC__SHIFT 0 +#define NV04_M2MF_FORMAT_INPUT_INC_1 0x00000001 +#define NV04_M2MF_FORMAT_INPUT_INC_2 0x00000002 +#define NV04_M2MF_FORMAT_INPUT_INC_4 0x00000004 +#define NV50_M2MF_FORMAT_INPUT_INC_8 0x00000008 +#define NV50_M2MF_FORMAT_INPUT_INC_16 0x00000010 +#define NV04_M2MF_FORMAT_OUTPUT_INC__MASK 0x0000ff00 +#define NV04_M2MF_FORMAT_OUTPUT_INC__SHIFT 8 +#define NV04_M2MF_FORMAT_OUTPUT_INC_1 0x00000100 +#define NV04_M2MF_FORMAT_OUTPUT_INC_2 0x00000200 +#define NV04_M2MF_FORMAT_OUTPUT_INC_4 0x00000400 +#define NV50_M2MF_FORMAT_OUTPUT_INC_8 0x00000800 +#define NV50_M2MF_FORMAT_OUTPUT_INC_16 0x00001000 + +#define NV04_M2MF_BUF_NOTIFY 0x00000328 + + +#endif /* NV_M2MF_XML */ diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h new file mode 100644 index 00000000000..cb7653c3fe2 --- /dev/null +++ b/src/gallium/drivers/nouveau/nv_object.xml.h @@ -0,0 +1,231 @@ +#ifndef NV_OBJECT_XML +#define NV_OBJECT_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv30-40_3d.xml ( 31709 bytes, from 2010-09-05 07:53:14) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_3ddefs.xml ( 15193 bytes, from 2010-09-05 07:50:15) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <[email protected]> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <[email protected]> (koala_br) +- Carlos Martin <[email protected]> (carlosmn) +- Christoph Bumiller <[email protected]> (calim, chrisbmr) +- Dawid Gajownik <[email protected]> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <[email protected]> (lumag) +- EdB <[email protected]> (edb_) +- Erik Waling <[email protected]> (erikwaling) +- Francisco Jerez <[email protected]> (curro, curro_, currojerez) +- imirkin <[email protected]> (imirkin) +- jb17bsome <[email protected]> (jb17bsome) +- Jeremy Kolb <[email protected]> (kjeremy) +- Laurent Carlier <[email protected]> (lordheavy) +- Luca Barbieri <[email protected]> (lb, lb1) +- Maarten Maathuis <[email protected]> (stillunknown) +- Marcin Kościelnicki <[email protected]> (mwk, koriakin) +- Mark Carey <[email protected]> (careym) +- Matthieu Castet <[email protected]> (mat-c) +- nvidiaman <[email protected]> (nvidiaman) +- Patrice Mandin <[email protected]> (pmandin, pmdata) +- Pekka Paalanen <[email protected]> (pq, ppaalanen) +- Peter Popov <[email protected]> (ironpeter) +- Richard Hughes <[email protected]> (hughsient) +- Rudi Cilibrasi <[email protected]> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <[email protected]> (leroutier) +- Stephane Marchesin <[email protected]> (marcheu) +- sturmflut <[email protected]> (sturmflut) +- Sylvain Munaut <[email protected]> +- Victor Stinner <[email protected]> (haypo) +- Wladmir van der Laan <[email protected]> (miathan6) +- Younes Manton <[email protected]> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define NV01_ROOT 0x00000001 +#define NV01_CONTEXT_DMA 0x00000002 +#define NV01_DEVICE 0x00000003 +#define NV01_TIMER 0x00000004 +#define NV01_NULL 0x00000030 +#define NV01_MEMORY_LOCAL_BANKED 0x0000003d +#define NV01_MAPPING_SYSTEM 0x0000003e +#define NV03_MEMORY_LOCAL_CURSOR 0x0000003f +#define NV01_MEMORY_LOCAL_LINEAR 0x00000040 +#define NV01_MAPPING_LOCAL 0x00000041 +#define NV03_VIDEO_LUT_CURSOR_DAC 0x00000046 +#define NV03_CHANNEL_PIO 0x0000006a +#define NV03_CHANNEL_DMA 0x0000006b +#define NV10_VIDEO_DISPLAY 0x0000007c +#define NV01_CONTEXT_BETA1 0x00000012 +#define NV04_BETA_SOLID 0x00000072 +#define NV01_CONTEXT_COLOR_KEY 0x00000017 +#define NV04_CONTEXT_COLOR_KEY 0x00000057 +#define NV01_CONTEXT_PATTERN 0x00000018 +#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019 +#define NV03_CONTEXT_ROP 0x00000043 +#define NV04_IMAGE_PATTERN 0x00000044 +#define NV01_RENDER_SOLID_LINE 0x0000001c +#define NV04_RENDER_SOLID_LINE 0x0000005c +#define NV30_RENDER_SOLID_LINE 0x0000035c +#define NV40_RENDER_SOLID_LINE 0x0000305c +#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d +#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d +#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e +#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e +#define NV01_IMAGE_BLIT 0x0000001f +#define NV04_IMAGE_BLIT 0x0000005f +#define NV11_IMAGE_BLIT 0x0000009f +#define NV01_IMAGE_FROM_CPU 0x00000021 +#define NV04_IMAGE_FROM_CPU 0x00000061 +#define NV05_IMAGE_FROM_CPU 0x00000065 +#define NV10_IMAGE_FROM_CPU 0x0000008a +#define NV30_IMAGE_FROM_CPU 0x0000038a +#define NV40_IMAGE_FROM_CPU 0x0000308a +#define NV03_STRETCHED_IMAGE_FROM_CPU 0x00000036 +#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076 +#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066 +#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366 +#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066 +#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037 +#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077 +#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063 +#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089 +#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389 +#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089 +#define NV50_SCALED_IMAGE_FROM_MEMORY 0x00005089 +#define NV04_DVD_SUBPICTURE 0x00000038 +#define NV10_DVD_SUBPICTURE 0x00000088 +#define NV03_GDI_RECTANGLE_TEXT 0x0000004b +#define NV04_GDI_RECTANGLE_TEXT 0x0000004a +#define NV04_SWIZZLED_SURFACE 0x00000052 +#define NV11_SWIZZLED_SURFACE 0x0000009e +#define NV30_SWIZZLED_SURFACE 0x0000039e +#define NV40_SWIZZLED_SURFACE 0x0000309e +#define NV03_CONTEXT_SURFACE_DST 0x00000058 +#define NV03_CONTEXT_SURFACE_SRC 0x00000059 +#define NV04_CONTEXT_SURFACES_2D 0x00000042 +#define NV10_CONTEXT_SURFACES_2D 0x00000062 +#define NV30_CONTEXT_SURFACES_2D 0x00000362 +#define NV40_CONTEXT_SURFACES_2D 0x00003062 +#define NV50_CONTEXT_SURFACES_2D 0x00005062 +#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060 +#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064 +#define NV30_INDEXED_IMAGE_FROM_CPU 0x00000364 +#define NV40_INDEXED_IMAGE_FROM_CPU 0x00003064 +#define NV10_TEXTURE_FROM_CPU 0x0000007b +#define NV30_TEXTURE_FROM_CPU 0x0000037b +#define NV40_TEXTURE_FROM_CPU 0x0000307b +#define NV04_M2MF 0x00000039 +#define NV50_M2MF 0x00005039 +#define NVC0_M2MF 0x00009039 +#define NV03_TEXTURED_TRIANGLE 0x00000048 +#define NV04_TEXTURED_TRIANGLE 0x00000054 +#define NV10_TEXTURED_TRIANGLE 0x00000094 +#define NV04_MULTITEX_TRIANGLE 0x00000055 +#define NV10_MULTITEX_TRIANGLE 0x00000095 +#define NV03_CONTEXT_SURFACE_COLOR 0x0000005a +#define NV03_CONTEXT_SURFACE_ZETA 0x0000005b +#define NV04_CONTEXT_SURFACES_3D 0x00000053 +#define NV10_CONTEXT_SURFACES_3D 0x00000093 +#define NV10_3D 0x00000056 +#define NV11_3D 0x00000096 +#define NV17_3D 0x00000099 +#define NV20_3D 0x00000097 +#define NV25_3D 0x00000597 +#define NV30_3D 0x00000397 +#define NV35_3D 0x00000497 +#define NV34_3D 0x00000697 +#define NV40_3D 0x00004097 +#define NV44_3D 0x00004497 +#define NV50_3D 0x00005097 +#define NV84_3D 0x00008297 +#define NVA0_3D 0x00008397 +#define NVA3_3D 0x00008597 +#define NVAF_3D 0x00008697 +#define NVC0_3D 0x00009097 +#define NV50_2D 0x0000502d +#define NVC0_2D 0x0000902d +#define NV50_COMPUTE 0x000050c0 +#define NVA3_COMPUTE 0x000085c0 +#define NVC0_COMPUTE 0x000090c0 +#define NV01_SUBCHAN__SIZE 0x00002000 +#define NV01_SUBCHAN 0x00000000 + +#define NV01_SUBCHAN_OBJECT 0x00000000 + + +#define NV84_SUBCHAN_QUERY_ADDRESS_HIGH 0x00000010 + +#define NV84_SUBCHAN_QUERY_ADDRESS_LOW 0x00000014 + +#define NV84_SUBCHAN_QUERY_COUNTER 0x00000018 + +#define NV84_SUBCHAN_QUERY_GET 0x0000001c + +#define NV84_SUBCHAN_UNK20 0x00000020 + +#define NV84_SUBCHAN_UNK24 0x00000024 + +#define NV10_SUBCHAN_REF_CNT 0x00000050 + + +#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 + +#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 + +#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 + +#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c + +#define NV50_SUBCHAN_UNK80 0x00000080 + +#define NV01_GRAPH 0x00000000 + +#define NV04_GRAPH_NOP 0x00000100 + +#define NV01_GRAPH_NOTIFY 0x00000104 +#define NV01_GRAPH_NOTIFY_WRITE 0x00000000 +#define NV01_GRAPH_NOTIFY_WRITE_AND_AWAKEN 0x00000001 + +#define NV50_GRAPH_WAIT_FOR_IDLE 0x00000110 + +#define NVA3_GRAPH_UNK0120 0x00000120 + +#define NVA3_GRAPH_UNK0124 0x00000124 + +#define NV40_GRAPH_PM_TRIGGER 0x00000140 + + +#endif /* NV_OBJECT_XML */ diff --git a/src/gallium/drivers/nv50/nv50_context.h b/src/gallium/drivers/nv50/nv50_context.h index d24d6c50ea8..6ec9095a741 100644 --- a/src/gallium/drivers/nv50/nv50_context.h +++ b/src/gallium/drivers/nv50/nv50_context.h @@ -16,6 +16,7 @@ #include "nouveau/nouveau_winsys.h" #include "nouveau/nouveau_gldefs.h" #include "nouveau/nouveau_stateobj.h" +#include "nv50_reg.h" #include "nv50_screen.h" #include "nv50_program.h" diff --git a/src/gallium/drivers/nv50/nv50_formats.c b/src/gallium/drivers/nv50/nv50_formats.c index e1c7dae3063..3be39d5337a 100644 --- a/src/gallium/drivers/nv50/nv50_formats.c +++ b/src/gallium/drivers/nv50/nv50_formats.c @@ -22,7 +22,7 @@ #include "nv50_screen.h" #include "nv50_texture.h" -#include "nouveau/nouveau_class.h" +#include "nv50_reg.h" #include "pipe/p_defines.h" #define A_(cr, cg, cb, ca, t0, t1, t2, t3, sz, r) \ diff --git a/src/gallium/drivers/nv50/nv50_program.h b/src/gallium/drivers/nv50/nv50_program.h index d8b6e8d6d14..97d2933c3ee 100644 --- a/src/gallium/drivers/nv50/nv50_program.h +++ b/src/gallium/drivers/nv50/nv50_program.h @@ -25,7 +25,6 @@ #include "pipe/p_state.h" #include "tgsi/tgsi_scan.h" -#include "nouveau/nouveau_class.h" #define NV50_CAP_MAX_PROGRAM_TEMPS 64 diff --git a/src/gallium/drivers/nv50/nv50_reg.h b/src/gallium/drivers/nv50/nv50_reg.h new file mode 100644 index 00000000000..365576fdd07 --- /dev/null +++ b/src/gallium/drivers/nv50/nv50_reg.h @@ -0,0 +1,1824 @@ +/************************************************************************* + + Autogenerated file, do not edit ! + + This file was generated by renouveau-gen from renouveau.xml, the + XML database of nvidia objects and methods. renouveau-gen and + renouveau.xml can be found in CVS module renouveau of sourceforge.net + project nouveau: + +cvs -z3 -d:pserver:[email protected]:/cvsroot/nouveau co -P renouveau + +************************************************************************** + + Copyright (C) 2006-2008 : + Dmitry Baryshkov, + Laurent Carlier, + Matthieu Castet, + Dawid Gajownik, + Jeremy Kolb, + Stephane Loeuillet, + Patrice Mandin, + Stephane Marchesin, + Serge Martin, + Sylvain Munaut, + Simon Raffeiner, + Ben Skeggs, + Erik Waling, + koala_br, + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*************************************************************************/ + + +#ifndef NOUVEAU_REG_H +#define NOUVEAU_REG_H 1 + + +#define NV04_MEMORY_TO_MEMORY_FORMAT 0x00000039 + +#define NV04_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 +#define NV04_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN 0x00000184 +#define NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT 0x00000188 +#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c +#define NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310 +#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 +#define NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 +#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c +#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT 0 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x000000ff +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT 8 +#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x0000ff00 +#define NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328 + + +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 + +#define NV50_MEMORY_TO_MEMORY_FORMAT_SERIALIZE 0x00000110 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN 0x00000210 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z 0x00000214 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_SHIFT 0 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_MASK 0x0000ffff +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_SHIFT 16 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_MASK 0xffff0000 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT 0x0000022c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z 0x00000230 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_SHIFT 0 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_MASK 0x0000ffff +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_SHIFT 16 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_MASK 0xffff0000 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c + + +#define NV50_2D 0x0000502d + +#define NV50_2D_NOP 0x00000100 +#define NV50_2D_NOTIFY 0x00000104 +#define NV50_2D_SERIALIZE 0x00000110 +#define NV50_2D_DMA_NOTIFY 0x00000180 +#define NV50_2D_DMA_DST 0x00000184 +#define NV50_2D_DMA_SRC 0x00000188 +#define NV50_2D_DMA_COND 0x0000018c +#define NV50_2D_DST_FORMAT 0x00000200 +#define NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_DST_FORMAT_R32G32B32A32_SINT 0x000000c1 +#define NV50_2D_DST_FORMAT_R32G32B32A32_UINT 0x000000c2 +#define NV50_2D_DST_FORMAT_R32G32B32X32_FLOAT 0x000000c3 +#define NV50_2D_DST_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_DST_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_DST_FORMAT_R16G16B16A16_SINT 0x000000c8 +#define NV50_2D_DST_FORMAT_R16G16B16A16_UINT 0x000000c9 +#define NV50_2D_DST_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_DST_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_DST_FORMAT_R32G32_SINT 0x000000cc +#define NV50_2D_DST_FORMAT_R32G32_UINT 0x000000cd +#define NV50_2D_DST_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_DST_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_DST_FORMAT_A8R8G8B8_SRGB 0x000000d0 +#define NV50_2D_DST_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_DST_FORMAT_A2B10G10R10_UINT 0x000000d2 +#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d5 +#define NV50_2D_DST_FORMAT_A8B8G8R8_SRGB 0x000000d6 +#define NV50_2D_DST_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_DST_FORMAT_A8B8G8R8_SINT 0x000000d8 +#define NV50_2D_DST_FORMAT_A8B8G8R8_UINT 0x000000d9 +#define NV50_2D_DST_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_DST_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_DST_FORMAT_R16G16_SINT 0x000000dc +#define NV50_2D_DST_FORMAT_R16G16_UINT 0x000000dd +#define NV50_2D_DST_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_DST_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_DST_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_DST_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_DST_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_DST_FORMAT_X8R8G8B8_SRGB 0x000000e7 +#define NV50_2D_DST_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_DST_FORMAT_A1R5G5B5_UNORM 0x000000e9 +#define NV50_2D_DST_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_DST_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_DST_FORMAT_R8G8_SINT 0x000000ec +#define NV50_2D_DST_FORMAT_R8G8_UINT 0x000000ed +#define NV50_2D_DST_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_DST_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_DST_FORMAT_R16_SINT 0x000000f0 +#define NV50_2D_DST_FORMAT_R16_UINT 0x000000f1 +#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000f2 +#define NV50_2D_DST_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_DST_FORMAT_R8_SNORM 0x000000f4 +#define NV50_2D_DST_FORMAT_R8_SINT 0x000000f5 +#define NV50_2D_DST_FORMAT_R8_UINT 0x000000f6 +#define NV50_2D_DST_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_DST_FORMAT_X1R5G5B5_UNORM 0x000000f8 +#define NV50_2D_DST_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_DST_FORMAT_X8B8G8R8_SRGB 0x000000fa +#define NV50_2D_DST_LINEAR 0x00000204 +#define NV50_2D_DST_TILE_MODE 0x00000208 +#define NV50_2D_DST_DEPTH 0x0000020c +#define NV50_2D_DST_LAYER 0x00000210 +#define NV50_2D_DST_PITCH 0x00000214 +#define NV50_2D_DST_WIDTH 0x00000218 +#define NV50_2D_DST_HEIGHT 0x0000021c +#define NV50_2D_DST_ADDRESS_HIGH 0x00000220 +#define NV50_2D_DST_ADDRESS_LOW 0x00000224 +#define NV50_2D_SRC_FORMAT 0x00000230 +#define NV50_2D_SRC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_SRC_FORMAT_R32G32B32A32_SINT 0x000000c1 +#define NV50_2D_SRC_FORMAT_R32G32B32A32_UINT 0x000000c2 +#define NV50_2D_SRC_FORMAT_R32G32B32X32_FLOAT 0x000000c3 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_SINT 0x000000c8 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_UINT 0x000000c9 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_SRC_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_SRC_FORMAT_R32G32_SINT 0x000000cc +#define NV50_2D_SRC_FORMAT_R32G32_UINT 0x000000cd +#define NV50_2D_SRC_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_SRC_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_SRC_FORMAT_A8R8G8B8_SRGB 0x000000d0 +#define NV50_2D_SRC_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_SRC_FORMAT_A2B10G10R10_UINT 0x000000d2 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d5 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_SRGB 0x000000d6 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_SINT 0x000000d8 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_UINT 0x000000d9 +#define NV50_2D_SRC_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_SRC_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_SRC_FORMAT_R16G16_SINT 0x000000dc +#define NV50_2D_SRC_FORMAT_R16G16_UINT 0x000000dd +#define NV50_2D_SRC_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_SRC_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_SRC_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_SRC_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_SRC_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_SRC_FORMAT_X8R8G8B8_SRGB 0x000000e7 +#define NV50_2D_SRC_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_SRC_FORMAT_A1R5G5B5_UNORM 0x000000e9 +#define NV50_2D_SRC_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_SRC_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_SRC_FORMAT_R8G8_SINT 0x000000ec +#define NV50_2D_SRC_FORMAT_R8G8_UINT 0x000000ed +#define NV50_2D_SRC_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_SRC_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_SRC_FORMAT_R16_SINT 0x000000f0 +#define NV50_2D_SRC_FORMAT_R16_UINT 0x000000f1 +#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000f2 +#define NV50_2D_SRC_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_SRC_FORMAT_R8_SNORM 0x000000f4 +#define NV50_2D_SRC_FORMAT_R8_SINT 0x000000f5 +#define NV50_2D_SRC_FORMAT_R8_UINT 0x000000f6 +#define NV50_2D_SRC_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_SRC_FORMAT_X1R5G5B5_UNORM 0x000000f8 +#define NV50_2D_SRC_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_SRC_FORMAT_X8B8G8R8_SRGB 0x000000fa +#define NV50_2D_SRC_LINEAR 0x00000234 +#define NV50_2D_SRC_TILE_MODE 0x00000238 +#define NV50_2D_SRC_DEPTH 0x0000023c +#define NV50_2D_SRC_LAYER 0x00000240 +#define NV50_2D_SRC_PITCH 0x00000244 +#define NV50_2D_SRC_WIDTH 0x00000248 +#define NV50_2D_SRC_HEIGHT 0x0000024c +#define NV50_2D_SRC_ADDRESS_HIGH 0x00000250 +#define NV50_2D_SRC_ADDRESS_LOW 0x00000254 +#define NV50_2D_COND_ADDRESS_HIGH 0x00000264 +#define NV50_2D_COND_ADDRESS_LOW 0x00000268 +#define NV50_2D_COND_MODE 0x0000026c +#define NV50_2D_COND_MODE_NEVER 0x00000000 +#define NV50_2D_COND_MODE_ALWAYS 0x00000001 +#define NV50_2D_COND_MODE_RES 0x00000002 +#define NV50_2D_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 +#define NV50_2D_COND_MODE_RES_OR_ID 0x00000004 +#define NV50_2D_CLIP_X 0x00000280 +#define NV50_2D_CLIP_Y 0x00000284 +#define NV50_2D_CLIP_W 0x00000288 +#define NV50_2D_CLIP_H 0x0000028c +#define NV50_2D_CLIP_ENABLE 0x00000290 +#define NV50_2D_COLOR_KEY_FORMAT 0x00000294 +#define NV50_2D_COLOR_KEY_FORMAT_16BPP 0x00000000 +#define NV50_2D_COLOR_KEY_FORMAT_15BPP 0x00000001 +#define NV50_2D_COLOR_KEY_FORMAT_24BPP 0x00000002 +#define NV50_2D_COLOR_KEY_FORMAT_30BPP 0x00000003 +#define NV50_2D_COLOR_KEY_FORMAT_8BPP 0x00000004 +#define NV50_2D_COLOR_KEY_FORMAT_16BPP2 0x00000005 +#define NV50_2D_COLOR_KEY_FORMAT_32BPP 0x00000006 +#define NV50_2D_COLOR_KEY 0x00000298 +#define NV50_2D_COLOR_KEY_ENABLE 0x0000029c +#define NV50_2D_ROP 0x000002a0 +#define NV50_2D_OPERATION 0x000002ac +#define NV50_2D_OPERATION_SRCCOPY_AND 0x00000000 +#define NV50_2D_OPERATION_ROP_AND 0x00000001 +#define NV50_2D_OPERATION_BLEND_AND 0x00000002 +#define NV50_2D_OPERATION_SRCCOPY 0x00000003 +#define NV50_2D_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV50_2D_OPERATION_BLEND_PREMULT 0x00000005 +#define NV50_2D_PATTERN_FORMAT 0x000002e8 +#define NV50_2D_PATTERN_FORMAT_16BPP 0x00000000 +#define NV50_2D_PATTERN_FORMAT_15BPP 0x00000001 +#define NV50_2D_PATTERN_FORMAT_32BPP 0x00000002 +#define NV50_2D_PATTERN_FORMAT_8BPP 0x00000003 +#define NV50_2D_PATTERN_COLOR(x) (0x000002f0+((x)*4)) +#define NV50_2D_PATTERN_COLOR__SIZE 0x00000002 +#define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4)) +#define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002 +#define NV50_2D_DRAW_SHAPE 0x00000580 +#define NV50_2D_DRAW_SHAPE_POINTS 0x00000000 +#define NV50_2D_DRAW_SHAPE_LINES 0x00000001 +#define NV50_2D_DRAW_SHAPE_LINE_STRIP 0x00000002 +#define NV50_2D_DRAW_SHAPE_TRIANGLES 0x00000003 +#define NV50_2D_DRAW_SHAPE_RECTANGLES 0x00000004 +#define NV50_2D_DRAW_COLOR_FORMAT 0x00000584 +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_SINT 0x000000c1 +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_UINT 0x000000c2 +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32X32_FLOAT 0x000000c3 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SINT 0x000000c8 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UINT 0x000000c9 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_SINT 0x000000cc +#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_UINT 0x000000cd +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_SRGB 0x000000d0 +#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UINT 0x000000d2 +#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UNORM 0x000000d5 +#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SRGB 0x000000d6 +#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SINT 0x000000d8 +#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UINT 0x000000d9 +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SINT 0x000000dc +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UINT 0x000000dd +#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_DRAW_COLOR_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_DRAW_COLOR_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_DRAW_COLOR_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_SRGB 0x000000e7 +#define NV50_2D_DRAW_COLOR_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_DRAW_COLOR_FORMAT_A1R5G5B5_UNORM 0x000000e9 +#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SINT 0x000000ec +#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UINT 0x000000ed +#define NV50_2D_DRAW_COLOR_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_DRAW_COLOR_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_DRAW_COLOR_FORMAT_R16_SINT 0x000000f0 +#define NV50_2D_DRAW_COLOR_FORMAT_R16_UINT 0x000000f1 +#define NV50_2D_DRAW_COLOR_FORMAT_R16_FLOAT 0x000000f2 +#define NV50_2D_DRAW_COLOR_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_DRAW_COLOR_FORMAT_R8_SNORM 0x000000f4 +#define NV50_2D_DRAW_COLOR_FORMAT_R8_SINT 0x000000f5 +#define NV50_2D_DRAW_COLOR_FORMAT_R8_UINT 0x000000f6 +#define NV50_2D_DRAW_COLOR_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_DRAW_COLOR_FORMAT_X1R5G5B5_UNORM 0x000000f8 +#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_SRGB 0x000000fa +#define NV50_2D_DRAW_COLOR 0x00000588 +#define NV50_2D_DRAW_POINT16 0x000005e0 +#define NV50_2D_DRAW_POINT16_X_SHIFT 0 +#define NV50_2D_DRAW_POINT16_X_MASK 0x0000ffff +#define NV50_2D_DRAW_POINT16_Y_SHIFT 16 +#define NV50_2D_DRAW_POINT16_Y_MASK 0xffff0000 +#define NV50_2D_DRAW_POINT32_X(x) (0x00000600+((x)*8)) +#define NV50_2D_DRAW_POINT32_X__SIZE 0x00000040 +#define NV50_2D_DRAW_POINT32_Y(x) (0x00000604+((x)*8)) +#define NV50_2D_DRAW_POINT32_Y__SIZE 0x00000040 +#define NV50_2D_SIFC_BITMAP_ENABLE 0x00000800 +#define NV50_2D_SIFC_FORMAT 0x00000804 +#define NV50_2D_SIFC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_SIFC_FORMAT_R32G32B32A32_SINT 0x000000c1 +#define NV50_2D_SIFC_FORMAT_R32G32B32A32_UINT 0x000000c2 +#define NV50_2D_SIFC_FORMAT_R32G32B32X32_FLOAT 0x000000c3 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SINT 0x000000c8 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UINT 0x000000c9 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_SIFC_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_SIFC_FORMAT_R32G32_SINT 0x000000cc +#define NV50_2D_SIFC_FORMAT_R32G32_UINT 0x000000cd +#define NV50_2D_SIFC_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_SIFC_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_SIFC_FORMAT_A8R8G8B8_SRGB 0x000000d0 +#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UINT 0x000000d2 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d5 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SRGB 0x000000d6 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SINT 0x000000d8 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UINT 0x000000d9 +#define NV50_2D_SIFC_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_SIFC_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_SIFC_FORMAT_R16G16_SINT 0x000000dc +#define NV50_2D_SIFC_FORMAT_R16G16_UINT 0x000000dd +#define NV50_2D_SIFC_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_SIFC_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_SIFC_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_SIFC_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_SIFC_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_SIFC_FORMAT_X8R8G8B8_SRGB 0x000000e7 +#define NV50_2D_SIFC_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_SIFC_FORMAT_A1R5G5B5_UNORM 0x000000e9 +#define NV50_2D_SIFC_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_SIFC_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_SIFC_FORMAT_R8G8_SINT 0x000000ec +#define NV50_2D_SIFC_FORMAT_R8G8_UINT 0x000000ed +#define NV50_2D_SIFC_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_SIFC_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_SIFC_FORMAT_R16_SINT 0x000000f0 +#define NV50_2D_SIFC_FORMAT_R16_UINT 0x000000f1 +#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000f2 +#define NV50_2D_SIFC_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_SIFC_FORMAT_R8_SNORM 0x000000f4 +#define NV50_2D_SIFC_FORMAT_R8_SINT 0x000000f5 +#define NV50_2D_SIFC_FORMAT_R8_UINT 0x000000f6 +#define NV50_2D_SIFC_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_SIFC_FORMAT_X1R5G5B5_UNORM 0x000000f8 +#define NV50_2D_SIFC_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_SIFC_FORMAT_X8B8G8R8_SRGB 0x000000fa +#define NV50_2D_SIFC_BITMAP_UNK808 0x00000808 +#define NV50_2D_SIFC_BITMAP_LSB_FIRST 0x0000080c +#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE 0x00000810 +#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_PACKED 0x00000000 +#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_BYTE 0x00000001 +#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_WORD 0x00000002 +#define NV50_2D_SIFC_BITMAP_COLOR_BIT0 0x00000814 +#define NV50_2D_SIFC_BITMAP_COLOR_BIT1 0x00000818 +#define NV50_2D_SIFC_BITMAP_WRITE_BIT0_ENABLE 0x0000081c +#define NV50_2D_SIFC_WIDTH 0x00000838 +#define NV50_2D_SIFC_HEIGHT 0x0000083c +#define NV50_2D_SIFC_DX_DU_FRACT 0x00000840 +#define NV50_2D_SIFC_DX_DU_INT 0x00000844 +#define NV50_2D_SIFC_DY_DV_FRACT 0x00000848 +#define NV50_2D_SIFC_DY_DV_INT 0x0000084c +#define NV50_2D_SIFC_DST_X_FRACT 0x00000850 +#define NV50_2D_SIFC_DST_X_INT 0x00000854 +#define NV50_2D_SIFC_DST_Y_FRACT 0x00000858 +#define NV50_2D_SIFC_DST_Y_INT 0x0000085c +#define NV50_2D_SIFC_DATA 0x00000860 +#define NV50_2D_BLIT_DST_X 0x000008b0 +#define NV50_2D_BLIT_DST_Y 0x000008b4 +#define NV50_2D_BLIT_DST_W 0x000008b8 +#define NV50_2D_BLIT_DST_H 0x000008bc +#define NV50_2D_BLIT_DU_DX_FRACT 0x000008c0 +#define NV50_2D_BLIT_DU_DX_INT 0x000008c4 +#define NV50_2D_BLIT_DV_DY_FRACT 0x000008c8 +#define NV50_2D_BLIT_DV_DY_INT 0x000008cc +#define NV50_2D_BLIT_SRC_X_FRACT 0x000008d0 +#define NV50_2D_BLIT_SRC_X_INT 0x000008d4 +#define NV50_2D_BLIT_SRC_Y_FRACT 0x000008d8 +#define NV50_2D_BLIT_SRC_Y_INT 0x000008dc + + +#define NV50TCL 0x00005097 + +#define NV50TCL_NOP 0x00000100 +#define NV50TCL_NOTIFY 0x00000104 +#define NV50TCL_SERIALIZE 0x00000110 +#define NV50TCL_DMA_NOTIFY 0x00000180 +#define NV50TCL_DMA_ZETA 0x00000184 +#define NV50TCL_DMA_QUERY 0x00000188 +#define NV50TCL_DMA_VTXBUF0 0x0000018c +#define NV50TCL_DMA_LOCAL 0x00000190 +#define NV50TCL_DMA_STACK 0x00000194 +#define NV50TCL_DMA_CODE_CB 0x00000198 +#define NV50TCL_DMA_TSC 0x0000019c +#define NV50TCL_DMA_TIC 0x000001a0 +#define NV50TCL_DMA_TEXTURE 0x000001a4 +#define NV50TCL_DMA_STRMOUT 0x000001a8 +#define NV50TCL_DMA_CLIPID 0x000001ac +#define NV50TCL_DMA_COLOR(x) (0x000001c0+((x)*4)) +#define NV50TCL_DMA_COLOR__SIZE 0x00000008 +#define NV50TCL_RT_ADDRESS_HIGH(x) (0x00000200+((x)*32)) +#define NV50TCL_RT_ADDRESS_HIGH__SIZE 0x00000008 +#define NV50TCL_RT_ADDRESS_LOW(x) (0x00000204+((x)*32)) +#define NV50TCL_RT_ADDRESS_LOW__SIZE 0x00000008 +#define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32)) +#define NV50TCL_RT_FORMAT__SIZE 0x00000008 +#define NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50TCL_RT_FORMAT_R32G32B32A32_SINT 0x000000c1 +#define NV50TCL_RT_FORMAT_R32G32B32A32_UINT 0x000000c2 +#define NV50TCL_RT_FORMAT_R32G32B32X32_FLOAT 0x000000c3 +#define NV50TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50TCL_RT_FORMAT_R16G16B16A16_SINT 0x000000c8 +#define NV50TCL_RT_FORMAT_R16G16B16A16_UINT 0x000000c9 +#define NV50TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50TCL_RT_FORMAT_R32G32_SINT 0x000000cc +#define NV50TCL_RT_FORMAT_R32G32_UINT 0x000000cd +#define NV50TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50TCL_RT_FORMAT_A8R8G8B8_SRGB 0x000000d0 +#define NV50TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50TCL_RT_FORMAT_A2B10G10R10_UINT 0x000000d2 +#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d5 +#define NV50TCL_RT_FORMAT_A8B8G8R8_SRGB 0x000000d6 +#define NV50TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50TCL_RT_FORMAT_A8B8G8R8_SINT 0x000000d8 +#define NV50TCL_RT_FORMAT_A8B8G8R8_UINT 0x000000d9 +#define NV50TCL_RT_FORMAT_R16G16_UNORM 0x000000da +#define NV50TCL_RT_FORMAT_R16G16_SNORM 0x000000db +#define NV50TCL_RT_FORMAT_R16G16_SINT 0x000000dc +#define NV50TCL_RT_FORMAT_R16G16_UINT 0x000000dd +#define NV50TCL_RT_FORMAT_R16G16_FLOAT 0x000000de +#define NV50TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50TCL_RT_FORMAT_R32_FLOAT 0x000000e5 +#define NV50TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50TCL_RT_FORMAT_X8R8G8B8_SRGB 0x000000e7 +#define NV50TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50TCL_RT_FORMAT_A1R5G5B5_UNORM 0x000000e9 +#define NV50TCL_RT_FORMAT_R8G8_UNORM 0x000000ea +#define NV50TCL_RT_FORMAT_R8G8_SNORM 0x000000eb +#define NV50TCL_RT_FORMAT_R8G8_SINT 0x000000ec +#define NV50TCL_RT_FORMAT_R8G8_UINT 0x000000ed +#define NV50TCL_RT_FORMAT_R16_UNORM 0x000000ee +#define NV50TCL_RT_FORMAT_R16_SNORM 0x000000ef +#define NV50TCL_RT_FORMAT_R16_SINT 0x000000f0 +#define NV50TCL_RT_FORMAT_R16_UINT 0x000000f1 +#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000f2 +#define NV50TCL_RT_FORMAT_R8_UNORM 0x000000f3 +#define NV50TCL_RT_FORMAT_R8_SNORM 0x000000f4 +#define NV50TCL_RT_FORMAT_R8_SINT 0x000000f5 +#define NV50TCL_RT_FORMAT_R8_UINT 0x000000f6 +#define NV50TCL_RT_FORMAT_A8_UNORM 0x000000f7 +#define NV50TCL_RT_FORMAT_X1R5G5B5_UNORM 0x000000f8 +#define NV50TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50TCL_RT_FORMAT_X8B8G8R8_SRGB 0x000000fa +#define NV50TCL_RT_TILE_MODE(x) (0x0000020c+((x)*32)) +#define NV50TCL_RT_TILE_MODE__SIZE 0x00000008 +#define NV50TCL_RT_LAYER_STRIDE(x) (0x00000210+((x)*32)) +#define NV50TCL_RT_LAYER_STRIDE__SIZE 0x00000008 +#define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4)) +#define NV50TCL_VTX_ATTR_1F__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_2H(x) (0x00000340+((x)*4)) +#define NV50TCL_VTX_ATTR_2H__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_2H_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_2H_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_2H_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_2H_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_2F_X(x) (0x00000380+((x)*8)) +#define NV50TCL_VTX_ATTR_2F_X__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_2F_Y(x) (0x00000384+((x)*8)) +#define NV50TCL_VTX_ATTR_2F_Y__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_3F_X(x) (0x00000400+((x)*16)) +#define NV50TCL_VTX_ATTR_3F_X__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_3F_Y(x) (0x00000404+((x)*16)) +#define NV50TCL_VTX_ATTR_3F_Y__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_3F_Z(x) (0x00000408+((x)*16)) +#define NV50TCL_VTX_ATTR_3F_Z__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4F_X(x) (0x00000500+((x)*16)) +#define NV50TCL_VTX_ATTR_4F_X__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4F_Y(x) (0x00000504+((x)*16)) +#define NV50TCL_VTX_ATTR_4F_Y__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4F_Z(x) (0x00000508+((x)*16)) +#define NV50TCL_VTX_ATTR_4F_Z__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4F_W(x) (0x0000050c+((x)*16)) +#define NV50TCL_VTX_ATTR_4F_W__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4H_0(x) (0x00000600+((x)*8)) +#define NV50TCL_VTX_ATTR_4H_0__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4H_0_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4H_0_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4H_0_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_4H_0_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4H_1(x) (0x00000604+((x)*8)) +#define NV50TCL_VTX_ATTR_4H_1__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4H_1_Z_SHIFT 0 +#define NV50TCL_VTX_ATTR_4H_1_Z_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4H_1_W_SHIFT 16 +#define NV50TCL_VTX_ATTR_4H_1_W_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_2I(x) (0x00000680+((x)*4)) +#define NV50TCL_VTX_ATTR_2I__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_2I_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_2I_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_2I_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_2I_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_2NI(x) (0x000006c0+((x)*4)) +#define NV50TCL_VTX_ATTR_2NI__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_2NI_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_2NI_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_2NI_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_2NI_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4I_0(x) (0x00000700+((x)*8)) +#define NV50TCL_VTX_ATTR_4I_0__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4I_0_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4I_0_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4I_0_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_4I_0_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4I_1(x) (0x00000704+((x)*8)) +#define NV50TCL_VTX_ATTR_4I_1__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4I_1_Z_SHIFT 0 +#define NV50TCL_VTX_ATTR_4I_1_Z_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4I_1_W_SHIFT 16 +#define NV50TCL_VTX_ATTR_4I_1_W_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4NI_0(x) (0x00000780+((x)*8)) +#define NV50TCL_VTX_ATTR_4NI_0__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4NI_0_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4NI_0_X_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4NI_0_Y_SHIFT 16 +#define NV50TCL_VTX_ATTR_4NI_0_Y_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4NI_1(x) (0x00000784+((x)*8)) +#define NV50TCL_VTX_ATTR_4NI_1__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4NI_1_Z_SHIFT 0 +#define NV50TCL_VTX_ATTR_4NI_1_Z_MASK 0x0000ffff +#define NV50TCL_VTX_ATTR_4NI_1_W_SHIFT 16 +#define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000 +#define NV50TCL_VTX_ATTR_4UB(x) (0x00000800+((x)*4)) +#define NV50TCL_VTX_ATTR_4UB__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4UB_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4UB_X_MASK 0x000000ff +#define NV50TCL_VTX_ATTR_4UB_Y_SHIFT 8 +#define NV50TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00 +#define NV50TCL_VTX_ATTR_4UB_Z_SHIFT 16 +#define NV50TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000 +#define NV50TCL_VTX_ATTR_4UB_W_SHIFT 24 +#define NV50TCL_VTX_ATTR_4UB_W_MASK 0xff000000 +#define NV50TCL_VTX_ATTR_4B(x) (0x00000840+((x)*4)) +#define NV50TCL_VTX_ATTR_4B__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4B_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4B_X_MASK 0x000000ff +#define NV50TCL_VTX_ATTR_4B_Y_SHIFT 8 +#define NV50TCL_VTX_ATTR_4B_Y_MASK 0x0000ff00 +#define NV50TCL_VTX_ATTR_4B_Z_SHIFT 16 +#define NV50TCL_VTX_ATTR_4B_Z_MASK 0x00ff0000 +#define NV50TCL_VTX_ATTR_4B_W_SHIFT 24 +#define NV50TCL_VTX_ATTR_4B_W_MASK 0xff000000 +#define NV50TCL_VTX_ATTR_4NUB(x) (0x00000880+((x)*4)) +#define NV50TCL_VTX_ATTR_4NUB__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4NUB_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4NUB_X_MASK 0x000000ff +#define NV50TCL_VTX_ATTR_4NUB_Y_SHIFT 8 +#define NV50TCL_VTX_ATTR_4NUB_Y_MASK 0x0000ff00 +#define NV50TCL_VTX_ATTR_4NUB_Z_SHIFT 16 +#define NV50TCL_VTX_ATTR_4NUB_Z_MASK 0x00ff0000 +#define NV50TCL_VTX_ATTR_4NUB_W_SHIFT 24 +#define NV50TCL_VTX_ATTR_4NUB_W_MASK 0xff000000 +#define NV50TCL_VTX_ATTR_4NB(x) (0x000008c0+((x)*4)) +#define NV50TCL_VTX_ATTR_4NB__SIZE 0x00000010 +#define NV50TCL_VTX_ATTR_4NB_X_SHIFT 0 +#define NV50TCL_VTX_ATTR_4NB_X_MASK 0x000000ff +#define NV50TCL_VTX_ATTR_4NB_Y_SHIFT 8 +#define NV50TCL_VTX_ATTR_4NB_Y_MASK 0x0000ff00 +#define NV50TCL_VTX_ATTR_4NB_Z_SHIFT 16 +#define NV50TCL_VTX_ATTR_4NB_Z_MASK 0x00ff0000 +#define NV50TCL_VTX_ATTR_4NB_W_SHIFT 24 +#define NV50TCL_VTX_ATTR_4NB_W_MASK 0xff000000 +#define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16)) +#define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010 +#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT 0 +#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x00000fff +#define NV50TCL_VERTEX_ARRAY_FORMAT_ENABLE (1 << 29) +#define NV50TCL_VERTEX_ARRAY_START_HIGH(x) (0x00000904+((x)*16)) +#define NV50TCL_VERTEX_ARRAY_START_HIGH__SIZE 0x00000010 +#define NV50TCL_VERTEX_ARRAY_START_LOW(x) (0x00000908+((x)*16)) +#define NV50TCL_VERTEX_ARRAY_START_LOW__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_SCALE_X(x) (0x00000a00+((x)*32)) +#define NV50TCL_VIEWPORT_SCALE_X__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_SCALE_Y(x) (0x00000a04+((x)*32)) +#define NV50TCL_VIEWPORT_SCALE_Y__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_SCALE_Z(x) (0x00000a08+((x)*32)) +#define NV50TCL_VIEWPORT_SCALE_Z__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_TRANSLATE_X(x) (0x00000a0c+((x)*32)) +#define NV50TCL_VIEWPORT_TRANSLATE_X__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_TRANSLATE_Y(x) (0x00000a10+((x)*32)) +#define NV50TCL_VIEWPORT_TRANSLATE_Y__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_TRANSLATE_Z(x) (0x00000a14+((x)*32)) +#define NV50TCL_VIEWPORT_TRANSLATE_Z__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_HORIZ(x) (0x00000c00+((x)*16)) +#define NV50TCL_VIEWPORT_HORIZ__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0 +#define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff +#define NV50TCL_VIEWPORT_HORIZ_W_SHIFT 16 +#define NV50TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000 +#define NV50TCL_VIEWPORT_VERT(x) (0x00000c04+((x)*16)) +#define NV50TCL_VIEWPORT_VERT__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_VERT_Y_SHIFT 0 +#define NV50TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff +#define NV50TCL_VIEWPORT_VERT_H_SHIFT 16 +#define NV50TCL_VIEWPORT_VERT_H_MASK 0xffff0000 +#define NV50TCL_DEPTH_RANGE_NEAR(x) (0x00000c08+((x)*16)) +#define NV50TCL_DEPTH_RANGE_NEAR__SIZE 0x00000010 +#define NV50TCL_DEPTH_RANGE_FAR(x) (0x00000c0c+((x)*16)) +#define NV50TCL_DEPTH_RANGE_FAR__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_CLIP_HORIZ(x) (0x00000d00+((x)*8)) +#define NV50TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008 +#define NV50TCL_VIEWPORT_CLIP_HORIZ_MIN_SHIFT 0 +#define NV50TCL_VIEWPORT_CLIP_HORIZ_MIN_MASK 0x0000ffff +#define NV50TCL_VIEWPORT_CLIP_HORIZ_MAX_SHIFT 16 +#define NV50TCL_VIEWPORT_CLIP_HORIZ_MAX_MASK 0xffff0000 +#define NV50TCL_VIEWPORT_CLIP_VERT(x) (0x00000d04+((x)*8)) +#define NV50TCL_VIEWPORT_CLIP_VERT__SIZE 0x00000008 +#define NV50TCL_VIEWPORT_CLIP_VERT_MIN_SHIFT 0 +#define NV50TCL_VIEWPORT_CLIP_VERT_MIN_MASK 0x0000ffff +#define NV50TCL_VIEWPORT_CLIP_VERT_MAX_SHIFT 16 +#define NV50TCL_VIEWPORT_CLIP_VERT_MAX_MASK 0xffff0000 +#define NV50TCL_CLIPID_REGION_HORIZ(x) (0x00000d40+((x)*8)) +#define NV50TCL_CLIPID_REGION_HORIZ__SIZE 0x00000004 +#define NV50TCL_CLIPID_REGION_VERT(x) (0x00000d44+((x)*8)) +#define NV50TCL_CLIPID_REGION_VERT__SIZE 0x00000004 +#define NV50TCL_VERTEX_BUFFER_FIRST 0x00000d74 +#define NV50TCL_VERTEX_BUFFER_COUNT 0x00000d78 +#define NV50TCL_CLEAR_COLOR(x) (0x00000d80+((x)*4)) +#define NV50TCL_CLEAR_COLOR__SIZE 0x00000004 +#define NV50TCL_CLEAR_DEPTH 0x00000d90 +#define NV50TCL_STACK_ADDRESS_HIGH 0x00000d94 +#define NV50TCL_STACK_ADDRESS_LOW 0x00000d98 +#define NV50TCL_STACK_SIZE_LOG 0x00000d9c +#define NV50TCL_CLEAR_STENCIL 0x00000da0 +#define NV50TCL_STRMOUT_PRIMITIVE_COUNT 0x00000da8 +#define NV50TCL_POLYGON_MODE_FRONT 0x00000dac +#define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NV50TCL_POLYGON_MODE_FRONT_FILL 0x00001b02 +#define NV50TCL_POLYGON_MODE_BACK 0x00000db0 +#define NV50TCL_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NV50TCL_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NV50TCL_POLYGON_MODE_BACK_FILL 0x00001b02 +#define NV50TCL_POLYGON_SMOOTH_ENABLE 0x00000db4 +#define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0 +#define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4 +#define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8 +#define NV50TCL_WATCHDOG_TIMER 0x00000de4 +#define NV50TCL_WINDOW_OFFSET_X 0x00000df8 +#define NV50TCL_WINDOW_OFFSET_Y 0x00000dfc +#define NV50TCL_SCISSOR_ENABLE(x) (0x00000e00+((x)*16)) +#define NV50TCL_SCISSOR_ENABLE__SIZE 0x00000010 +#define NV50TCL_SCISSOR_HORIZ(x) (0x00000e04+((x)*16)) +#define NV50TCL_SCISSOR_HORIZ__SIZE 0x00000010 +#define NV50TCL_SCISSOR_HORIZ_MIN_SHIFT 0 +#define NV50TCL_SCISSOR_HORIZ_MIN_MASK 0x0000ffff +#define NV50TCL_SCISSOR_HORIZ_MAX_SHIFT 16 +#define NV50TCL_SCISSOR_HORIZ_MAX_MASK 0xffff0000 +#define NV50TCL_SCISSOR_VERT(x) (0x00000e08+((x)*16)) +#define NV50TCL_SCISSOR_VERT__SIZE 0x00000010 +#define NV50TCL_SCISSOR_VERT_MIN_SHIFT 0 +#define NV50TCL_SCISSOR_VERT_MIN_MASK 0x0000ffff +#define NV50TCL_SCISSOR_VERT_MAX_SHIFT 16 +#define NV50TCL_SCISSOR_VERT_MAX_MASK 0xffff0000 +#define NV50TCL_CB_ADDR 0x00000f00 +#define NV50TCL_CB_ADDR_ID_SHIFT 8 +#define NV50TCL_CB_ADDR_ID_MASK 0x003fff00 +#define NV50TCL_CB_ADDR_BUFFER_SHIFT 0 +#define NV50TCL_CB_ADDR_BUFFER_MASK 0x0000007f +#define NV50TCL_CB_DATA(x) (0x00000f04+((x)*4)) +#define NV50TCL_CB_DATA__SIZE 0x00000010 +#define NV50TCL_LOCAL_WARPS_LOG_ALLOC 0x00000f44 +#define NV50TCL_LOCAL_WARPS_NO_CLAMP 0x00000f48 +#define NV50TCL_STACK_WARPS_LOG_ALLOC 0x00000f4c +#define NV50TCL_STACK_WARPS_NO_CLAMP 0x00000f50 +#define NV50TCL_STENCIL_BACK_FUNC_REF 0x00000f54 +#define NV50TCL_STENCIL_BACK_MASK 0x00000f58 +#define NV50TCL_STENCIL_BACK_FUNC_MASK 0x00000f5c +#define NV50TCL_GP_ADDRESS_HIGH 0x00000f70 +#define NV50TCL_GP_ADDRESS_LOW 0x00000f74 +#define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c +#define NV50TCL_VP_ADDRESS_LOW 0x00000f80 +#define NV50TCL_VERTEX_RUNOUT_HIGH 0x00000f84 +#define NV50TCL_VERTEX_RUNOUT_LOW 0x00000f88 +#define NV50TCL_DEPTH_BOUNDS(x) (0x00000f9c+((x)*4)) +#define NV50TCL_DEPTH_BOUNDS__SIZE 0x00000002 +#define NV50TCL_FP_ADDRESS_HIGH 0x00000fa4 +#define NV50TCL_FP_ADDRESS_LOW 0x00000fa8 +#define NV50TCL_MSAA_MASK(x) (0x00000fbc+((x)*4)) +#define NV50TCL_MSAA_MASK__SIZE 0x00000004 +#define NV50TCL_CLIPID_ADDRESS_HIGH 0x00000fcc +#define NV50TCL_CLIPID_ADDRESS_LOW 0x00000fd0 +#define NV50TCL_ZETA_ADDRESS_HIGH 0x00000fe0 +#define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4 +#define NV50TCL_ZETA_FORMAT 0x00000fe8 +#define NV50TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a +#define NV50TCL_ZETA_FORMAT_Z16_UNORM 0x00000013 +#define NV50TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014 +#define NV50TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015 +#define NV50TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016 +#define NV50TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019 +#define NV50TCL_ZETA_TILE_MODE 0x00000fec +#define NV50TCL_ZETA_LAYER_STRIDE 0x00000ff0 +#define NV50TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_SHIFT 0 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_MASK 0x0000ffff +#define NV50TCL_SCREEN_SCISSOR_VERT 0x00000ff8 +#define NV50TCL_SCREEN_SCISSOR_VERT_H_SHIFT 16 +#define NV50TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000 +#define NV50TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0 +#define NV50TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff +#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(x) (0x00001080+((x)*8)) +#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH__SIZE 0x00000010 +#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW(x) (0x00001084+((x)*8)) +#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW__SIZE 0x00000010 +#define NV50TCL_RT_CONTROL 0x0000121c +#define NV50TCL_RT_CONTROL_COUNT_SHIFT 0 +#define NV50TCL_RT_CONTROL_COUNT_MASK 0x0000000f +#define NV50TCL_RT_CONTROL_MAP0_SHIFT 4 +#define NV50TCL_RT_CONTROL_MAP0_MASK 0x00000070 +#define NV50TCL_RT_CONTROL_MAP1_SHIFT 7 +#define NV50TCL_RT_CONTROL_MAP1_MASK 0x00000380 +#define NV50TCL_RT_CONTROL_MAP2_SHIFT 10 +#define NV50TCL_RT_CONTROL_MAP2_MASK 0x00001c00 +#define NV50TCL_RT_CONTROL_MAP3_SHIFT 13 +#define NV50TCL_RT_CONTROL_MAP3_MASK 0x0000e000 +#define NV50TCL_RT_CONTROL_MAP4_SHIFT 16 +#define NV50TCL_RT_CONTROL_MAP4_MASK 0x00070000 +#define NV50TCL_RT_CONTROL_MAP5_SHIFT 19 +#define NV50TCL_RT_CONTROL_MAP5_MASK 0x00380000 +#define NV50TCL_RT_CONTROL_MAP6_SHIFT 22 +#define NV50TCL_RT_CONTROL_MAP6_MASK 0x01c00000 +#define NV50TCL_RT_CONTROL_MAP7_SHIFT 25 +#define NV50TCL_RT_CONTROL_MAP7_MASK 0x0e000000 +#define NV50TCL_RT_ARRAY_MODE 0x00001224 +#define NV50TCL_RT_ARRAY_MODE_LAYERS_SHIFT 0 +#define NV50TCL_RT_ARRAY_MODE_LAYERS_MASK 0x0000ffff +#define NV50TCL_RT_ARRAY_MODE_VOLUME (1 << 16) +#define NV50TCL_ZETA_HORIZ 0x00001228 +#define NV50TCL_ZETA_VERT 0x0000122c +#define NV50TCL_ZETA_ARRAY_MODE 0x00001230 +#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_SHIFT 0 +#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_MASK 0x0000ffff +#define NV50TCL_ZETA_ARRAY_MODE_UNK (1 << 16) +#define NV50TCL_LINKED_TSC 0x00001234 +#define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8)) +#define NV50TCL_RT_HORIZ__SIZE 0x00000008 +#define NV50TCL_RT_VERT(x) (0x00001244+((x)*8)) +#define NV50TCL_RT_VERT__SIZE 0x00000008 +#define NV50TCL_CB_DEF_ADDRESS_HIGH 0x00001280 +#define NV50TCL_CB_DEF_ADDRESS_LOW 0x00001284 +#define NV50TCL_CB_DEF_SET 0x00001288 +#define NV50TCL_CB_DEF_SET_SIZE_SHIFT 0 +#define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff +#define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16 +#define NV50TCL_CB_DEF_SET_BUFFER_MASK 0x007f0000 +#define NV50TCL_STRMOUT_BUFFERS_CTRL 0x00001294 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_INTERLEAVED (1 << 0) +#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_SHIFT 4 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_MASK 0x000000f0 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_SHIFT 8 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_MASK 0x0000ff00 +#define NV50TCL_FP_RESULT_COUNT 0x00001298 +#define NV50TCL_DEPTH_TEST_ENABLE 0x000012cc +#define NV50TCL_SHADE_MODEL 0x000012d4 +#define NV50TCL_SHADE_MODEL_FLAT 0x00001d00 +#define NV50TCL_SHADE_MODEL_SMOOTH 0x00001d01 +#define NV50TCL_LOCAL_ADDRESS_HIGH 0x000012d8 +#define NV50TCL_LOCAL_ADDRESS_LOW 0x000012dc +#define NV50TCL_LOCAL_SIZE_LOG 0x000012e0 +#define NV50TCL_DEPTH_WRITE_ENABLE 0x000012e8 +#define NV50TCL_ALPHA_TEST_ENABLE 0x000012ec +#define NV50TCL_PM_SET(x) (0x000012f0+((x)*4)) +#define NV50TCL_PM_SET__SIZE 0x00000004 +#define NV50TCL_VB_ELEMENT_U8_SETUP 0x00001300 +#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_SHIFT 30 +#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_MASK 0xc0000000 +#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_SHIFT 0 +#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_MASK 0x3fffffff +#define NV50TCL_VB_ELEMENT_U8 0x00001304 +#define NV50TCL_VB_ELEMENT_U8_I0_SHIFT 0 +#define NV50TCL_VB_ELEMENT_U8_I0_MASK 0x000000ff +#define NV50TCL_VB_ELEMENT_U8_I1_SHIFT 8 +#define NV50TCL_VB_ELEMENT_U8_I1_MASK 0x0000ff00 +#define NV50TCL_VB_ELEMENT_U8_I2_SHIFT 16 +#define NV50TCL_VB_ELEMENT_U8_I2_MASK 0x00ff0000 +#define NV50TCL_VB_ELEMENT_U8_I3_SHIFT 24 +#define NV50TCL_VB_ELEMENT_U8_I3_MASK 0xff000000 +#define NV50TCL_DEPTH_TEST_FUNC 0x0000130c +#define NV50TCL_DEPTH_TEST_FUNC_NEVER 0x00000200 +#define NV50TCL_DEPTH_TEST_FUNC_LESS 0x00000201 +#define NV50TCL_DEPTH_TEST_FUNC_EQUAL 0x00000202 +#define NV50TCL_DEPTH_TEST_FUNC_LEQUAL 0x00000203 +#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204 +#define NV50TCL_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205 +#define NV50TCL_DEPTH_TEST_FUNC_GEQUAL 0x00000206 +#define NV50TCL_DEPTH_TEST_FUNC_ALWAYS 0x00000207 +#define NV50TCL_ALPHA_TEST_REF 0x00001310 +#define NV50TCL_ALPHA_TEST_FUNC 0x00001314 +#define NV50TCL_ALPHA_TEST_FUNC_NEVER 0x00000200 +#define NV50TCL_ALPHA_TEST_FUNC_LESS 0x00000201 +#define NV50TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202 +#define NV50TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203 +#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204 +#define NV50TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205 +#define NV50TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206 +#define NV50TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207 +#define NV50TCL_BLEND_COLOR(x) (0x0000131c+((x)*4)) +#define NV50TCL_BLEND_COLOR__SIZE 0x00000004 +#define NV50TCL_TIC_FLUSH 0x00001330 +#define NV50TCL_TSC_FLUSH 0x00001334 +#define NV50TCL_TEX_CACHE_CTL 0x00001338 +#define NV50TCL_BLEND_EQUATION_RGB 0x00001340 +#define NV50TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 +#define NV50TCL_BLEND_EQUATION_RGB_MIN 0x00008007 +#define NV50TCL_BLEND_EQUATION_RGB_MAX 0x00008008 +#define NV50TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a +#define NV50TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV50TCL_BLEND_FUNC_SRC_RGB 0x00001344 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ZERO 0x00004000 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE 0x00004001 +#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00004300 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00004302 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00004304 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV50TCL_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00004306 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00004307 +#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00004308 +#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x0000c001 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 +#define NV50TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x0000c003 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 +#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC1_COLOR 0x0000c900 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 +#define NV50TCL_BLEND_FUNC_SRC_RGB_SRC1_ALPHA 0x0000c902 +#define NV50TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 +#define NV50TCL_BLEND_FUNC_DST_RGB 0x00001348 +#define NV50TCL_BLEND_FUNC_DST_RGB_ZERO 0x00004000 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE 0x00004001 +#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00004300 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00004302 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV50TCL_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00004304 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV50TCL_BLEND_FUNC_DST_RGB_DST_COLOR 0x00004306 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00004307 +#define NV50TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00004308 +#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x0000c001 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x0000c002 +#define NV50TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x0000c003 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 +#define NV50TCL_BLEND_FUNC_DST_RGB_SRC1_COLOR 0x0000c900 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_COLOR 0x0000c901 +#define NV50TCL_BLEND_FUNC_DST_RGB_SRC1_ALPHA 0x0000c902 +#define NV50TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC1_ALPHA 0x0000c903 +#define NV50TCL_BLEND_EQUATION_ALPHA 0x0000134c +#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_ADD 0x00008006 +#define NV50TCL_BLEND_EQUATION_ALPHA_MIN 0x00008007 +#define NV50TCL_BLEND_EQUATION_ALPHA_MAX 0x00008008 +#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x0000800a +#define NV50TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV50TCL_BLEND_FUNC_SRC_ALPHA 0x00001350 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ZERO 0x00004000 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE 0x00004001 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x00004300 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x00004302 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x00004304 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x00004306 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x00004308 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x0000c001 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x0000c003 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC1_COLOR 0x0000c900 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_SRC1_ALPHA 0x0000c902 +#define NV50TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 +#define NV50TCL_BLEND_FUNC_DST_ALPHA 0x00001358 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ZERO 0x00004000 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE 0x00004001 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x00004300 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x00004302 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x00004304 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x00004306 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x00004307 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x00004308 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x0000c001 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x0000c002 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x0000c003 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x0000c004 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC1_COLOR 0x0000c900 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_COLOR 0x0000c901 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_SRC1_ALPHA 0x0000c902 +#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC1_ALPHA 0x0000c903 +#define NV50TCL_BLEND_ENABLE(x) (0x00001360+((x)*4)) +#define NV50TCL_BLEND_ENABLE__SIZE 0x00000008 +#define NV50TCL_STENCIL_FRONT_ENABLE 0x00001380 +#define NV50TCL_STENCIL_FRONT_OP_FAIL 0x00001384 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a +#define NV50TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL 0x00001388 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR 0x00001e02 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS 0x0000138c +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR 0x00001e02 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC 0x00001390 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 +#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 +#define NV50TCL_STENCIL_FRONT_FUNC_REF 0x00001394 +#define NV50TCL_STENCIL_FRONT_MASK 0x00001398 +#define NV50TCL_STENCIL_FRONT_FUNC_MASK 0x0000139c +#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8 +#define NV50TCL_Y_ORIGIN_BOTTOM 0x000013ac +#define NV50TCL_LINE_WIDTH 0x000013b0 +#define NV50TCL_TEX_LIMITS(x) (0x000013b4+((x)*4)) +#define NV50TCL_TEX_LIMITS__SIZE 0x00000003 +#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0 +#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f +#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4 +#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0 +#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4)) +#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008 +#define NV50TCL_VP_START_ID 0x0000140c +#define NV50TCL_GP_START_ID 0x00001410 +#define NV50TCL_FP_START_ID 0x00001414 +#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420 +#define NV50TCL_VB_ELEMENT_BASE 0x00001434 +#define NV50TCL_INSTANCE_BASE 0x00001438 +#define NV50TCL_CODE_CB_FLUSH 0x00001440 +#define NV50TCL_BIND_TSC(x) (0x00001444+((x)*8)) +#define NV50TCL_BIND_TSC__SIZE 0x00000003 +#define NV50TCL_BIND_TSC_VALID (1 << 0) +#define NV50TCL_BIND_TSC_SAMPLER_SHIFT 4 +#define NV50TCL_BIND_TSC_SAMPLER_MASK 0x000000f0 +#define NV50TCL_BIND_TSC_TSC_SHIFT 12 +#define NV50TCL_BIND_TSC_TSC_MASK 0x001ff000 +#define NV50TCL_BIND_TIC(x) (0x00001448+((x)*8)) +#define NV50TCL_BIND_TIC__SIZE 0x00000003 +#define NV50TCL_BIND_TIC_VALID (1 << 0) +#define NV50TCL_BIND_TIC_TEXTURE_SHIFT 1 +#define NV50TCL_BIND_TIC_TEXTURE_MASK 0x000001fe +#define NV50TCL_BIND_TIC_TIC_SHIFT 9 +#define NV50TCL_BIND_TIC_TIC_MASK 0x7ffffe00 +#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4)) +#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020 +#define NV50TCL_CLIPID_HEIGHT 0x00001504 +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510 +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_6 (1 << 6) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_7 (1 << 7) +#define NV50TCL_SAMPLECNT_ENABLE 0x00001514 +#define NV50TCL_POINT_SIZE 0x00001518 +#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520 +#define NV50TCL_SAMPLECNT_RESET 0x00001530 +#define NV50TCL_ZETA_ENABLE 0x00001538 +#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c +#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0) +#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4) +#define NV50TCL_NOPERSPECTIVE_BITMAP(x) (0x00001540+((x)*4)) +#define NV50TCL_NOPERSPECTIVE_BITMAP__SIZE 0x00000004 +#define NV50TCL_COND_ADDRESS_HIGH 0x00001550 +#define NV50TCL_COND_ADDRESS_LOW 0x00001554 +#define NV50TCL_COND_MODE 0x00001558 +#define NV50TCL_COND_MODE_NEVER 0x00000000 +#define NV50TCL_COND_MODE_ALWAYS 0x00000001 +#define NV50TCL_COND_MODE_RES 0x00000002 +#define NV50TCL_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 +#define NV50TCL_COND_MODE_RES_OR_ID 0x00000004 +#define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c +#define NV50TCL_TSC_ADDRESS_LOW 0x00001560 +#define NV50TCL_TSC_LIMIT 0x00001564 +#define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c +#define NV50TCL_LINE_SMOOTH_ENABLE 0x00001570 +#define NV50TCL_TIC_ADDRESS_HIGH 0x00001574 +#define NV50TCL_TIC_ADDRESS_LOW 0x00001578 +#define NV50TCL_TIC_LIMIT 0x0000157c +#define NV50TCL_PM_CONTROL(x) (0x00001580+((x)*4)) +#define NV50TCL_PM_CONTROL__SIZE 0x00000004 +#define NV50TCL_PM_CONTROL_UNK0 (1 << 0) +#define NV50TCL_PM_CONTROL_UNK1_SHIFT 4 +#define NV50TCL_PM_CONTROL_UNK1_MASK 0x00000070 +#define NV50TCL_PM_CONTROL_UNK2_SHIFT 8 +#define NV50TCL_PM_CONTROL_UNK2_MASK 0xffffff00 +#define NV50TCL_STENCIL_BACK_ENABLE 0x00001594 +#define NV50TCL_STENCIL_BACK_OP_FAIL 0x00001598 +#define NV50TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 +#define NV50TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a +#define NV50TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00 +#define NV50TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02 +#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03 +#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL 0x0000159c +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_BACK_OP_ZPASS 0x000015a0 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a +#define NV50TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC 0x000015a4 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 +#define NV50TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 +#define NV50TCL_FRAMEBUFFER_SRGB 0x000015b8 +#define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc +#define NV50TCL_GP_BUILTIN_RESULT_EN 0x000015cc +#define NV50TCL_GP_BUILTIN_RESULT_EN_VPORT_IDX (1 << 0) +#define NV50TCL_GP_BUILTIN_RESULT_EN_LAYER_IDX (1 << 16) +#define NV50TCL_MULTISAMPLE_MODE 0x000015d0 +#define NV50TCL_MULTISAMPLE_MODE_1X 0x00000000 +#define NV50TCL_MULTISAMPLE_MODE_2XMS 0x00000001 +#define NV50TCL_MULTISAMPLE_MODE_4XMS 0x00000002 +#define NV50TCL_MULTISAMPLE_MODE_8XMS 0x00000004 +#define NV50TCL_MULTISAMPLE_MODE_4XMS_4XCS 0x00000008 +#define NV50TCL_MULTISAMPLE_MODE_4XMS_12XCS 0x00000009 +#define NV50TCL_MULTISAMPLE_MODE_8XMS_8XCS 0x0000000a +#define NV50TCL_VERTEX_BEGIN 0x000015dc +#define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000 +#define NV50TCL_VERTEX_BEGIN_LINES 0x00000001 +#define NV50TCL_VERTEX_BEGIN_LINE_LOOP 0x00000002 +#define NV50TCL_VERTEX_BEGIN_LINE_STRIP 0x00000003 +#define NV50TCL_VERTEX_BEGIN_TRIANGLES 0x00000004 +#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP 0x00000005 +#define NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN 0x00000006 +#define NV50TCL_VERTEX_BEGIN_QUADS 0x00000007 +#define NV50TCL_VERTEX_BEGIN_QUAD_STRIP 0x00000008 +#define NV50TCL_VERTEX_BEGIN_POLYGON 0x00000009 +#define NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY 0x0000000a +#define NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY 0x0000000b +#define NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY 0x0000000c +#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY 0x0000000d +#define NV50TCL_VERTEX_BEGIN_PATCHES 0x0000000e +#define NV50TCL_VERTEX_END 0x000015e0 +#define NV50TCL_EDGEFLAG_ENABLE 0x000015e4 +#define NV50TCL_VB_ELEMENT_U32 0x000015e8 +#define NV50TCL_VB_ELEMENT_U16_SETUP 0x000015ec +#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_SHIFT 30 +#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_MASK 0xc0000000 +#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_SHIFT 0 +#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_MASK 0x3fffffff +#define NV50TCL_VB_ELEMENT_U16 0x000015f0 +#define NV50TCL_VB_ELEMENT_U16_I0_SHIFT 0 +#define NV50TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff +#define NV50TCL_VB_ELEMENT_U16_I1_SHIFT 16 +#define NV50TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000 +#define NV50TCL_VERTEX_BASE_HIGH 0x000015f4 +#define NV50TCL_VERTEX_BASE_LOW 0x000015f8 +#define NV50TCL_VERTEX_DATA 0x00001640 +#define NV50TCL_PRIM_RESTART_ENABLE 0x00001644 +#define NV50TCL_PRIM_RESTART_INDEX 0x00001648 +#define NV50TCL_VP_GP_BUILTIN_ATTR_EN 0x0000164c +#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID (1 << 0) +#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID (1 << 4) +#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID (1 << 8) +#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_UNK12 (1 << 12) +#define NV50TCL_VP_ATTR_EN_0 0x00001650 +#define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28 +#define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000 +#define NV50TCL_VP_ATTR_EN_0_7_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_7_XNNN 0x10000000 +#define NV50TCL_VP_ATTR_EN_0_7_NYNN 0x20000000 +#define NV50TCL_VP_ATTR_EN_0_7_XYNN 0x30000000 +#define NV50TCL_VP_ATTR_EN_0_7_NNZN 0x40000000 +#define NV50TCL_VP_ATTR_EN_0_7_XNZN 0x50000000 +#define NV50TCL_VP_ATTR_EN_0_7_NYZN 0x60000000 +#define NV50TCL_VP_ATTR_EN_0_7_XYZN 0x70000000 +#define NV50TCL_VP_ATTR_EN_0_7_NNNW 0x80000000 +#define NV50TCL_VP_ATTR_EN_0_7_XNNW 0x90000000 +#define NV50TCL_VP_ATTR_EN_0_7_NYNW 0xa0000000 +#define NV50TCL_VP_ATTR_EN_0_7_XYNW 0xb0000000 +#define NV50TCL_VP_ATTR_EN_0_7_NNZW 0xc0000000 +#define NV50TCL_VP_ATTR_EN_0_7_XNZW 0xd0000000 +#define NV50TCL_VP_ATTR_EN_0_7_NYZW 0xe0000000 +#define NV50TCL_VP_ATTR_EN_0_7_XYZW 0xf0000000 +#define NV50TCL_VP_ATTR_EN_0_6_SHIFT 24 +#define NV50TCL_VP_ATTR_EN_0_6_MASK 0x0f000000 +#define NV50TCL_VP_ATTR_EN_0_6_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_6_XNNN 0x01000000 +#define NV50TCL_VP_ATTR_EN_0_6_NYNN 0x02000000 +#define NV50TCL_VP_ATTR_EN_0_6_XYNN 0x03000000 +#define NV50TCL_VP_ATTR_EN_0_6_NNZN 0x04000000 +#define NV50TCL_VP_ATTR_EN_0_6_XNZN 0x05000000 +#define NV50TCL_VP_ATTR_EN_0_6_NYZN 0x06000000 +#define NV50TCL_VP_ATTR_EN_0_6_XYZN 0x07000000 +#define NV50TCL_VP_ATTR_EN_0_6_NNNW 0x08000000 +#define NV50TCL_VP_ATTR_EN_0_6_XNNW 0x09000000 +#define NV50TCL_VP_ATTR_EN_0_6_NYNW 0x0a000000 +#define NV50TCL_VP_ATTR_EN_0_6_XYNW 0x0b000000 +#define NV50TCL_VP_ATTR_EN_0_6_NNZW 0x0c000000 +#define NV50TCL_VP_ATTR_EN_0_6_XNZW 0x0d000000 +#define NV50TCL_VP_ATTR_EN_0_6_NYZW 0x0e000000 +#define NV50TCL_VP_ATTR_EN_0_6_XYZW 0x0f000000 +#define NV50TCL_VP_ATTR_EN_0_5_SHIFT 20 +#define NV50TCL_VP_ATTR_EN_0_5_MASK 0x00f00000 +#define NV50TCL_VP_ATTR_EN_0_5_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_5_XNNN 0x00100000 +#define NV50TCL_VP_ATTR_EN_0_5_NYNN 0x00200000 +#define NV50TCL_VP_ATTR_EN_0_5_XYNN 0x00300000 +#define NV50TCL_VP_ATTR_EN_0_5_NNZN 0x00400000 +#define NV50TCL_VP_ATTR_EN_0_5_XNZN 0x00500000 +#define NV50TCL_VP_ATTR_EN_0_5_NYZN 0x00600000 +#define NV50TCL_VP_ATTR_EN_0_5_XYZN 0x00700000 +#define NV50TCL_VP_ATTR_EN_0_5_NNNW 0x00800000 +#define NV50TCL_VP_ATTR_EN_0_5_XNNW 0x00900000 +#define NV50TCL_VP_ATTR_EN_0_5_NYNW 0x00a00000 +#define NV50TCL_VP_ATTR_EN_0_5_XYNW 0x00b00000 +#define NV50TCL_VP_ATTR_EN_0_5_NNZW 0x00c00000 +#define NV50TCL_VP_ATTR_EN_0_5_XNZW 0x00d00000 +#define NV50TCL_VP_ATTR_EN_0_5_NYZW 0x00e00000 +#define NV50TCL_VP_ATTR_EN_0_5_XYZW 0x00f00000 +#define NV50TCL_VP_ATTR_EN_0_4_SHIFT 16 +#define NV50TCL_VP_ATTR_EN_0_4_MASK 0x000f0000 +#define NV50TCL_VP_ATTR_EN_0_4_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_4_XNNN 0x00010000 +#define NV50TCL_VP_ATTR_EN_0_4_NYNN 0x00020000 +#define NV50TCL_VP_ATTR_EN_0_4_XYNN 0x00030000 +#define NV50TCL_VP_ATTR_EN_0_4_NNZN 0x00040000 +#define NV50TCL_VP_ATTR_EN_0_4_XNZN 0x00050000 +#define NV50TCL_VP_ATTR_EN_0_4_NYZN 0x00060000 +#define NV50TCL_VP_ATTR_EN_0_4_XYZN 0x00070000 +#define NV50TCL_VP_ATTR_EN_0_4_NNNW 0x00080000 +#define NV50TCL_VP_ATTR_EN_0_4_XNNW 0x00090000 +#define NV50TCL_VP_ATTR_EN_0_4_NYNW 0x000a0000 +#define NV50TCL_VP_ATTR_EN_0_4_XYNW 0x000b0000 +#define NV50TCL_VP_ATTR_EN_0_4_NNZW 0x000c0000 +#define NV50TCL_VP_ATTR_EN_0_4_XNZW 0x000d0000 +#define NV50TCL_VP_ATTR_EN_0_4_NYZW 0x000e0000 +#define NV50TCL_VP_ATTR_EN_0_4_XYZW 0x000f0000 +#define NV50TCL_VP_ATTR_EN_0_3_SHIFT 12 +#define NV50TCL_VP_ATTR_EN_0_3_MASK 0x0000f000 +#define NV50TCL_VP_ATTR_EN_0_3_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_3_XNNN 0x00001000 +#define NV50TCL_VP_ATTR_EN_0_3_NYNN 0x00002000 +#define NV50TCL_VP_ATTR_EN_0_3_XYNN 0x00003000 +#define NV50TCL_VP_ATTR_EN_0_3_NNZN 0x00004000 +#define NV50TCL_VP_ATTR_EN_0_3_XNZN 0x00005000 +#define NV50TCL_VP_ATTR_EN_0_3_NYZN 0x00006000 +#define NV50TCL_VP_ATTR_EN_0_3_XYZN 0x00007000 +#define NV50TCL_VP_ATTR_EN_0_3_NNNW 0x00008000 +#define NV50TCL_VP_ATTR_EN_0_3_XNNW 0x00009000 +#define NV50TCL_VP_ATTR_EN_0_3_NYNW 0x0000a000 +#define NV50TCL_VP_ATTR_EN_0_3_XYNW 0x0000b000 +#define NV50TCL_VP_ATTR_EN_0_3_NNZW 0x0000c000 +#define NV50TCL_VP_ATTR_EN_0_3_XNZW 0x0000d000 +#define NV50TCL_VP_ATTR_EN_0_3_NYZW 0x0000e000 +#define NV50TCL_VP_ATTR_EN_0_3_XYZW 0x0000f000 +#define NV50TCL_VP_ATTR_EN_0_2_SHIFT 8 +#define NV50TCL_VP_ATTR_EN_0_2_MASK 0x00000f00 +#define NV50TCL_VP_ATTR_EN_0_2_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_2_XNNN 0x00000100 +#define NV50TCL_VP_ATTR_EN_0_2_NYNN 0x00000200 +#define NV50TCL_VP_ATTR_EN_0_2_XYNN 0x00000300 +#define NV50TCL_VP_ATTR_EN_0_2_NNZN 0x00000400 +#define NV50TCL_VP_ATTR_EN_0_2_XNZN 0x00000500 +#define NV50TCL_VP_ATTR_EN_0_2_NYZN 0x00000600 +#define NV50TCL_VP_ATTR_EN_0_2_XYZN 0x00000700 +#define NV50TCL_VP_ATTR_EN_0_2_NNNW 0x00000800 +#define NV50TCL_VP_ATTR_EN_0_2_XNNW 0x00000900 +#define NV50TCL_VP_ATTR_EN_0_2_NYNW 0x00000a00 +#define NV50TCL_VP_ATTR_EN_0_2_XYNW 0x00000b00 +#define NV50TCL_VP_ATTR_EN_0_2_NNZW 0x00000c00 +#define NV50TCL_VP_ATTR_EN_0_2_XNZW 0x00000d00 +#define NV50TCL_VP_ATTR_EN_0_2_NYZW 0x00000e00 +#define NV50TCL_VP_ATTR_EN_0_2_XYZW 0x00000f00 +#define NV50TCL_VP_ATTR_EN_0_1_SHIFT 4 +#define NV50TCL_VP_ATTR_EN_0_1_MASK 0x000000f0 +#define NV50TCL_VP_ATTR_EN_0_1_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_1_XNNN 0x00000010 +#define NV50TCL_VP_ATTR_EN_0_1_NYNN 0x00000020 +#define NV50TCL_VP_ATTR_EN_0_1_XYNN 0x00000030 +#define NV50TCL_VP_ATTR_EN_0_1_NNZN 0x00000040 +#define NV50TCL_VP_ATTR_EN_0_1_XNZN 0x00000050 +#define NV50TCL_VP_ATTR_EN_0_1_NYZN 0x00000060 +#define NV50TCL_VP_ATTR_EN_0_1_XYZN 0x00000070 +#define NV50TCL_VP_ATTR_EN_0_1_NNNW 0x00000080 +#define NV50TCL_VP_ATTR_EN_0_1_XNNW 0x00000090 +#define NV50TCL_VP_ATTR_EN_0_1_NYNW 0x000000a0 +#define NV50TCL_VP_ATTR_EN_0_1_XYNW 0x000000b0 +#define NV50TCL_VP_ATTR_EN_0_1_NNZW 0x000000c0 +#define NV50TCL_VP_ATTR_EN_0_1_XNZW 0x000000d0 +#define NV50TCL_VP_ATTR_EN_0_1_NYZW 0x000000e0 +#define NV50TCL_VP_ATTR_EN_0_1_XYZW 0x000000f0 +#define NV50TCL_VP_ATTR_EN_0_0_SHIFT 0 +#define NV50TCL_VP_ATTR_EN_0_0_MASK 0x0000000f +#define NV50TCL_VP_ATTR_EN_0_0_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_0_0_XNNN 0x00000001 +#define NV50TCL_VP_ATTR_EN_0_0_NYNN 0x00000002 +#define NV50TCL_VP_ATTR_EN_0_0_XYNN 0x00000003 +#define NV50TCL_VP_ATTR_EN_0_0_NNZN 0x00000004 +#define NV50TCL_VP_ATTR_EN_0_0_XNZN 0x00000005 +#define NV50TCL_VP_ATTR_EN_0_0_NYZN 0x00000006 +#define NV50TCL_VP_ATTR_EN_0_0_XYZN 0x00000007 +#define NV50TCL_VP_ATTR_EN_0_0_NNNW 0x00000008 +#define NV50TCL_VP_ATTR_EN_0_0_XNNW 0x00000009 +#define NV50TCL_VP_ATTR_EN_0_0_NYNW 0x0000000a +#define NV50TCL_VP_ATTR_EN_0_0_XYNW 0x0000000b +#define NV50TCL_VP_ATTR_EN_0_0_NNZW 0x0000000c +#define NV50TCL_VP_ATTR_EN_0_0_XNZW 0x0000000d +#define NV50TCL_VP_ATTR_EN_0_0_NYZW 0x0000000e +#define NV50TCL_VP_ATTR_EN_0_0_XYZW 0x0000000f +#define NV50TCL_VP_ATTR_EN_1 0x00001654 +#define NV50TCL_VP_ATTR_EN_1_15_SHIFT 28 +#define NV50TCL_VP_ATTR_EN_1_15_MASK 0xf0000000 +#define NV50TCL_VP_ATTR_EN_1_15_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_15_XNNN 0x10000000 +#define NV50TCL_VP_ATTR_EN_1_15_NYNN 0x20000000 +#define NV50TCL_VP_ATTR_EN_1_15_XYNN 0x30000000 +#define NV50TCL_VP_ATTR_EN_1_15_NNZN 0x40000000 +#define NV50TCL_VP_ATTR_EN_1_15_XNZN 0x50000000 +#define NV50TCL_VP_ATTR_EN_1_15_NYZN 0x60000000 +#define NV50TCL_VP_ATTR_EN_1_15_XYZN 0x70000000 +#define NV50TCL_VP_ATTR_EN_1_15_NNNW 0x80000000 +#define NV50TCL_VP_ATTR_EN_1_15_XNNW 0x90000000 +#define NV50TCL_VP_ATTR_EN_1_15_NYNW 0xa0000000 +#define NV50TCL_VP_ATTR_EN_1_15_XYNW 0xb0000000 +#define NV50TCL_VP_ATTR_EN_1_15_NNZW 0xc0000000 +#define NV50TCL_VP_ATTR_EN_1_15_XNZW 0xd0000000 +#define NV50TCL_VP_ATTR_EN_1_15_NYZW 0xe0000000 +#define NV50TCL_VP_ATTR_EN_1_15_XYZW 0xf0000000 +#define NV50TCL_VP_ATTR_EN_1_14_SHIFT 24 +#define NV50TCL_VP_ATTR_EN_1_14_MASK 0x0f000000 +#define NV50TCL_VP_ATTR_EN_1_14_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_14_XNNN 0x01000000 +#define NV50TCL_VP_ATTR_EN_1_14_NYNN 0x02000000 +#define NV50TCL_VP_ATTR_EN_1_14_XYNN 0x03000000 +#define NV50TCL_VP_ATTR_EN_1_14_NNZN 0x04000000 +#define NV50TCL_VP_ATTR_EN_1_14_XNZN 0x05000000 +#define NV50TCL_VP_ATTR_EN_1_14_NYZN 0x06000000 +#define NV50TCL_VP_ATTR_EN_1_14_XYZN 0x07000000 +#define NV50TCL_VP_ATTR_EN_1_14_NNNW 0x08000000 +#define NV50TCL_VP_ATTR_EN_1_14_XNNW 0x09000000 +#define NV50TCL_VP_ATTR_EN_1_14_NYNW 0x0a000000 +#define NV50TCL_VP_ATTR_EN_1_14_XYNW 0x0b000000 +#define NV50TCL_VP_ATTR_EN_1_14_NNZW 0x0c000000 +#define NV50TCL_VP_ATTR_EN_1_14_XNZW 0x0d000000 +#define NV50TCL_VP_ATTR_EN_1_14_NYZW 0x0e000000 +#define NV50TCL_VP_ATTR_EN_1_14_XYZW 0x0f000000 +#define NV50TCL_VP_ATTR_EN_1_13_SHIFT 20 +#define NV50TCL_VP_ATTR_EN_1_13_MASK 0x00f00000 +#define NV50TCL_VP_ATTR_EN_1_13_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_13_XNNN 0x00100000 +#define NV50TCL_VP_ATTR_EN_1_13_NYNN 0x00200000 +#define NV50TCL_VP_ATTR_EN_1_13_XYNN 0x00300000 +#define NV50TCL_VP_ATTR_EN_1_13_NNZN 0x00400000 +#define NV50TCL_VP_ATTR_EN_1_13_XNZN 0x00500000 +#define NV50TCL_VP_ATTR_EN_1_13_NYZN 0x00600000 +#define NV50TCL_VP_ATTR_EN_1_13_XYZN 0x00700000 +#define NV50TCL_VP_ATTR_EN_1_13_NNNW 0x00800000 +#define NV50TCL_VP_ATTR_EN_1_13_XNNW 0x00900000 +#define NV50TCL_VP_ATTR_EN_1_13_NYNW 0x00a00000 +#define NV50TCL_VP_ATTR_EN_1_13_XYNW 0x00b00000 +#define NV50TCL_VP_ATTR_EN_1_13_NNZW 0x00c00000 +#define NV50TCL_VP_ATTR_EN_1_13_XNZW 0x00d00000 +#define NV50TCL_VP_ATTR_EN_1_13_NYZW 0x00e00000 +#define NV50TCL_VP_ATTR_EN_1_13_XYZW 0x00f00000 +#define NV50TCL_VP_ATTR_EN_1_12_SHIFT 16 +#define NV50TCL_VP_ATTR_EN_1_12_MASK 0x000f0000 +#define NV50TCL_VP_ATTR_EN_1_12_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_12_XNNN 0x00010000 +#define NV50TCL_VP_ATTR_EN_1_12_NYNN 0x00020000 +#define NV50TCL_VP_ATTR_EN_1_12_XYNN 0x00030000 +#define NV50TCL_VP_ATTR_EN_1_12_NNZN 0x00040000 +#define NV50TCL_VP_ATTR_EN_1_12_XNZN 0x00050000 +#define NV50TCL_VP_ATTR_EN_1_12_NYZN 0x00060000 +#define NV50TCL_VP_ATTR_EN_1_12_XYZN 0x00070000 +#define NV50TCL_VP_ATTR_EN_1_12_NNNW 0x00080000 +#define NV50TCL_VP_ATTR_EN_1_12_XNNW 0x00090000 +#define NV50TCL_VP_ATTR_EN_1_12_NYNW 0x000a0000 +#define NV50TCL_VP_ATTR_EN_1_12_XYNW 0x000b0000 +#define NV50TCL_VP_ATTR_EN_1_12_NNZW 0x000c0000 +#define NV50TCL_VP_ATTR_EN_1_12_XNZW 0x000d0000 +#define NV50TCL_VP_ATTR_EN_1_12_NYZW 0x000e0000 +#define NV50TCL_VP_ATTR_EN_1_12_XYZW 0x000f0000 +#define NV50TCL_VP_ATTR_EN_1_11_SHIFT 12 +#define NV50TCL_VP_ATTR_EN_1_11_MASK 0x0000f000 +#define NV50TCL_VP_ATTR_EN_1_11_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_11_XNNN 0x00001000 +#define NV50TCL_VP_ATTR_EN_1_11_NYNN 0x00002000 +#define NV50TCL_VP_ATTR_EN_1_11_XYNN 0x00003000 +#define NV50TCL_VP_ATTR_EN_1_11_NNZN 0x00004000 +#define NV50TCL_VP_ATTR_EN_1_11_XNZN 0x00005000 +#define NV50TCL_VP_ATTR_EN_1_11_NYZN 0x00006000 +#define NV50TCL_VP_ATTR_EN_1_11_XYZN 0x00007000 +#define NV50TCL_VP_ATTR_EN_1_11_NNNW 0x00008000 +#define NV50TCL_VP_ATTR_EN_1_11_XNNW 0x00009000 +#define NV50TCL_VP_ATTR_EN_1_11_NYNW 0x0000a000 +#define NV50TCL_VP_ATTR_EN_1_11_XYNW 0x0000b000 +#define NV50TCL_VP_ATTR_EN_1_11_NNZW 0x0000c000 +#define NV50TCL_VP_ATTR_EN_1_11_XNZW 0x0000d000 +#define NV50TCL_VP_ATTR_EN_1_11_NYZW 0x0000e000 +#define NV50TCL_VP_ATTR_EN_1_11_XYZW 0x0000f000 +#define NV50TCL_VP_ATTR_EN_1_10_SHIFT 8 +#define NV50TCL_VP_ATTR_EN_1_10_MASK 0x00000f00 +#define NV50TCL_VP_ATTR_EN_1_10_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_10_XNNN 0x00000100 +#define NV50TCL_VP_ATTR_EN_1_10_NYNN 0x00000200 +#define NV50TCL_VP_ATTR_EN_1_10_XYNN 0x00000300 +#define NV50TCL_VP_ATTR_EN_1_10_NNZN 0x00000400 +#define NV50TCL_VP_ATTR_EN_1_10_XNZN 0x00000500 +#define NV50TCL_VP_ATTR_EN_1_10_NYZN 0x00000600 +#define NV50TCL_VP_ATTR_EN_1_10_XYZN 0x00000700 +#define NV50TCL_VP_ATTR_EN_1_10_NNNW 0x00000800 +#define NV50TCL_VP_ATTR_EN_1_10_XNNW 0x00000900 +#define NV50TCL_VP_ATTR_EN_1_10_NYNW 0x00000a00 +#define NV50TCL_VP_ATTR_EN_1_10_XYNW 0x00000b00 +#define NV50TCL_VP_ATTR_EN_1_10_NNZW 0x00000c00 +#define NV50TCL_VP_ATTR_EN_1_10_XNZW 0x00000d00 +#define NV50TCL_VP_ATTR_EN_1_10_NYZW 0x00000e00 +#define NV50TCL_VP_ATTR_EN_1_10_XYZW 0x00000f00 +#define NV50TCL_VP_ATTR_EN_1_9_SHIFT 4 +#define NV50TCL_VP_ATTR_EN_1_9_MASK 0x000000f0 +#define NV50TCL_VP_ATTR_EN_1_9_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_9_XNNN 0x00000010 +#define NV50TCL_VP_ATTR_EN_1_9_NYNN 0x00000020 +#define NV50TCL_VP_ATTR_EN_1_9_XYNN 0x00000030 +#define NV50TCL_VP_ATTR_EN_1_9_NNZN 0x00000040 +#define NV50TCL_VP_ATTR_EN_1_9_XNZN 0x00000050 +#define NV50TCL_VP_ATTR_EN_1_9_NYZN 0x00000060 +#define NV50TCL_VP_ATTR_EN_1_9_XYZN 0x00000070 +#define NV50TCL_VP_ATTR_EN_1_9_NNNW 0x00000080 +#define NV50TCL_VP_ATTR_EN_1_9_XNNW 0x00000090 +#define NV50TCL_VP_ATTR_EN_1_9_NYNW 0x000000a0 +#define NV50TCL_VP_ATTR_EN_1_9_XYNW 0x000000b0 +#define NV50TCL_VP_ATTR_EN_1_9_NNZW 0x000000c0 +#define NV50TCL_VP_ATTR_EN_1_9_XNZW 0x000000d0 +#define NV50TCL_VP_ATTR_EN_1_9_NYZW 0x000000e0 +#define NV50TCL_VP_ATTR_EN_1_9_XYZW 0x000000f0 +#define NV50TCL_VP_ATTR_EN_1_8_SHIFT 0 +#define NV50TCL_VP_ATTR_EN_1_8_MASK 0x0000000f +#define NV50TCL_VP_ATTR_EN_1_8_NONE 0x00000000 +#define NV50TCL_VP_ATTR_EN_1_8_XNNN 0x00000001 +#define NV50TCL_VP_ATTR_EN_1_8_NYNN 0x00000002 +#define NV50TCL_VP_ATTR_EN_1_8_XYNN 0x00000003 +#define NV50TCL_VP_ATTR_EN_1_8_NNZN 0x00000004 +#define NV50TCL_VP_ATTR_EN_1_8_XNZN 0x00000005 +#define NV50TCL_VP_ATTR_EN_1_8_NYZN 0x00000006 +#define NV50TCL_VP_ATTR_EN_1_8_XYZN 0x00000007 +#define NV50TCL_VP_ATTR_EN_1_8_NNNW 0x00000008 +#define NV50TCL_VP_ATTR_EN_1_8_XNNW 0x00000009 +#define NV50TCL_VP_ATTR_EN_1_8_NYNW 0x0000000a +#define NV50TCL_VP_ATTR_EN_1_8_XYNW 0x0000000b +#define NV50TCL_VP_ATTR_EN_1_8_NNZW 0x0000000c +#define NV50TCL_VP_ATTR_EN_1_8_XNZW 0x0000000d +#define NV50TCL_VP_ATTR_EN_1_8_NYZW 0x0000000e +#define NV50TCL_VP_ATTR_EN_1_8_XYZW 0x0000000f +#define NV50TCL_POINT_SPRITE_CTRL 0x00001660 +#define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c +#define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680 +#define NV50TCL_PROVOKING_VERTEX_LAST 0x00001684 +#define NV50TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688 +#define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c +#define NV50TCL_SET_PROGRAM_CB 0x00001694 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_SHIFT 4 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_MASK 0x000000f0 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_VERTEX 0x00000000 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_GEOMETRY 0x00000020 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_FRAGMENT 0x00000030 +#define NV50TCL_SET_PROGRAM_CB_INDEX_SHIFT 8 +#define NV50TCL_SET_PROGRAM_CB_INDEX_MASK 0x00000f00 +#define NV50TCL_SET_PROGRAM_CB_BUFFER_SHIFT 12 +#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000 +#define NV50TCL_SET_PROGRAM_CB_VALID (1 << 0) +#define NV50TCL_VP_RESULT_MAP_SIZE 0x000016ac +#define NV50TCL_VP_REG_ALLOC_TEMP 0x000016b0 +#define NV50TCL_VP_REG_ALLOC_RESULT 0x000016b8 +#define NV50TCL_VP_RESULT_MAP(x) (0x000016bc+((x)*4)) +#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000010 +#define NV50TCL_VP_RESULT_MAP_0_SHIFT 0 +#define NV50TCL_VP_RESULT_MAP_0_MASK 0x000000ff +#define NV50TCL_VP_RESULT_MAP_1_SHIFT 8 +#define NV50TCL_VP_RESULT_MAP_1_MASK 0x0000ff00 +#define NV50TCL_VP_RESULT_MAP_2_SHIFT 16 +#define NV50TCL_VP_RESULT_MAP_2_MASK 0x00ff0000 +#define NV50TCL_VP_RESULT_MAP_3_SHIFT 24 +#define NV50TCL_VP_RESULT_MAP_3_MASK 0xff000000 +#define NV50TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4)) +#define NV50TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 +#define NV50TCL_GP_ENABLE 0x00001798 +#define NV50TCL_GP_REG_ALLOC_TEMP 0x000017a0 +#define NV50TCL_GP_REG_ALLOC_RESULT 0x000017a8 +#define NV50TCL_GP_RESULT_MAP_SIZE 0x000017ac +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE 0x000017b0 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS 0x00000001 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP 0x00000002 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000003 +#define NV50TCL_RASTERIZE_ENABLE 0x000017b4 +#define NV50TCL_STRMOUT_ENABLE 0x000017b8 +#define NV50TCL_GP_RESULT_MAP(x) (0x000017fc+((x)*4)) +#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000020 +#define NV50TCL_GP_RESULT_MAP_0_SHIFT 0 +#define NV50TCL_GP_RESULT_MAP_0_MASK 0x000000ff +#define NV50TCL_GP_RESULT_MAP_1_SHIFT 8 +#define NV50TCL_GP_RESULT_MAP_1_MASK 0x0000ff00 +#define NV50TCL_GP_RESULT_MAP_2_SHIFT 16 +#define NV50TCL_GP_RESULT_MAP_2_MASK 0x00ff0000 +#define NV50TCL_GP_RESULT_MAP_3_SHIFT 24 +#define NV50TCL_GP_RESULT_MAP_3_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_0 0x00001904 +#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_SHIFT 8 +#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_MASK 0x0000ff00 +#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_SHIFT 16 +#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_MASK 0x00ff0000 +#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_SHIFT 24 +#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_1 0x00001908 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_SHIFT 8 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_MASK 0x0000ff00 +#define NV50TCL_MAP_SEMANTIC_2 0x0000190c +#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_3 0x00001910 +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_EN (1 << 0) +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_SHIFT 4 +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_MASK 0x00000ff0 +#define NV50TCL_MAP_SEMANTIC_4 0x00001914 +#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_MASK 0x000000ff +#define NV50TCL_CULL_FACE_ENABLE 0x00001918 +#define NV50TCL_FRONT_FACE 0x0000191c +#define NV50TCL_FRONT_FACE_CW 0x00000900 +#define NV50TCL_FRONT_FACE_CCW 0x00000901 +#define NV50TCL_CULL_FACE 0x00001920 +#define NV50TCL_CULL_FACE_FRONT 0x00000404 +#define NV50TCL_CULL_FACE_BACK 0x00000405 +#define NV50TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 +#define NV50TCL_VIEWPORT_TRANSFORM_EN 0x0000192c +#define NV50TCL_VIEW_VOLUME_CLIP_CTRL 0x0000193c +#define NV50TCL_VIEWPORT_CLIP_RECTS_EN 0x0000194c +#define NV50TCL_VIEWPORT_CLIP_MODE 0x00001950 +#define NV50TCL_VIEWPORT_CLIP_MODE_INCLUDE 0x00000000 +#define NV50TCL_VIEWPORT_CLIP_MODE_EXCLUDE 0x00000001 +#define NV50TCL_VIEWPORT_CLIP_MODE_UNKNOWN 0x00000002 +#define NV50TCL_FP_CTRL_UNK196C 0x0000196c +#define NV50TCL_CLIPID_ENABLE 0x0000197c +#define NV50TCL_CLIPID_WIDTH 0x00001980 +#define NV50TCL_CLIPID_ID 0x00001984 +#define NV50TCL_FP_INTERPOLANT_CTRL 0x00001988 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_SHIFT 24 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_MASK 0xff000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NONE 0x00000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNN 0x01000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNN 0x02000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNN 0x03000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZN 0x04000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZN 0x05000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZN 0x06000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZN 0x07000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNNW 0x08000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNW 0x09000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNW 0x0a000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNW 0x0b000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZW 0x0c000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZW 0x0d000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZW 0x0e000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZW 0x0f000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_SHIFT 16 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_MASK 0x00ff0000 +#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_SHIFT 8 +#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_MASK 0x0000ff00 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 0 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x000000ff +#define NV50TCL_FP_REG_ALLOC_TEMP 0x0000198c +#define NV50TCL_REG_MODE 0x000019a0 +#define NV50TCL_REG_MODE_PACKED 0x00000001 +#define NV50TCL_REG_MODE_STRIPED 0x00000002 +#define NV50TCL_FP_CONTROL 0x000019a8 +#define NV50TCL_FP_CONTROL_MULTIPLE_RESULTS (1 << 0) +#define NV50TCL_FP_CONTROL_EXPORTS_Z (1 << 8) +#define NV50TCL_FP_CONTROL_USES_KIL (1 << 20) +#define NV50TCL_DEPTH_BOUNDS_EN 0x000019bc +#define NV50TCL_LOGIC_OP_ENABLE 0x000019c4 +#define NV50TCL_LOGIC_OP 0x000019c8 +#define NV50TCL_LOGIC_OP_CLEAR 0x00001500 +#define NV50TCL_LOGIC_OP_AND 0x00001501 +#define NV50TCL_LOGIC_OP_AND_REVERSE 0x00001502 +#define NV50TCL_LOGIC_OP_COPY 0x00001503 +#define NV50TCL_LOGIC_OP_AND_INVERTED 0x00001504 +#define NV50TCL_LOGIC_OP_NOOP 0x00001505 +#define NV50TCL_LOGIC_OP_XOR 0x00001506 +#define NV50TCL_LOGIC_OP_OR 0x00001507 +#define NV50TCL_LOGIC_OP_NOR 0x00001508 +#define NV50TCL_LOGIC_OP_EQUIV 0x00001509 +#define NV50TCL_LOGIC_OP_INVERT 0x0000150a +#define NV50TCL_LOGIC_OP_OR_REVERSE 0x0000150b +#define NV50TCL_LOGIC_OP_COPY_INVERTED 0x0000150c +#define NV50TCL_LOGIC_OP_OR_INVERTED 0x0000150d +#define NV50TCL_LOGIC_OP_NAND 0x0000150e +#define NV50TCL_LOGIC_OP_SET 0x0000150f +#define NV50TCL_CLEAR_BUFFERS 0x000019d0 +#define NV50TCL_CLEAR_BUFFERS_Z (1 << 0) +#define NV50TCL_CLEAR_BUFFERS_S (1 << 1) +#define NV50TCL_CLEAR_BUFFERS_R (1 << 2) +#define NV50TCL_CLEAR_BUFFERS_G (1 << 3) +#define NV50TCL_CLEAR_BUFFERS_B (1 << 4) +#define NV50TCL_CLEAR_BUFFERS_A (1 << 5) +#define NV50TCL_CLEAR_BUFFERS_RT_SHIFT 6 +#define NV50TCL_CLEAR_BUFFERS_RT_MASK 0x000003c0 +#define NV50TCL_CLEAR_BUFFERS_LAYER_SHIFT 10 +#define NV50TCL_CLEAR_BUFFERS_LAYER_MASK 0x0007fc00 +#define NV50TCL_COLOR_MASK(x) (0x00001a00+((x)*4)) +#define NV50TCL_COLOR_MASK__SIZE 0x00000008 +#define NV50TCL_COLOR_MASK_R_SHIFT 0 +#define NV50TCL_COLOR_MASK_R_MASK 0x0000000f +#define NV50TCL_COLOR_MASK_G_SHIFT 4 +#define NV50TCL_COLOR_MASK_G_MASK 0x000000f0 +#define NV50TCL_COLOR_MASK_B_SHIFT 8 +#define NV50TCL_COLOR_MASK_B_MASK 0x00000f00 +#define NV50TCL_COLOR_MASK_A_SHIFT 12 +#define NV50TCL_COLOR_MASK_A_MASK 0x0000f000 +#define NV50TCL_STRMOUT_ADDRESS_HIGH(x) (0x00001a80+((x)*16)) +#define NV50TCL_STRMOUT_ADDRESS_HIGH__SIZE 0x00000004 +#define NV50TCL_STRMOUT_ADDRESS_LOW(x) (0x00001a84+((x)*16)) +#define NV50TCL_STRMOUT_ADDRESS_LOW__SIZE 0x00000004 +#define NV50TCL_STRMOUT_NUM_ATTRIBS(x) (0x00001a88+((x)*16)) +#define NV50TCL_STRMOUT_NUM_ATTRIBS__SIZE 0x00000004 +#define NV50TCL_VERTEX_ARRAY_ATTRIB(x) (0x00001ac0+((x)*4)) +#define NV50TCL_VERTEX_ARRAY_ATTRIB__SIZE 0x00000010 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_SHIFT 0 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x0000000f +#define NV50TCL_VERTEX_ARRAY_ATTRIB_CONST (1 << 4) +#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_SHIFT 5 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_MASK 0x0007ffe0 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_SHIFT 19 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_MASK 0x01f80000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 0x00080000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32 0x00100000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16 0x00180000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32 0x00200000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16 0x00280000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8 0x00500000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16 0x00780000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32 0x00900000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8 0x00980000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8 0x00c00000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16 0x00d80000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8 0x00e80000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_2_10_10_10 0x01800000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SHIFT 25 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_MASK 0x0e000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT 0x0e000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM 0x02000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM 0x04000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED 0x0a000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED 0x0c000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT 0x08000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT 0x06000000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_BGRA (1 << 31) +#define NV50TCL_QUERY_ADDRESS_HIGH 0x00001b00 +#define NV50TCL_QUERY_ADDRESS_LOW 0x00001b04 +#define NV50TCL_QUERY_SEQUENCE 0x00001b08 +#define NV50TCL_QUERY_GET 0x00001b0c + + +#define NV84TCL 0x00008297 + + + +#define NVA0TCL 0x00008397 + + + +#define NVA8TCL 0x00008597 + + + +#define NV50_COMPUTE 0x000050c0 + +#define NV50_COMPUTE_NOP 0x00000100 +#define NV50_COMPUTE_NOTIFY 0x00000104 +#define NV50_COMPUTE_SERIALIZE 0x00000110 +#define NV50_COMPUTE_DMA_NOTIFY 0x00000180 +#define NV50_COMPUTE_DMA_GLOBAL 0x000001a0 +#define NV50_COMPUTE_DMA_QUERY 0x000001a4 +#define NV50_COMPUTE_DMA_LOCAL 0x000001b8 +#define NV50_COMPUTE_DMA_STACK 0x000001bc +#define NV50_COMPUTE_DMA_CODE_CB 0x000001c0 +#define NV50_COMPUTE_DMA_TSC 0x000001c4 +#define NV50_COMPUTE_DMA_TIC 0x000001c8 +#define NV50_COMPUTE_DMA_TEXTURE 0x000001cc +#define NV50_COMPUTE_CP_ADDRESS_HIGH 0x00000210 +#define NV50_COMPUTE_CP_ADDRESS_LOW 0x00000214 +#define NV50_COMPUTE_STACK_ADDRESS_HIGH 0x00000218 +#define NV50_COMPUTE_STACK_ADDRESS_LOW 0x0000021c +#define NV50_COMPUTE_STACK_SIZE_LOG 0x00000220 +#define NV50_COMPUTE_TSC_ADDRESS_HIGH 0x0000022c +#define NV50_COMPUTE_TSC_ADDRESS_LOW 0x00000230 +#define NV50_COMPUTE_TSC_LIMIT 0x00000234 +#define NV50_COMPUTE_CB_ADDR 0x00000238 +#define NV50_COMPUTE_CB_ADDR_ID_SHIFT 8 +#define NV50_COMPUTE_CB_ADDR_ID_MASK 0x003fff00 +#define NV50_COMPUTE_CB_ADDR_BUFFER_SHIFT 0 +#define NV50_COMPUTE_CB_ADDR_BUFFER_MASK 0x0000007f +#define NV50_COMPUTE_CB_DATA(x) (0x0000023c+((x)*4)) +#define NV50_COMPUTE_CB_DATA__SIZE 0x00000010 +#define NV50_COMPUTE_DELAY1 0x00000284 +#define NV50_COMPUTE_WATCHDOG_TIMER 0x00000288 +#define NV50_COMPUTE_DELAY2 0x0000028c +#define NV50_COMPUTE_LOCAL_ADDRESS_HIGH 0x00000294 +#define NV50_COMPUTE_LOCAL_ADDRESS_LOW 0x00000298 +#define NV50_COMPUTE_LOCAL_SIZE_LOG 0x0000029c +#define NV50_COMPUTE_CB_DEF_ADDRESS_HIGH 0x000002a4 +#define NV50_COMPUTE_CB_DEF_ADDRESS_LOW 0x000002a8 +#define NV50_COMPUTE_CB_DEF_SET 0x000002ac +#define NV50_COMPUTE_CB_DEF_SET_SIZE_SHIFT 0 +#define NV50_COMPUTE_CB_DEF_SET_SIZE_MASK 0x0000ffff +#define NV50_COMPUTE_CB_DEF_SET_BUFFER_SHIFT 16 +#define NV50_COMPUTE_CB_DEF_SET_BUFFER_MASK 0x007f0000 +#define NV50_COMPUTE_BLOCK_ALLOC 0x000002b4 +#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_SHIFT 0 +#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_MASK 0x0000ffff +#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_SHIFT 16 +#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_MASK 0xffff0000 +#define NV50_COMPUTE_LANES32_ENABLE 0x000002b8 +#define NV50_COMPUTE_CP_REG_ALLOC_TEMP 0x000002c0 +#define NV50_COMPUTE_TIC_ADDRESS_HIGH 0x000002c4 +#define NV50_COMPUTE_TIC_ADDRESS_LOW 0x000002c8 +#define NV50_COMPUTE_TIC_LIMIT 0x000002cc +#define NV50_COMPUTE_PM_SET(x) (0x000002d0+((x)*4)) +#define NV50_COMPUTE_PM_SET__SIZE 0x00000004 +#define NV50_COMPUTE_PM_CONTROL(x) (0x000002e0+((x)*4)) +#define NV50_COMPUTE_PM_CONTROL__SIZE 0x00000004 +#define NV50_COMPUTE_PM_CONTROL_UNK0 (1 << 0) +#define NV50_COMPUTE_PM_CONTROL_UNK1_SHIFT 4 +#define NV50_COMPUTE_PM_CONTROL_UNK1_MASK 0x00000070 +#define NV50_COMPUTE_PM_CONTROL_UNK2_SHIFT 8 +#define NV50_COMPUTE_PM_CONTROL_UNK2_MASK 0xffffff00 +#define NV50_COMPUTE_LOCAL_WARPS_LOG_ALLOC 0x000002fc +#define NV50_COMPUTE_LOCAL_WARPS_NO_CLAMP 0x00000300 +#define NV50_COMPUTE_STACK_WARPS_LOG_ALLOC 0x00000304 +#define NV50_COMPUTE_STACK_WARPS_NO_CLAMP 0x00000308 +#define NV50_COMPUTE_QUERY_ADDRESS_HIGH 0x00000310 +#define NV50_COMPUTE_QUERY_ADDRESS_LOW 0x00000314 +#define NV50_COMPUTE_QUERY_COUNTER 0x00000318 +#define NV50_COMPUTE_QUERY_GET 0x0000031c +#define NV50_COMPUTE_COND_ADDRESS_HIGH 0x00000320 +#define NV50_COMPUTE_COND_ADDRESS_LOW 0x00000324 +#define NV50_COMPUTE_COND_MODE 0x00000328 +#define NV50_COMPUTE_COND_MODE_NEVER 0x00000000 +#define NV50_COMPUTE_COND_MODE_ALWAYS 0x00000001 +#define NV50_COMPUTE_COND_MODE_RES 0x00000002 +#define NV50_COMPUTE_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003 +#define NV50_COMPUTE_COND_MODE_RES_OR_ID 0x00000004 +#define NV50_COMPUTE_LAUNCH 0x00000368 +#define NV50_COMPUTE_USER_PARAM_COUNT 0x00000374 +#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_SHIFT 8 +#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_MASK 0x0000ff00 +#define NV50_COMPUTE_LINKED_TSC 0x00000378 +#define NV50_COMPUTE_CODE_CB_FLUSH 0x00000380 +#define NV50_COMPUTE_GRIDDIM 0x000003a4 +#define NV50_COMPUTE_GRIDDIM_X_SHIFT 0 +#define NV50_COMPUTE_GRIDDIM_X_MASK 0x0000ffff +#define NV50_COMPUTE_GRIDDIM_Y_SHIFT 16 +#define NV50_COMPUTE_GRIDDIM_Y_MASK 0xffff0000 +#define NV50_COMPUTE_SHARED_SIZE 0x000003a8 +#define NV50_COMPUTE_BLOCKDIM_YX 0x000003ac +#define NV50_COMPUTE_BLOCKDIM_YX_X_SHIFT 0 +#define NV50_COMPUTE_BLOCKDIM_YX_X_MASK 0x0000ffff +#define NV50_COMPUTE_BLOCKDIM_YX_Y_SHIFT 16 +#define NV50_COMPUTE_BLOCKDIM_YX_Y_MASK 0xffff0000 +#define NV50_COMPUTE_BLOCKDIM_Z 0x000003b0 +#define NV50_COMPUTE_CP_START_ID 0x000003b4 +#define NV50_COMPUTE_REG_MODE 0x000003b8 +#define NV50_COMPUTE_REG_MODE_PACKED 0x00000001 +#define NV50_COMPUTE_REG_MODE_STRIPED 0x00000002 +#define NV50_COMPUTE_TEX_LIMITS 0x000003bc +#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0 +#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f +#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4 +#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0 +#define NV50_COMPUTE_BIND_TSC 0x000003c0 +#define NV50_COMPUTE_BIND_TSC_VALID (1 << 0) +#define NV50_COMPUTE_BIND_TSC_SAMPLER_SHIFT 4 +#define NV50_COMPUTE_BIND_TSC_SAMPLER_MASK 0x000000f0 +#define NV50_COMPUTE_BIND_TSC_TSC_SHIFT 12 +#define NV50_COMPUTE_BIND_TSC_TSC_MASK 0x001ff000 +#define NV50_COMPUTE_BIND_TIC 0x000003c4 +#define NV50_COMPUTE_BIND_TIC_VALID (1 << 0) +#define NV50_COMPUTE_BIND_TIC_TEXTURE_SHIFT 1 +#define NV50_COMPUTE_BIND_TIC_TEXTURE_MASK 0x000001fe +#define NV50_COMPUTE_BIND_TIC_TIC_SHIFT 9 +#define NV50_COMPUTE_BIND_TIC_TIC_MASK 0x7ffffe00 +#define NV50_COMPUTE_SET_PROGRAM_CB 0x000003c8 +#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_SHIFT 8 +#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_MASK 0x00000f00 +#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_SHIFT 12 +#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000 +#define NV50_COMPUTE_SET_PROGRAM_CB_VALID (1 << 0) +#define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH(x) (0x00000400+((x)*32)) +#define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH__SIZE 0x00000010 +#define NV50_COMPUTE_GLOBAL_ADDRESS_LOW(x) (0x00000404+((x)*32)) +#define NV50_COMPUTE_GLOBAL_ADDRESS_LOW__SIZE 0x00000010 +#define NV50_COMPUTE_GLOBAL_PITCH(x) (0x00000408+((x)*32)) +#define NV50_COMPUTE_GLOBAL_PITCH__SIZE 0x00000010 +#define NV50_COMPUTE_GLOBAL_LIMIT(x) (0x0000040c+((x)*32)) +#define NV50_COMPUTE_GLOBAL_LIMIT__SIZE 0x00000010 +#define NV50_COMPUTE_GLOBAL_MODE(x) (0x00000410+((x)*32)) +#define NV50_COMPUTE_GLOBAL_MODE__SIZE 0x00000010 +#define NV50_COMPUTE_GLOBAL_MODE_LINEAR (1 << 0) +#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_SHIFT 8 +#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_MASK 0x00000f00 +#define NV50_COMPUTE_USER_PARAM(x) (0x00000600+((x)*4)) +#define NV50_COMPUTE_USER_PARAM__SIZE 0x00000040 + + +#endif /* NOUVEAU_REG_H */ diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index 24a6d8055c8..49af9b59beb 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -85,8 +85,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 1; case PIPE_CAP_GLSL: return 1; - case PIPE_CAP_GEOMETRY_SHADER4: - return 0; case PIPE_CAP_ANISOTROPIC_FILTER: return 1; case PIPE_CAP_POINT_SPRITE: @@ -110,8 +108,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_SWIZZLE: return 1; - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 1; case PIPE_CAP_BLEND_EQUATION_SEPARATE: return 1; case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -126,38 +122,51 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */ + case PIPE_CAP_DEPTH_CLAMP: + return 1; + default: + NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); + return 0; + } +} + +static int +nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, + enum pipe_shader_cap param) +{ + switch(shader) { + case PIPE_SHADER_FRAGMENT: + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_GEOMETRY: + break; + default: + return 0; + } + + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: /* arbitrary limit */ return 16384; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */ + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: /* need stack bo */ return 4; - case PIPE_CAP_MAX_VS_INPUTS: - return 16; - case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */ - return 64 / 4; - case PIPE_CAP_MAX_VS_CONSTS: - case PIPE_CAP_MAX_FS_CONSTS: + case PIPE_SHADER_CAP_MAX_INPUTS: /* 128 / 4 with GP */ + if (shader == PIPE_SHADER_GEOMETRY) + return 128 / 4; + else + return 64 / 4; + case PIPE_SHADER_CAP_MAX_CONSTS: return 65536 / 16; - case PIPE_CAP_MAX_VS_ADDRS: - case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */ + case PIPE_SHADER_CAP_MAX_ADDRS: /* no spilling atm */ return 1; - case PIPE_CAP_MAX_VS_PREDS: - case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */ + case PIPE_SHADER_CAP_MAX_PREDS: /* not yet handled */ return 0; - case PIPE_CAP_MAX_VS_TEMPS: - case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */ + case PIPE_SHADER_CAP_MAX_TEMPS: /* no spilling atm */ return NV50_CAP_MAX_PROGRAM_TEMPS; - case PIPE_CAP_DEPTH_CLAMP: + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; default: - NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); return 0; } } @@ -292,6 +301,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) pscreen->winsys = ws; pscreen->destroy = nv50_screen_destroy; pscreen->get_param = nv50_screen_get_param; + pscreen->get_shader_param = nv50_screen_get_shader_param; pscreen->get_paramf = nv50_screen_get_paramf; pscreen->is_format_supported = nv50_screen_is_format_supported; pscreen->context_create = nv50_create; diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile index 6cbbad699eb..46bb0823881 100644 --- a/src/gallium/drivers/nvfx/Makefile +++ b/src/gallium/drivers/nvfx/Makefile @@ -19,14 +19,8 @@ C_SOURCES = \ nvfx_resource.c \ nvfx_screen.c \ nvfx_state.c \ - nvfx_state_blend.c \ - nvfx_state_emit.c \ + nvfx_state_emit.c \ nvfx_state_fb.c \ - nvfx_state_rasterizer.c \ - nvfx_state_scissor.c \ - nvfx_state_stipple.c \ - nvfx_state_viewport.c \ - nvfx_state_zsa.c \ nvfx_surface.c \ nvfx_transfer.c \ nvfx_vbo.c \ diff --git a/src/gallium/drivers/nvfx/SConscript b/src/gallium/drivers/nvfx/SConscript index 80e3ef2257f..f1041e77633 100644 --- a/src/gallium/drivers/nvfx/SConscript +++ b/src/gallium/drivers/nvfx/SConscript @@ -24,14 +24,8 @@ nvfx = env.ConvenienceLibrary( 'nvfx_resource.c', 'nvfx_screen.c', 'nvfx_state.c', - 'nvfx_state_blend.c', 'nvfx_state_emit.c', 'nvfx_state_fb.c', - 'nvfx_state_rasterizer.c', - 'nvfx_state_scissor.c', - 'nvfx_state_stipple.c', - 'nvfx_state_viewport.c', - 'nvfx_state_zsa.c', 'nvfx_surface.c', 'nvfx_transfer.c', 'nvfx_vbo.c', diff --git a/src/gallium/drivers/nvfx/nv01_2d.xml.h b/src/gallium/drivers/nvfx/nv01_2d.xml.h new file mode 100644 index 00000000000..b963eb7edce --- /dev/null +++ b/src/gallium/drivers/nvfx/nv01_2d.xml.h @@ -0,0 +1,1343 @@ +#ifndef NV01_2D_XML +#define NV01_2D_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv01_2d.xml ( 33462 bytes, from 2010-08-05 19:38:53) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <[email protected]> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <[email protected]> (koala_br) +- Carlos Martin <[email protected]> (carlosmn) +- Christoph Bumiller <[email protected]> (calim, chrisbmr) +- Dawid Gajownik <[email protected]> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <[email protected]> (lumag) +- EdB <[email protected]> (edb_) +- Erik Waling <[email protected]> (erikwaling) +- Francisco Jerez <[email protected]> (curro, curro_, currojerez) +- imirkin <[email protected]> (imirkin) +- jb17bsome <[email protected]> (jb17bsome) +- Jeremy Kolb <[email protected]> (kjeremy) +- Laurent Carlier <[email protected]> (lordheavy) +- Luca Barbieri <[email protected]> (lb, lb1) +- Maarten Maathuis <[email protected]> (stillunknown) +- Marcin Kościelnicki <[email protected]> (mwk, koriakin) +- Mark Carey <[email protected]> (careym) +- Matthieu Castet <[email protected]> (mat-c) +- nvidiaman <[email protected]> (nvidiaman) +- Patrice Mandin <[email protected]> (pmandin, pmdata) +- Pekka Paalanen <[email protected]> (pq, ppaalanen) +- Peter Popov <[email protected]> (ironpeter) +- Richard Hughes <[email protected]> (hughsient) +- Rudi Cilibrasi <[email protected]> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <[email protected]> (leroutier) +- Stephane Marchesin <[email protected]> (marcheu) +- sturmflut <[email protected]> (sturmflut) +- Sylvain Munaut <[email protected]> +- Victor Stinner <[email protected]> (haypo) +- Wladmir van der Laan <[email protected]> (miathan6) +- Younes Manton <[email protected]> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + + +#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300 + + +#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180 + +#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300 + + +#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304 + + +#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300 + +#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304 + +#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308 + +#define NV01_CONTEXT_PATTERN_COLOR(i0) (0x00000310 + 0x4*(i0)) +#define NV01_CONTEXT_PATTERN_COLOR__ESIZE 0x00000004 +#define NV01_CONTEXT_PATTERN_COLOR__LEN 0x00000002 + +#define NV01_CONTEXT_PATTERN_PATTERN(i0) (0x00000318 + 0x4*(i0)) +#define NV01_CONTEXT_PATTERN_PATTERN__ESIZE 0x00000004 +#define NV01_CONTEXT_PATTERN_PATTERN__LEN 0x00000002 + + +#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__MASK 0xffff0000 +#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__SHIFT 16 + +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__MASK 0x0000ffff +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__SHIFT 0 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__MASK 0xffff0000 +#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__SHIFT 16 + + +#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180 + +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184 + +#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188 + + +#define NV50_CONTEXT_SURFACES_2D_SRC_LINEAR 0x00000200 + +#define NV50_CONTEXT_SURFACES_2D_SRC_TILE_MODE 0x00000204 + +#define NV50_CONTEXT_SURFACES_2D_SRC_WIDTH 0x00000208 + +#define NV50_CONTEXT_SURFACES_2D_SRC_HEIGHT 0x0000020c + +#define NV50_CONTEXT_SURFACES_2D_UNK0210 0x00000210 + +#define NV50_CONTEXT_SURFACES_2D_UNK0214 0x00000214 + +#define NV50_CONTEXT_SURFACES_2D_DST_LINEAR 0x00000218 + +#define NV50_CONTEXT_SURFACES_2D_DST_TILE_MODE 0x0000021c + +#define NV50_CONTEXT_SURFACES_2D_DST_WIDTH 0x00000220 + +#define NV50_CONTEXT_SURFACES_2D_DST_HEIGHT 0x00000224 + +#define NV50_CONTEXT_SURFACES_2D_UNK0228 0x00000228 + +#define NV50_CONTEXT_SURFACES_2D_UNK022C 0x0000022c + +#define NV50_CONTEXT_SURFACES_2D_OFFSET_SOURCE_HIGH 0x00000230 + +#define NV50_CONTEXT_SURFACES_2D_OFFSET_DESTIN_HIGH 0x00000234 + +#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a +#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b + +#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__MASK 0x0000ffff +#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__SHIFT 0 +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__MASK 0xffff0000 +#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__SHIFT 16 + +#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308 + +#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c + + +#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180 + +#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184 + +#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__MASK 0x000000ff +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__SHIFT 0 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009 +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a +#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__MASK 0x00ff0000 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT 16 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__MASK 0xff000000 +#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT 24 + +#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304 + + +#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180 + +#define NV03_CONTEXT_ROP_ROP 0x00000300 + + +#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180 + +#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002 + +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001 +#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002 + +#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001 +#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002 + +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310 + +#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314 + +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318 + +#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c + +#define NV04_IMAGE_PATTERN_PATTERN_Y8(i0) (0x00000400 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_Y8__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_Y8__LEN 0x00000010 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__MASK 0x00ff0000 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__MASK 0xff000000 +#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__SHIFT 24 + +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(i0) (0x00000500 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__LEN 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__MASK 0x000007e0 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__MASK 0x0000f800 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__SHIFT 11 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__MASK 0x07e00000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__MASK 0xf8000000 +#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__SHIFT 27 + +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(i0) (0x00000600 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__LEN 0x00000020 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__MASK 0x0000001f +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__MASK 0x000003e0 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__SHIFT 5 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__MASK 0x00007c00 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__SHIFT 10 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__MASK 0x001f0000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__SHIFT 16 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__MASK 0x03e00000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__SHIFT 21 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__MASK 0x7c000000 +#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__SHIFT 26 + +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(i0) (0x00000700 + 0x4*(i0)) +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__ESIZE 0x00000004 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__LEN 0x00000040 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__MASK 0x000000ff +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__SHIFT 0 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__MASK 0x0000ff00 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__SHIFT 8 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__MASK 0x00ff0000 +#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__SHIFT 16 + + +#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_LINE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_LINE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_LINE_LINE_POINT0(i0) (0x00000400 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT0__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_LINE_POINT1(i0) (0x00000404 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE_POINT1__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(i0) (0x00000480 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(i0) (0x00000484 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(i0) (0x00000488 + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(i0) (0x0000048c + 0x10*(i0)) +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_POLYLINE(i0) (0x00000500 + 0x4*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE__ESIZE 0x00000004 +#define NV01_RENDER_SOLID_LINE_POLYLINE__LEN 0x00000020 +#define NV01_RENDER_SOLID_LINE_POLYLINE_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_POLYLINE_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(i0) (0x00000580 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(i0) (0x00000584 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(i0) (0x00000600 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__LEN 0x00000010 + +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(i0) (0x00000604 + 0x8*(i0)) +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__SHIFT 16 + + +#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_TRIANGLE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(i0) (0x00000400 + 0x4*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__ESIZE 0x00000004 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__LEN 0x00000020 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(i0) (0x00000480 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(i0) (0x00000484 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(i0) (0x00000500 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__LEN 0x00000008 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(i0) (0x00000504 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(i0) (0x00000508 + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(i0) (0x0000050c + 0x10*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__ESIZE 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__LEN 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(i0) (0x00000580 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__LEN 0x00000010 + +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(i0) (0x00000584 + 0x8*(i0)) +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__SHIFT 16 + + +#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c + +#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180 + +#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184 + +#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 + +#define NV04_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188 + +#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c + +#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190 + +#define NV01_RENDER_SOLID_RECTANGLE_SURFACE_DST 0x00000194 + + +#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194 + +#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198 + +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304 + +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__LEN 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__MASK 0xffff0000 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__SHIFT 16 + +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0)) +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__ESIZE 0x00000008 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__LEN 0x00000010 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__MASK 0x0000ffff +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__SHIFT 0 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__MASK 0xffff0000 +#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__SHIFT 16 + + +#define NV01_IMAGE_BLIT_PATCH 0x0000010c + + +#define NV11_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108 + +#define NV11_IMAGE_BLIT_UNK120 0x00000120 + +#define NV11_IMAGE_BLIT_UNK124 0x00000124 + +#define NV11_IMAGE_BLIT_UNK128 0x00000128 + +#define NV11_IMAGE_BLIT_UNK12C 0x0000012c + +#define NV11_IMAGE_BLIT_UNK130 0x00000130 + +#define NV11_IMAGE_BLIT_UNK134 0x00000134 + +#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180 + +#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184 + +#define NV04_IMAGE_BLIT_COLOR_KEY 0x00000184 + +#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188 + +#define NV01_IMAGE_BLIT_PATTERN 0x0000018c + +#define NV04_IMAGE_BLIT_PATTERN 0x0000018c + +#define NV01_IMAGE_BLIT_ROP 0x00000190 + +#define NV01_IMAGE_BLIT_BETA1 0x00000194 + + +#define NV01_IMAGE_BLIT_SURFACE_SRC 0x00000198 + +#define NV01_IMAGE_BLIT_SURFACE_DST 0x0000019c + + +#define NV04_IMAGE_BLIT_BETA4 0x00000198 + +#define NV04_IMAGE_BLIT_SURFACES 0x0000019c + +#define NV01_IMAGE_BLIT_OPERATION 0x000002fc +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_IMAGE_BLIT_POINT_IN 0x00000300 +#define NV01_IMAGE_BLIT_POINT_IN_X__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_IN_X__SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_IN_Y__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_POINT_IN_Y__SHIFT 16 + +#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304 +#define NV01_IMAGE_BLIT_POINT_OUT_X__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_POINT_OUT_X__SHIFT 0 +#define NV01_IMAGE_BLIT_POINT_OUT_Y__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_POINT_OUT_Y__SHIFT 16 + +#define NV01_IMAGE_BLIT_SIZE 0x00000308 +#define NV01_IMAGE_BLIT_SIZE_W__MASK 0x0000ffff +#define NV01_IMAGE_BLIT_SIZE_W__SHIFT 0 +#define NV01_IMAGE_BLIT_SIZE_H__MASK 0xffff0000 +#define NV01_IMAGE_BLIT_SIZE_H__SHIFT 16 + + +#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184 + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188 + +#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c + +#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190 + +#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194 + +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198 + +#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c + +#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 + +#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0 + +#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0 + +#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4 + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8 + +#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec + +#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0 + +#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4 + +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8 + +#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc + +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 + +#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV04_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 + +#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c + +#define NV04_IMAGE_FROM_CPU_PATTERN 0x0000018c + +#define NV01_IMAGE_FROM_CPU_ROP 0x00000190 + +#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194 + + +#define NV01_IMAGE_FROM_CPU_SURFACE_DST 0x00000198 + + +#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198 + +#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c + +#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + +#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000 +#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003 +#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_R5G6G5 0x00000001 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005 + +#define NV01_IMAGE_FROM_CPU_POINT 0x00000304 +#define NV01_IMAGE_FROM_CPU_POINT_X__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_POINT_X__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_POINT_Y__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_POINT_Y__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff +#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000 +#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16 + +#define NV01_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV01_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV01_IMAGE_FROM_CPU_COLOR__LEN 0x00000020 + +#define NV04_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV04_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV04_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190 + + +#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE_DST 0x00000194 + + +#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194 + +#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198 + +#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c + +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__MASK 0x0000ffff +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__SHIFT 0 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__MASK 0xffff0000 +#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__SHIFT 16 + +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700 + + +#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 + +#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c + +#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190 + + +#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE_DST 0x00000194 + + +#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194 + +#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 + +#define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008 +#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c + +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT 16 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__MASK 0x00ff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__SHIFT 16 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__MASK 0xff000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__SHIFT 24 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 + +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__MASK 0x0000ffff +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__SHIFT 0 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__MASK 0xffff0000 +#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__SHIFT 16 + + +#define NV50_SCALED_IMAGE_FROM_MEMORY_OFFSET_HIGH 0x00000410 + +#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_LINEAR 0x00000414 + +#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_TILE_MODE 0x00000418 + + +#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 + +#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184 + +#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188 + +#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000019c + +#define NV03_GDI_RECTANGLE_TEXT_SURFACE_DST 0x00000190 + +#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc + +#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc + +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc + +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000c00 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000020 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(i0) (0x00001000 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__LEN 0x00000020 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec + +#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000 +#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16 + +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00001400 + 0x4*(i0)) +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004 +#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000020 + + +#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c + +#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180 + +#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184 + +#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188 + +#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c + +#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190 + +#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194 + +#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198 + +#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002 +#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc + +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc + +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(i0) (0x00000600 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(i0) (0x00000604 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__LEN 0x00000020 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000800 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000080 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00000c00 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000080 + +#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__SHIFT 28 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(i0) (0x00001000 + 0x4*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__ESIZE 0x00000004 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__LEN 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__MASK 0x000000ff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__MASK 0x000fff00 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__SHIFT 8 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__MASK 0xfff00000 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__SHIFT 20 + +#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__MASK 0x0fffffff +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__MASK 0xf0000000 +#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__SHIFT 28 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(i0) (0x00001800 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__LEN 0x00000100 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__MASK 0x0000ffff +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__SHIFT 0 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__MASK 0xffff0000 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__SHIFT 16 + +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(i0) (0x00001804 + 0x8*(i0)) +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__ESIZE 0x00000008 +#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__LEN 0x00000100 + + +#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108 + +#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180 + +#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184 + +#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300 + +#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304 +#define NV10_TEXTURE_FROM_CPU_POINT_X__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_POINT_X__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_POINT_Y__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_POINT_Y__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308 +#define NV10_TEXTURE_FROM_CPU_SIZE_W__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_SIZE_W__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_SIZE_H__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_SIZE_H__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__MASK 0x0000ffff +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__SHIFT 0 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__MASK 0xffff0000 +#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__SHIFT 16 + +#define NV10_TEXTURE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0)) +#define NV10_TEXTURE_FROM_CPU_COLOR__ESIZE 0x00000004 +#define NV10_TEXTURE_FROM_CPU_COLOR__LEN 0x00000700 + + +#endif /* NV01_2D_XML */ diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c index c05312219b6..e0e65e7a87f 100644 --- a/src/gallium/drivers/nvfx/nv04_2d.c +++ b/src/gallium/drivers/nvfx/nv04_2d.c @@ -33,7 +33,6 @@ #include <stdlib.h> #include <stdio.h> #include <stdint.h> -#include <nouveau/nouveau_class.h> #include <nouveau/nouveau_device.h> #include <nouveau/nouveau_pushbuf.h> #include <nouveau/nouveau_channel.h> @@ -42,6 +41,10 @@ #include <nouveau/nouveau_grobj.h> #include "nv04_2d.h" +#include "nouveau/nv_object.xml.h" +#include "nouveau/nv_m2mf.xml.h" +#include "nv01_2d.xml.h" + /* avoid depending on Mesa/Gallium */ #ifdef __GNUC__ #define likely(x) __builtin_expect(!!(x), 1) @@ -107,7 +110,7 @@ static inline unsigned log2i(unsigned i) //#define NV04_REGION_DEBUG // Yes, we really want to inline everything, since all the functions are used only once -#if defined(__GNUC__) && defined(DEBUG) +#if defined(__GNUC__) && !defined(DEBUG) #define inline __attribute__((always_inline)) inline #endif @@ -365,19 +368,21 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int { if(rgn->pitch > 0) { - int delta; - assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal! - delta = rgn->offset & ((1 << shift) - 1); if(h <= 1) { - rgn->x += delta >> rgn->bpps; + int delta; + rgn->offset += rgn->y * rgn->pitch + (rgn->x << rgn->bpps); + delta = rgn->offset & ((1 << shift) - 1); + rgn->y = 0; + rgn->x = delta >> rgn->bpps; rgn->offset -= delta; rgn->pitch = align((rgn->x + w) << rgn->bpps, 1 << shift); } else { + int delta = rgn->offset & ((1 << shift) - 1); int newxo = (rgn->x << rgn->bpps) + delta; int dy = newxo / rgn->pitch; newxo -= dy * rgn->pitch; @@ -723,15 +728,58 @@ ms: nouveau_bo_unmap(dst->bo); } +static inline int +nv04_region_cs2d_format(struct nv04_region* rgn) +{ + switch(rgn->bpps) { + case 0: + return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; + case 1: + if(rgn->one_bits >= 1) + return NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5; + else + return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5; + case 2: + if(rgn->one_bits >= 8) + return NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8; + else + return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8; + default: + return -1; + } +} + +static inline int +nv04_region_sifm_format(struct nv04_region* rgn) +{ + switch(rgn->bpps) { + case 0: + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8; + case 1: + if(rgn->one_bits >= 1) + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5; + else + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5; + case 2: + if(rgn->one_bits >= 8) + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8; + else + return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8; + default: + return -1; + } +} static void nv04_region_copy_swizzle(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, - int w, int h, int cs2d_format, int sifm_format) + int w, int h) { struct nouveau_channel *chan = ctx->swzsurf->channel; struct nouveau_grobj *swzsurf = ctx->swzsurf; struct nouveau_grobj *sifm = ctx->sifm; + int cs2d_format = nv04_region_cs2d_format(dst); + int sifm_format = nv04_region_sifm_format(src); /* Max width & height may not be the same on all HW, but must be POT */ unsigned max_shift = 10; unsigned cw = 1 << max_shift; @@ -768,8 +816,8 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); OUT_RING (chan, cs2d_format | - log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | - log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); + log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT | + log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT); BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1); OUT_RELOCo(chan, src->bo, @@ -796,19 +844,19 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, OUT_RELOCl(chan, dst->bo, dst_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); - OUT_RING (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); + BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); + OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); OUT_RING (chan, sifm_format); OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY); - OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT)); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | rw); - OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT)); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | rw); + OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT | rw); + OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT | rw); OUT_RING (chan, 1 << 20); OUT_RING (chan, 1 << 20); BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4); - OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | align(rw, 8)); + OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT | align(rw, 8)); OUT_RING (chan, src->pitch | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); @@ -828,7 +876,7 @@ nv04_copy_m2mf_begin(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, stru struct nouveau_channel *chan = ctx->m2mf->channel; struct nouveau_grobj *m2mf = ctx->m2mf; MARK_RING (chan, 3 + commands * 9, 2 + commands * 2); - BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2); + BEGIN_RING(chan, m2mf, NV04_M2MF_DMA_BUFFER_IN, 2); OUT_RELOCo(chan, srcbo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dstbo, @@ -845,7 +893,7 @@ nv04_copy_m2mf_body(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int* fprintf(stderr, "\t\t\tCOPY_M2MF_BODY [%i, %i] <%i[%u]> lin %u <- <%i[%u]> lin %u\n", size, lines, dstbo->handle, *pdstoff, dstpitch, srcbo->handle, *psrcoff, srcpitch); #endif - BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); + BEGIN_RING(chan, m2mf, NV04_M2MF_OFFSET_IN, 8); OUT_RELOCl(chan, srcbo, *psrcoff, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); OUT_RELOCl(chan, dstbo, *pdstoff, @@ -949,11 +997,12 @@ nv04_region_copy_m2mf(struct nv04_2d_context *ctx, struct nv04_region *dst, stru } static inline void -nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h, int format) +nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h) { struct nouveau_channel *chan = ctx->surf2d->channel; struct nouveau_grobj *surf2d = ctx->surf2d; struct nouveau_grobj *blit = ctx->blit; + int cs2d_format = nv04_region_cs2d_format(dst); #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tRGN_COPY_BLIT [%i, %i: %i] ", w, h, dst->bpps); @@ -974,7 +1023,7 @@ nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, stru OUT_RELOCo(chan, src->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4); - OUT_RING (chan, format); + OUT_RING (chan, cs2d_format); OUT_RING (chan, (dst->pitch << 16) | src->pitch); OUT_RELOCl(chan, src->bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -1001,12 +1050,12 @@ nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, stru // dst and src may be modified, and the possibly modified version should be passed to nv04_region_cpu if necessary int nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, - int w, int h, int cs2d_format, int sifm_format, int dst_to_gpu, int src_on_gpu) + int w, int h, int dst_to_gpu, int src_on_gpu) { assert(src->bpps == dst->bpps); #ifdef NV04_REGION_DEBUG - fprintf(stderr, "RGN_COPY%s [%i, %i: %i] ", (cs2d_format >= 0) ? "_2D" : "_NO2D", w, h, dst->bpps); + fprintf(stderr, "RGN_COPY [%i, %i: %i] ", w, h, dst->bpps); for(int i = 0; i < 2; ++i) { int gpu = i ? src_on_gpu : dst_to_gpu; @@ -1059,7 +1108,7 @@ nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct { if (!dst->pitch) { - if(cs2d_format < 0 || sifm_format < 0 || !dst_to_gpu) + if(!dst_to_gpu) { #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tCOPY_ENG3D\n"); @@ -1070,25 +1119,29 @@ nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct { assert(!nv04_region_align(dst, w, h, 6)); - nv04_region_copy_swizzle(ctx, dst, src, w, h, cs2d_format, sifm_format); + nv04_region_copy_swizzle(ctx, dst, src, w, h); return 0; } } else { /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback - * to NV_MEMORY_TO_MEMORY_FORMAT in this case. + * to NV_M2MF in this case. * TODO: is this also true for the source? possibly not + * TODO: should we just always use m2mf? + * TODO: if not, add support for multiple operations to copy_blit */ - if ((cs2d_format < 0) - || !dst_to_gpu + if (!dst_to_gpu + || w > 2047 + || h > 2047 + || (w & 1) || nv04_region_align(src, w, h, 6) || nv04_region_align(dst, w, h, 6) ) nv04_region_copy_m2mf(ctx, dst, src, w, h); else - nv04_region_copy_blit(ctx, dst, src, w, h, cs2d_format); + nv04_region_copy_blit(ctx, dst, src, w, h); return 0; } @@ -1110,26 +1163,25 @@ nv04_region_fill_gdirect(struct nv04_2d_context *ctx, struct nv04_region* dst, i assert(!(dst->pitch & 63) && dst->pitch); nv04_region_assert(dst, w, h); - if(dst->bpps == 0) + switch(dst->bpps) { + case 0: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; - } - else if(dst->bpps == 1) - { + break; + case 1: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y16; - } - else if(dst->bpps == 2) - { + break; + case 2: gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8; cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y32; - } - else - { + break; + default: assert(0); gdirect_format = 0; cs2d_format = 0; + break; } MARK_RING (chan, 15, 4); @@ -1225,7 +1277,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) return NULL; } - BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); + BEGIN_RING(chan, ctx->m2mf, NV04_M2MF_DMA_NOTIFY, 1); OUT_RING (chan, ctx->ntfy->handle); if (chan->device->chipset < 0x10) @@ -1247,7 +1299,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) if (chan->device->chipset < 0x10) class = NV04_IMAGE_BLIT; else - class = NV12_IMAGE_BLIT; + class = NV11_IMAGE_BLIT; ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit); if (ret) { @@ -1257,7 +1309,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1); OUT_RING (chan, ctx->ntfy->handle); - BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1); + BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACES, 1); OUT_RING (chan, ctx->surf2d->handle); BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1); OUT_RING (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY); @@ -1285,7 +1337,7 @@ nv04_2d_context_init(struct nouveau_channel* chan) class = NV04_SWIZZLED_SURFACE; break; case 0x20: - class = NV20_SWIZZLED_SURFACE; + class = NV11_SWIZZLED_SURFACE; break; case 0x30: class = NV30_SWIZZLED_SURFACE; diff --git a/src/gallium/drivers/nvfx/nv04_2d.h b/src/gallium/drivers/nvfx/nv04_2d.h index e638b8c8740..00ee5bc0b23 100644 --- a/src/gallium/drivers/nvfx/nv04_2d.h +++ b/src/gallium/drivers/nvfx/nv04_2d.h @@ -43,10 +43,31 @@ struct nv04_region { int offset; unsigned pitch; // 0 -> swizzled unsigned bpps; // bpp shift (0, 1, 2; 3, 4 for fp/compressed) + unsigned one_bits; // number of high bits read and written as ones (for "no-alpha" optimization) unsigned x, y, z; unsigned w, h, d; }; +static inline void +nv04_region_try_to_linearize(struct nv04_region* rgn) +{ + assert(!rgn->pitch); + + if(rgn->d <= 1) + { + if(rgn->h <= 1 || rgn->w <= 2) + rgn->pitch = rgn->w << rgn->bpps; + } + else + { + if(rgn->h <= 2 && rgn->w <= 2) + { + rgn->pitch = rgn->w << rgn->bpps; + rgn->offset += rgn->z * rgn->h * rgn->pitch; + } + } +} + void nv04_memcpy(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int dstoff, @@ -75,7 +96,6 @@ int nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h, - int cs2d_format, int sifm_format, int dst_to_gpu, int src_on_gpu); int diff --git a/src/gallium/drivers/nvfx/nv30-40_3d.xml.h b/src/gallium/drivers/nvfx/nv30-40_3d.xml.h new file mode 100644 index 00000000000..a705a6bd3f2 --- /dev/null +++ b/src/gallium/drivers/nvfx/nv30-40_3d.xml.h @@ -0,0 +1,2022 @@ +#ifndef NV30_40_3D_XML +#define NV30_40_3D_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- nv30-40_3d.xml ( 31709 bytes, from 2010-09-05 08:00:50) +- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50) +- nv_3ddefs.xml ( 15391 bytes, from 2010-09-05 08:00:46) +- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53) +- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53) +- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53) + +Copyright (C) 2006-2010 by the following authors: +- Artur Huillet <[email protected]> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <[email protected]> (koala_br) +- Carlos Martin <[email protected]> (carlosmn) +- Christoph Bumiller <[email protected]> (calim, chrisbmr) +- Dawid Gajownik <[email protected]> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <[email protected]> (lumag) +- EdB <[email protected]> (edb_) +- Erik Waling <[email protected]> (erikwaling) +- Francisco Jerez <[email protected]> (curro, curro_, currojerez) +- imirkin <[email protected]> (imirkin) +- jb17bsome <[email protected]> (jb17bsome) +- Jeremy Kolb <[email protected]> (kjeremy) +- Laurent Carlier <[email protected]> (lordheavy) +- Luca Barbieri <[email protected]> (lb, lb1) +- Maarten Maathuis <[email protected]> (stillunknown) +- Marcin Kościelnicki <[email protected]> (mwk, koriakin) +- Mark Carey <[email protected]> (careym) +- Matthieu Castet <[email protected]> (mat-c) +- nvidiaman <[email protected]> (nvidiaman) +- Patrice Mandin <[email protected]> (pmandin, pmdata) +- Pekka Paalanen <[email protected]> (pq, ppaalanen) +- Peter Popov <[email protected]> (ironpeter) +- Richard Hughes <[email protected]> (hughsient) +- Rudi Cilibrasi <[email protected]> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <[email protected]> (leroutier) +- Stephane Marchesin <[email protected]> (marcheu) +- sturmflut <[email protected]> (sturmflut) +- Sylvain Munaut <[email protected]> +- Victor Stinner <[email protected]> (haypo) +- Wladmir van der Laan <[email protected]> (miathan6) +- Younes Manton <[email protected]> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + + +#define NV30_3D_DMA_NOTIFY 0x00000180 + +#define NV30_3D_DMA_TEXTURE0 0x00000184 + +#define NV30_3D_DMA_TEXTURE1 0x00000188 + +#define NV30_3D_DMA_COLOR1 0x0000018c + +#define NV30_3D_DMA_UNK190 0x00000190 + +#define NV30_3D_DMA_COLOR0 0x00000194 + +#define NV30_3D_DMA_ZETA 0x00000198 + +#define NV30_3D_DMA_VTXBUF0 0x0000019c + +#define NV30_3D_DMA_VTXBUF1 0x000001a0 + +#define NV30_3D_DMA_FENCE 0x000001a4 + +#define NV30_3D_DMA_QUERY 0x000001a8 + +#define NV30_3D_DMA_UNK1AC 0x000001ac + +#define NV30_3D_DMA_UNK1B0 0x000001b0 + +#define NV40_3D_DMA_COLOR2 0x000001b4 + +#define NV40_3D_DMA_COLOR3 0x000001b8 + +#define NV30_3D_RT_HORIZ 0x00000200 +#define NV30_3D_RT_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_RT_HORIZ_X__SHIFT 0 +#define NV30_3D_RT_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_RT_HORIZ_W__SHIFT 16 + +#define NV30_3D_RT_VERT 0x00000204 +#define NV30_3D_RT_VERT_Y__MASK 0x0000ffff +#define NV30_3D_RT_VERT_Y__SHIFT 0 +#define NV30_3D_RT_VERT_H__MASK 0xffff0000 +#define NV30_3D_RT_VERT_H__SHIFT 16 + +#define NV30_3D_RT_FORMAT 0x00000208 +#define NV30_3D_RT_FORMAT_COLOR__MASK 0x0000001f +#define NV30_3D_RT_FORMAT_COLOR__SHIFT 0 +#define NV30_3D_RT_FORMAT_COLOR_R5G6B5 0x00000003 +#define NV30_3D_RT_FORMAT_COLOR_X8R8G8B8 0x00000005 +#define NV30_3D_RT_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define NV30_3D_RT_FORMAT_COLOR_B8 0x00000009 +#define NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT 0x0000000b +#define NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT 0x0000000c +#define NV30_3D_RT_FORMAT_COLOR_R32_FLOAT 0x0000000d +#define NV30_3D_RT_FORMAT_COLOR_UNK0D 0x0000000d +#define NV30_3D_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f +#define NV30_3D_RT_FORMAT_COLOR_A8B8G8R8 0x00000010 +#define NV30_3D_RT_FORMAT_ZETA__MASK 0x000000e0 +#define NV30_3D_RT_FORMAT_ZETA__SHIFT 5 +#define NV30_3D_RT_FORMAT_ZETA_Z16 0x00000020 +#define NV30_3D_RT_FORMAT_ZETA_Z24S8 0x00000040 +#define NV30_3D_RT_FORMAT_TYPE__MASK 0x00000f00 +#define NV30_3D_RT_FORMAT_TYPE__SHIFT 8 +#define NV30_3D_RT_FORMAT_TYPE_LINEAR 0x00000100 +#define NV30_3D_RT_FORMAT_TYPE_SWIZZLED 0x00000200 +#define NV30_3D_RT_FORMAT_LOG2_WIDTH__MASK 0x00ff0000 +#define NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT 16 +#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__MASK 0xff000000 +#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT 24 + +#define NV30_3D_COLOR0_PITCH 0x0000020c +#define NV30_3D_COLOR0_PITCH_COLOR0__MASK 0x0000ffff +#define NV30_3D_COLOR0_PITCH_COLOR0__SHIFT 0 +#define NV30_3D_COLOR0_PITCH_ZETA__MASK 0xffff0000 +#define NV30_3D_COLOR0_PITCH_ZETA__SHIFT 16 + +#define NV40_3D_COLOR0_PITCH 0x0000020c + +#define NV30_3D_COLOR0_OFFSET 0x00000210 + +#define NV30_3D_ZETA_OFFSET 0x00000214 + +#define NV30_3D_COLOR1_OFFSET 0x00000218 + +#define NV30_3D_COLOR1_PITCH 0x0000021c + +#define NV30_3D_RT_ENABLE 0x00000220 +#define NV30_3D_RT_ENABLE_COLOR0 0x00000001 +#define NV30_3D_RT_ENABLE_COLOR1 0x00000002 +#define NV40_3D_RT_ENABLE_COLOR2 0x00000004 +#define NV40_3D_RT_ENABLE_COLOR3 0x00000008 +#define NV30_3D_RT_ENABLE_MRT 0x00000010 + +#define NV40_3D_ZETA_PITCH 0x0000022c + +#define NV30_3D_LMA_DEPTH_PITCH 0x0000022c + +#define NV30_3D_LMA_DEPTH_OFFSET 0x00000230 + +#define NV30_3D_TEX_UNITS_ENABLE 0x0000023c +#define NV30_3D_TEX_UNITS_ENABLE_TX0 0x00000001 +#define NV30_3D_TEX_UNITS_ENABLE_TX1 0x00000002 +#define NV30_3D_TEX_UNITS_ENABLE_TX2 0x00000004 +#define NV30_3D_TEX_UNITS_ENABLE_TX3 0x00000008 +#define NV30_3D_TEX_UNITS_ENABLE_TX4 0x00000010 +#define NV30_3D_TEX_UNITS_ENABLE_TX5 0x00000020 +#define NV30_3D_TEX_UNITS_ENABLE_TX6 0x00000040 +#define NV30_3D_TEX_UNITS_ENABLE_TX7 0x00000080 + +#define NV30_3D_TEX_MATRIX_ENABLE(i0) (0x00000240 + 0x4*(i0)) +#define NV30_3D_TEX_MATRIX_ENABLE__ESIZE 0x00000004 +#define NV30_3D_TEX_MATRIX_ENABLE__LEN 0x00000008 + +#define NV40_3D_COLOR2_PITCH 0x00000280 + +#define NV40_3D_COLOR3_PITCH 0x00000284 + +#define NV40_3D_COLOR2_OFFSET 0x00000288 + +#define NV40_3D_COLOR3_OFFSET 0x0000028c + +#define NV30_3D_VIEWPORT_TX_ORIGIN 0x000002b8 +#define NV30_3D_VIEWPORT_TX_ORIGIN_X__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_TX_ORIGIN_X__SHIFT 0 +#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__SHIFT 16 + +#define NV30_3D_VIEWPORT_CLIP_MODE 0x000002bc + +#define NV30_3D_VIEWPORT_CLIP_HORIZ(i0) (0x000002c0 + 0x8*(i0)) +#define NV30_3D_VIEWPORT_CLIP_HORIZ__ESIZE 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_HORIZ__LEN 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__SHIFT 0 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__SHIFT 16 + +#define NV30_3D_VIEWPORT_CLIP_VERT(i0) (0x000002c4 + 0x8*(i0)) +#define NV30_3D_VIEWPORT_CLIP_VERT__ESIZE 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_VERT__LEN 0x00000008 +#define NV30_3D_VIEWPORT_CLIP_VERT_T__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_CLIP_VERT_T__SHIFT 0 +#define NV30_3D_VIEWPORT_CLIP_VERT_D__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_CLIP_VERT_D__SHIFT 16 + +#define NV30_3D_DITHER_ENABLE 0x00000300 + +#define NV30_3D_ALPHA_FUNC_ENABLE 0x00000304 + +#define NV30_3D_ALPHA_FUNC_FUNC 0x00000308 +#define NV30_3D_ALPHA_FUNC_FUNC_NEVER 0x00000200 +#define NV30_3D_ALPHA_FUNC_FUNC_LESS 0x00000201 +#define NV30_3D_ALPHA_FUNC_FUNC_EQUAL 0x00000202 +#define NV30_3D_ALPHA_FUNC_FUNC_LEQUAL 0x00000203 +#define NV30_3D_ALPHA_FUNC_FUNC_GREATER 0x00000204 +#define NV30_3D_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_ALPHA_FUNC_FUNC_GEQUAL 0x00000206 +#define NV30_3D_ALPHA_FUNC_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_ALPHA_FUNC_REF 0x0000030c + +#define NV30_3D_BLEND_FUNC_ENABLE 0x00000310 + +#define NV30_3D_BLEND_FUNC_SRC 0x00000314 +#define NV30_3D_BLEND_FUNC_SRC_RGB__MASK 0x0000ffff +#define NV30_3D_BLEND_FUNC_SRC_RGB__SHIFT 0 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE 0x00000001 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307 +#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308 +#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003 +#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA__MASK 0xffff0000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA__SHIFT 16 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000 +#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 + +#define NV30_3D_BLEND_FUNC_DST 0x00000318 +#define NV30_3D_BLEND_FUNC_DST_RGB__MASK 0x0000ffff +#define NV30_3D_BLEND_FUNC_DST_RGB__SHIFT 0 +#define NV30_3D_BLEND_FUNC_DST_RGB_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE 0x00000001 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303 +#define NV30_3D_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305 +#define NV30_3D_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307 +#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308 +#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002 +#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003 +#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004 +#define NV30_3D_BLEND_FUNC_DST_ALPHA__MASK 0xffff0000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA__SHIFT 16 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE 0x00010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000 +#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 + +#define NV30_3D_BLEND_COLOR 0x0000031c +#define NV30_3D_BLEND_COLOR_B__MASK 0x000000ff +#define NV30_3D_BLEND_COLOR_B__SHIFT 0 +#define NV30_3D_BLEND_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_BLEND_COLOR_G__SHIFT 8 +#define NV30_3D_BLEND_COLOR_R__MASK 0x00ff0000 +#define NV30_3D_BLEND_COLOR_R__SHIFT 16 +#define NV30_3D_BLEND_COLOR_A__MASK 0xff000000 +#define NV30_3D_BLEND_COLOR_A__SHIFT 24 + +#define NV30_3D_BLEND_EQUATION 0x00000320 +#define NV30_3D_BLEND_EQUATION_FUNC_ADD 0x00008006 +#define NV30_3D_BLEND_EQUATION_MIN 0x00008007 +#define NV30_3D_BLEND_EQUATION_MAX 0x00008008 +#define NV30_3D_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a +#define NV30_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b + +#define NV40_3D_BLEND_EQUATION 0x00000320 +#define NV40_3D_BLEND_EQUATION_RGB__MASK 0x0000ffff +#define NV40_3D_BLEND_EQUATION_RGB__SHIFT 0 +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006 +#define NV40_3D_BLEND_EQUATION_RGB_MIN 0x00008007 +#define NV40_3D_BLEND_EQUATION_RGB_MAX 0x00008008 +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a +#define NV40_3D_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b +#define NV40_3D_BLEND_EQUATION_ALPHA__MASK 0xffff0000 +#define NV40_3D_BLEND_EQUATION_ALPHA__SHIFT 16 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_ADD 0x80060000 +#define NV40_3D_BLEND_EQUATION_ALPHA_MIN 0x80070000 +#define NV40_3D_BLEND_EQUATION_ALPHA_MAX 0x80080000 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x800a0000 +#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x800b0000 + +#define NV30_3D_COLOR_MASK 0x00000324 +#define NV30_3D_COLOR_MASK_B 0x000000ff +#define NV30_3D_COLOR_MASK_G 0x0000ff00 +#define NV30_3D_COLOR_MASK_R 0x00ff0000 +#define NV30_3D_COLOR_MASK_A 0xff000000 + +#define NV30_3D_STENCIL(i0) (0x00000328 + 0x20*(i0)) +#define NV30_3D_STENCIL__ESIZE 0x00000020 +#define NV30_3D_STENCIL__LEN 0x00000002 + +#define NV30_3D_STENCIL_ENABLE(i0) (0x00000328 + 0x20*(i0)) + +#define NV30_3D_STENCIL_MASK(i0) (0x0000032c + 0x20*(i0)) + +#define NV30_3D_STENCIL_FUNC_FUNC(i0) (0x00000330 + 0x20*(i0)) +#define NV30_3D_STENCIL_FUNC_FUNC_NEVER 0x00000200 +#define NV30_3D_STENCIL_FUNC_FUNC_LESS 0x00000201 +#define NV30_3D_STENCIL_FUNC_FUNC_EQUAL 0x00000202 +#define NV30_3D_STENCIL_FUNC_FUNC_LEQUAL 0x00000203 +#define NV30_3D_STENCIL_FUNC_FUNC_GREATER 0x00000204 +#define NV30_3D_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_STENCIL_FUNC_FUNC_GEQUAL 0x00000206 +#define NV30_3D_STENCIL_FUNC_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_STENCIL_FUNC_REF(i0) (0x00000334 + 0x20*(i0)) + +#define NV30_3D_STENCIL_FUNC_MASK(i0) (0x00000338 + 0x20*(i0)) + +#define NV30_3D_STENCIL_OP_FAIL(i0) (0x0000033c + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_FAIL_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_FAIL_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_FAIL_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_FAIL_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_FAIL_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_FAIL_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_FAIL_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_FAIL_DECR_WRAP 0x00008508 + +#define NV30_3D_STENCIL_OP_ZFAIL(i0) (0x00000340 + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_ZFAIL_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_ZFAIL_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_ZFAIL_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_ZFAIL_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_ZFAIL_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_ZFAIL_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508 + +#define NV30_3D_STENCIL_OP_ZPASS(i0) (0x00000344 + 0x20*(i0)) +#define NV30_3D_STENCIL_OP_ZPASS_ZERO 0x00000000 +#define NV30_3D_STENCIL_OP_ZPASS_INVERT 0x0000150a +#define NV30_3D_STENCIL_OP_ZPASS_KEEP 0x00001e00 +#define NV30_3D_STENCIL_OP_ZPASS_REPLACE 0x00001e01 +#define NV30_3D_STENCIL_OP_ZPASS_INCR 0x00001e02 +#define NV30_3D_STENCIL_OP_ZPASS_DECR 0x00001e03 +#define NV30_3D_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507 +#define NV30_3D_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508 + +#define NV30_3D_SHADE_MODEL 0x00000368 +#define NV30_3D_SHADE_MODEL_FLAT 0x00001d00 +#define NV30_3D_SHADE_MODEL_SMOOTH 0x00001d01 + +#define NV30_3D_FOG_ENABLE 0x0000036c + +#define NV30_3D_FOG_COLOR 0x00000370 +#define NV30_3D_FOG_COLOR_R__MASK 0x000000ff +#define NV30_3D_FOG_COLOR_R__SHIFT 0 +#define NV30_3D_FOG_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_FOG_COLOR_G__SHIFT 8 +#define NV30_3D_FOG_COLOR_B__MASK 0x00ff0000 +#define NV30_3D_FOG_COLOR_B__SHIFT 16 +#define NV30_3D_FOG_COLOR_A__MASK 0xff000000 +#define NV30_3D_FOG_COLOR_A__SHIFT 24 + +#define NV40_3D_MRT_COLOR_MASK 0x00000370 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_A 0x00000010 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_R 0x00000020 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_G 0x00000040 +#define NV40_3D_MRT_COLOR_MASK_BUFFER1_B 0x00000080 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_A 0x00000100 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_R 0x00000200 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_G 0x00000400 +#define NV40_3D_MRT_COLOR_MASK_BUFFER2_B 0x00000800 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_A 0x00001000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_R 0x00002000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_G 0x00004000 +#define NV40_3D_MRT_COLOR_MASK_BUFFER3_B 0x00008000 + +#define NV30_3D_COLOR_LOGIC_OP_ENABLE 0x00000374 + +#define NV30_3D_COLOR_LOGIC_OP_OP 0x00000378 +#define NV30_3D_COLOR_LOGIC_OP_OP_CLEAR 0x00001500 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND 0x00001501 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502 +#define NV30_3D_COLOR_LOGIC_OP_OP_COPY 0x00001503 +#define NV30_3D_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504 +#define NV30_3D_COLOR_LOGIC_OP_OP_NOOP 0x00001505 +#define NV30_3D_COLOR_LOGIC_OP_OP_XOR 0x00001506 +#define NV30_3D_COLOR_LOGIC_OP_OP_OR 0x00001507 +#define NV30_3D_COLOR_LOGIC_OP_OP_NOR 0x00001508 +#define NV30_3D_COLOR_LOGIC_OP_OP_EQUIV 0x00001509 +#define NV30_3D_COLOR_LOGIC_OP_OP_INVERT 0x0000150a +#define NV30_3D_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b +#define NV30_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c +#define NV30_3D_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d +#define NV30_3D_COLOR_LOGIC_OP_OP_NAND 0x0000150e +#define NV30_3D_COLOR_LOGIC_OP_OP_SET 0x0000150f + +#define NV30_3D_NORMALIZE_ENABLE 0x0000037c + +#define NV30_3D_COLOR_MATERIAL 0x00000390 +#define NV30_3D_COLOR_MATERIAL_FRONT_EMISSION_ENABLE 0x00000001 +#define NV30_3D_COLOR_MATERIAL_FRONT_AMBIENT_ENABLE 0x00000004 +#define NV30_3D_COLOR_MATERIAL_FRONT_DIFFUSE_ENABLE 0x00000010 +#define NV30_3D_COLOR_MATERIAL_FRONT_SPECULAR_ENABLE 0x00000040 +#define NV30_3D_COLOR_MATERIAL_BACK_EMISSION_ENABLE 0x00000100 +#define NV30_3D_COLOR_MATERIAL_BACK_AMBIENT_ENABLE 0x00000400 +#define NV30_3D_COLOR_MATERIAL_BACK_DIFFUSE_ENABLE 0x00001000 +#define NV30_3D_COLOR_MATERIAL_BACK_SPECULAR_ENABLE 0x00004000 + +#define NV30_3D_DEPTH_RANGE_NEAR 0x00000394 + +#define NV30_3D_DEPTH_RANGE_FAR 0x00000398 + +#define NV30_3D_COLOR_MATERIAL_FRONT 0x000003a0 + + +#define NV30_3D_COLOR_MATERIAL_FRONT_R 0x000003a0 + +#define NV30_3D_COLOR_MATERIAL_FRONT_G 0x000003a4 + +#define NV30_3D_COLOR_MATERIAL_FRONT_B 0x000003a8 + +#define NV30_3D_COLOR_MATERIAL_FRONT_A 0x000003ac + +#define NV40_3D_MIPMAP_ROUNDING 0x000003b0 +#define NV40_3D_MIPMAP_ROUNDING_MODE__MASK 0x00100000 +#define NV40_3D_MIPMAP_ROUNDING_MODE__SHIFT 20 +#define NV40_3D_MIPMAP_ROUNDING_MODE_UP 0x00000000 +#define NV40_3D_MIPMAP_ROUNDING_MODE_DOWN 0x00100000 + +#define NV30_3D_LINE_WIDTH 0x000003b8 + +#define NV30_3D_LINE_SMOOTH_ENABLE 0x000003bc + + + +#define NV30_3D_TEX_GEN_MODE(i0, i1) (0x00000400 + 0x10*(i0) + 0x4*(i1)) +#define NV30_3D_TEX_GEN_MODE__ESIZE 0x00000004 +#define NV30_3D_TEX_GEN_MODE__LEN 0x00000004 +#define NV30_3D_TEX_GEN_MODE_FALSE 0x00000000 +#define NV30_3D_TEX_GEN_MODE_EYE_LINEAR 0x00002400 +#define NV30_3D_TEX_GEN_MODE_OBJECT_LINEAR 0x00002401 +#define NV30_3D_TEX_GEN_MODE_SPHERE_MAP 0x00002402 +#define NV30_3D_TEX_GEN_MODE_NORMAL_MAP 0x00008511 +#define NV30_3D_TEX_GEN_MODE_REFLECTION_MAP 0x00008512 + +#define NV30_3D_MODELVIEW_MATRIX(i0) (0x00000480 + 0x4*(i0)) +#define NV30_3D_MODELVIEW_MATRIX__ESIZE 0x00000004 +#define NV30_3D_MODELVIEW_MATRIX__LEN 0x00000010 + +#define NV30_3D_INVERSE_MODELVIEW_MATRIX(i0) (0x00000580 + 0x4*(i0)) +#define NV30_3D_INVERSE_MODELVIEW_MATRIX__ESIZE 0x00000004 +#define NV30_3D_INVERSE_MODELVIEW_MATRIX__LEN 0x0000000c + +#define NV30_3D_PROJECTION_MATRIX(i0) (0x00000680 + 0x4*(i0)) +#define NV30_3D_PROJECTION_MATRIX__ESIZE 0x00000004 +#define NV30_3D_PROJECTION_MATRIX__LEN 0x00000010 + + +#define NV30_3D_TEX_MATRIX(i0, i1) (0x000006c0 + 0x40*(i0) + 0x4*(i1)) +#define NV30_3D_TEX_MATRIX__ESIZE 0x00000004 +#define NV30_3D_TEX_MATRIX__LEN 0x00000010 + +#define NV30_3D_SCISSOR_HORIZ 0x000008c0 +#define NV30_3D_SCISSOR_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_SCISSOR_HORIZ_X__SHIFT 0 +#define NV30_3D_SCISSOR_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_SCISSOR_HORIZ_W__SHIFT 16 + +#define NV30_3D_SCISSOR_VERT 0x000008c4 +#define NV30_3D_SCISSOR_VERT_Y__MASK 0x0000ffff +#define NV30_3D_SCISSOR_VERT_Y__SHIFT 0 +#define NV30_3D_SCISSOR_VERT_H__MASK 0xffff0000 +#define NV30_3D_SCISSOR_VERT_H__SHIFT 16 + +#define NV30_3D_FOG_COORD_DIST 0x000008c8 + +#define NV30_3D_FOG_MODE 0x000008cc + +#define NV30_3D_FOG_EQUATION_CONSTANT 0x000008d0 + +#define NV30_3D_FOG_EQUATION_LINEAR 0x000008d4 + +#define NV30_3D_FOG_EQUATION_QUADRATIC 0x000008d8 + +#define NV30_3D_FP_ACTIVE_PROGRAM 0x000008e4 +#define NV30_3D_FP_ACTIVE_PROGRAM_DMA0 0x00000001 +#define NV30_3D_FP_ACTIVE_PROGRAM_DMA1 0x00000002 +#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__MASK 0xfffffffc +#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__SHIFT 2 + + +#define NV30_3D_RC_COLOR0 0x000008ec +#define NV30_3D_RC_COLOR0_B__MASK 0x000000ff +#define NV30_3D_RC_COLOR0_B__SHIFT 0 +#define NV30_3D_RC_COLOR0_G__MASK 0x0000ff00 +#define NV30_3D_RC_COLOR0_G__SHIFT 8 +#define NV30_3D_RC_COLOR0_R__MASK 0x00ff0000 +#define NV30_3D_RC_COLOR0_R__SHIFT 16 +#define NV30_3D_RC_COLOR0_A__MASK 0xff000000 +#define NV30_3D_RC_COLOR0_A__SHIFT 24 + +#define NV30_3D_RC_COLOR1 0x000008f0 +#define NV30_3D_RC_COLOR1_B__MASK 0x000000ff +#define NV30_3D_RC_COLOR1_B__SHIFT 0 +#define NV30_3D_RC_COLOR1_G__MASK 0x0000ff00 +#define NV30_3D_RC_COLOR1_G__SHIFT 8 +#define NV30_3D_RC_COLOR1_R__MASK 0x00ff0000 +#define NV30_3D_RC_COLOR1_R__SHIFT 16 +#define NV30_3D_RC_COLOR1_A__MASK 0xff000000 +#define NV30_3D_RC_COLOR1_A__SHIFT 24 + +#define NV30_3D_RC_FINAL0 0x000008f4 +#define NV30_3D_RC_FINAL0_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_FINAL0_D_INPUT__SHIFT 0 +#define NV30_3D_RC_FINAL0_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_FINAL0_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_FINAL0_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_FINAL0_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_FINAL0_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_FINAL0_C_INPUT__SHIFT 8 +#define NV30_3D_RC_FINAL0_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_FINAL0_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_FINAL0_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_FINAL0_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_FINAL0_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_FINAL0_B_INPUT__SHIFT 16 +#define NV30_3D_RC_FINAL0_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_FINAL0_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_FINAL0_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_FINAL0_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_FINAL0_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_FINAL0_A_INPUT__SHIFT 24 +#define NV30_3D_RC_FINAL0_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_FINAL0_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_FINAL0_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_FINAL1 0x000008f8 +#define NV30_3D_RC_FINAL1_COLOR_SUM_CLAMP 0x00000080 +#define NV30_3D_RC_FINAL1_G_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_FINAL1_G_INPUT__SHIFT 8 +#define NV30_3D_RC_FINAL1_G_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_FINAL1_G_INPUT_FOG 0x00000300 +#define NV30_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_FINAL1_G_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_FINAL1_G_MAPPING__SHIFT 13 +#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_FINAL1_F_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_FINAL1_F_INPUT__SHIFT 16 +#define NV30_3D_RC_FINAL1_F_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_FINAL1_F_INPUT_FOG 0x00030000 +#define NV30_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_FINAL1_F_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_FINAL1_F_MAPPING__SHIFT 21 +#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_FINAL1_E_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_FINAL1_E_INPUT__SHIFT 24 +#define NV30_3D_RC_FINAL1_E_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_FINAL1_E_INPUT_FOG 0x03000000 +#define NV30_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_FINAL1_E_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING__SHIFT 29 +#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_ENABLE 0x000008fc +#define NV30_3D_RC_ENABLE_NUM_COMBINERS__MASK 0x0000000f +#define NV30_3D_RC_ENABLE_NUM_COMBINERS__SHIFT 0 +#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR0 0x0000f000 +#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR1 0x000f0000 + + +#define NV30_3D_RC_IN_ALPHA(i0) (0x00000900 + 0x20*(i0)) +#define NV30_3D_RC_IN_ALPHA_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_IN_ALPHA_D_INPUT__SHIFT 0 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_IN_ALPHA_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT__SHIFT 8 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT__SHIFT 16 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT__SHIFT 24 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_IN_RGB(i0) (0x00000904 + 0x20*(i0)) +#define NV30_3D_RC_IN_RGB_D_INPUT__MASK 0x0000000f +#define NV30_3D_RC_IN_RGB_D_INPUT__SHIFT 0 +#define NV30_3D_RC_IN_RGB_D_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_IN_RGB_D_INPUT_FOG 0x00000003 +#define NV30_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d +#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__MASK 0x00000010 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__SHIFT 4 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010 +#define NV30_3D_RC_IN_RGB_D_MAPPING__MASK 0x000000e0 +#define NV30_3D_RC_IN_RGB_D_MAPPING__SHIFT 5 +#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020 +#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040 +#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060 +#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080 +#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0 +#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0 +#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0 +#define NV30_3D_RC_IN_RGB_C_INPUT__MASK 0x00000f00 +#define NV30_3D_RC_IN_RGB_C_INPUT__SHIFT 8 +#define NV30_3D_RC_IN_RGB_C_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_IN_RGB_C_INPUT_FOG 0x00000300 +#define NV30_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__MASK 0x00001000 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__SHIFT 12 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000 +#define NV30_3D_RC_IN_RGB_C_MAPPING__MASK 0x0000e000 +#define NV30_3D_RC_IN_RGB_C_MAPPING__SHIFT 13 +#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000 +#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000 +#define NV30_3D_RC_IN_RGB_B_INPUT__MASK 0x000f0000 +#define NV30_3D_RC_IN_RGB_B_INPUT__SHIFT 16 +#define NV30_3D_RC_IN_RGB_B_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000 +#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000 +#define NV30_3D_RC_IN_RGB_B_INPUT_FOG 0x00030000 +#define NV30_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000 +#define NV30_3D_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__MASK 0x00100000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__SHIFT 20 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000 +#define NV30_3D_RC_IN_RGB_B_MAPPING__MASK 0x00e00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING__SHIFT 21 +#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000 +#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000 +#define NV30_3D_RC_IN_RGB_A_INPUT__MASK 0x0f000000 +#define NV30_3D_RC_IN_RGB_A_INPUT__SHIFT 24 +#define NV30_3D_RC_IN_RGB_A_INPUT_ZERO 0x00000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_FOG 0x03000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000 +#define NV30_3D_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__MASK 0x10000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__SHIFT 28 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000 +#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING__MASK 0xe0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING__SHIFT 29 +#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000 +#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000 + +#define NV30_3D_RC_CONSTANT_COLOR0(i0) (0x00000908 + 0x20*(i0)) +#define NV30_3D_RC_CONSTANT_COLOR0_B__MASK 0x000000ff +#define NV30_3D_RC_CONSTANT_COLOR0_B__SHIFT 0 +#define NV30_3D_RC_CONSTANT_COLOR0_G__MASK 0x0000ff00 +#define NV30_3D_RC_CONSTANT_COLOR0_G__SHIFT 8 +#define NV30_3D_RC_CONSTANT_COLOR0_R__MASK 0x00ff0000 +#define NV30_3D_RC_CONSTANT_COLOR0_R__SHIFT 16 +#define NV30_3D_RC_CONSTANT_COLOR0_A__MASK 0xff000000 +#define NV30_3D_RC_CONSTANT_COLOR0_A__SHIFT 24 + +#define NV30_3D_RC_CONSTANT_COLOR1(i0) (0x0000090c + 0x20*(i0)) +#define NV30_3D_RC_CONSTANT_COLOR1_B__MASK 0x000000ff +#define NV30_3D_RC_CONSTANT_COLOR1_B__SHIFT 0 +#define NV30_3D_RC_CONSTANT_COLOR1_G__MASK 0x0000ff00 +#define NV30_3D_RC_CONSTANT_COLOR1_G__SHIFT 8 +#define NV30_3D_RC_CONSTANT_COLOR1_R__MASK 0x00ff0000 +#define NV30_3D_RC_CONSTANT_COLOR1_R__SHIFT 16 +#define NV30_3D_RC_CONSTANT_COLOR1_A__MASK 0xff000000 +#define NV30_3D_RC_CONSTANT_COLOR1_A__SHIFT 24 + +#define NV30_3D_RC_OUT_ALPHA(i0) (0x00000910 + 0x20*(i0)) +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__MASK 0x0000000f +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__SHIFT 0 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__MASK 0x000000f0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__SHIFT 4 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__MASK 0x00000f00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__SHIFT 8 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT 0x00001000 +#define NV30_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT 0x00002000 +#define NV30_3D_RC_OUT_ALPHA_MUX_SUM 0x00004000 +#define NV30_3D_RC_OUT_ALPHA_BIAS__MASK 0x00008000 +#define NV30_3D_RC_OUT_ALPHA_BIAS__SHIFT 15 +#define NV30_3D_RC_OUT_ALPHA_BIAS_NONE 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV30_3D_RC_OUT_ALPHA_SCALE__MASK 0x00030000 +#define NV30_3D_RC_OUT_ALPHA_SCALE__SHIFT 16 +#define NV30_3D_RC_OUT_ALPHA_SCALE_NONE 0x00000000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00010000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00020000 +#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00030000 + +#define NV30_3D_RC_OUT_RGB(i0) (0x00000914 + 0x20*(i0)) +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__MASK 0x0000000f +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__SHIFT 0 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009 +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e +#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__MASK 0x000000f0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__SHIFT 4 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0 +#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__MASK 0x00000f00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__SHIFT 8 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00 +#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00 +#define NV30_3D_RC_OUT_RGB_CD_DOT_PRODUCT 0x00001000 +#define NV30_3D_RC_OUT_RGB_AB_DOT_PRODUCT 0x00002000 +#define NV30_3D_RC_OUT_RGB_MUX_SUM 0x00004000 +#define NV30_3D_RC_OUT_RGB_BIAS__MASK 0x00008000 +#define NV30_3D_RC_OUT_RGB_BIAS__SHIFT 15 +#define NV30_3D_RC_OUT_RGB_BIAS_NONE 0x00000000 +#define NV30_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000 +#define NV30_3D_RC_OUT_RGB_SCALE__MASK 0x00030000 +#define NV30_3D_RC_OUT_RGB_SCALE__SHIFT 16 +#define NV30_3D_RC_OUT_RGB_SCALE_NONE 0x00000000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00010000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00020000 +#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00030000 + +#define NV30_3D_VIEWPORT_HORIZ 0x00000a00 +#define NV30_3D_VIEWPORT_HORIZ_X__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_HORIZ_X__SHIFT 0 +#define NV30_3D_VIEWPORT_HORIZ_W__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_HORIZ_W__SHIFT 16 + +#define NV30_3D_VIEWPORT_VERT 0x00000a04 +#define NV30_3D_VIEWPORT_VERT_Y__MASK 0x0000ffff +#define NV30_3D_VIEWPORT_VERT_Y__SHIFT 0 +#define NV30_3D_VIEWPORT_VERT_H__MASK 0xffff0000 +#define NV30_3D_VIEWPORT_VERT_H__SHIFT 16 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x00000a10 + + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14 + +#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18 + +#define NV30_3D_VIEWPORT_TRANSLATE 0x00000a20 + + +#define NV30_3D_VIEWPORT_TRANSLATE_X 0x00000a20 + +#define NV30_3D_VIEWPORT_TRANSLATE_Y 0x00000a24 + +#define NV30_3D_VIEWPORT_TRANSLATE_Z 0x00000a28 + +#define NV30_3D_VIEWPORT_TRANSLATE_W 0x00000a2c + +#define NV30_3D_VIEWPORT_SCALE 0x00000a30 + + +#define NV30_3D_VIEWPORT_SCALE_X 0x00000a30 + +#define NV30_3D_VIEWPORT_SCALE_Y 0x00000a34 + +#define NV30_3D_VIEWPORT_SCALE_Z 0x00000a38 + +#define NV30_3D_VIEWPORT_SCALE_W 0x00000a3c + +#define NV30_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000a60 + +#define NV30_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000a64 + +#define NV30_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000a68 + +#define NV30_3D_DEPTH_FUNC 0x00000a6c +#define NV30_3D_DEPTH_FUNC_NEVER 0x00000200 +#define NV30_3D_DEPTH_FUNC_LESS 0x00000201 +#define NV30_3D_DEPTH_FUNC_EQUAL 0x00000202 +#define NV30_3D_DEPTH_FUNC_LEQUAL 0x00000203 +#define NV30_3D_DEPTH_FUNC_GREATER 0x00000204 +#define NV30_3D_DEPTH_FUNC_NOTEQUAL 0x00000205 +#define NV30_3D_DEPTH_FUNC_GEQUAL 0x00000206 +#define NV30_3D_DEPTH_FUNC_ALWAYS 0x00000207 + +#define NV30_3D_DEPTH_WRITE_ENABLE 0x00000a70 + +#define NV30_3D_DEPTH_TEST_ENABLE 0x00000a74 + +#define NV30_3D_POLYGON_OFFSET_FACTOR 0x00000a78 + +#define NV30_3D_POLYGON_OFFSET_UNITS 0x00000a7c + +#define NV30_3D_VTX_ATTR_3I_XY(i0) (0x00000a80 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_3I_XY__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_3I_XY__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_3I_XY_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_3I_XY_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_3I_XY_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_3I_XY_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_3I_Z(i0) (0x00000a84 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_3I_Z__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_3I_Z__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_3I_Z_Z__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_3I_Z_Z__SHIFT 0 + +#define NV30_3D_TEX_FILTER_OPTIMIZATION(i0) (0x00000b00 + 0x4*(i0)) +#define NV30_3D_TEX_FILTER_OPTIMIZATION__ESIZE 0x00000004 +#define NV30_3D_TEX_FILTER_OPTIMIZATION__LEN 0x00000004 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__MASK 0x0000001f +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__SHIFT 0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__MASK 0x000001c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__SHIFT 6 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__MASK 0x00007c00 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__SHIFT 10 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00 +#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00 + +#define NV40_3D_UNK0B40(i0) (0x00000b40 + 0x4*(i0)) +#define NV40_3D_UNK0B40__ESIZE 0x00000004 +#define NV40_3D_UNK0B40__LEN 0x00000008 + +#define NV30_3D_VP_UPLOAD_INST(i0) (0x00000b80 + 0x4*(i0)) +#define NV30_3D_VP_UPLOAD_INST__ESIZE 0x00000004 +#define NV30_3D_VP_UPLOAD_INST__LEN 0x00000004 + + +#define NV30_3D_TEX_CLIP_PLANE(i0) (0x00000e00 + 0x10*(i0)) + + +#define NV30_3D_TEX_CLIP_PLANE_X(i0) (0x00000e00 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_Y(i0) (0x00000e04 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_Z(i0) (0x00000e08 + 0x10*(i0)) + +#define NV30_3D_TEX_CLIP_PLANE_W(i0) (0x00000e0c + 0x10*(i0)) + +#define NV30_3D_LIGHT 0x00001000 + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT(i0) (0x00001000 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(i0) (0x00001000 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(i0) (0x00001004 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(i0) (0x00001008 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE(i0) (0x0000100c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(i0) (0x0000100c + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(i0) (0x00001010 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(i0) (0x00001014 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR(i0) (0x00001018 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(i0) (0x00001018 + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(i0) (0x0000101c + 0x40*(i0)) + +#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(i0) (0x00001020 + 0x40*(i0)) + +#define NV30_3D_LIGHT_UNK24(i0) (0x00001024 + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR(i0) (0x00001028 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_HALF_VECTOR_X(i0) (0x00001028 + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR_Y(i0) (0x0000102c + 0x40*(i0)) + +#define NV30_3D_LIGHT_HALF_VECTOR_Z(i0) (0x00001030 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION(i0) (0x00001034 + 0x40*(i0)) + + +#define NV30_3D_LIGHT_DIRECTION_X(i0) (0x00001034 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION_Y(i0) (0x00001038 + 0x40*(i0)) + +#define NV30_3D_LIGHT_DIRECTION_Z(i0) (0x0000103c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_SPOT_CUTOFF_A(i0) (0x00001200 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_B(i0) (0x00001204 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_C(i0) (0x00001208 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR(i0) (0x0000120c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_SPOT_DIR_X(i0) (0x0000120c + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR_Y(i0) (0x00001210 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_DIR_Z(i0) (0x00001214 + 0x40*(i0)) + +#define NV30_3D_LIGHT_SPOT_CUTOFF_D(i0) (0x00001218 + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION(i0) (0x0000121c + 0x40*(i0)) + + +#define NV30_3D_LIGHT_POSITION_X(i0) (0x0000121c + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION_Y(i0) (0x00001220 + 0x40*(i0)) + +#define NV30_3D_LIGHT_POSITION_Z(i0) (0x00001224 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION(i0) (0x00001228 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_CONSTANT(i0) (0x00001228 + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_LINEAR(i0) (0x0000122c + 0x40*(i0)) + +#define NV30_3D_LIGHT_ATTENUATION_QUADRATIC(i0) (0x00001230 + 0x40*(i0)) + +#define NV30_3D_FRONT_MATERIAL_SHININESS(i0) (0x00001400 + 0x4*(i0)) +#define NV30_3D_FRONT_MATERIAL_SHININESS__ESIZE 0x00000004 +#define NV30_3D_FRONT_MATERIAL_SHININESS__LEN 0x00000006 + +#define NV30_3D_ENABLED_LIGHTS 0x00001420 + +#define NV30_3D_VERTEX_TWO_SIDE_ENABLE 0x0000142c + +#define NV30_3D_FP_REG_CONTROL 0x00001450 +#define NV30_3D_FP_REG_CONTROL_UNK0__MASK 0x0000ffff +#define NV30_3D_FP_REG_CONTROL_UNK0__SHIFT 0 +#define NV30_3D_FP_REG_CONTROL_UNK1__MASK 0xffff0000 +#define NV30_3D_FP_REG_CONTROL_UNK1__SHIFT 16 + +#define NV30_3D_FLATSHADE_FIRST 0x00001454 + +#define NV30_3D_EDGEFLAG 0x0000145c +#define NV30_3D_EDGEFLAG_ENABLE 0x00000001 + +#define NV30_3D_VP_CLIP_PLANES_ENABLE 0x00001478 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 0x00000002 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 0x00000020 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 0x00000200 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 0x00002000 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 0x00020000 +#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5 0x00200000 + +#define NV30_3D_POLYGON_STIPPLE_ENABLE 0x0000147c + +#define NV30_3D_POLYGON_STIPPLE_PATTERN(i0) (0x00001480 + 0x4*(i0)) +#define NV30_3D_POLYGON_STIPPLE_PATTERN__ESIZE 0x00000004 +#define NV30_3D_POLYGON_STIPPLE_PATTERN__LEN 0x00000020 + +#define NV30_3D_VTX_ATTR_3F(i0) (0x00001500 + 0x10*(i0)) +#define NV30_3D_VTX_ATTR_3F__ESIZE 0x00000010 +#define NV30_3D_VTX_ATTR_3F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_3F_X(i0) (0x00001500 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_3F_Y(i0) (0x00001504 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_3F_Z(i0) (0x00001508 + 0x10*(i0)) + + +#define NV30_3D_VP_CLIP_PLANE(i0, i1) (0x00001600 + 0x10*(i0) + 0x4*(i1)) +#define NV30_3D_VP_CLIP_PLANE__ESIZE 0x00000004 +#define NV30_3D_VP_CLIP_PLANE__LEN 0x00000004 + +#define NV30_3D_VTXBUF(i0) (0x00001680 + 0x4*(i0)) +#define NV30_3D_VTXBUF__ESIZE 0x00000004 +#define NV30_3D_VTXBUF__LEN 0x00000010 +#define NV30_3D_VTXBUF_OFFSET__MASK 0x0fffffff +#define NV30_3D_VTXBUF_OFFSET__SHIFT 0 +#define NV30_3D_VTXBUF_DMA1 0x80000000 + +#define NV40_3D_VTX_CACHE_INVALIDATE 0x00001714 + +#define NV30_3D_VTXFMT(i0) (0x00001740 + 0x4*(i0)) +#define NV30_3D_VTXFMT__ESIZE 0x00000004 +#define NV30_3D_VTXFMT__LEN 0x00000010 +#define NV30_3D_VTXFMT_TYPE__MASK 0x0000000f +#define NV30_3D_VTXFMT_TYPE__SHIFT 0 +#define NV30_3D_VTXFMT_TYPE_B8G8R8A8_UNORM 0x00000000 +#define NV30_3D_VTXFMT_TYPE_V16_SNORM 0x00000001 +#define NV30_3D_VTXFMT_TYPE_V32_FLOAT 0x00000002 +#define NV30_3D_VTXFMT_TYPE_V16_FLOAT 0x00000003 +#define NV30_3D_VTXFMT_TYPE_U8_UNORM 0x00000004 +#define NV30_3D_VTXFMT_TYPE_V16_SSCALED 0x00000005 +#define NV30_3D_VTXFMT_TYPE_U8_USCALED 0x00000007 +#define NV30_3D_VTXFMT_SIZE__MASK 0x000000f0 +#define NV30_3D_VTXFMT_SIZE__SHIFT 4 +#define NV30_3D_VTXFMT_STRIDE__MASK 0x0000ff00 +#define NV30_3D_VTXFMT_STRIDE__SHIFT 8 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x000017a0 + + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4 + +#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8 + +#define NV30_3D_COLOR_MATERIAL_BACK 0x000017b0 + + +#define NV30_3D_COLOR_MATERIAL_BACK_R 0x000017b0 + +#define NV30_3D_COLOR_MATERIAL_BACK_G 0x000017b4 + +#define NV30_3D_COLOR_MATERIAL_BACK_B 0x000017b8 + +#define NV30_3D_COLOR_MATERIAL_BACK_A 0x000017bc + +#define NV30_3D_QUERY_RESET 0x000017c8 + +#define NV30_3D_QUERY_ENABLE 0x000017cc + +#define NV30_3D_QUERY_GET 0x00001800 +#define NV30_3D_QUERY_GET_OFFSET__MASK 0x00ffffff +#define NV30_3D_QUERY_GET_OFFSET__SHIFT 0 +#define NV30_3D_QUERY_GET_UNK24__MASK 0xff000000 +#define NV30_3D_QUERY_GET_UNK24__SHIFT 24 + +#define NV30_3D_VERTEX_BEGIN_END 0x00001808 +#define NV30_3D_VERTEX_BEGIN_END_STOP 0x00000000 +#define NV30_3D_VERTEX_BEGIN_END_POINTS 0x00000001 +#define NV30_3D_VERTEX_BEGIN_END_LINES 0x00000002 +#define NV30_3D_VERTEX_BEGIN_END_LINE_LOOP 0x00000003 +#define NV30_3D_VERTEX_BEGIN_END_LINE_STRIP 0x00000004 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLES 0x00000005 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006 +#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007 +#define NV30_3D_VERTEX_BEGIN_END_QUADS 0x00000008 +#define NV30_3D_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009 +#define NV30_3D_VERTEX_BEGIN_END_POLYGON 0x0000000a + +#define NV30_3D_VB_ELEMENT_U16 0x0000180c +#define NV30_3D_VB_ELEMENT_U16_0__MASK 0x0000ffff +#define NV30_3D_VB_ELEMENT_U16_0__SHIFT 0 +#define NV30_3D_VB_ELEMENT_U16_1__MASK 0xffff0000 +#define NV30_3D_VB_ELEMENT_U16_1__SHIFT 16 + +#define NV30_3D_VB_ELEMENT_U32 0x00001810 + +#define NV30_3D_VB_VERTEX_BATCH 0x00001814 +#define NV30_3D_VB_VERTEX_BATCH_OFFSET__MASK 0x00ffffff +#define NV30_3D_VB_VERTEX_BATCH_OFFSET__SHIFT 0 +#define NV30_3D_VB_VERTEX_BATCH_COUNT__MASK 0xff000000 +#define NV30_3D_VB_VERTEX_BATCH_COUNT__SHIFT 24 + +#define NV30_3D_VERTEX_DATA 0x00001818 + +#define NV30_3D_IDXBUF_OFFSET 0x0000181c + +#define NV30_3D_IDXBUF_FORMAT 0x00001820 +#define NV30_3D_IDXBUF_FORMAT_DMA1 0x00000001 +#define NV30_3D_IDXBUF_FORMAT_TYPE__MASK 0x000000f0 +#define NV30_3D_IDXBUF_FORMAT_TYPE__SHIFT 4 +#define NV30_3D_IDXBUF_FORMAT_TYPE_U32 0x00000000 +#define NV30_3D_IDXBUF_FORMAT_TYPE_U16 0x00000010 + +#define NV30_3D_VB_INDEX_BATCH 0x00001824 +#define NV30_3D_VB_INDEX_BATCH_START__MASK 0x00ffffff +#define NV30_3D_VB_INDEX_BATCH_START__SHIFT 0 +#define NV30_3D_VB_INDEX_BATCH_COUNT__MASK 0xff000000 +#define NV30_3D_VB_INDEX_BATCH_COUNT__SHIFT 24 + +#define NV30_3D_POLYGON_MODE_FRONT 0x00001828 +#define NV30_3D_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NV30_3D_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NV30_3D_POLYGON_MODE_FRONT_FILL 0x00001b02 + +#define NV30_3D_POLYGON_MODE_BACK 0x0000182c +#define NV30_3D_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NV30_3D_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NV30_3D_POLYGON_MODE_BACK_FILL 0x00001b02 + +#define NV30_3D_CULL_FACE 0x00001830 +#define NV30_3D_CULL_FACE_FRONT 0x00000404 +#define NV30_3D_CULL_FACE_BACK 0x00000405 +#define NV30_3D_CULL_FACE_FRONT_AND_BACK 0x00000408 + +#define NV30_3D_FRONT_FACE 0x00001834 +#define NV30_3D_FRONT_FACE_CW 0x00000900 +#define NV30_3D_FRONT_FACE_CCW 0x00000901 + +#define NV30_3D_POLYGON_SMOOTH_ENABLE 0x00001838 + +#define NV30_3D_CULL_FACE_ENABLE 0x0000183c + +#define NV30_3D_TEX_PALETTE_OFFSET(i0) (0x00001840 + 0x4*(i0)) +#define NV30_3D_TEX_PALETTE_OFFSET__ESIZE 0x00000004 +#define NV30_3D_TEX_PALETTE_OFFSET__LEN 0x00000008 + +#define NV40_3D_TEX_SIZE1(i0) (0x00001840 + 0x4*(i0)) +#define NV40_3D_TEX_SIZE1__ESIZE 0x00000004 +#define NV40_3D_TEX_SIZE1__LEN 0x00000008 +#define NV40_3D_TEX_SIZE1_DEPTH__MASK 0xfff00000 +#define NV40_3D_TEX_SIZE1_DEPTH__SHIFT 20 +#define NV40_3D_TEX_SIZE1_PITCH__MASK 0x0000ffff +#define NV40_3D_TEX_SIZE1_PITCH__SHIFT 0 + +#define NV30_3D_VTX_ATTR_2F(i0) (0x00001880 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_2F__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_2F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_2F_X(i0) (0x00001880 + 0x8*(i0)) + +#define NV30_3D_VTX_ATTR_2F_Y(i0) (0x00001884 + 0x8*(i0)) + +#define NV30_3D_VTX_ATTR_2I(i0) (0x00001900 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_2I__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_2I__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_2I_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_2I_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_2I_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_2I_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_4UB(i0) (0x00001940 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_4UB__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_4UB__LEN 0x00000010 +#define NV30_3D_VTX_ATTR_4UB_X__MASK 0x000000ff +#define NV30_3D_VTX_ATTR_4UB_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_4UB_Y__MASK 0x0000ff00 +#define NV30_3D_VTX_ATTR_4UB_Y__SHIFT 8 +#define NV30_3D_VTX_ATTR_4UB_Z__MASK 0x00ff0000 +#define NV30_3D_VTX_ATTR_4UB_Z__SHIFT 16 +#define NV30_3D_VTX_ATTR_4UB_W__MASK 0xff000000 +#define NV30_3D_VTX_ATTR_4UB_W__SHIFT 24 + +#define NV30_3D_VTX_ATTR_4I(i0) (0x00001980 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I__ESIZE 0x00000008 +#define NV30_3D_VTX_ATTR_4I__LEN 0x00000010 + +#define NV30_3D_VTX_ATTR_4I_XY(i0) (0x00001980 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I_XY_X__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_4I_XY_X__SHIFT 0 +#define NV30_3D_VTX_ATTR_4I_XY_Y__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_4I_XY_Y__SHIFT 16 + +#define NV30_3D_VTX_ATTR_4I_ZW(i0) (0x00001984 + 0x8*(i0)) +#define NV30_3D_VTX_ATTR_4I_ZW_Z__MASK 0x0000ffff +#define NV30_3D_VTX_ATTR_4I_ZW_Z__SHIFT 0 +#define NV30_3D_VTX_ATTR_4I_ZW_W__MASK 0xffff0000 +#define NV30_3D_VTX_ATTR_4I_ZW_W__SHIFT 16 + +#define NV30_3D_TEX_OFFSET(i0) (0x00001a00 + 0x20*(i0)) +#define NV30_3D_TEX_OFFSET__ESIZE 0x00000020 +#define NV30_3D_TEX_OFFSET__LEN 0x00000008 + +#define NV30_3D_TEX_FORMAT(i0) (0x00001a04 + 0x20*(i0)) +#define NV30_3D_TEX_FORMAT__ESIZE 0x00000020 +#define NV30_3D_TEX_FORMAT__LEN 0x00000008 +#define NV30_3D_TEX_FORMAT_DMA0 0x00000001 +#define NV30_3D_TEX_FORMAT_DMA1 0x00000002 +#define NV30_3D_TEX_FORMAT_CUBIC 0x00000004 +#define NV30_3D_TEX_FORMAT_NO_BORDER 0x00000008 +#define NV30_3D_TEX_FORMAT_DIMS__MASK 0x000000f0 +#define NV30_3D_TEX_FORMAT_DIMS__SHIFT 4 +#define NV30_3D_TEX_FORMAT_DIMS_1D 0x00000010 +#define NV30_3D_TEX_FORMAT_DIMS_2D 0x00000020 +#define NV30_3D_TEX_FORMAT_DIMS_3D 0x00000030 +#define NV30_3D_TEX_FORMAT_FORMAT__MASK 0x0000ff00 +#define NV30_3D_TEX_FORMAT_FORMAT__SHIFT 8 +#define NV30_3D_TEX_FORMAT_FORMAT_L8 0x00000000 +#define NV30_3D_TEX_FORMAT_FORMAT_I8 0x00000100 +#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200 +#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000400 +#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000500 +#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000600 +#define NV30_3D_TEX_FORMAT_FORMAT_X8R8G8B8 0x00000700 +#define NV30_3D_TEX_FORMAT_FORMAT_INDEX8 0x00000b00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT1 0x00000c00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT3 0x00000e00 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT5 0x00000f00 +#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000 +#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100 +#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200 +#define NV30_3D_TEX_FORMAT_FORMAT_L8_RECT 0x00001300 +#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8_RECT 0x00001700 +#define NV30_3D_TEX_FORMAT_FORMAT_A8L8 0x00001a00 +#define NV30_3D_TEX_FORMAT_FORMAT_I8_RECT 0x00001b00 +#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00 +#define NV30_3D_TEX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00 +#define NV30_3D_TEX_FORMAT_FORMAT_A8L8_RECT 0x00002000 +#define NV30_3D_TEX_FORMAT_FORMAT_Z24 0x00002a00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z24_RECT 0x00002b00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z16 0x00002c00 +#define NV30_3D_TEX_FORMAT_FORMAT_Z16_RECT 0x00002d00 +#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8 0x00002800 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO16 0x00003300 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO16_RECT 0x00003600 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO8 0x00004400 +#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500 +#define NV30_3D_TEX_FORMAT_FORMAT_HILO8_RECT 0x00004600 +#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700 +#define NV30_3D_TEX_FORMAT_FORMAT_A16 0x00003200 +#define NV30_3D_TEX_FORMAT_FORMAT_A16_RECT 0x00003500 +#define NV30_3D_TEX_FORMAT_FORMAT_UNK3F 0x00003f00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00 +#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00 +#define NV40_3D_TEX_FORMAT_FORMAT__MASK 0x00001f00 +#define NV40_3D_TEX_FORMAT_FORMAT__SHIFT 8 +#define NV40_3D_TEX_FORMAT_FORMAT_L8 0x00000100 +#define NV40_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200 +#define NV40_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000300 +#define NV40_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000400 +#define NV40_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000500 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT1 0x00000600 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT3 0x00000700 +#define NV40_3D_TEX_FORMAT_FORMAT_DXT5 0x00000800 +#define NV40_3D_TEX_FORMAT_FORMAT_A8L8 0x00000b00 +#define NV40_3D_TEX_FORMAT_FORMAT_Z24 0x00001000 +#define NV40_3D_TEX_FORMAT_FORMAT_Z16 0x00001200 +#define NV40_3D_TEX_FORMAT_FORMAT_A16 0x00001400 +#define NV40_3D_TEX_FORMAT_FORMAT_A16L16 0x00001500 +#define NV40_3D_TEX_FORMAT_FORMAT_HILO8 0x00001800 +#define NV40_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00001a00 +#define NV40_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00001b00 +#define NV40_3D_TEX_FORMAT_LINEAR 0x00002000 +#define NV40_3D_TEX_FORMAT_RECT 0x00004000 +#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__MASK 0x000f0000 +#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT 16 +#define NV30_3D_TEX_FORMAT_MIPMAP 0x00080000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__MASK 0x00f00000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT 20 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__MASK 0x0f000000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT 24 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__MASK 0xf0000000 +#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT 28 + +#define NV30_3D_TEX_WRAP(i0) (0x00001a08 + 0x20*(i0)) +#define NV30_3D_TEX_WRAP__ESIZE 0x00000020 +#define NV30_3D_TEX_WRAP__LEN 0x00000008 +#define NV30_3D_TEX_WRAP_S__MASK 0x000000ff +#define NV30_3D_TEX_WRAP_S__SHIFT 0 +#define NV30_3D_TEX_WRAP_S_REPEAT 0x00000001 +#define NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002 +#define NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003 +#define NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER 0x00000004 +#define NV30_3D_TEX_WRAP_S_CLAMP 0x00000005 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007 +#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP 0x00000008 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__MASK 0x00000070 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__SHIFT 4 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030 +#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070 +#define NV30_3D_TEX_WRAP_T__MASK 0x00000f00 +#define NV30_3D_TEX_WRAP_T__SHIFT 8 +#define NV30_3D_TEX_WRAP_T_REPEAT 0x00000100 +#define NV30_3D_TEX_WRAP_T_MIRRORED_REPEAT 0x00000200 +#define NV30_3D_TEX_WRAP_T_CLAMP_TO_EDGE 0x00000300 +#define NV30_3D_TEX_WRAP_T_CLAMP_TO_BORDER 0x00000400 +#define NV30_3D_TEX_WRAP_T_CLAMP 0x00000500 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE 0x00000600 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER 0x00000700 +#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP 0x00000800 +#define NV30_3D_TEX_WRAP_EXPAND_NORMAL 0x0000f000 +#define NV30_3D_TEX_WRAP_R__MASK 0x000f0000 +#define NV30_3D_TEX_WRAP_R__SHIFT 16 +#define NV30_3D_TEX_WRAP_R_REPEAT 0x00010000 +#define NV30_3D_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000 +#define NV30_3D_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000 +#define NV30_3D_TEX_WRAP_R_CLAMP_TO_BORDER 0x00040000 +#define NV30_3D_TEX_WRAP_R_CLAMP 0x00050000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000 +#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP 0x00080000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__MASK 0x00f00000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__SHIFT 20 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000 +#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000 +#define NV30_3D_TEX_WRAP_RCOMP__MASK 0xf0000000 +#define NV30_3D_TEX_WRAP_RCOMP__SHIFT 28 +#define NV30_3D_TEX_WRAP_RCOMP_NEVER 0x00000000 +#define NV30_3D_TEX_WRAP_RCOMP_GREATER 0x10000000 +#define NV30_3D_TEX_WRAP_RCOMP_EQUAL 0x20000000 +#define NV30_3D_TEX_WRAP_RCOMP_GEQUAL 0x30000000 +#define NV30_3D_TEX_WRAP_RCOMP_LESS 0x40000000 +#define NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL 0x50000000 +#define NV30_3D_TEX_WRAP_RCOMP_LEQUAL 0x60000000 +#define NV30_3D_TEX_WRAP_RCOMP_ALWAYS 0x70000000 + +#define NV30_3D_TEX_ENABLE(i0) (0x00001a0c + 0x20*(i0)) +#define NV30_3D_TEX_ENABLE__ESIZE 0x00000020 +#define NV30_3D_TEX_ENABLE__LEN 0x00000008 +#define NV30_3D_TEX_ENABLE_ANISO__MASK 0x00000030 +#define NV30_3D_TEX_ENABLE_ANISO__SHIFT 4 +#define NV30_3D_TEX_ENABLE_ANISO_NONE 0x00000000 +#define NV30_3D_TEX_ENABLE_ANISO_2X 0x00000010 +#define NV30_3D_TEX_ENABLE_ANISO_4X 0x00000020 +#define NV30_3D_TEX_ENABLE_ANISO_8X 0x00000030 +#define NV40_3D_TEX_ENABLE_ANISO__MASK 0x000000f0 +#define NV40_3D_TEX_ENABLE_ANISO__SHIFT 4 +#define NV40_3D_TEX_ENABLE_ANISO_NONE 0x00000000 +#define NV40_3D_TEX_ENABLE_ANISO_2X 0x00000010 +#define NV40_3D_TEX_ENABLE_ANISO_4X 0x00000020 +#define NV40_3D_TEX_ENABLE_ANISO_6X 0x00000030 +#define NV40_3D_TEX_ENABLE_ANISO_8X 0x00000040 +#define NV40_3D_TEX_ENABLE_ANISO_10X 0x00000050 +#define NV40_3D_TEX_ENABLE_ANISO_12X 0x00000060 +#define NV40_3D_TEX_ENABLE_ANISO_16X 0x00000070 +#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x0003c000 +#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 14 +#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x00038000 +#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 15 +#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x3c000000 +#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 26 +#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x38000000 +#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 27 +#define NV30_3D_TEX_ENABLE_ENABLE 0x40000000 +#define NV40_3D_TEX_ENABLE_ENABLE 0x80000000 + +#define NV30_3D_TEX_SWIZZLE(i0) (0x00001a10 + 0x20*(i0)) +#define NV30_3D_TEX_SWIZZLE__ESIZE 0x00000020 +#define NV30_3D_TEX_SWIZZLE__LEN 0x00000008 +#define NV30_3D_TEX_SWIZZLE_S1_W__MASK 0x00000003 +#define NV30_3D_TEX_SWIZZLE_S1_W__SHIFT 0 +#define NV30_3D_TEX_SWIZZLE_S1_W_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_W_Z 0x00000001 +#define NV30_3D_TEX_SWIZZLE_S1_W_Y 0x00000002 +#define NV30_3D_TEX_SWIZZLE_S1_W_X 0x00000003 +#define NV30_3D_TEX_SWIZZLE_S1_Z__MASK 0x0000000c +#define NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT 2 +#define NV30_3D_TEX_SWIZZLE_S1_Z_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_Z_Z 0x00000004 +#define NV30_3D_TEX_SWIZZLE_S1_Z_Y 0x00000008 +#define NV30_3D_TEX_SWIZZLE_S1_Z_X 0x0000000c +#define NV30_3D_TEX_SWIZZLE_S1_Y__MASK 0x00000030 +#define NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT 4 +#define NV30_3D_TEX_SWIZZLE_S1_Y_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_Y_Z 0x00000010 +#define NV30_3D_TEX_SWIZZLE_S1_Y_Y 0x00000020 +#define NV30_3D_TEX_SWIZZLE_S1_Y_X 0x00000030 +#define NV30_3D_TEX_SWIZZLE_S1_X__MASK 0x000000c0 +#define NV30_3D_TEX_SWIZZLE_S1_X__SHIFT 6 +#define NV30_3D_TEX_SWIZZLE_S1_X_W 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S1_X_Z 0x00000040 +#define NV30_3D_TEX_SWIZZLE_S1_X_Y 0x00000080 +#define NV30_3D_TEX_SWIZZLE_S1_X_X 0x000000c0 +#define NV30_3D_TEX_SWIZZLE_S0_W__MASK 0x00000300 +#define NV30_3D_TEX_SWIZZLE_S0_W__SHIFT 8 +#define NV30_3D_TEX_SWIZZLE_S0_W_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_W_ONE 0x00000100 +#define NV30_3D_TEX_SWIZZLE_S0_W_S1 0x00000200 +#define NV30_3D_TEX_SWIZZLE_S0_Z__MASK 0x00000c00 +#define NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT 10 +#define NV30_3D_TEX_SWIZZLE_S0_Z_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_Z_ONE 0x00000400 +#define NV30_3D_TEX_SWIZZLE_S0_Z_S1 0x00000800 +#define NV30_3D_TEX_SWIZZLE_S0_Y__MASK 0x00003000 +#define NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT 12 +#define NV30_3D_TEX_SWIZZLE_S0_Y_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_Y_ONE 0x00001000 +#define NV30_3D_TEX_SWIZZLE_S0_Y_S1 0x00002000 +#define NV30_3D_TEX_SWIZZLE_S0_X__MASK 0x0000c000 +#define NV30_3D_TEX_SWIZZLE_S0_X__SHIFT 14 +#define NV30_3D_TEX_SWIZZLE_S0_X_ZERO 0x00000000 +#define NV30_3D_TEX_SWIZZLE_S0_X_ONE 0x00004000 +#define NV30_3D_TEX_SWIZZLE_S0_X_S1 0x00008000 +#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__MASK 0xffff0000 +#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT 16 + +#define NV30_3D_TEX_FILTER(i0) (0x00001a14 + 0x20*(i0)) +#define NV30_3D_TEX_FILTER__ESIZE 0x00000020 +#define NV30_3D_TEX_FILTER__LEN 0x00000008 +#define NV30_3D_TEX_FILTER_LOD_BIAS__MASK 0x00000f00 +#define NV30_3D_TEX_FILTER_LOD_BIAS__SHIFT 8 +#define NV30_3D_TEX_FILTER_MIN__MASK 0x000f0000 +#define NV30_3D_TEX_FILTER_MIN__SHIFT 16 +#define NV30_3D_TEX_FILTER_MIN_NEAREST 0x00010000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR 0x00020000 +#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x00030000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x00040000 +#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x00050000 +#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x00060000 +#define NV30_3D_TEX_FILTER_MAG__MASK 0x0f000000 +#define NV30_3D_TEX_FILTER_MAG__SHIFT 24 +#define NV30_3D_TEX_FILTER_MAG_NEAREST 0x01000000 +#define NV30_3D_TEX_FILTER_MAG_LINEAR 0x02000000 +#define NV30_3D_TEX_FILTER_SIGNED_BLUE 0x10000000 +#define NV30_3D_TEX_FILTER_SIGNED_GREEN 0x20000000 +#define NV30_3D_TEX_FILTER_SIGNED_RED 0x40000000 +#define NV30_3D_TEX_FILTER_SIGNED_ALPHA 0x80000000 + +#define NV30_3D_TEX_NPOT_SIZE(i0) (0x00001a18 + 0x20*(i0)) +#define NV30_3D_TEX_NPOT_SIZE__ESIZE 0x00000020 +#define NV30_3D_TEX_NPOT_SIZE__LEN 0x00000008 +#define NV30_3D_TEX_NPOT_SIZE_H__MASK 0x0000ffff +#define NV30_3D_TEX_NPOT_SIZE_H__SHIFT 0 +#define NV30_3D_TEX_NPOT_SIZE_W__MASK 0xffff0000 +#define NV30_3D_TEX_NPOT_SIZE_W__SHIFT 16 + +#define NV30_3D_TEX_BORDER_COLOR(i0) (0x00001a1c + 0x20*(i0)) +#define NV30_3D_TEX_BORDER_COLOR__ESIZE 0x00000020 +#define NV30_3D_TEX_BORDER_COLOR__LEN 0x00000008 +#define NV30_3D_TEX_BORDER_COLOR_B__MASK 0x000000ff +#define NV30_3D_TEX_BORDER_COLOR_B__SHIFT 0 +#define NV30_3D_TEX_BORDER_COLOR_G__MASK 0x0000ff00 +#define NV30_3D_TEX_BORDER_COLOR_G__SHIFT 8 +#define NV30_3D_TEX_BORDER_COLOR_R__MASK 0x00ff0000 +#define NV30_3D_TEX_BORDER_COLOR_R__SHIFT 16 +#define NV30_3D_TEX_BORDER_COLOR_A__MASK 0xff000000 +#define NV30_3D_TEX_BORDER_COLOR_A__SHIFT 24 + +#define NV30_3D_VTX_ATTR_4F(i0) (0x00001c00 + 0x10*(i0)) +#define NV30_3D_VTX_ATTR_4F__ESIZE 0x00000010 +#define NV30_3D_VTX_ATTR_4F__LEN 0x00000010 + + +#define NV30_3D_VTX_ATTR_4F_X(i0) (0x00001c00 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_Y(i0) (0x00001c04 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_Z(i0) (0x00001c08 + 0x10*(i0)) + +#define NV30_3D_VTX_ATTR_4F_W(i0) (0x00001c0c + 0x10*(i0)) + +#define NV30_3D_FP_CONTROL 0x00001d60 +#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__MASK 0x0000000f +#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__SHIFT 0 +#define NV30_3D_FP_CONTROL_USES_KIL 0x00000080 +#define NV40_3D_FP_CONTROL_KIL 0x00000080 +#define NV40_3D_FP_CONTROL_TEMP_COUNT__MASK 0xff000000 +#define NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT 24 + +#define NV30_3D_DEPTH_CONTROL 0x00001d78 +#define NV30_3D_DEPTH_CONTROL_CLAMP 0x000000f0 + +#define NV30_3D_MULTISAMPLE_CONTROL 0x00001d7c +#define NV30_3D_MULTISAMPLE_CONTROL_ENABLE 0x00000001 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_COVERAGE 0x00000010 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_ONE 0x00000100 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__MASK 0xffff0000 +#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__SHIFT 16 + +#define NV30_3D_COORD_CONVENTIONS 0x00001d88 +#define NV30_3D_COORD_CONVENTIONS_HEIGHT__MASK 0x00000fff +#define NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT 0 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN__MASK 0x00001000 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN__SHIFT 12 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN_NORMAL 0x00000000 +#define NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED 0x00001000 +#define NV30_3D_COORD_CONVENTIONS_CENTER__MASK 0x00010000 +#define NV30_3D_COORD_CONVENTIONS_CENTER__SHIFT 16 +#define NV30_3D_COORD_CONVENTIONS_CENTER_HALF_INTEGER 0x00000000 +#define NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER 0x00010000 + +#define NV30_3D_CLEAR_DEPTH_VALUE 0x00001d8c + +#define NV30_3D_CLEAR_COLOR_VALUE 0x00001d90 +#define NV30_3D_CLEAR_COLOR_VALUE_B__MASK 0x000000ff +#define NV30_3D_CLEAR_COLOR_VALUE_B__SHIFT 0 +#define NV30_3D_CLEAR_COLOR_VALUE_G__MASK 0x0000ff00 +#define NV30_3D_CLEAR_COLOR_VALUE_G__SHIFT 8 +#define NV30_3D_CLEAR_COLOR_VALUE_R__MASK 0x00ff0000 +#define NV30_3D_CLEAR_COLOR_VALUE_R__SHIFT 16 +#define NV30_3D_CLEAR_COLOR_VALUE_A__MASK 0xff000000 +#define NV30_3D_CLEAR_COLOR_VALUE_A__SHIFT 24 + +#define NV30_3D_CLEAR_BUFFERS 0x00001d94 +#define NV30_3D_CLEAR_BUFFERS_DEPTH 0x00000001 +#define NV30_3D_CLEAR_BUFFERS_STENCIL 0x00000002 +#define NV30_3D_CLEAR_BUFFERS_COLOR_R 0x00000010 +#define NV30_3D_CLEAR_BUFFERS_COLOR_G 0x00000020 +#define NV30_3D_CLEAR_BUFFERS_COLOR_B 0x00000040 +#define NV30_3D_CLEAR_BUFFERS_COLOR_A 0x00000080 + +#define NV30_3D_DO_VERTICES 0x00001dac + +#define NV30_3D_LINE_STIPPLE_ENABLE 0x00001db4 + +#define NV30_3D_LINE_STIPPLE_PATTERN 0x00001db8 +#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__MASK 0x0000ffff +#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__SHIFT 0 +#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__MASK 0xffff0000 +#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__SHIFT 16 + +#define NV30_3D_BACK_MATERIAL_SHININESS(i0) (0x00001e20 + 0x4*(i0)) +#define NV30_3D_BACK_MATERIAL_SHININESS__ESIZE 0x00000004 +#define NV30_3D_BACK_MATERIAL_SHININESS__LEN 0x00000006 + +#define NV30_3D_VTX_ATTR_1F(i0) (0x00001e40 + 0x4*(i0)) +#define NV30_3D_VTX_ATTR_1F__ESIZE 0x00000004 +#define NV30_3D_VTX_ATTR_1F__LEN 0x00000010 + +#define NV30_3D_ENGINE 0x00001e94 +#define NV30_3D_ENGINE_FP 0x00000001 +#define NV30_3D_ENGINE_VP 0x00000002 +#define NV30_3D_ENGINE_FIXED 0x00000004 + +#define NV30_3D_VP_UPLOAD_FROM_ID 0x00001e9c + +#define NV30_3D_VP_START_FROM_ID 0x00001ea0 + +#define NV30_3D_POINT_PARAMETERS(i0) (0x00001ec0 + 0x4*(i0)) +#define NV30_3D_POINT_PARAMETERS__ESIZE 0x00000004 +#define NV30_3D_POINT_PARAMETERS__LEN 0x00000008 + +#define NV30_3D_POINT_SIZE 0x00001ee0 + +#define NV30_3D_POINT_PARAMETERS_ENABLE 0x00001ee4 + +#define NV30_3D_POINT_SPRITE 0x00001ee8 +#define NV30_3D_POINT_SPRITE_ENABLE 0x00000001 +#define NV30_3D_POINT_SPRITE_R_MODE__MASK 0x00000006 +#define NV30_3D_POINT_SPRITE_R_MODE__SHIFT 1 +#define NV30_3D_POINT_SPRITE_R_MODE_ZERO 0x00000000 +#define NV30_3D_POINT_SPRITE_R_MODE_R 0x00000002 +#define NV30_3D_POINT_SPRITE_R_MODE_S 0x00000004 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_0 0x00000100 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_1 0x00000200 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_2 0x00000400 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_3 0x00000800 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_4 0x00001000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_5 0x00002000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_6 0x00004000 +#define NV30_3D_POINT_SPRITE_COORD_REPLACE_7 0x00008000 + +#define NV30_3D_VP_UPLOAD_CONST_ID 0x00001efc + +#define NV30_3D_VP_UPLOAD_CONST(i0) (0x00001f00 + 0x10*(i0)) +#define NV30_3D_VP_UPLOAD_CONST__ESIZE 0x00000010 +#define NV30_3D_VP_UPLOAD_CONST__LEN 0x00000004 + + +#define NV30_3D_VP_UPLOAD_CONST_X(i0) (0x00001f00 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_Y(i0) (0x00001f04 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_Z(i0) (0x00001f08 + 0x10*(i0)) + +#define NV30_3D_VP_UPLOAD_CONST_W(i0) (0x00001f0c + 0x10*(i0)) + +#define NV30_3D_UNK1F80(i0) (0x00001f80 + 0x4*(i0)) +#define NV30_3D_UNK1F80__ESIZE 0x00000004 +#define NV30_3D_UNK1F80__LEN 0x00000010 + +#define NV40_3D_TEX_CACHE_CTL 0x00001fd8 + +#define NV40_3D_VP_ATTRIB_EN 0x00001ff0 + +#define NV40_3D_VP_RESULT_EN 0x00001ff4 + + +#endif /* NV30_40_3D_XML */ diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c index 0c3d43fd573..d6ede5b40a1 100644 --- a/src/gallium/drivers/nvfx/nv30_fragtex.c +++ b/src/gallium/drivers/nvfx/nv30_fragtex.c @@ -14,11 +14,11 @@ nv30_sampler_state_init(struct pipe_context *pipe, if (cso->max_anisotropy >= 2) { if (cso->max_anisotropy >= 8) - ps->en |= NV34TCL_TX_ENABLE_ANISO_8X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_8X; else if (cso->max_anisotropy >= 4) - ps->en |= NV34TCL_TX_ENABLE_ANISO_4X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_4X; else if (cso->max_anisotropy >= 2) - ps->en |= NV34TCL_TX_ENABLE_ANISO_2X; + ps->en |= NV30_3D_TEX_ENABLE_ANISO_2X; } limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0)); @@ -27,7 +27,7 @@ nv30_sampler_state_init(struct pipe_context *pipe, ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0); ps->min_lod = (int)CLAMP(cso->min_lod, 0.0, 15.0); - ps->en |= NV34TCL_TX_ENABLE_ENABLE; + ps->en |= NV30_3D_TEX_ENABLE_ENABLE; } void @@ -42,10 +42,10 @@ nv30_sampler_view_init(struct pipe_context *pipe, assert(tf->fmt[0] >= 0); txf = sv->u.init_fmt; - txf |= (level != sv->base.last_level ? NV34TCL_TX_FORMAT_MIPMAP : 0); - txf |= util_logbase2(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT; - txf |= util_logbase2(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT; - txf |= util_logbase2(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT; + txf |= (level != sv->base.last_level ? NV30_3D_TEX_FORMAT_MIPMAP : 0); + txf |= util_logbase2(u_minify(pt->width0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT; + txf |= util_logbase2(u_minify(pt->height0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT; + txf |= util_logbase2(u_minify(pt->depth0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT; txf |= 0x10000; sv->u.nv30.fmt[0] = tf->fmt[0] | txf; @@ -53,7 +53,7 @@ nv30_sampler_view_init(struct pipe_context *pipe, sv->u.nv30.fmt[2] = tf->fmt[2] | txf; sv->u.nv30.fmt[3] = tf->fmt[3] | txf; - sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT); + sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT); if(pt->height0 <= 1 || util_format_is_compressed(sv->base.format)) sv->u.nv30.rect = -1; @@ -102,13 +102,13 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit) txf = sv->u.nv30.fmt[ps->compare + (use_rect ? 2 : 0)]; MARK_RING(chan, 9, 2); - OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8)); OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap); - OUT_RING(chan, ps->en | (min_lod << NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT) | (max_lod << NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT)); + OUT_RING(chan, ps->en | (min_lod << NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT) | (max_lod << NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT)); OUT_RING(chan, sv->swizzle); OUT_RING(chan, ps->filt | sv->filt); OUT_RING(chan, sv->npot_size); diff --git a/src/gallium/drivers/nvfx/nv30_vertprog.h b/src/gallium/drivers/nvfx/nv30_vertprog.h index 9a68f5c1fb0..e8c16b0341a 100644 --- a/src/gallium/drivers/nvfx/nv30_vertprog.h +++ b/src/gallium/drivers/nvfx/nv30_vertprog.h @@ -60,6 +60,9 @@ /* DWORD 0 */ +/* guess that this is the same as nv40 */ +#define NV30_VP_INST_INDEX_INPUT (1 << 27) + #define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24) #define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */ #define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */ @@ -136,6 +139,9 @@ # define NV30_VP_INST_DEST_TC(n) (8+(n)) # define NV30_VP_INST_DEST_CLP(n) (17 + (n)) +/* guess that this is the same as nv40 */ +#define NV30_VP_INST_INDEX_CONST (1 << 1) + /* Useful to split the source selection regs into their pieces */ #define NV30_VP_SRC0_HIGH_SHIFT 6 #define NV30_VP_SRC0_HIGH_MASK 0x00007FC0 diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c index 106ce71a079..d4fb73702da 100644 --- a/src/gallium/drivers/nvfx/nv40_fragtex.c +++ b/src/gallium/drivers/nvfx/nv40_fragtex.c @@ -14,19 +14,19 @@ nv40_sampler_state_init(struct pipe_context *pipe, ps->wrap |= (1 << 5); if (cso->max_anisotropy >= 16) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_16X; else if (cso->max_anisotropy >= 12) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_12X; else if (cso->max_anisotropy >= 10) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_10X; else if (cso->max_anisotropy >= 8) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_8X; else if (cso->max_anisotropy >= 6) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_6X; else if (cso->max_anisotropy >= 4) - ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_4X; else - ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X; + ps->en |= NV40_3D_TEX_ENABLE_ANISO_2X; } limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0)); @@ -35,7 +35,7 @@ nv40_sampler_state_init(struct pipe_context *pipe, ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0); ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0); - ps->en |= NV40TCL_TEX_ENABLE_ENABLE; + ps->en |= NV40_3D_TEX_ENABLE_ENABLE; } void @@ -52,21 +52,21 @@ nv40_sampler_view_init(struct pipe_context *pipe, txf = sv->u.init_fmt; txf |= 0x8000; if(pt->target == PIPE_TEXTURE_CUBE) - txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT); + txf |= ((pt->last_level + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT); else - txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT); + txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT); if (!mt->linear_pitch) sv->u.nv40.npot_size2 = 0; else { sv->u.nv40.npot_size2 = mt->linear_pitch; - txf |= NV40TCL_TEX_FORMAT_LINEAR; + txf |= NV40_3D_TEX_FORMAT_LINEAR; } sv->u.nv40.fmt[0] = tf->fmt[4] | txf; sv->u.nv40.fmt[1] = tf->fmt[5] | txf; - sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40TCL_TEX_SIZE1_DEPTH_SHIFT); + sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40_3D_TEX_SIZE1_DEPTH__SHIFT); sv->lod_offset = (sv->base.first_level - level) * 256; sv->max_lod_limit = (sv->base.last_level - level) * 256; @@ -87,17 +87,17 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit) txf = sv->u.nv40.fmt[ps->compare] | ps->fmt; MARK_RING(chan, 11, 2); - OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8)); OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap); OUT_RING(chan, ps->en | (min_lod << 19) | (max_lod << 7)); OUT_RING(chan, sv->swizzle); OUT_RING(chan, ps->filt | sv->filt); OUT_RING(chan, sv->npot_size); OUT_RING(chan, ps->bcol); - OUT_RING(chan, RING_3D(NV40TCL_TEX_SIZE1(unit), 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_SIZE1(unit), 1)); OUT_RING(chan, sv->u.nv40.npot_size2); nvfx->hw_txf[unit] = txf; diff --git a/src/gallium/drivers/nvfx/nv40_vertprog.h b/src/gallium/drivers/nvfx/nv40_vertprog.h index 3d0a1fe3d10..c1f2208f513 100644 --- a/src/gallium/drivers/nvfx/nv40_vertprog.h +++ b/src/gallium/drivers/nvfx/nv40_vertprog.h @@ -38,6 +38,7 @@ #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) /* use address reg as index into attribs */ #define NV40_VP_INST_INDEX_INPUT (1 << 27) +#define NV40_VP_INST_SATURATE (1 << 26) #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) #define NV40_VP_INST_SRC2_ABS (1 << 23) diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c index 5a2fa14c887..95834d23273 100644 --- a/src/gallium/drivers/nvfx/nvfx_context.c +++ b/src/gallium/drivers/nvfx/nvfx_context.c @@ -13,14 +13,14 @@ nvfx_flush(struct pipe_context *pipe, unsigned flags, struct nvfx_context *nvfx = nvfx_context(pipe); struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; /* XXX: we need to actually be intelligent here */ if (flags & PIPE_FLUSH_TEXTURE_CACHE) { - BEGIN_RING(chan, eng3d, 0x1fd8, 1); - OUT_RING (chan, 2); - BEGIN_RING(chan, eng3d, 0x1fd8, 1); - OUT_RING (chan, 1); + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(0x1fd8, 1)); + OUT_RING(chan, 2); + OUT_RING(chan, RING_3D(0x1fd8, 1)); + OUT_RING(chan, 1); } FIRE_RING(chan); @@ -76,6 +76,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv) nvfx->pipe.flush = nvfx_flush; nvfx->is_nv4x = screen->is_nv4x; + nvfx->use_nv4x = screen->use_nv4x; /* TODO: it seems that nv30 might have fixed function clipping usable with vertex programs * However, my code for that doesn't work, so use vp clipping for all cards, which works. */ diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h index 4c654bfa8ba..6ef2a6945d7 100644 --- a/src/gallium/drivers/nvfx/nvfx_context.h +++ b/src/gallium/drivers/nvfx/nvfx_context.h @@ -18,7 +18,7 @@ #include "nouveau/nouveau_winsys.h" #include "nouveau/nouveau_gldefs.h" - +#include "nv30-40_3d.xml.h" #include "nvfx_state.h" #define NOUVEAU_ERR(fmt, args...) \ @@ -141,22 +141,17 @@ struct nvfx_context { struct nvfx_screen *screen; unsigned is_nv4x; /* either 0 or ~0 */ + unsigned use_nv4x; /* either 0 or ~0 */ boolean use_vp_clipping; struct draw_context *draw; - struct blitter_context* blitter; + /* one is for user-requested operations, the other is for temporary copying inside them */ + struct blitter_context* blitter[2]; + unsigned blitters_in_use; struct list_head render_cache; /* HW state derived from pipe states */ struct nvfx_state state; - struct { - struct nvfx_vertex_program *vertprog; - - unsigned nr_attribs; - unsigned hw[PIPE_MAX_SHADER_INPUTS]; - unsigned draw[PIPE_MAX_SHADER_INPUTS]; - unsigned emit[PIPE_MAX_SHADER_INPUTS]; - } swtnl; enum { HW, SWTNL, SWRAST @@ -168,7 +163,7 @@ struct nvfx_context { struct pipe_scissor_state scissor; unsigned stipple[32]; struct pipe_clip_state clip; - struct nvfx_vertex_program *vertprog; + struct nvfx_pipe_vertex_program *vertprog; struct nvfx_pipe_fragment_program *fragprog; struct pipe_resource *constbuf[PIPE_SHADER_TYPES]; unsigned constbuf_nr[PIPE_SHADER_TYPES]; @@ -183,6 +178,7 @@ struct nvfx_context { struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS]; struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS]; struct nvfx_pipe_fragment_program* dummy_fs; + struct pipe_query* query; unsigned nr_samplers; unsigned nr_textures; @@ -199,13 +195,14 @@ struct nvfx_context { int use_vertex_buffers; unsigned hw_vtxelt_nr; - uint8_t hw_samplers; - uint32_t hw_txf[8]; + unsigned hw_samplers; + uint32_t hw_txf[16]; struct nvfx_render_target hw_rt[4]; struct nvfx_render_target hw_zeta; int hw_pointsprite_control; int hw_vp_output; struct nvfx_fragment_program* hw_fragprog; + struct nvfx_vertex_program* hw_vertprog; unsigned relocs_needed; }; @@ -324,6 +321,7 @@ extern void nvfx_init_transfer_functions(struct pipe_context *pipe); /* nvfx_vbo.c */ extern boolean nvfx_vbo_validate(struct nvfx_context *nvfx); +extern void nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx); extern void nvfx_vbo_relocate(struct nvfx_context *nvfx); extern void nvfx_idxbuf_validate(struct nvfx_context* nvfx); extern void nvfx_idxbuf_relocate(struct nvfx_context* nvfx); @@ -346,25 +344,25 @@ static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned att { switch (ncomp) { case 4: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_4F_X(attrib), 4)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_4F_X(attrib), 4)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); OUT_RING(chan, fui(v[2])); OUT_RING(chan, fui(v[3])); break; case 3: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_3F_X(attrib), 3)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_3F_X(attrib), 3)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); OUT_RING(chan, fui(v[2])); break; case 2: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_2F_X(attrib), 2)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_2F_X(attrib), 2)); OUT_RING(chan, fui(v[0])); OUT_RING(chan, fui(v[1])); break; case 1: - OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_1F(attrib), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_1F(attrib), 1)); OUT_RING(chan, fui(v[0])); break; } diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c index 2601d5b8e2e..61f888a8ea2 100644 --- a/src/gallium/drivers/nvfx/nvfx_draw.c +++ b/src/gallium/drivers/nvfx/nvfx_draw.c @@ -1,6 +1,5 @@ #include "pipe/p_shader_tokens.h" #include "util/u_inlines.h" -#include "tgsi/tgsi_ureg.h" #include "util/u_pack_color.h" @@ -11,11 +10,6 @@ #include "nvfx_context.h" #include "nvfx_resource.h" -/* Simple, but crappy, swtnl path, hopefully we wont need to hit this very - * often at all. Uses "quadro style" vertex submission + a fixed vertex - * layout to avoid the need to generate a vertex program or vtxfmt. - */ - struct nvfx_render_stage { struct draw_stage stage; struct nvfx_context *nvfx; @@ -28,58 +22,18 @@ nvfx_render_stage(struct draw_stage *stage) return (struct nvfx_render_stage *)stage; } -static INLINE void -nvfx_render_vertex(struct nvfx_context *nvfx, const struct vertex_header *v) +static void +nvfx_render_flush(struct draw_stage *stage, unsigned flags) { - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - unsigned i; + struct nvfx_render_stage *rs = nvfx_render_stage(stage); + struct nvfx_context *nvfx = rs->nvfx; + struct nouveau_channel *chan = nvfx->screen->base.channel; - for (i = 0; i < nvfx->swtnl.nr_attribs; i++) { - unsigned idx = nvfx->swtnl.draw[i]; - unsigned hw = nvfx->swtnl.hw[i]; - - WAIT_RING(chan, 5); - switch (nvfx->swtnl.emit[i]) { - case EMIT_OMIT: - break; - case EMIT_1F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 1); - break; - case EMIT_2F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 2); - break; - case EMIT_3F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 3); - break; - case EMIT_4F: - nvfx_emit_vtx_attr(chan, hw, v->data[idx], 4); - break; - case 0xff: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4F_X(hw), 4); - OUT_RING (chan, fui(v->data[idx][0] / v->data[idx][3])); - OUT_RING (chan, fui(v->data[idx][1] / v->data[idx][3])); - OUT_RING (chan, fui(v->data[idx][2] / v->data[idx][3])); - OUT_RING (chan, fui(1.0f / v->data[idx][3])); - break; - case EMIT_4UB: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4UB(hw), 1); - OUT_RING (chan, pack_ub4(float_to_ubyte(v->data[idx][0]), - float_to_ubyte(v->data[idx][1]), - float_to_ubyte(v->data[idx][2]), - float_to_ubyte(v->data[idx][3]))); - case EMIT_4UB_BGRA: - BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4UB(hw), 1); - OUT_RING (chan, pack_ub4(float_to_ubyte(v->data[idx][2]), - float_to_ubyte(v->data[idx][1]), - float_to_ubyte(v->data[idx][0]), - float_to_ubyte(v->data[idx][3]))); - break; - default: - assert(0); - break; - } + if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) { + assert(AVAIL_RING(chan) >= 2); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP); + rs->prim = NV30_3D_VERTEX_BEGIN_END_STOP; } } @@ -92,82 +46,87 @@ nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim, struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - unsigned i; + boolean no_elements = nvfx->vertprog->draw_no_elements; + unsigned num_attribs = nvfx->vertprog->draw_elements; - /* Ensure there's room for 4xfloat32 + potentially 3 begin/end */ - if (AVAIL_RING(chan) < ((count * 20) + 6)) { - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - NOUVEAU_ERR("AIII, missed flush\n"); - assert(0); - } + /* we need to account the flush as well here even if it is done afterthis + * function + */ + if (AVAIL_RING(chan) < ((1 + count * num_attribs * 4) + 6 + 64)) { + nvfx_render_flush(stage, 0); FIRE_RING(chan); nvfx_state_emit(nvfx); + + assert(AVAIL_RING(chan) >= ((1 + count * num_attribs * 4) + 6 + 64)); } /* Switch primitive modes if necessary */ if (rs->prim != mode) { - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); + if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) { + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP); } - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); + /* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */ + /* this seems to cause issues on nv3x, and also be unneeded there */ + if(nvfx->is_nv4x) + { + int i; + for(i = 0; i < 32; ++i) + { + OUT_RING(chan, RING_3D(0x1dac, 1)); + OUT_RING(chan, 0); + } + } + + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING (chan, mode); rs->prim = mode; } - /* Emit vertex data */ - for (i = 0; i < count; i++) - nvfx_render_vertex(nvfx, prim->v[i]); - - /* If it's likely we'll need to empty the push buffer soon, finish - * off the primitive now. - */ - if (AVAIL_RING(chan) < ((count * 20) + 6)) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); - rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; + OUT_RING(chan, RING_3D_NI(NV30_3D_VERTEX_DATA, num_attribs * 4 * count)); + if(no_elements) { + OUT_RING(chan, 0); + OUT_RING(chan, 0); + OUT_RING(chan, 0); + OUT_RING(chan, 0); + } else { + for (unsigned i = 0; i < count; ++i) + { + struct vertex_header* v = prim->v[i]; + /* TODO: disable divide where it's causing the problem, and remove this hack */ + OUT_RING(chan, fui(v->data[0][0] / v->data[0][3])); + OUT_RING(chan, fui(v->data[0][1] / v->data[0][3])); + OUT_RING(chan, fui(v->data[0][2] / v->data[0][3])); + OUT_RING(chan, fui(1.0f / v->data[0][3])); + OUT_RINGp(chan, &v->data[1][0], 4 * (num_attribs - 1)); + } } } static void nvfx_render_point(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_POINTS, 1); + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_POINTS, 1); } static void nvfx_render_line(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_LINES, 2); + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_LINES, 2); } static void nvfx_render_tri(struct draw_stage *draw, struct prim_header *prim) { - nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_TRIANGLES, 3); -} - -static void -nvfx_render_flush(struct draw_stage *draw, unsigned flags) -{ - struct nvfx_render_stage *rs = nvfx_render_stage(draw); - struct nvfx_context *nvfx = rs->nvfx; - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - - if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { - BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1); - OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); - rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; - } + nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_TRIANGLES, 3); } static void nvfx_render_reset_stipple_counter(struct draw_stage *draw) { + /* this doesn't really seem to work, but it matters rather little */ + nvfx_render_flush(draw, 0); } static void @@ -176,40 +135,11 @@ nvfx_render_destroy(struct draw_stage *draw) FREE(draw); } -static struct nvfx_vertex_program * -nvfx_create_drawvp(struct nvfx_context *nvfx) -{ - struct ureg_program *ureg; - uint i; - - ureg = ureg_create( TGSI_PROCESSOR_VERTEX ); - if (ureg == NULL) - return NULL; - - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), ureg_DECL_vs_input(ureg, 0)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0), ureg_DECL_vs_input(ureg, 3)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 1), ureg_DECL_vs_input(ureg, 4)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_BCOLOR, 0), ureg_DECL_vs_input(ureg, 3)); - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_BCOLOR, 1), ureg_DECL_vs_input(ureg, 4)); - ureg_MOV(ureg, - ureg_writemask(ureg_DECL_output(ureg, TGSI_SEMANTIC_FOG, 1), TGSI_WRITEMASK_X), - ureg_DECL_vs_input(ureg, 5)); - for (i = 0; i < 8; ++i) - ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, i), ureg_DECL_vs_input(ureg, 8 + i)); - - ureg_END( ureg ); - - return ureg_create_shader_and_destroy( ureg, &nvfx->pipe ); -} - struct draw_stage * nvfx_draw_render_stage(struct nvfx_context *nvfx) { struct nvfx_render_stage *render = CALLOC_STRUCT(nvfx_render_stage); - if (!nvfx->swtnl.vertprog) - nvfx->swtnl.vertprog = nvfx_create_drawvp(nvfx); - render->nvfx = nvfx; render->stage.draw = nvfx->draw; render->stage.point = nvfx_render_point; @@ -231,6 +161,7 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info if (!nvfx_state_validate_swtnl(nvfx)) return; + nvfx_state_emit(nvfx); /* these must be passed without adding the offsets */ @@ -256,62 +187,3 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info draw_flush(nvfx->draw); } - -static INLINE void -emit_attrib(struct nvfx_context *nvfx, unsigned hw, unsigned emit, - unsigned semantic, unsigned index) -{ - unsigned draw_out = draw_find_shader_output(nvfx->draw, semantic, index); - unsigned a = nvfx->swtnl.nr_attribs++; - - nvfx->swtnl.hw[a] = hw; - nvfx->swtnl.emit[a] = emit; - nvfx->swtnl.draw[a] = draw_out; -} - -void -nvfx_vtxfmt_validate(struct nvfx_context *nvfx) -{ - struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog; - unsigned colour = 0, texcoords = 0, fog = 0, i; - - /* Determine needed fragprog inputs */ - for (i = 0; i < pfp->info.num_inputs; i++) { - switch (pfp->info.input_semantic_name[i]) { - case TGSI_SEMANTIC_POSITION: - break; - case TGSI_SEMANTIC_COLOR: - colour |= (1 << pfp->info.input_semantic_index[i]); - break; - case TGSI_SEMANTIC_GENERIC: - texcoords |= (1 << pfp->info.input_semantic_index[i]); - break; - case TGSI_SEMANTIC_FOG: - fog = 1; - break; - default: - assert(0); - } - } - - nvfx->swtnl.nr_attribs = 0; - - /* Map draw vtxprog output to hw attribute IDs */ - for (i = 0; i < 2; i++) { - if (!(colour & (1 << i))) - continue; - emit_attrib(nvfx, 3 + i, EMIT_4F, TGSI_SEMANTIC_COLOR, i); - } - - for (i = 0; i < 8; i++) { - if (!(texcoords & (1 << i))) - continue; - emit_attrib(nvfx, 8 + i, EMIT_4F, TGSI_SEMANTIC_GENERIC, i); - } - - if (fog) { - emit_attrib(nvfx, 5, EMIT_1F, TGSI_SEMANTIC_FOG, 0); - } - - emit_attrib(nvfx, 0, 0xff, TGSI_SEMANTIC_POSITION, 0); -} diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c index 275672a31fa..d97cab8db19 100644 --- a/src/gallium/drivers/nvfx/nvfx_fragprog.c +++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c @@ -1,3 +1,4 @@ +#include <float.h> #include "pipe/p_context.h" #include "pipe/p_defines.h" #include "pipe/p_state.h" @@ -14,9 +15,6 @@ #include "nvfx_shader.h" #include "nvfx_resource.h" -#define MAX_CONSTS 128 -#define MAX_IMM 32 - struct nvfx_fpc { struct nvfx_pipe_fragment_program* pfp; struct nvfx_fragment_program *fp; @@ -33,13 +31,9 @@ struct nvfx_fpc { unsigned inst_offset; unsigned have_const; - struct { - int pipe; - float vals[4]; - } consts[MAX_CONSTS]; - int nr_consts; + struct util_dynarray imm_data; - struct nvfx_reg imm[MAX_IMM]; + struct nvfx_reg* r_imm; unsigned nr_imm; unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */ @@ -72,19 +66,14 @@ release_temps(struct nvfx_fpc *fpc) fpc->r_temps_discard = 0ULL; } -static INLINE struct nvfx_reg -constant(struct nvfx_fpc *fpc, int pipe, float vals[4]) +static inline struct nvfx_reg +nvfx_fp_imm(struct nvfx_fpc *fpc, float a, float b, float c, float d) { - int idx; - - if (fpc->nr_consts == MAX_CONSTS) - assert(0); - idx = fpc->nr_consts++; + float v[4] = {a, b, c, d}; + int idx = fpc->imm_data.size >> 4; - fpc->consts[idx].pipe = pipe; - if (pipe == -1) - memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float)); - return nvfx_reg(NVFXSR_CONST, idx); + memcpy(util_dynarray_grow(&fpc->imm_data, sizeof(float) * 4), v, 4 * sizeof(float)); + return nvfx_reg(NVFXSR_IMM, idx); } static void @@ -121,26 +110,35 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src) //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index); util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1); break; + case NVFXSR_IMM: + if (!fpc->have_const) { + grow_insns(fpc, 4); + hw = &fp->insn[fpc->inst_offset]; + fpc->have_const = 1; + } + + memcpy(&fp->insn[fpc->inst_offset + 4], + (float*)fpc->imm_data.data + src.reg.index * 4, + sizeof(uint32_t) * 4); + + sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT); + break; case NVFXSR_CONST: if (!fpc->have_const) { grow_insns(fpc, 4); + hw = &fp->insn[fpc->inst_offset]; fpc->have_const = 1; } - hw = &fp->insn[fpc->inst_offset]; - if (fpc->consts[src.reg.index].pipe >= 0) { + { struct nvfx_fragment_program_data *fpd; fp->consts = realloc(fp->consts, ++fp->nr_consts * sizeof(*fpd)); fpd = &fp->consts[fp->nr_consts - 1]; fpd->offset = fpc->inst_offset + 4; - fpd->index = fpc->consts[src.reg.index].pipe; + fpd->index = src.reg.index; memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4); - } else { - memcpy(&fp->insn[fpc->inst_offset + 4], - fpc->consts[src.reg.index].vals, - sizeof(uint32_t) * 4); } sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT); @@ -207,7 +205,7 @@ nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn) memset(hw, 0, sizeof(uint32_t) * 4); if (insn.op == NVFX_FP_OP_OPCODE_KIL) - fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL; + fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL; hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT); hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT); hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT); @@ -408,11 +406,11 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) } break; case TGSI_FILE_CONSTANT: - src.reg = constant(fpc, fsrc->Register.Index, NULL); + src.reg = nvfx_reg(NVFXSR_CONST, fsrc->Register.Index); break; case TGSI_FILE_IMMEDIATE: assert(fsrc->Register.Index < fpc->nr_imm); - src.reg = fpc->imm[fsrc->Register.Index]; + src.reg = fpc->r_imm[fsrc->Register.Index]; break; case TGSI_FILE_TEMPORARY: src.reg = fpc->r_temp[fsrc->Register.Index]; @@ -434,6 +432,9 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc) src.swz[1] = fsrc->Register.SwizzleY; src.swz[2] = fsrc->Register.SwizzleZ; src.swz[3] = fsrc->Register.SwizzleW; + src.indirect = 0; + src.indirect_reg = 0; + src.indirect_swz = 0; return src; } @@ -470,7 +471,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, { const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct nvfx_insn insn; - struct nvfx_src src[3], tmp, tmp2; + struct nvfx_src src[3], tmp; struct nvfx_reg dst; int mask, sat, unit = 0; int ai = -1, ci = -1, ii = -1; @@ -495,7 +496,21 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, switch (fsrc->Register.File) { case TGSI_FILE_INPUT: - if (ai == -1 || ai == fsrc->Register.Index) { + if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0 + || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA + || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA + )) { + /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */ + struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1)); + addend.swz[0] = fsrc->Register.SwizzleX; + addend.swz[1] = fsrc->Register.SwizzleY; + addend.swz[2] = fsrc->Register.SwizzleZ; + addend.swz[3] = fsrc->Register.SwizzleW; + src[i] = nvfx_src(temp(fpc)); + nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none)); + } else if (ai == -1 || ai == fsrc->Register.Index) { ai = fsrc->Register.Index; src[i] = tgsi_src(fpc, fsrc); } else { @@ -629,7 +644,27 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_LG2: nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none)); break; -// case TGSI_OPCODE_LIT: + case TGSI_OPCODE_LIT: + if(!nvfx->is_nv4x) + nvfx_fp_emit(fpc, arith(sat, LIT_NV30, dst, mask, src[0], src[1], src[2])); + else { + /* we use FLT_MIN, so that log2 never gives -infinity, and thus multiplication by + * specular 0 always gives 0, so that ex2 gives 1, to satisfy the 0^0 = 1 requirement + * + * NOTE: if we start using half precision, we might need an fp16 FLT_MIN here instead + */ + struct nvfx_src maxs = nvfx_src(nvfx_fp_imm(fpc, 0, FLT_MIN, 0, 0)); + tmp = nvfx_src(temp(fpc)); + if (ci>= 0 || ii >= 0) { + nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, maxs, none, none)); + maxs = tmp; + } + nvfx_fp_emit(fpc, arith(0, MAX, tmp.reg, NVFX_FP_MASK_Y | NVFX_FP_MASK_W, swz(src[0], X, X, X, Y), swz(maxs, X, X, Y, Y), none)); + nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), none, none)); + nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), swz(src[0], W, W, W, W), none)); + nvfx_fp_emit(fpc, arith(sat, LITEX2_NV40, dst, mask, swz(tmp, Y, Y, W, W), none, none)); + } + break; case TGSI_OPCODE_LRP: if(!nvfx->is_nv4x) nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2])); @@ -735,12 +770,24 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SSG: - tmp = nvfx_src(temp(fpc)); - tmp2 = nvfx_src(temp(fpc)); - nvfx_fp_emit(fpc, arith(0, SGT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none)); - nvfx_fp_emit(fpc, arith(0, SLT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none)); - nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, tmp, neg(tmp2), none)); + { + struct nvfx_src minones = swz(nvfx_src(nvfx_fp_imm(fpc, -1, -1, -1, -1)), X, X, X, X); + + insn = arith(sat, MOV, dst, mask, src[0], none, none); + insn.cc_update = 1; + nvfx_fp_emit(fpc, insn); + + insn = arith(0, STR, dst, mask, none, none, none); + insn.cc_test = NVFX_COND_GT; + nvfx_fp_emit(fpc, insn); + + if(!sat) { + insn = arith(0, MOV, dst, mask, minones, none, none); + insn.cc_test = NVFX_COND_LT; + nvfx_fp_emit(fpc, insn); + } break; + } case TGSI_OPCODE_STR: nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none)); break; @@ -784,7 +831,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_IF: // MOVRC0 R31 (TR0.xyzw), R<src>: // IF (NE.xxxx) ELSE <else> END <end> - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_if(fpc, src[0]); break; @@ -792,7 +839,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_ELSE: { uint32_t *hw; - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)]; @@ -803,7 +850,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_ENDIF: { uint32_t *hw; - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)]; @@ -826,19 +873,19 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, break; case TGSI_OPCODE_CAL: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_cal(fpc, finst->Label.Label); break; case TGSI_OPCODE_RET: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_ret(fpc); break; case TGSI_OPCODE_BGNLOOP: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; /* TODO: we should support using two nested REPs to allow a > 255 iteration count */ nv40_fp_rep(fpc, 255, finst->Label.Label); @@ -848,7 +895,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, break; case TGSI_OPCODE_BRK: - if(!nvfx->is_nv4x) + if(!nvfx->use_nv4x) goto nv3x_cflow; nv40_fp_brk(fpc); break; @@ -903,7 +950,7 @@ nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case 2: hw = 3; break; case 3: hw = 4; break; } - if(hw > ((nvfx->is_nv4x) ? 4 : 2)) { + if(hw > ((nvfx->use_nv4x) ? 4 : 2)) { NOUVEAU_ERR("bad rcol index\n"); return FALSE; } @@ -924,19 +971,17 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc) struct tgsi_parse_context p; int high_temp = -1, i; struct util_semantic_set set; - float const0v[4] = {0, 0, 0, 0}; - struct nvfx_reg const0; + unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8; fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT); - if(fpc->fp->num_slots > 8) + if(fpc->fp->num_slots > num_texcoords) return FALSE; - util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8); - util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8); + util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, num_texcoords); + util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, num_texcoords); memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input)); - const0 = constant(fpc, -1, const0v); - assert(const0.index == 0); + fpc->r_imm = CALLOC(fpc->pfp->info.immediate_count, sizeof(struct nvfx_reg)); tgsi_parse_init(&p, fpc->pfp->pipe.tokens); while (!tgsi_parse_end_of_tokens(&p)) { @@ -967,19 +1012,14 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc) case TGSI_TOKEN_TYPE_IMMEDIATE: { struct tgsi_full_immediate *imm; - float vals[4]; imm = &p.FullToken.FullImmediate; assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32); - assert(fpc->nr_imm < MAX_IMM); + assert(fpc->nr_imm < fpc->pfp->info.immediate_count); - vals[0] = imm->u[0].Float; - vals[1] = imm->u[1].Float; - vals[2] = imm->u[2].Float; - vals[3] = imm->u[3].Float; - fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals); - } + fpc->r_imm[fpc->nr_imm++] = nvfx_fp_imm(fpc, imm->u[0].Float, imm->u[1].Float, imm->u[2].Float, imm->u[3].Float); break; + } default: break; } @@ -1025,11 +1065,21 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, if (!fpc) goto out_err; - fpc->max_temps = nvfx->is_nv4x ? 48 : 32; + fpc->max_temps = nvfx->use_nv4x ? 48 : 32; fpc->pfp = pfp; fpc->fp = fp; fpc->num_regs = 2; + for (unsigned i = 0; i < pfp->info.num_properties; ++i) { + if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) { + if(pfp->info.properties[i].data[0]) + fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED; + } else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) { + if(pfp->info.properties[i].data[0]) + fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER; + } + } + if (!nvfx_fragprog_prepare(nvfx, fpc)) goto out_err; @@ -1040,8 +1090,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, { struct nvfx_reg reg = temp(fpc); struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots)); - float v[4] = {1, -1, 0, 0}; - struct nvfx_src imm = nvfx_src(constant(fpc, -1, v)); + struct nvfx_src imm = nvfx_src(nvfx_fp_imm(fpc, 1, -1, 0, 0)); fpc->sprite_coord_temp = reg.index; fpc->r_temps_discard = 0ULL; @@ -1078,7 +1127,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx, if(!nvfx->is_nv4x) fp->fp_control |= (fpc->num_regs-1)/2; else - fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT; + fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT; /* Terminate final instruction */ if(fp->insn) @@ -1119,6 +1168,7 @@ out: FREE(fpc->r_temp); util_dynarray_fini(&fpc->if_stack); util_dynarray_fini(&fpc->label_relocs); + util_dynarray_fini(&fpc->imm_data); //util_dynarray_fini(&fpc->loop_stack); FREE(fpc); } @@ -1230,7 +1280,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) pfp->fps[key] = fp; } - vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog; + vp = nvfx->hw_vertprog; if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) { int sprite_real_input = -1; @@ -1450,17 +1500,17 @@ update: nvfx->hw_fragprog = fp; MARK_RING(chan, 8, 1); - OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1)); + OUT_RING(chan, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1)); OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, - NV34TCL_FP_ACTIVE_PROGRAM_DMA1); - OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1)); + NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, + NV30_3D_FP_ACTIVE_PROGRAM_DMA1); + OUT_RING(chan, RING_3D(NV30_3D_FP_CONTROL, 1)); OUT_RING(chan, fp->fp_control); if(!nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1)); + OUT_RING(chan, RING_3D(NV30_3D_FP_REG_CONTROL, 1)); OUT_RING(chan, (1<<16)|0x4); - OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_UNITS_ENABLE, 1)); OUT_RING(chan, fp->samplers); } } @@ -1470,7 +1520,7 @@ update: if(pointsprite_control != nvfx->hw_pointsprite_control) { WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_POINT_SPRITE, 1)); OUT_RING(chan, pointsprite_control); nvfx->hw_pointsprite_control = pointsprite_control; } @@ -1489,10 +1539,10 @@ nvfx_fragprog_relocate(struct nvfx_context *nvfx) unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART? fp_flags |= NOUVEAU_BO_DUMMY; MARK_RING(chan, 2, 2); - OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0); OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, - NV34TCL_FP_ACTIVE_PROGRAM_DMA1); + NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, + NV30_3D_FP_ACTIVE_PROGRAM_DMA1); nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG; } diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c index 6503c7afcbf..1d6b4e24cbc 100644 --- a/src/gallium/drivers/nvfx/nvfx_fragtex.c +++ b/src/gallium/drivers/nvfx/nvfx_fragtex.c @@ -12,12 +12,12 @@ nvfx_sampler_state_create(struct pipe_context *pipe, ps = MALLOC(sizeof(struct nvfx_sampler_state)); /* on nv30, we use this as an internal flag */ - ps->fmt = cso->normalized_coords ? 0 : NV40TCL_TEX_FORMAT_RECT; + ps->fmt = cso->normalized_coords ? 0 : NV40_3D_TEX_FORMAT_RECT; ps->en = 0; ps->filt = nvfx_tex_filter(cso) | 0x2000; /*voodoo*/ - ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) | - (nvfx_tex_wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) | - (nvfx_tex_wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT); + ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV30_3D_TEX_WRAP_S__SHIFT) | + (nvfx_tex_wrap_mode(cso->wrap_t) << NV30_3D_TEX_WRAP_T__SHIFT) | + (nvfx_tex_wrap_mode(cso->wrap_r) << NV30_3D_TEX_WRAP_R__SHIFT); ps->compare = FALSE; if(cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) @@ -80,21 +80,21 @@ nvfx_create_sampler_view(struct pipe_context *pipe, pipe_resource_reference(&sv->base.texture, pt); sv->base.context = pipe; - txf = NV34TCL_TX_FORMAT_NO_BORDER; + txf = NV30_3D_TEX_FORMAT_NO_BORDER; switch (pt->target) { case PIPE_TEXTURE_CUBE: - txf |= NV34TCL_TX_FORMAT_CUBIC; + txf |= NV30_3D_TEX_FORMAT_CUBIC; /* fall-through */ case PIPE_TEXTURE_2D: case PIPE_TEXTURE_RECT: - txf |= NV34TCL_TX_FORMAT_DIMS_2D; + txf |= NV30_3D_TEX_FORMAT_DIMS_2D; break; case PIPE_TEXTURE_3D: - txf |= NV34TCL_TX_FORMAT_DIMS_3D; + txf |= NV30_3D_TEX_FORMAT_DIMS_3D; break; case PIPE_TEXTURE_1D: - txf |= NV34TCL_TX_FORMAT_DIMS_1D; + txf |= NV30_3D_TEX_FORMAT_DIMS_1D; break; default: assert(0); @@ -102,14 +102,14 @@ nvfx_create_sampler_view(struct pipe_context *pipe, sv->u.init_fmt = txf; sv->swizzle = 0 - | (tf->src[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S0_Z_SHIFT) - | (tf->src[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S0_Y_SHIFT) - | (tf->src[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S0_X_SHIFT) - | (tf->src[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S0_W_SHIFT) - | (tf->comp[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S1_Z_SHIFT) - | (tf->comp[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S1_Y_SHIFT) - | (tf->comp[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S1_X_SHIFT) - | (tf->comp[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S1_W_SHIFT); + | (tf->src[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT) + | (tf->src[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT) + | (tf->src[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S0_X__SHIFT) + | (tf->src[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S0_W__SHIFT) + | (tf->comp[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT) + | (tf->comp[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT) + | (tf->comp[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S1_X__SHIFT) + | (tf->comp[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S1_W__SHIFT); sv->filt = tf->sign; sv->wrap = tf->wrap; @@ -118,18 +118,18 @@ nvfx_create_sampler_view(struct pipe_context *pipe, if (pt->target == PIPE_TEXTURE_CUBE) { sv->offset = 0; - sv->npot_size = (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0; + sv->npot_size = (pt->width0 << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | pt->height0; } else { sv->offset = nvfx_subresource_offset(pt, 0, sv->base.first_level, 0); - sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | u_minify(pt->height0, sv->base.first_level); + sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | u_minify(pt->height0, sv->base.first_level); /* apparently, we need to ignore the t coordinate for 1D textures to fix piglit tex1d-2dborder */ if(pt->target == PIPE_TEXTURE_1D) { - sv->wrap_mask &=~ NV34TCL_TX_WRAP_T_MASK; - sv->wrap |= NV34TCL_TX_WRAP_T_REPEAT; + sv->wrap_mask &=~ NV30_3D_TEX_WRAP_T__MASK; + sv->wrap |= NV30_3D_TEX_WRAP_T_REPEAT; } } @@ -199,7 +199,7 @@ nvfx_fragtex_validate(struct nvfx_context *nvfx) } else { WAIT_RING(chan, 2); /* this is OK for nv40 too */ - OUT_RING(chan, RING_3D(NV34TCL_TX_ENABLE(unit), 1)); + OUT_RING(chan, RING_3D(NV30_3D_TEX_ENABLE(unit), 1)); OUT_RING(chan, 0); nvfx->hw_samplers &= ~(1 << unit); } @@ -227,10 +227,10 @@ nvfx_fragtex_relocate(struct nvfx_context *nvfx) bo = mt->base.bo; MARK_RING(chan, 3, 3); - OUT_RELOC(chan, bo, RING_3D(NV34TCL_TX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_TEX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0); OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_DUMMY, 0, 0); OUT_RELOC(chan, bo, nvfx->hw_txf[unit], tex_flags | NOUVEAU_BO_OR | NOUVEAU_BO_DUMMY, - NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); + NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1); } nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX; } @@ -246,32 +246,32 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx) nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy; } -#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1 -#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3 -#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT1_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT1 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT3_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT3 +#define NV30_3D_TEX_FORMAT_FORMAT_DXT5_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT5 -#define NV40TCL_TEX_FORMAT_FORMAT_HILO16 NV40TCL_TEX_FORMAT_FORMAT_A16L16 +#define NV40_3D_TEX_FORMAT_FORMAT_HILO16 NV40_3D_TEX_FORMAT_FORMAT_A16L16 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F 0x00004a00 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA16F -#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F 0x00004b00 -#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA32F -#define NV34TCL_TX_FORMAT_FORMAT_R32F 0x00004c00 -#define NV34TCL_TX_FORMAT_FORMAT_R32F_RECT NV34TCL_TX_FORMAT_FORMAT_R32F +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00004a00 +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA16F +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00004b00 +#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA32F +#define NV30_3D_TEX_FORMAT_FORMAT_R32F 0x00004c00 +#define NV30_3D_TEX_FORMAT_FORMAT_R32F_RECT NV30_3D_TEX_FORMAT_FORMAT_R32F // TODO: guess! -#define NV40TCL_TEX_FORMAT_FORMAT_R32F 0x00001c00 +#define NV40_3D_TEX_FORMAT_FORMAT_R32F 0x00001c00 #define SRGB 0x00700000 #define __(m,tf,tfc,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign,wrap) \ [PIPE_FORMAT_##m] = { \ - {NV34TCL_TX_FORMAT_FORMAT_##tf, \ - NV34TCL_TX_FORMAT_FORMAT_##tfc, \ - NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT, \ - NV34TCL_TX_FORMAT_FORMAT_##tfc##_RECT, \ - NV40TCL_TEX_FORMAT_FORMAT_##tf, \ - NV40TCL_TEX_FORMAT_FORMAT_##tfc}, \ + {NV30_3D_TEX_FORMAT_FORMAT_##tf, \ + NV30_3D_TEX_FORMAT_FORMAT_##tfc, \ + NV30_3D_TEX_FORMAT_FORMAT_##tf##_RECT, \ + NV30_3D_TEX_FORMAT_FORMAT_##tfc##_RECT, \ + NV40_3D_TEX_FORMAT_FORMAT_##tf, \ + NV40_3D_TEX_FORMAT_FORMAT_##tfc}, \ sign, wrap, \ {ts0z, ts0y, ts0x, ts0w, 0, 1}, {ts1z, ts1y, ts1x, ts1w, 0, 0} \ } @@ -293,7 +293,7 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx) #define Z 1 #define W 0 -#define SNORM ((NV34TCL_TX_FILTER_SIGNED_RED) | (NV34TCL_TX_FILTER_SIGNED_GREEN) | (NV34TCL_TX_FILTER_SIGNED_BLUE) | (NV34TCL_TX_FILTER_SIGNED_ALPHA)) +#define SNORM ((NV30_3D_TEX_FILTER_SIGNED_RED) | (NV30_3D_TEX_FILTER_SIGNED_GREEN) | (NV30_3D_TEX_FILTER_SIGNED_BLUE) | (NV30_3D_TEX_FILTER_SIGNED_ALPHA)) #define UNORM 0 struct nvfx_texture_format diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c index 0916aaa8289..7677fde40cb 100644 --- a/src/gallium/drivers/nvfx/nvfx_miptree.c +++ b/src/gallium/drivers/nvfx/nvfx_miptree.c @@ -214,6 +214,7 @@ nvfx_miptree_surface_del(struct pipe_surface *ps) if(!ns->temp) { + assert(!util_dirty_surface_is_dirty(&ns->base)); util_surfaces_detach(&((struct nvfx_miptree*)ps->texture)->surfaces, ps); pipe_resource_reference(&ps->texture, 0); FREE(ps); diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c index ffe7e983578..ebf47e6ed30 100644 --- a/src/gallium/drivers/nvfx/nvfx_push.c +++ b/src/gallium/drivers/nvfx/nvfx_push.c @@ -29,7 +29,7 @@ emit_edgeflag(void *priv, boolean enabled) struct push_context* ctx = priv; struct nouveau_channel *chan = ctx->chan; - OUT_RING(chan, RING_3D(NV34TCL_EDGEFLAG_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_EDGEFLAG, 1)); OUT_RING(chan, enabled ? 1 : 0); } @@ -44,7 +44,7 @@ emit_vertices_lookup8(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -64,7 +64,7 @@ emit_vertices_lookup16(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -84,7 +84,7 @@ emit_vertices_lookup32(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -103,7 +103,7 @@ emit_vertices(void *priv, unsigned start, unsigned count) unsigned push = MIN2(count, ctx->max_vertices_per_packet); unsigned length = push * ctx->vertex_length; - OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length)); + OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length)); ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur); ctx->chan->cur += length; @@ -141,13 +141,13 @@ emit_ranges(void* priv, unsigned start, unsigned vc, unsigned reg) static void emit_ib_ranges(void* priv, unsigned start, unsigned vc) { - emit_ranges(priv, start, vc, NV34TCL_VB_INDEX_BATCH); + emit_ranges(priv, start, vc, NV30_3D_VB_INDEX_BATCH); } static void emit_vb_ranges(void* priv, unsigned start, unsigned vc) { - emit_ranges(priv, start, vc, NV34TCL_VB_VERTEX_BATCH); + emit_ranges(priv, start, vc, NV30_3D_VB_VERTEX_BATCH); } static INLINE void @@ -159,7 +159,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc) int idxbias = ctx->idxbias; if (vc & 1) { - OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1)); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -168,7 +168,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc) unsigned i; unsigned push = MIN2(vc, 2047 * 2); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1)); for (i = 0; i < push; i+=2) OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias)); @@ -186,7 +186,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc) int idxbias = ctx->idxbias; if (vc & 1) { - OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1)); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -195,7 +195,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc) unsigned i; unsigned push = MIN2(vc, 2047 * 2); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1)); for (i = 0; i < push; i+=2) OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias)); @@ -215,7 +215,7 @@ emit_elt32(void* priv, unsigned start, unsigned vc) while (vc) { unsigned push = MIN2(vc, 2047); - OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U32, push)); + OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U32, push)); assert(AVAIL_RING(chan) >= push); if(idxbias) { @@ -379,10 +379,10 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) } } - OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING(chan, hw_mode); done = util_split_prim_next(&s, max_verts); - OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1)); OUT_RING(chan, 0); if(done) diff --git a/src/gallium/drivers/nvfx/nvfx_query.c b/src/gallium/drivers/nvfx/nvfx_query.c index 1dab20c41a0..3935ffd7f92 100644 --- a/src/gallium/drivers/nvfx/nvfx_query.c +++ b/src/gallium/drivers/nvfx/nvfx_query.c @@ -49,9 +49,10 @@ nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq) struct nvfx_query *q = nvfx_query(pq); struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; uint64_t tmp; + assert(!nvfx->query); + /* Happens when end_query() is called, then another begin_query() * without querying the result in-between. For now we'll wait for * the existing query to notify completion, but it could be better. @@ -71,27 +72,35 @@ nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq) nouveau_notifier_reset(nvfx->screen->query, q->object->start); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_RESET, 1); - OUT_RING (chan, 1); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_UNK17CC, 1); - OUT_RING (chan, 1); + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_RESET, 1)); + OUT_RING(chan, 1); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 1); q->ready = FALSE; + + nvfx->query = pq; } static void nvfx_query_end(struct pipe_context *pipe, struct pipe_query *pq) { struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_screen *screen = nvfx->screen; - struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; + struct nouveau_channel *chan = nvfx->screen->base.channel; struct nvfx_query *q = nvfx_query(pq); - BEGIN_RING(chan, eng3d, NV34TCL_QUERY_GET, 1); - OUT_RING (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) | - ((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT)); + assert(nvfx->query == pq); + + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_GET, 1)); + OUT_RING (chan, (0x01 << NV30_3D_QUERY_GET_UNK24__SHIFT) | + ((q->object->start * 32) << NV30_3D_QUERY_GET_OFFSET__SHIFT)); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 0); FIRE_RING(chan); + + nvfx->query = 0; } static boolean diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c index 65ca265d45c..3f177b7ed07 100644 --- a/src/gallium/drivers/nvfx/nvfx_screen.c +++ b/src/gallium/drivers/nvfx/nvfx_screen.c @@ -4,15 +4,15 @@ #include "util/u_simple_screen.h" #include "nouveau/nouveau_screen.h" - +#include "nouveau/nv_object.xml.h" #include "nvfx_context.h" #include "nvfx_screen.h" #include "nvfx_resource.h" #include "nvfx_tex.h" -#define NV30TCL_CHIPSET_3X_MASK 0x00000003 -#define NV34TCL_CHIPSET_3X_MASK 0x00000010 -#define NV35TCL_CHIPSET_3X_MASK 0x000001e0 +#define NV30_3D_CHIPSET_3X_MASK 0x00000003 +#define NV34_3D_CHIPSET_3X_MASK 0x00000010 +#define NV35_3D_CHIPSET_3X_MASK 0x000001e0 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf #define NV4X_GRCLASS4497_CHIPSETS 0x00005450 @@ -25,10 +25,9 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) switch (param) { case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: - /* TODO: check this */ - return screen->is_nv4x ? 16 : 8; + return 16; case PIPE_CAP_NPOT_TEXTURES: - return !!screen->is_nv4x; + return screen->advertise_npot; case PIPE_CAP_TWO_SIDED_STENCIL: return 1; case PIPE_CAP_GLSL: @@ -38,7 +37,7 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POINT_SPRITE: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: - return screen->is_nv4x ? 4 : 2; + return screen->use_nv4x ? 4 : 2; case PIPE_CAP_OCCLUSION_QUERY: return 1; case PIPE_CAP_TIMER_QUERY: @@ -54,15 +53,13 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return 13; case PIPE_CAP_TEXTURE_MIRROR_CLAMP: - return !!screen->is_nv4x; + return !!screen->use_nv4x; case PIPE_CAP_TEXTURE_MIRROR_REPEAT: return 1; case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: return 0; /* We have 4 on nv40 - but unsupported currently */ - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 0; case PIPE_CAP_BLEND_EQUATION_SEPARATE: - return !!screen->is_nv4x; + return screen->advertise_blend_equation_separate; case PIPE_CAP_MAX_COMBINED_SAMPLERS: return 16; case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -75,59 +72,90 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - return 1; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: - return 0; - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - return 4096; - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static - value (nv30:0/nv40:4) ? */ - return screen->is_nv4x ? 4 : 0; - case PIPE_CAP_MAX_FS_INPUTS: - return 10; - case PIPE_CAP_MAX_FS_CONSTS: - return screen->is_nv4x ? 224 : 32; - case PIPE_CAP_MAX_FS_TEMPS: - return 32; - case PIPE_CAP_MAX_FS_ADDRS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_MAX_FS_PREDS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - return screen->is_nv4x ? 512 : 256; - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - return screen->is_nv4x ? 512 : 0; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static - value (nv30:1/nv40:4) ? */ - return screen->is_nv4x ? 4 : 1; - case PIPE_CAP_MAX_VS_INPUTS: - return 16; - case PIPE_CAP_MAX_VS_CONSTS: - return 256; - case PIPE_CAP_MAX_VS_TEMPS: - return screen->is_nv4x ? 32 : 13; - case PIPE_CAP_MAX_VS_ADDRS: - return 2; - case PIPE_CAP_MAX_VS_PREDS: - return screen->is_nv4x ? 1 : 0; - case PIPE_CAP_GEOMETRY_SHADER4: - return 0; + return 1; case PIPE_CAP_DEPTH_CLAMP: return 0; // TODO: implement depth clamp default: - NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); + NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param); return 0; } } +static int +nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param) +{ + struct nvfx_screen *screen = nvfx_screen(pscreen); + + switch(shader) { + case PIPE_SHADER_FRAGMENT: + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 4096; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static + value (nv30:0/nv40:4) ? */ + return screen->use_nv4x ? 4 : 0; + case PIPE_SHADER_CAP_MAX_INPUTS: + return screen->use_nv4x ? 12 : 10; + case PIPE_SHADER_CAP_MAX_CONSTS: + return screen->use_nv4x ? 224 : 32; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 32; + case PIPE_SHADER_CAP_MAX_ADDRS: + return screen->use_nv4x ? 1 : 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* we could expose these, but nothing uses them */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 0; + default: + break; + } + break; + case PIPE_SHADER_VERTEX: + switch(param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + return screen->use_nv4x ? 512 : 256; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return screen->use_nv4x ? 512 : 0; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static + value (nv30:1/nv40:4) ? */ + return screen->use_nv4x ? 4 : 1; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 16; + case PIPE_SHADER_CAP_MAX_CONSTS: + /* - 6 is for clip planes; Gallium should be fixed to put + * them in the vertex shader itself, so we don't need to reserve these */ + return (screen->use_nv4x ? 468 : 256) - 6; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + return screen->use_nv4x ? 32 : 13; + case PIPE_SHADER_CAP_MAX_ADDRS: + return 2; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* we could expose these, but nothing uses them */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + default: + break; + } + break; + default: + break; + } + return 0; +} + static float nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param) { @@ -141,9 +169,9 @@ nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_POINT_WIDTH_AA: return 64.0; case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: - return screen->is_nv4x ? 16.0 : 8.0; + return screen->use_nv4x ? 16.0 : 8.0; case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: - return screen->is_nv4x ? 16.0 : 4.0; + return 15.0; default: NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param); return 0.0; @@ -168,6 +196,14 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen, case PIPE_FORMAT_B8G8R8X8_UNORM: case PIPE_FORMAT_B5G6R5_UNORM: break; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + if(!screen->advertise_fp16) + return FALSE; + break; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + if(!screen->advertise_fp32) + return FALSE; + break; default: return FALSE; } @@ -188,8 +224,11 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen, struct nvfx_texture_format* tf = &nvfx_texture_formats[format]; if(util_format_is_s3tc(format) && !util_format_s3tc_enabled) return FALSE; - - if(screen->is_nv4x) + if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16) + return FALSE; + if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32) + return FALSE; + if(screen->use_nv4x) { if(tf->fmt[4] < 0) return FALSE; @@ -245,9 +284,9 @@ static void nv30_screen_init(struct nvfx_screen *screen) /* TODO: perhaps we should do some of this on nv40 too? */ for (i=1; i<8; i++) { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1)); OUT_RING(chan, 0); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1)); OUT_RING(chan, 0); } @@ -283,14 +322,14 @@ static void nv30_screen_init(struct nvfx_screen *screen) OUT_RING(chan, RING_3D(0x1d88, 1)); OUT_RING(chan, 0x00001200); - OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1)); OUT_RING(chan, 0); - OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2)); OUT_RING(chan, fui(0.0)); OUT_RING(chan, fui(1.0)); - OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1)); + OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1)); OUT_RING(chan, 0xffff0000); /* enables use of vp rather than fixed-function somehow */ @@ -302,10 +341,13 @@ static void nv40_screen_init(struct nvfx_screen *screen) { struct nouveau_channel *chan = screen->base.channel; - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2)); + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2)); OUT_RING(chan, screen->base.channel->vram->handle); OUT_RING(chan, screen->base.channel->vram->handle); + OUT_RING(chan, RING_3D(0x1450, 1)); + OUT_RING(chan, 0x00000004); + OUT_RING(chan, RING_3D(0x1ea4, 3)); OUT_RING(chan, 0x00000010); OUT_RING(chan, 0x01000100); @@ -316,7 +358,7 @@ static void nv40_screen_init(struct nvfx_screen *screen) OUT_RING(chan, 0x06144321); OUT_RING(chan, RING_3D(0x1fc8, 2)); OUT_RING(chan, 0xedcba987); - OUT_RING(chan, 0x00000021); + OUT_RING(chan, 0x0000006f); OUT_RING(chan, RING_3D(0x1fd0, 1)); OUT_RING(chan, 0x00171615); OUT_RING(chan, RING_3D(0x1fd4, 1)); @@ -325,9 +367,12 @@ static void nv40_screen_init(struct nvfx_screen *screen) OUT_RING(chan, RING_3D(0x1ef8, 1)); OUT_RING(chan, 0x0020ffff); OUT_RING(chan, RING_3D(0x1d64, 1)); - OUT_RING(chan, 0x00d30000); + OUT_RING(chan, 0x01d300d4); OUT_RING(chan, RING_3D(0x1e94, 1)); OUT_RING(chan, 0x00000001); + + OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1)); + OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN); } static unsigned @@ -344,19 +389,6 @@ nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen) vram_hack_default = 1; vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default); -#ifdef DEBUG - if(!vram_hack) - { - fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n" - "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n"); - } - else - { - fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n" - "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n"); - } -#endif - return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART; } @@ -396,29 +428,30 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) pscreen->winsys = ws; pscreen->destroy = nvfx_screen_destroy; pscreen->get_param = nvfx_screen_get_param; + pscreen->get_shader_param = nvfx_screen_get_shader_param; pscreen->get_paramf = nvfx_screen_get_paramf; pscreen->is_format_supported = nvfx_screen_is_format_supported; pscreen->context_create = nvfx_create; switch (dev->chipset & 0xf0) { case 0x30: - if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0397; - else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0697; - else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) - eng3d_class = 0x0497; + if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV30_3D; + else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV34_3D; + else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f))) + eng3d_class = NV35_3D; break; case 0x40: if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV40TCL; + eng3d_class = NV40_3D; else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV44TCL; + eng3d_class = NV44_3D; screen->is_nv4x = ~0; break; case 0x60: if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f))) - eng3d_class = NV44TCL; + eng3d_class = NV44_3D; screen->is_nv4x = ~0; break; } @@ -428,17 +461,37 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) return NULL; } - screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE); + screen->advertise_npot = !!screen->is_nv4x; + screen->advertise_blend_equation_separate = !!screen->is_nv4x; + screen->use_nv4x = screen->is_nv4x; + + if(screen->is_nv4x) { + if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE)) + screen->use_nv4x = 0; + if(!debug_get_bool_option("NVFX_NPOT", TRUE)) + screen->advertise_npot = 0; + if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE)) + screen->advertise_blend_equation_separate = 0; + } + + screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE); screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE); screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384); screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0")); screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0")); + /* We don't advertise these by default because filtering and blending doesn't work as + * it should, due to several restrictions. + * The only exception is fp16 on nv40. + */ + screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x); + screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0); + screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen); /* surely both nv3x and nv44 support index buffers too: find out how and test that */ - if(eng3d_class == NV40TCL) + if(eng3d_class == NV40_3D) screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags; if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags) @@ -487,8 +540,8 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) LIST_INITHEAD(&screen->query_list); /* Vtxprog resources */ - if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) || - nouveau_resource_init(&screen->vp_data_heap, 0, 256)) { + if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) || + nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) { nvfx_screen_destroy(pscreen); return NULL; } @@ -497,25 +550,25 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) /* Static eng3d initialisation */ /* note that we just started using the channel, so we must have space in the pushbuffer */ - OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1)); OUT_RING(chan, screen->sync->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1)); OUT_RING(chan, chan->vram->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->vram->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2)); OUT_RING(chan, 0); OUT_RING(chan, screen->query->handle); - OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2)); OUT_RING(chan, chan->vram->handle); OUT_RING(chan, chan->vram->handle); diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h index 1b79235ae0d..b1f07187c78 100644 --- a/src/gallium/drivers/nvfx/nvfx_screen.h +++ b/src/gallium/drivers/nvfx/nvfx_screen.h @@ -15,10 +15,15 @@ struct nvfx_screen { struct nvfx_context *cur_ctx; unsigned is_nv4x; /* either 0 or ~0 */ + unsigned use_nv4x; /* either 0 or ~0 */ boolean force_swtnl; boolean trace_draw; unsigned vertex_buffer_reloc_flags; unsigned index_buffer_reloc_flags; + unsigned advertise_fp16; + unsigned advertise_fp32; + unsigned advertise_npot; + unsigned advertise_blend_equation_separate; /* HW graphics objects */ struct nouveau_grobj *eng3d; diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h index 35006eec3d4..46406b27940 100644 --- a/src/gallium/drivers/nvfx/nvfx_shader.h +++ b/src/gallium/drivers/nvfx/nvfx_shader.h @@ -263,6 +263,7 @@ /* NV40 only fragment program opcodes */ #define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F +#define NVFX_FP_OP_OPCODE_LITEX2_NV40 0x3C /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/ #define NV40_FP_OP_BRA_OPCODE_BRK 0x0 @@ -378,8 +379,9 @@ #define NVFXSR_OUTPUT 1 #define NVFXSR_INPUT 2 #define NVFXSR_TEMP 3 -#define NVFXSR_CONST 4 -#define NVFXSR_RELOCATED 5 +#define NVFXSR_CONST 5 +#define NVFXSR_IMM 6 +#define NVFXSR_RELOCATED 7 #define NVFX_COND_FL 0 #define NVFX_COND_LT 1 @@ -414,14 +416,16 @@ #define abs(s) nvfx_src_abs((s)) struct nvfx_reg { - uint8_t type; + int8_t type; uint32_t index; }; struct nvfx_src { struct nvfx_reg reg; - /* src only */ + uint8_t indirect : 1; + uint8_t indirect_reg : 1; + uint8_t indirect_swz : 2; uint8_t negate : 1; uint8_t abs : 1; uint8_t swz[4]; @@ -483,6 +487,7 @@ nvfx_src(struct nvfx_reg reg) .abs = 0, .negate = 0, .swz = { 0, 1, 2, 3 }, + .indirect = 0, }; return temp; } diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c index 5bd7dc07f02..b767846a99e 100644 --- a/src/gallium/drivers/nvfx/nvfx_state.c +++ b/src/gallium/drivers/nvfx/nvfx_state.c @@ -20,26 +20,26 @@ nvfx_blend_state_create(struct pipe_context *pipe, struct nouveau_statebuf_builder sb = sb_init(bso->sb); if (cso->rt[0].blend_enable) { - sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 3); + sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 3); sb_data(sb, 1); sb_data(sb, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) | nvgl_blend_func(cso->rt[0].rgb_src_factor)); sb_data(sb, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 | nvgl_blend_func(cso->rt[0].rgb_dst_factor)); if(nvfx->screen->base.device->chipset < 0x40) { - sb_method(sb, NV34TCL_BLEND_EQUATION, 1); + sb_method(sb, NV30_3D_BLEND_EQUATION, 1); sb_data(sb, nvgl_blend_eqn(cso->rt[0].rgb_func)); } else { - sb_method(sb, NV40TCL_BLEND_EQUATION, 1); + sb_method(sb, NV40_3D_BLEND_EQUATION, 1); sb_data(sb, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 | nvgl_blend_eqn(cso->rt[0].rgb_func)); } } else { - sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 1); + sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 1); sb_data(sb, 0); } - sb_method(sb, NV34TCL_COLOR_MASK, 1); + sb_method(sb, NV30_3D_COLOR_MASK, 1); sb_data(sb, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) | ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) | ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) | @@ -48,15 +48,15 @@ nvfx_blend_state_create(struct pipe_context *pipe, /* TODO: add NV40 MRT color mask */ if (cso->logicop_enable) { - sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2); + sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 2); sb_data(sb, 1); sb_data(sb, nvgl_logicop_func(cso->logicop_func)); } else { - sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1); + sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 1); sb_data(sb, 0); } - sb_method(sb, NV34TCL_DITHER_ENABLE, 1); + sb_method(sb, NV30_3D_DITHER_ENABLE, 1); sb_data(sb, cso->dither ? 1 : 0); bso->sb_len = sb_len(sb, bso->sb); @@ -94,64 +94,64 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe, * sprite_coord_origin */ - sb_method(sb, NV34TCL_SHADE_MODEL, 1); - sb_data(sb, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT : - NV34TCL_SHADE_MODEL_SMOOTH); + sb_method(sb, NV30_3D_SHADE_MODEL, 1); + sb_data(sb, cso->flatshade ? NV30_3D_SHADE_MODEL_FLAT : + NV30_3D_SHADE_MODEL_SMOOTH); - sb_method(sb, NV34TCL_VERTEX_TWO_SIDE_ENABLE, 1); + sb_method(sb, NV30_3D_VERTEX_TWO_SIDE_ENABLE, 1); sb_data(sb, cso->light_twoside); - sb_method(sb, NV34TCL_LINE_WIDTH, 2); + sb_method(sb, NV30_3D_LINE_WIDTH, 2); sb_data(sb, (unsigned char)(cso->line_width * 8.0) & 0xff); sb_data(sb, cso->line_smooth ? 1 : 0); - sb_method(sb, NV34TCL_LINE_STIPPLE_ENABLE, 2); + sb_method(sb, NV30_3D_LINE_STIPPLE_ENABLE, 2); sb_data(sb, cso->line_stipple_enable ? 1 : 0); sb_data(sb, (cso->line_stipple_pattern << 16) | cso->line_stipple_factor); - sb_method(sb, NV34TCL_POINT_SIZE, 1); + sb_method(sb, NV30_3D_POINT_SIZE, 1); sb_data(sb, fui(cso->point_size)); - sb_method(sb, NV34TCL_POLYGON_MODE_FRONT, 6); + sb_method(sb, NV30_3D_POLYGON_MODE_FRONT, 6); sb_data(sb, nvgl_polygon_mode(cso->fill_front)); sb_data(sb, nvgl_polygon_mode(cso->fill_back)); switch (cso->cull_face) { case PIPE_FACE_FRONT: - sb_data(sb, NV34TCL_CULL_FACE_FRONT); + sb_data(sb, NV30_3D_CULL_FACE_FRONT); break; case PIPE_FACE_BACK: - sb_data(sb, NV34TCL_CULL_FACE_BACK); + sb_data(sb, NV30_3D_CULL_FACE_BACK); break; case PIPE_FACE_FRONT_AND_BACK: - sb_data(sb, NV34TCL_CULL_FACE_FRONT_AND_BACK); + sb_data(sb, NV30_3D_CULL_FACE_FRONT_AND_BACK); break; default: - sb_data(sb, NV34TCL_CULL_FACE_BACK); + sb_data(sb, NV30_3D_CULL_FACE_BACK); break; } if (cso->front_ccw) { - sb_data(sb, NV34TCL_FRONT_FACE_CCW); + sb_data(sb, NV30_3D_FRONT_FACE_CCW); } else { - sb_data(sb, NV34TCL_FRONT_FACE_CW); + sb_data(sb, NV30_3D_FRONT_FACE_CW); } sb_data(sb, cso->poly_smooth ? 1 : 0); sb_data(sb, (cso->cull_face != PIPE_FACE_NONE) ? 1 : 0); - sb_method(sb, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); + sb_method(sb, NV30_3D_POLYGON_STIPPLE_ENABLE, 1); sb_data(sb, cso->poly_stipple_enable ? 1 : 0); - sb_method(sb, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3); + sb_method(sb, NV30_3D_POLYGON_OFFSET_POINT_ENABLE, 3); sb_data(sb, cso->offset_point); sb_data(sb, cso->offset_line); sb_data(sb, cso->offset_tri); if (cso->offset_point || cso->offset_line || cso->offset_tri) { - sb_method(sb, NV34TCL_POLYGON_OFFSET_FACTOR, 2); + sb_method(sb, NV30_3D_POLYGON_OFFSET_FACTOR, 2); sb_data(sb, fui(cso->offset_scale)); sb_data(sb, fui(cso->offset_units * 2)); } - sb_method(sb, NV34TCL_FLATSHADE_FIRST, 1); + sb_method(sb, NV30_3D_FLATSHADE_FIRST, 1); sb_data(sb, cso->flatshade_first); rsso->pipe = *cso; @@ -201,41 +201,41 @@ nvfx_depth_stencil_alpha_state_create(struct pipe_context *pipe, struct nvfx_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso)); struct nouveau_statebuf_builder sb = sb_init(zsaso->sb); - sb_method(sb, NV34TCL_DEPTH_FUNC, 1); + sb_method(sb, NV30_3D_DEPTH_FUNC, 1); sb_data (sb, nvgl_comparison_op(cso->depth.func)); - sb_method(sb, NV34TCL_ALPHA_FUNC_ENABLE, 3); + sb_method(sb, NV30_3D_ALPHA_FUNC_ENABLE, 3); sb_data (sb, cso->alpha.enabled ? 1 : 0); sb_data (sb, nvgl_comparison_op(cso->alpha.func)); sb_data (sb, float_to_ubyte(cso->alpha.ref_value)); if (cso->stencil[0].enabled) { - sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 3); + sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 3); sb_data (sb, cso->stencil[0].enabled ? 1 : 0); sb_data (sb, cso->stencil[0].writemask); sb_data (sb, nvgl_comparison_op(cso->stencil[0].func)); - sb_method(sb, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4); + sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(0), 4); sb_data (sb, cso->stencil[0].valuemask); sb_data (sb, nvgl_stencil_op(cso->stencil[0].fail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[0].zfail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[0].zpass_op)); } else { - sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 1); + sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 1); sb_data (sb, 0); } if (cso->stencil[1].enabled) { - sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 3); + sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 3); sb_data (sb, cso->stencil[1].enabled ? 1 : 0); sb_data (sb, cso->stencil[1].writemask); sb_data (sb, nvgl_comparison_op(cso->stencil[1].func)); - sb_method(sb, NV34TCL_STENCIL_BACK_FUNC_MASK, 4); + sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(1), 4); sb_data (sb, cso->stencil[1].valuemask); sb_data (sb, nvgl_stencil_op(cso->stencil[1].fail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[1].zfail_op)); sb_data (sb, nvgl_stencil_op(cso->stencil[1].zpass_op)); } else { - sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 1); + sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 1); sb_data (sb, 0); } diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h index e9c1f2c26d2..8fafca1950c 100644 --- a/src/gallium/drivers/nvfx/nvfx_state.h +++ b/src/gallium/drivers/nvfx/nvfx_state.h @@ -17,13 +17,8 @@ struct nvfx_vertex_program_data { }; struct nvfx_vertex_program { - struct pipe_shader_state pipe; unsigned long long id; - struct draw_vertex_shader *draw; - - boolean translated; - struct nvfx_vertex_program_exec *insns; unsigned nr_insns; struct nvfx_vertex_program_data *consts; @@ -46,6 +41,20 @@ struct nvfx_vertex_program { struct util_dynarray const_relocs; }; +#define NVFX_VP_FAILED ((struct nvfx_vertex_program*)-1) + +struct nvfx_pipe_vertex_program { + struct pipe_shader_state pipe; + struct tgsi_shader_info info; + + unsigned draw_elements; + boolean draw_no_elements; + struct draw_vertex_shader *draw_vs; + struct nvfx_vertex_program* draw_vp; + + struct nvfx_vertex_program* vp; +}; + struct nvfx_fragment_program_data { unsigned offset; unsigned index; @@ -62,6 +71,7 @@ struct nvfx_fragment_program { unsigned samplers; unsigned point_sprite_control; unsigned or; + unsigned coord_conventions; uint32_t *insn; int insn_len; diff --git a/src/gallium/drivers/nvfx/nvfx_state_blend.c b/src/gallium/drivers/nvfx/nvfx_state_blend.c deleted file mode 100644 index fe34e98364c..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_blend.c +++ /dev/null @@ -1,22 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_blend_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len); -} - -void -nvfx_state_blend_colour_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - struct pipe_blend_color *bcol = &nvfx->blend_colour; - - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_BLEND_COLOR, 1)); - OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) | - (float_to_ubyte(bcol->color[0]) << 16) | - (float_to_ubyte(bcol->color[1]) << 8) | - (float_to_ubyte(bcol->color[2]) << 0))); -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c index 390bca8cdb5..501fdd4430c 100644 --- a/src/gallium/drivers/nvfx/nvfx_state_emit.c +++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c @@ -3,13 +3,191 @@ #include "nvfx_resource.h" #include "draw/draw_context.h" +void +nvfx_state_viewport_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + struct pipe_viewport_state *vpt = &nvfx->viewport; + + WAIT_RING(chan, 11); + if(nvfx->render_mode == HW) { + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8)); + OUT_RINGf(chan, vpt->translate[0]); + OUT_RINGf(chan, vpt->translate[1]); + OUT_RINGf(chan, vpt->translate[2]); + OUT_RINGf(chan, vpt->translate[3]); + OUT_RINGf(chan, vpt->scale[0]); + OUT_RINGf(chan, vpt->scale[1]); + OUT_RINGf(chan, vpt->scale[2]); + OUT_RINGf(chan, vpt->scale[3]); + OUT_RING(chan, RING_3D(0x1d78, 1)); + OUT_RING(chan, 1); + } else { + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8)); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 0.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RINGf(chan, 1.0f); + OUT_RING(chan, RING_3D(0x1d78, 1)); + OUT_RING(chan, nvfx->is_nv4x ? 0x110 : 1); + } +} + +void +nvfx_state_scissor_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe; + struct pipe_scissor_state *s = &nvfx->scissor; + + if ((rast->scissor == 0 && nvfx->state.scissor_enabled == 0)) + return; + nvfx->state.scissor_enabled = rast->scissor; + + WAIT_RING(chan, 3); + OUT_RING(chan, RING_3D(NV30_3D_SCISSOR_HORIZ, 2)); + if (nvfx->state.scissor_enabled) { + OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx); + OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny); + } else { + OUT_RING(chan, 4096 << 16); + OUT_RING(chan, 4096 << 16); + } +} + +void +nvfx_state_sr_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + struct pipe_stencil_ref *sr = &nvfx->stencil_ref; + + WAIT_RING(chan, 4); + OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(0), 1)); + OUT_RING(chan, sr->ref_value[0]); + OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(1), 1)); + OUT_RING(chan, sr->ref_value[1]); +} + +void +nvfx_state_blend_colour_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + struct pipe_blend_color *bcol = &nvfx->blend_colour; + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_BLEND_COLOR, 1)); + OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) | + (float_to_ubyte(bcol->color[0]) << 16) | + (float_to_ubyte(bcol->color[1]) << 8) | + (float_to_ubyte(bcol->color[2]) << 0))); +} + +void +nvfx_state_stipple_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel *chan = nvfx->screen->base.channel; + + WAIT_RING(chan, 33); + OUT_RING(chan, RING_3D(NV30_3D_POLYGON_STIPPLE_PATTERN(0), 32)); + OUT_RINGp(chan, nvfx->stipple, 32); +} + +static void +nvfx_coord_conventions_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned value = nvfx->hw_fragprog->coord_conventions; + if(value & NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED) + value |= nvfx->framebuffer.height << NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT; + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_COORD_CONVENTIONS, 1)); + OUT_RING(chan, value); +} + +static void +nvfx_ucp_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned enables[7] = + { + 0, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4, + NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5, + }; + + if(!nvfx->use_vp_clipping) + { + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1)); + OUT_RING(chan, 0); + + WAIT_RING(chan, 6 * 4 + 1); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANE(0, 0), nvfx->clip.nr * 4)); + OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4); + } + + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1)); + OUT_RING(chan, enables[nvfx->clip.nr]); +} + +static void +nvfx_vertprog_ucp_validate(struct nvfx_context* nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned i; + struct nvfx_vertex_program* vp = nvfx->hw_vertprog; + if(nvfx->clip.nr != vp->clip_nr) + { + unsigned idx; + WAIT_RING(chan, 14); + + /* remove last instruction bit */ + if(vp->clip_nr >= 0) + { + idx = vp->nr_insns - 7 + vp->clip_nr; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start + idx); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + OUT_RINGp (chan, vp->insns[idx].data, 4); + } + + /* set last instruction bit */ + idx = vp->nr_insns - 7 + nvfx->clip.nr; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start + idx); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + OUT_RINGp(chan, vp->insns[idx].data, 3); + OUT_RING(chan, vp->insns[idx].data[3] | 1); + vp->clip_nr = nvfx->clip.nr; + } + + // TODO: only do this for the ones changed + WAIT_RING(chan, 6 * 6); + for(i = 0; i < nvfx->clip.nr; ++i) + { + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, vp->data->start + i); + OUT_RINGp (chan, nvfx->clip.ucp[i], 4); + } +} + static boolean nvfx_state_validate_common(struct nvfx_context *nvfx) { struct nouveau_channel* chan = nvfx->screen->base.channel; unsigned dirty; unsigned still_dirty = 0; - int all_swizzled = -1; + int new_fb_mode = -1; /* 1 = all swizzled, 0 = make all linear */ boolean flush_tex_cache = FALSE; unsigned render_temps; @@ -41,10 +219,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->dirty & NVFX_NEW_FB) { nvfx->dirty &=~ NVFX_NEW_FB; - all_swizzled = nvfx_framebuffer_prepare(nvfx); + new_fb_mode = nvfx_framebuffer_prepare(nvfx); // TODO: make sure this doesn't happen, i.e. fbs have matching formats - assert(all_swizzled >= 0); + assert(new_fb_mode >= 0); } } @@ -52,7 +230,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->render_mode == HW) { - if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_VERTCONST | NVFX_NEW_UCP)) + if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_VERTCONST)) { if(!nvfx_vertprog_validate(nvfx)) return FALSE; @@ -74,12 +252,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) } else { - /* TODO: this looks a bit misdesigned */ - if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP)) - nvfx_vertprog_validate(nvfx); - - if(dirty & (NVFX_NEW_ARRAYS | NVFX_NEW_INDEX | NVFX_NEW_FRAGPROG)) - nvfx_vtxfmt_validate(nvfx); + if(dirty & NVFX_NEW_VERTPROG) { + assert(nvfx_vertprog_validate(nvfx)); + nvfx_vbo_swtnl_validate(nvfx); + } } if(dirty & NVFX_NEW_RAST) @@ -92,72 +268,10 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) nvfx_state_stipple_validate(nvfx); if(nvfx->dirty & NVFX_NEW_UCP) - { - unsigned enables[7] = - { - 0, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4, - NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5, - }; - - if(!nvfx->use_vp_clipping) - { - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1)); - OUT_RING(chan, 0); - - WAIT_RING(chan, 6 * 4 + 1); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANE_A(0), nvfx->clip.nr * 4)); - OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4); - } - - WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1)); - OUT_RING(chan, enables[nvfx->clip.nr]); - } + nvfx_ucp_validate(nvfx); if(nvfx->use_vp_clipping && (nvfx->dirty & (NVFX_NEW_UCP | NVFX_NEW_VERTPROG))) - { - unsigned i; - struct nvfx_vertex_program* vp = nvfx->vertprog; - if(nvfx->clip.nr != vp->clip_nr) - { - unsigned idx; - WAIT_RING(chan, 14); - - /* remove last instruction bit */ - if(vp->clip_nr >= 0) - { - idx = vp->nr_insns - 7 + vp->clip_nr; - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1)); - OUT_RING(chan, vp->exec->start + idx); - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4)); - OUT_RINGp (chan, vp->insns[idx].data, 4); - } - - /* set last instruction bit */ - idx = vp->nr_insns - 7 + nvfx->clip.nr; - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1)); - OUT_RING(chan, vp->exec->start + idx); - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4)); - OUT_RINGp(chan, vp->insns[idx].data, 3); - OUT_RING(chan, vp->insns[idx].data[3] | 1); - vp->clip_nr = nvfx->clip.nr; - } - - // TODO: only do this for the ones changed - WAIT_RING(chan, 6 * 6); - for(i = 0; i < nvfx->clip.nr; ++i) - { - OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5)); - OUT_RING(chan, vp->data->start + i); - OUT_RINGp (chan, nvfx->clip.ucp[i], 4); - } - } + nvfx_vertprog_ucp_validate(nvfx); if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST | NVFX_NEW_VERTPROG | NVFX_NEW_SPRITE)) { @@ -168,20 +282,20 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) if(nvfx->is_nv4x) { - unsigned vp_output = nvfx->vertprog->or | nvfx->hw_fragprog->or; + unsigned vp_output = nvfx->hw_vertprog->or | nvfx->hw_fragprog->or; vp_output |= (1 << (nvfx->clip.nr + 6)) - (1 << 6); if(vp_output != nvfx->hw_vp_output) { WAIT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1)); + OUT_RING(chan, RING_3D(NV40_3D_VP_RESULT_EN, 1)); OUT_RING(chan, vp_output); nvfx->hw_vp_output = vp_output; } } - if(all_swizzled >= 0) - nvfx_framebuffer_validate(nvfx, all_swizzled); + if(new_fb_mode >= 0) + nvfx_framebuffer_validate(nvfx, new_fb_mode); if(dirty & NVFX_NEW_BLEND) sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len); @@ -199,28 +313,31 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) etracer, neverball, foobillard, glest totally misrender TODO: find the right fix */ - if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (all_swizzled >= 0)) + if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (new_fb_mode >= 0)) { nvfx_state_viewport_validate(nvfx); } - if(dirty & NVFX_NEW_ZSA || (all_swizzled >= 0)) + if(dirty & NVFX_NEW_ZSA || (new_fb_mode >= 0)) { WAIT_RING(chan, 3); - OUT_RING(chan, RING_3D(NV34TCL_DEPTH_WRITE_ENABLE, 2)); + OUT_RING(chan, RING_3D(NV30_3D_DEPTH_WRITE_ENABLE, 2)); OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.writemask); OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.enabled); } + if((new_fb_mode >= 0) || (dirty & NVFX_NEW_FRAGPROG)) + nvfx_coord_conventions_validate(nvfx); + if(flush_tex_cache) { // TODO: what about nv30? if(nvfx->is_nv4x) { WAIT_RING(chan, 4); - OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1)); OUT_RING(chan, 2); - OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1)); + OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1)); OUT_RING(chan, 1); } } @@ -232,14 +349,18 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) { for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i) { - if(render_temps & (1 << i)) + if(render_temps & (1 << i)) { + assert(((struct nvfx_surface*)nvfx->framebuffer.cbufs[i])->temp); util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.cbufs[i]), (struct util_dirty_surface*)nvfx->framebuffer.cbufs[i]); + } } - if(render_temps & 0x80) + if(render_temps & 0x80) { + assert(((struct nvfx_surface*)nvfx->framebuffer.zsbuf)->temp); util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.zsbuf), (struct util_dirty_surface*)nvfx->framebuffer.zsbuf); + } } return TRUE; @@ -276,8 +397,6 @@ nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs) boolean nvfx_state_validate(struct nvfx_context *nvfx) { - boolean was_sw = nvfx->fallback_swtnl ? TRUE : FALSE; - if (nvfx->render_mode != HW) { /* Don't even bother trying to go back to hw if none * of the states that caused swtnl previously have changed. @@ -296,9 +415,6 @@ nvfx_state_validate(struct nvfx_context *nvfx) if(!nvfx_state_validate_common(nvfx)) return FALSE; - if (was_sw) - NOUVEAU_ERR("swtnl->hw\n"); - return TRUE; } @@ -309,7 +425,11 @@ nvfx_state_validate_swtnl(struct nvfx_context *nvfx) /* Setup for swtnl */ if (nvfx->render_mode == HW) { - NOUVEAU_ERR("hw->swtnl 0x%08x\n", nvfx->fallback_swtnl); + static boolean warned = FALSE; + if(!warned) { + NOUVEAU_ERR("hw->swtnl 0x%08x\n", nvfx->fallback_swtnl); + warned = TRUE; + } nvfx->pipe.flush(&nvfx->pipe, 0, NULL); nvfx->dirty |= (NVFX_NEW_VIEWPORT | NVFX_NEW_VERTPROG | @@ -317,8 +437,11 @@ nvfx_state_validate_swtnl(struct nvfx_context *nvfx) nvfx->render_mode = SWTNL; } - if (nvfx->draw_dirty & NVFX_NEW_VERTPROG) - draw_bind_vertex_shader(draw, nvfx->vertprog->draw); + if (nvfx->draw_dirty & NVFX_NEW_VERTPROG) { + if(!nvfx->vertprog->draw_vs) + nvfx->vertprog->draw_vs = draw_create_vertex_shader(draw, &nvfx->vertprog->pipe); + draw_bind_vertex_shader(draw, nvfx->vertprog->draw_vs); + } if (nvfx->draw_dirty & NVFX_NEW_RAST) draw_set_rasterizer_state(draw, &nvfx->rasterizer->pipe, diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c index 3b869d43a15..4ffc4de4520 100644 --- a/src/gallium/drivers/nvfx/nvfx_state_fb.c +++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c @@ -5,6 +5,7 @@ static inline boolean nvfx_surface_linear_renderable(struct pipe_surface* surf) { + /* TODO: precompute this in nvfx_surface creation */ return (surf->texture->flags & NVFX_RESOURCE_FLAG_LINEAR) && !(surf->offset & 63) && !(((struct nvfx_surface*)surf)->pitch & 63); @@ -13,13 +14,14 @@ nvfx_surface_linear_renderable(struct pipe_surface* surf) static inline boolean nvfx_surface_swizzled_renderable(struct pipe_framebuffer_state* fb, struct pipe_surface* surf) { - /* TODO: return FALSE if we have a format not supporting swizzled rendering (e.g. r8); currently those are not supported at all */ + /* TODO: precompute this in nvfx_surface creation */ return !((struct nvfx_miptree*)surf->texture)->linear_pitch && (surf->texture->target != PIPE_TEXTURE_3D || u_minify(surf->texture->depth0, surf->level) <= 1) && !(surf->offset & 127) && (surf->width == fb->width) && (surf->height == fb->height) - && !((struct nvfx_surface*)surf)->temp; + && !((struct nvfx_surface*)surf)->temp + && (surf->format == PIPE_FORMAT_B8G8R8A8_UNORM || surf->format == PIPE_FORMAT_B8G8R8X8_UNORM || surf->format == PIPE_FORMAT_B5G6R5_UNORM); } static boolean @@ -100,10 +102,10 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) unsigned w = fb->width; unsigned h = fb->height; - rt_enable = (NV34TCL_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1; - if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 | - NV40TCL_RT_ENABLE_COLOR2 | NV40TCL_RT_ENABLE_COLOR3)) - rt_enable |= NV34TCL_RT_ENABLE_MRT; + rt_enable = (NV30_3D_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1; + if (rt_enable & (NV30_3D_RT_ENABLE_COLOR1 | + NV40_3D_RT_ENABLE_COLOR2 | NV40_3D_RT_ENABLE_COLOR3)) + rt_enable |= NV30_3D_RT_ENABLE_MRT; nvfx->state.render_temps = 0; @@ -123,55 +125,63 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) if (prepare_result) { assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1))); - rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED | - (util_logbase2(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) | - (util_logbase2(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT); + rt_format = NV30_3D_RT_FORMAT_TYPE_SWIZZLED | + (util_logbase2(fb->width) << NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT) | + (util_logbase2(fb->height) << NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT); } else - rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR; + rt_format = NV30_3D_RT_FORMAT_TYPE_LINEAR; if(fb->nr_cbufs > 0) { switch (fb->cbufs[0]->format) { case PIPE_FORMAT_B8G8R8X8_UNORM: - rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_X8R8G8B8; break; case PIPE_FORMAT_B8G8R8A8_UNORM: case 0: - rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8; break; case PIPE_FORMAT_B5G6R5_UNORM: - rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5; + break; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + rt_format |= NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT; + break; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + rt_format |= NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT; break; default: assert(0); } } else if(fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) == 2) - rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5; else - rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8; if(fb->zsbuf) { switch (fb->zsbuf->format) { case PIPE_FORMAT_Z16_UNORM: - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16; break; case PIPE_FORMAT_S8_USCALED_Z24_UNORM: case PIPE_FORMAT_X8Z24_UNORM: case 0: - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8; break; default: assert(0); } } else if(fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) == 2) - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16; else - rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8; + rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8; + + MARK_RING(chan, 42, 10); - if ((rt_enable & NV34TCL_RT_ENABLE_COLOR0) || fb->zsbuf) { + if ((rt_enable & NV30_3D_RT_ENABLE_COLOR0) || fb->zsbuf) { struct nvfx_render_target *rt0 = &nvfx->hw_rt[0]; uint32_t pitch; - if(!(rt_enable & NV34TCL_RT_ENABLE_COLOR0)) + if(!(rt_enable & NV30_3D_RT_ENABLE_COLOR0)) rt0 = &nvfx->hw_zeta; pitch = rt0->pitch; @@ -186,23 +196,23 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) //printf("rendering to bo %p [%i] at offset %i with pitch %i\n", rt0->bo, rt0->bo->handle, rt0->offset, pitch); - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 1)); OUT_RELOC(chan, rt0->bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_COLOR0_PITCH, 2)); + OUT_RING(chan, RING_3D(NV30_3D_COLOR0_PITCH, 2)); OUT_RING(chan, pitch); OUT_RELOC(chan, rt0->bo, rt0->offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); } - if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) { - OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1)); + if (rt_enable & NV30_3D_RT_ENABLE_COLOR1) { + OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1)); OUT_RELOC(chan, nvfx->hw_rt[1].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_COLOR1_OFFSET, 2)); + OUT_RING(chan, RING_3D(NV30_3D_COLOR1_OFFSET, 2)); OUT_RELOC(chan, nvfx->hw_rt[1].bo, nvfx->hw_rt[1].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); @@ -211,71 +221,69 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result) if(nvfx->is_nv4x) { - if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) { - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 1)); + if (rt_enable & NV40_3D_RT_ENABLE_COLOR2) { + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 1)); OUT_RELOC(chan, nvfx->hw_rt[2].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV40TCL_COLOR2_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR2_OFFSET, 1)); OUT_RELOC(chan, nvfx->hw_rt[2].bo, nvfx->hw_rt[2].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - OUT_RING(chan, RING_3D(NV40TCL_COLOR2_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR2_PITCH, 1)); OUT_RING(chan, nvfx->hw_rt[2].pitch); } - if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) { - OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR3, 1)); + if (rt_enable & NV40_3D_RT_ENABLE_COLOR3) { + OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR3, 1)); OUT_RELOC(chan, nvfx->hw_rt[3].bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV40TCL_COLOR3_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR3_OFFSET, 1)); OUT_RELOC(chan, nvfx->hw_rt[3].bo, nvfx->hw_rt[3].offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - OUT_RING(chan, RING_3D(NV40TCL_COLOR3_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_COLOR3_PITCH, 1)); OUT_RING(chan, nvfx->hw_rt[3].pitch); } } if (fb->zsbuf) { - OUT_RING(chan, RING_3D(NV34TCL_DMA_ZETA, 1)); + OUT_RING(chan, RING_3D(NV30_3D_DMA_ZETA, 1)); OUT_RELOC(chan, nvfx->hw_zeta.bo, 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - OUT_RING(chan, RING_3D(NV34TCL_ZETA_OFFSET, 1)); + OUT_RING(chan, RING_3D(NV30_3D_ZETA_OFFSET, 1)); /* TODO: reverse engineer LMA */ OUT_RELOC(chan, nvfx->hw_zeta.bo, nvfx->hw_zeta.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1)); OUT_RING(chan, nvfx->hw_zeta.pitch); } } else if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1)); + OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1)); OUT_RING(chan, 64); } - OUT_RING(chan, RING_3D(NV34TCL_RT_ENABLE, 1)); + OUT_RING(chan, RING_3D(NV30_3D_RT_ENABLE, 1)); OUT_RING(chan, rt_enable); - OUT_RING(chan, RING_3D(NV34TCL_RT_HORIZ, 3)); + OUT_RING(chan, RING_3D(NV30_3D_RT_HORIZ, 3)); OUT_RING(chan, (w << 16) | 0); OUT_RING(chan, (h << 16) | 0); OUT_RING(chan, rt_format); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_HORIZ, 2)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_HORIZ, 2)); OUT_RING(chan, (w << 16) | 0); OUT_RING(chan, (h << 16) | 0); - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(0), 2)); OUT_RING(chan, ((w - 1) << 16) | 0); OUT_RING(chan, ((h - 1) << 16) | 0); - OUT_RING(chan, RING_3D(0x1d88, 1)); - OUT_RING(chan, (1 << 12) | h); if(!nvfx->is_nv4x) { /* Wonder why this is needed, context should all be set to zero on init */ /* TODO: we can most likely remove this, after putting it in context init */ - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TX_ORIGIN, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TX_ORIGIN, 1)); OUT_RING(chan, 0); } nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER; @@ -291,22 +299,22 @@ nvfx_framebuffer_relocate(struct nvfx_context *nvfx) #define DO_(var, pfx, name) \ if(var.bo) { \ - OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_DMA_##name, 1), rt_flags, 0, 0); \ + OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_DMA_##name, 1), rt_flags, 0, 0); \ OUT_RELOC(chan, var.bo, 0, \ rt_flags | NOUVEAU_BO_OR, \ chan->vram->handle, chan->gart->handle); \ - OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_##name##_OFFSET, 1), rt_flags, 0, 0); \ + OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_##name##_OFFSET, 1), rt_flags, 0, 0); \ OUT_RELOC(chan, var.bo, \ var.offset, rt_flags | NOUVEAU_BO_LOW, \ 0, 0); \ } #define DO(pfx, num) DO_(nvfx->hw_rt[num], pfx, COLOR##num) - DO(NV34, 0); - DO(NV34, 1); + DO(NV30, 0); + DO(NV30, 1); DO(NV40, 2); DO(NV40, 3); - DO_(nvfx->hw_zeta, NV34, ZETA); + DO_(nvfx->hw_zeta, NV30, ZETA); nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER; } diff --git a/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c b/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c deleted file mode 100644 index 7f14ae85d5a..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_rasterizer.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_rasterizer_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->rasterizer->sb, nvfx->rasterizer->sb_len); -} - diff --git a/src/gallium/drivers/nvfx/nvfx_state_scissor.c b/src/gallium/drivers/nvfx/nvfx_state_scissor.c deleted file mode 100644 index 9077266120a..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_scissor.c +++ /dev/null @@ -1,23 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_scissor_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe; - struct pipe_scissor_state *s = &nvfx->scissor; - - if ((rast->scissor == 0 && nvfx->state.scissor_enabled == 0)) - return; - nvfx->state.scissor_enabled = rast->scissor; - - WAIT_RING(chan, 3); - OUT_RING(chan, RING_3D(NV34TCL_SCISSOR_HORIZ, 2)); - if (nvfx->state.scissor_enabled) { - OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx); - OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny); - } else { - OUT_RING(chan, 4096 << 16); - OUT_RING(chan, 4096 << 16); - } -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_stipple.c b/src/gallium/drivers/nvfx/nvfx_state_stipple.c deleted file mode 100644 index b76e9dd3824..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_stipple.c +++ /dev/null @@ -1,11 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_stipple_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - - WAIT_RING(chan, 33); - OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32)); - OUT_RINGp(chan, nvfx->stipple, 32); -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_viewport.c b/src/gallium/drivers/nvfx/nvfx_state_viewport.c deleted file mode 100644 index e983b16f321..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_viewport.c +++ /dev/null @@ -1,35 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_viewport_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel *chan = nvfx->screen->base.channel; - struct pipe_viewport_state *vpt = &nvfx->viewport; - - WAIT_RING(chan, 11); - if(nvfx->render_mode == HW) { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8)); - OUT_RINGf(chan, vpt->translate[0]); - OUT_RINGf(chan, vpt->translate[1]); - OUT_RINGf(chan, vpt->translate[2]); - OUT_RINGf(chan, vpt->translate[3]); - OUT_RINGf(chan, vpt->scale[0]); - OUT_RINGf(chan, vpt->scale[1]); - OUT_RINGf(chan, vpt->scale[2]); - OUT_RINGf(chan, vpt->scale[3]); - OUT_RING(chan, RING_3D(0x1d78, 1)); - OUT_RING(chan, 1); - } else { - OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8)); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 0.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RINGf(chan, 1.0f); - OUT_RING(chan, RING_3D(0x1d78, 1)); - OUT_RING(chan, nvfx->is_nv4x ? 0x110 : 1); - } -} diff --git a/src/gallium/drivers/nvfx/nvfx_state_zsa.c b/src/gallium/drivers/nvfx/nvfx_state_zsa.c deleted file mode 100644 index 608605d32bd..00000000000 --- a/src/gallium/drivers/nvfx/nvfx_state_zsa.c +++ /dev/null @@ -1,21 +0,0 @@ -#include "nvfx_context.h" - -void -nvfx_state_zsa_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - sb_emit(chan, nvfx->zsa->sb, nvfx->zsa->sb_len); -} - -void -nvfx_state_sr_validate(struct nvfx_context *nvfx) -{ - struct nouveau_channel* chan = nvfx->screen->base.channel; - struct pipe_stencil_ref *sr = &nvfx->stencil_ref; - - WAIT_RING(chan, 4); - OUT_RING(chan, RING_3D(NV34TCL_STENCIL_FRONT_FUNC_REF, 1)); - OUT_RING(chan, sr->ref_value[0]); - OUT_RING(chan, RING_3D(NV34TCL_STENCIL_BACK_FUNC_REF, 1)); - OUT_RING(chan, sr->ref_value[1]); -} diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c index a5931b6e152..70adebc1be5 100644 --- a/src/gallium/drivers/nvfx/nvfx_surface.c +++ b/src/gallium/drivers/nvfx/nvfx_surface.c @@ -47,6 +47,9 @@ static INLINE void nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format) { unsigned bits = util_format_get_blocksizebits(format); + unsigned shift = 0; + rgn->one_bits = 0; + switch(bits) { case 8: @@ -54,43 +57,28 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format) break; case 16: rgn->bpps = 1; + if(format == PIPE_FORMAT_B5G5R5X1_UNORM) + rgn->one_bits = 1; break; case 32: rgn->bpps = 2; + if(format == PIPE_FORMAT_R8G8B8X8_UNORM || format == PIPE_FORMAT_B8G8R8X8_UNORM) + rgn->one_bits = 8; + break; + case 64: + rgn->bpps = 2; + shift = 1; + break; + case 128: + rgn->bpps = 2; + shift = 2; break; - default: - { - int shift; - assert(util_is_power_of_two(bits)); - shift = util_logbase2(bits) - 3; - assert(shift >= 2); - rgn->bpps = 2; - shift -= 2; - - rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; - rgn->y = util_format_get_nblocksy(format, rgn->y); - } } -} -static INLINE void -nvfx_region_fixup_swizzled(struct nv04_region* rgn, unsigned zslice, unsigned width, unsigned height, unsigned depth) -{ - // TODO: move this code to surface creation? - if((depth <= 1) && (height <= 1 || width <= 2)) - rgn->pitch = width << rgn->bpps; - else if(depth > 1 && height <= 2 && width <= 2) - { - rgn->pitch = width << rgn->bpps; - rgn->offset += (zslice * width * height) << rgn->bpps; - } - else - { - rgn->pitch = 0; - rgn->z = zslice; - rgn->w = width; - rgn->h = height; - rgn->d = depth; + if(shift) { + rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; + rgn->y = util_format_get_nblocksy(format, rgn->y); + rgn->w <<= shift; } } @@ -100,7 +88,6 @@ nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, rgn->x = x; rgn->y = y; rgn->z = 0; - nvfx_region_set_format(rgn, surf->base.base.format); if(surf->temp) { @@ -113,11 +100,22 @@ nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, } else { rgn->bo = ((struct nvfx_resource*)surf->base.base.texture)->bo; rgn->offset = surf->base.base.offset; - rgn->pitch = surf->pitch; - if(!(surf->base.base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR)) - nvfx_region_fixup_swizzled(rgn, surf->base.base.zslice, surf->base.base.width, surf->base.base.height, u_minify(surf->base.base.texture->depth0, surf->base.base.level)); + if(surf->base.base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR) + rgn->pitch = surf->pitch; + else + { + rgn->pitch = 0; + rgn->z = surf->base.base.zslice; + rgn->w = surf->base.base.width; + rgn->h = surf->base.base.height; + rgn->d = u_minify(surf->base.base.texture->depth0, surf->base.base.level); + } } + + nvfx_region_set_format(rgn, surf->base.base.format); + if(!rgn->pitch) + nv04_region_try_to_linearize(rgn); } static INLINE void @@ -135,67 +133,50 @@ nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* rgn->bo = ((struct nvfx_resource*)pt)->bo; rgn->offset = nvfx_subresource_offset(pt, sub.face, sub.level, z); - rgn->pitch = nvfx_subresource_pitch(pt, sub.level); rgn->x = x; rgn->y = y; - rgn->z = 0; - nvfx_region_set_format(rgn, pt->format); - if(!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR)) - nvfx_region_fixup_swizzled(rgn, z, u_minify(pt->width0, sub.level), u_minify(pt->height0, sub.level), u_minify(pt->depth0, sub.level)); -} - -// TODO: actually test this for all formats, it's probably wrong for some... - -static INLINE int -nvfx_surface_format(enum pipe_format format) -{ - switch(util_format_get_blocksize(format)) { - case 1: - return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8; - case 2: - //return NV04_CONTEXT_SURFACES_2D_FORMAT_Y16; - return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5; - case 4: - //if(format == PIPE_FORMAT_B8G8R8X8_UNORM || format == PIPE_FORMAT_B8G8R8A8_UNORM) - return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8; - //else - // return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32; - default: - return -1; + if(pt->flags & NVFX_RESOURCE_FLAG_LINEAR) + { + rgn->pitch = nvfx_subresource_pitch(pt, sub.level); + rgn->z = 0; } -} - -static INLINE int -nv04_scaled_image_format(enum pipe_format format) -{ - switch(util_format_get_blocksize(format)) { - case 1: - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8; - case 2: - //if(format == PIPE_FORMAT_B5G5R5A1_UNORM) - // return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5; - //else - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5; - case 4: - if(format == PIPE_FORMAT_B8G8R8X8_UNORM) - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8; - else - return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8; - default: - return -1; + else + { + rgn->pitch = 0; + rgn->z = z; + rgn->w = u_minify(pt->width0, sub.level); + rgn->h = u_minify(pt->height0, sub.level); + rgn->d = u_minify(pt->depth0, sub.level); } + + nvfx_region_set_format(rgn, pt->format); + if(!rgn->pitch) + nv04_region_try_to_linearize(rgn); } -// XXX: must save index buffer too! +// don't save index buffer because blitter doesn't setit static struct blitter_context* nvfx_get_blitter(struct pipe_context* pipe, int copy) { struct nvfx_context* nvfx = nvfx_context(pipe); + struct blitter_context** pblitter; + struct blitter_context* blitter; + + assert(nvfx->blitters_in_use < Elements(nvfx->blitter)); - struct blitter_context* blitter = nvfx->blitter; - if(!blitter) - nvfx->blitter = blitter = util_blitter_create(pipe); + if(nvfx->query && !nvfx->blitters_in_use) + { + struct nouveau_channel* chan = nvfx->screen->base.channel; + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 0); + } + + pblitter = &nvfx->blitter[nvfx->blitters_in_use++]; + if(!*pblitter) + *pblitter = util_blitter_create(pipe); + blitter = *pblitter; util_blitter_save_blend(blitter, nvfx->blend); util_blitter_save_depth_stencil_alpha(blitter, nvfx->zsa); @@ -218,6 +199,22 @@ nvfx_get_blitter(struct pipe_context* pipe, int copy) return blitter; } +static inline void +nvfx_put_blitter(struct pipe_context* pipe, struct blitter_context* blitter) +{ + struct nvfx_context* nvfx = nvfx_context(pipe); + --nvfx->blitters_in_use; + assert(nvfx->blitters_in_use >= 0); + + if(nvfx->query && !nvfx->blitters_in_use) + { + struct nouveau_channel* chan = nvfx->screen->base.channel; + WAIT_RING(chan, 2); + OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1)); + OUT_RING(chan, 1); + } +} + static unsigned nvfx_region_clone(struct nv04_2d_context* ctx, struct nv04_region* rgn, unsigned w, unsigned h, boolean for_read) { @@ -269,16 +266,21 @@ nvfx_resource_copy_region(struct pipe_context *pipe, if((!dst_to_gpu || !src_on_gpu) && small) ret = -1; /* use the CPU */ else - ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, - dstr->target == PIPE_BUFFER ? -1 : nvfx_surface_format(dstr->format), - dstr->target == PIPE_BUFFER ? -1 : nv04_scaled_image_format(dstr->format), - dst_to_gpu, src_on_gpu); + ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, dst_to_gpu, src_on_gpu); if(!ret) {} - else if(ret > 0 && dstr->bind & PIPE_BIND_RENDER_TARGET && srcr->bind & PIPE_BIND_SAMPLER_VIEW) + else if(ret > 0 + && dstr->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL) + && srcr->bind & PIPE_BIND_SAMPLER_VIEW) { + /* this currently works because we hack the bind flags on resource creation to be + * the maximum set that the resource type actually supports + * + * TODO: perhaps support reinterpreting the formats + */ struct blitter_context* blitter = nvfx_get_blitter(pipe, 1); util_blitter_copy_region(blitter, dstr, subdst, dstx, dsty, dstz, srcr, subsrc, srcx, srcy, srcz, w, h, TRUE); + nvfx_put_blitter(pipe, blitter); } else { @@ -371,11 +373,19 @@ nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int struct nvfx_surface* ns = (struct nvfx_surface*)surf; struct pipe_subresource tempsr, surfsr; struct nvfx_context* nvfx = nvfx_context(pipe); + struct nvfx_miptree* temp; + unsigned use_vertex_buffers; + boolean use_index_buffer; + unsigned base_vertex; + + /* temporarily detach the temp, so it isn't used in place of the actual resource */ + temp = ns->temp; + ns->temp = 0; // TODO: we really should do this validation before setting these variable in draw calls - unsigned use_vertex_buffers = nvfx->use_vertex_buffers; - boolean use_index_buffer = nvfx->use_index_buffer; - unsigned base_vertex = nvfx->base_vertex; + use_vertex_buffers = nvfx->use_vertex_buffers; + use_index_buffer = nvfx->use_index_buffer; + base_vertex = nvfx->base_vertex; tempsr.face = 0; tempsr.level = 0; @@ -383,9 +393,16 @@ nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int surfsr.level = surf->level; if(to_temp) - nvfx_resource_copy_region(pipe, &ns->temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height); + nvfx_resource_copy_region(pipe, &temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height); else - nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &ns->temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height); + nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height); + + /* If this triggers, it probably means we attempted to use the blitter + * but failed due to non-renderability of the target. + * Obviously, this would lead to infinite recursion if supported. */ + assert(!ns->temp); + + ns->temp = temp; nvfx->use_vertex_buffers = use_vertex_buffers; nvfx->use_index_buffer = use_index_buffer; @@ -409,6 +426,8 @@ nvfx_surface_create_temp(struct pipe_context* pipe, struct pipe_surface* surf) template.nr_samples = surf->texture->nr_samples; template.flags = NVFX_RESOURCE_FLAG_LINEAR; + assert(!ns->temp && !util_dirty_surface_is_dirty(&ns->base)); + ns->temp = (struct nvfx_miptree*)nvfx_miptree_create(pipe->screen, &template); nvfx_surface_copy_temp(pipe, surf, 1); } @@ -420,11 +439,10 @@ nvfx_surface_flush(struct pipe_context* pipe, struct pipe_surface* surf) struct nvfx_surface* ns = (struct nvfx_surface*)surf; boolean bound = FALSE; - /* must be done before the copy, otherwise the copy will use the temp as destination */ - util_dirty_surface_set_clean(nvfx_surface_get_dirty_surfaces(surf), &ns->base); - nvfx_surface_copy_temp(pipe, surf, 0); + util_dirty_surface_set_clean(nvfx_surface_get_dirty_surfaces(surf), &ns->base); + if(nvfx->framebuffer.zsbuf == surf) bound = TRUE; else @@ -459,6 +477,7 @@ nvfx_clear_render_target(struct pipe_context *pipe, // TODO: probably should use hardware clear here instead if possible struct blitter_context* blitter = nvfx_get_blitter(pipe, 0); util_blitter_clear_render_target(blitter, dst, rgba, dstx, dsty, width, height); + nvfx_put_blitter(pipe, blitter); } } @@ -477,6 +496,7 @@ nvfx_clear_depth_stencil(struct pipe_context *pipe, // TODO: probably should use hardware clear here instead if possible struct blitter_context* blitter = nvfx_get_blitter(pipe, 0); util_blitter_clear_depth_stencil(blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height); + nvfx_put_blitter(pipe, blitter); } } diff --git a/src/gallium/drivers/nvfx/nvfx_surface.h b/src/gallium/drivers/nvfx/nvfx_surface.h new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/src/gallium/drivers/nvfx/nvfx_surface.h diff --git a/src/gallium/drivers/nvfx/nvfx_tex.h b/src/gallium/drivers/nvfx/nvfx_tex.h index 34be936a891..2f2d7378085 100644 --- a/src/gallium/drivers/nvfx/nvfx_tex.h +++ b/src/gallium/drivers/nvfx/nvfx_tex.h @@ -4,7 +4,7 @@ #include "util/u_math.h" #include "pipe/p_defines.h" #include "pipe/p_state.h" -#include <nouveau/nouveau_class.h> + static inline unsigned nvfx_tex_wrap_mode(unsigned wrap) { @@ -12,36 +12,36 @@ nvfx_tex_wrap_mode(unsigned wrap) { switch (wrap) { case PIPE_TEX_WRAP_REPEAT: - ret = NV34TCL_TX_WRAP_S_REPEAT; + ret = NV30_3D_TEX_WRAP_S_REPEAT; break; case PIPE_TEX_WRAP_MIRROR_REPEAT: - ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT; + ret = NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT; break; case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE; + ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER; + ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_CLAMP: - ret = NV34TCL_TX_WRAP_S_CLAMP; + ret = NV30_3D_TEX_WRAP_S_CLAMP; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_MIRROR_CLAMP: - ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP; + ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP; break; default: assert(0); - ret = NV34TCL_TX_WRAP_S_REPEAT; + ret = NV30_3D_TEX_WRAP_S_REPEAT; break; } - return ret >> NV34TCL_TX_WRAP_S_SHIFT; + return ret >> NV30_3D_TEX_WRAP_S__SHIFT; } static inline unsigned @@ -49,21 +49,21 @@ nvfx_tex_wrap_compare_mode(unsigned func) { switch (func) { case PIPE_FUNC_NEVER: - return NV34TCL_TX_WRAP_RCOMP_NEVER; + return NV30_3D_TEX_WRAP_RCOMP_NEVER; case PIPE_FUNC_GREATER: - return NV34TCL_TX_WRAP_RCOMP_GREATER; + return NV30_3D_TEX_WRAP_RCOMP_GREATER; case PIPE_FUNC_EQUAL: - return NV34TCL_TX_WRAP_RCOMP_EQUAL; + return NV30_3D_TEX_WRAP_RCOMP_EQUAL; case PIPE_FUNC_GEQUAL: - return NV34TCL_TX_WRAP_RCOMP_GEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_GEQUAL; case PIPE_FUNC_LESS: - return NV34TCL_TX_WRAP_RCOMP_LESS; + return NV30_3D_TEX_WRAP_RCOMP_LESS; case PIPE_FUNC_NOTEQUAL: - return NV34TCL_TX_WRAP_RCOMP_NOTEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL; case PIPE_FUNC_LEQUAL: - return NV34TCL_TX_WRAP_RCOMP_LEQUAL; + return NV30_3D_TEX_WRAP_RCOMP_LEQUAL; case PIPE_FUNC_ALWAYS: - return NV34TCL_TX_WRAP_RCOMP_ALWAYS; + return NV30_3D_TEX_WRAP_RCOMP_ALWAYS; default: assert(0); return 0; @@ -75,11 +75,11 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) unsigned filter = 0; switch (cso->mag_img_filter) { case PIPE_TEX_FILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR; + filter |= NV30_3D_TEX_FILTER_MAG_LINEAR; break; case PIPE_TEX_FILTER_NEAREST: default: - filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST; + filter |= NV30_3D_TEX_FILTER_MAG_NEAREST; break; } @@ -87,14 +87,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) case PIPE_TEX_FILTER_LINEAR: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_LINEAR; break; } break; @@ -102,14 +102,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso) default: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST; + filter |= NV30_3D_TEX_FILTER_MIN_NEAREST; break; } break; diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c index e6e9a8f2e40..597664e7716 100644 --- a/src/gallium/drivers/nvfx/nvfx_vbo.c +++ b/src/gallium/drivers/nvfx/nvfx_vbo.c @@ -9,7 +9,7 @@ #include "nvfx_resource.h" #include "nouveau/nouveau_channel.h" -#include "nouveau/nouveau_class.h" + #include "nouveau/nouveau_pushbuf.h" static inline unsigned @@ -266,7 +266,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } - OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements)); + OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements)); if(nvfx->use_vertex_buffers) { unsigned idx = 0; @@ -281,7 +281,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) idx = ve->idx; } - OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT)); + OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV30_3D_VTXFMT_STRIDE__SHIFT)); ++idx; } if(idx != nvfx->vtxelt->num_elements) @@ -291,7 +291,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements); for(i = nvfx->vtxelt->num_elements; i < elements; ++i) - OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT); + OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT); if(nvfx->is_nv4x) { unsigned i; @@ -302,7 +302,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } } - OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements)); + OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements)); if(nvfx->use_vertex_buffers) { unsigned idx = 0; @@ -317,7 +317,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride, vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 0, NV34TCL_VTXBUF_ADDRESS_DMA1); + 0, NV30_3D_VTXBUF_DMA1); ++idx; } @@ -339,6 +339,44 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) } void +nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx) +{ + struct nouveau_channel* chan = nvfx->screen->base.channel; + unsigned num_outputs = nvfx->vertprog->draw_elements; + int elements = MAX2(num_outputs, nvfx->hw_vtxelt_nr); + + if (!elements) + return; + + WAIT_RING(chan, (1 + 6 + 1 + 2) + elements * 2); + + OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements)); + for(unsigned i = 0; i < num_outputs; ++i) + OUT_RING(chan, (4 << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT); + for(unsigned i = num_outputs; i < elements; ++i) + OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT); + + if(nvfx->is_nv4x) { + unsigned i; + /* seems to be some kind of cache flushing */ + for(i = 0; i < 3; ++i) { + OUT_RING(chan, RING_3D(0x1718, 1)); + OUT_RING(chan, 0); + } + } + + OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements)); + for (unsigned i = 0; i < elements; i++) + OUT_RING(chan, 0); + + OUT_RING(chan, RING_3D(0x1710, 1)); + OUT_RING(chan, 0); + + nvfx->hw_vtxelt_nr = num_outputs; + nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF; +} + +void nvfx_vbo_relocate(struct nvfx_context *nvfx) { struct nouveau_channel* chan; @@ -357,11 +395,11 @@ nvfx_vbo_relocate(struct nvfx_context *nvfx) struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index]; struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo; - OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(ve->idx), 1), + OUT_RELOC(chan, bo, RING_3D(NV30_3D_VTXBUF(ve->idx), 1), vb_flags, 0, 0); OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride, vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 0, NV34TCL_VTXBUF_ADDRESS_DMA1); + 0, NV30_3D_VTXBUF_DMA1); } nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF; } @@ -370,7 +408,7 @@ static void nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags) { struct nouveau_channel* chan = nvfx->screen->base.channel; - unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV34TCL_IDXBUF_FORMAT_TYPE_U16 : NV34TCL_IDXBUF_FORMAT_TYPE_U32; + unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV30_3D_IDXBUF_FORMAT_TYPE_U16 : NV30_3D_IDXBUF_FORMAT_TYPE_U32; struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo; ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD; @@ -378,12 +416,12 @@ nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags) MARK_RING(chan, 3, 3); if(ib_flags & NOUVEAU_BO_DUMMY) - OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2), ib_flags, 0, 0); + OUT_RELOC(chan, bo, RING_3D(NV30_3D_IDXBUF_OFFSET, 2), ib_flags, 0, 0); else - OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2)); + OUT_RING(chan, RING_3D(NV30_3D_IDXBUF_OFFSET, 2)); OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0); OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR, - 0, NV34TCL_IDXBUF_FORMAT_DMA1); + 0, NV30_3D_IDXBUF_FORMAT_DMA1); nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF; } @@ -401,27 +439,27 @@ nvfx_idxbuf_relocate(struct nvfx_context* nvfx) unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] = { - [PIPE_FORMAT_R32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R32G32B32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT, - [PIPE_FORMAT_R16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16B16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT, - [PIPE_FORMAT_R8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8A8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM, - [PIPE_FORMAT_R8G8B8A8_USCALED] = NV34TCL_VTXFMT_TYPE_8_USCALED, - [PIPE_FORMAT_R16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16B16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16G16B16A16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM, - [PIPE_FORMAT_R16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16B16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, - [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED, + [PIPE_FORMAT_R32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32B32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT, + [PIPE_FORMAT_R16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16B16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT, + [PIPE_FORMAT_R8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8A8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM, + [PIPE_FORMAT_R8G8B8A8_USCALED] = NV30_3D_VTXFMT_TYPE_U8_USCALED, + [PIPE_FORMAT_R16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16B16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16G16B16A16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM, + [PIPE_FORMAT_R16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16B16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, + [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED, }; static void * @@ -476,7 +514,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, if(ve->instance_divisor) { struct nvfx_low_frequency_element* lfve; - cso->vtxfmt[i] = NV34TCL_VTXFMT_TYPE_32_FLOAT; + cso->vtxfmt[i] = NV30_3D_VTXFMT_TYPE_V32_FLOAT; //if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT) if(0) @@ -511,14 +549,14 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, if(type) { transkey.element[idx].output_format = ve->src_format; - cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type; + cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | type; } else { unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT}; transkey.element[idx].output_format = float32[ncomp - 1]; cso->needs_translate = TRUE; - cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT; + cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT; } transkey.element[idx].output_offset = transkey.output_stride; transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3; @@ -527,7 +565,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, cso->translate = translate_create(&transkey); cso->vertex_length = transkey.output_stride >> 2; - cso->max_vertices_per_packet = 2047 / cso->vertex_length; + cso->max_vertices_per_packet = 2047 / MAX2(cso->vertex_length, 1); return (void *)cso; } diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c index ea7e88c5613..23f045ecf6c 100644 --- a/src/gallium/drivers/nvfx/nvfx_vertprog.c +++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c @@ -8,6 +8,7 @@ #include "tgsi/tgsi_parse.h" #include "tgsi/tgsi_dump.h" #include "tgsi/tgsi_util.h" +#include "tgsi/tgsi_ureg.h" #include "draw/draw_context.h" @@ -37,7 +38,9 @@ struct nvfx_loop_entry struct nvfx_vpc { struct nvfx_context* nvfx; + struct pipe_shader_state pipe; struct nvfx_vertex_program *vp; + struct tgsi_shader_info* info; struct nvfx_vertex_program_exec *vpi; @@ -46,6 +49,8 @@ struct nvfx_vpc { struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; struct nvfx_reg *r_address; struct nvfx_reg *r_temp; + struct nvfx_reg *r_const; + struct nvfx_reg r_0_1; struct nvfx_reg *imm; unsigned nr_imm; @@ -105,8 +110,8 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w) return nvfx_reg(NVFXSR_CONST, idx); } -#define arith(s,o,d,m,s0,s1,s2) \ - nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2)) +#define arith(s,t,o,d,m,s0,s1,s2) \ + nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2)) static void emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src) @@ -152,6 +157,18 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) | (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT))); + if(src.indirect) { + if(src.reg.type == NVFXSR_CONST) + hw[3] |= NVFX_VP(INST_INDEX_CONST); + else if(src.reg.type == NVFXSR_INPUT) + hw[0] |= NVFX_VP(INST_INDEX_INPUT); + else + assert(0); + if(src.indirect_reg) + hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1); + hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT); + } + switch (pos) { case 0: hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >> @@ -279,6 +296,13 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn) if(insn.cc_update) hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE); + if(insn.sat) + { + assert(nvfx->use_nv4x); + if(nvfx->use_nv4x) + hw[0] |= NV40_VP_INST_SATURATE; + } + if(!nvfx->is_nv4x) { if(slot == 0) hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT); @@ -317,6 +341,9 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn) emit_src(nvfx, vpc, hw, 0, insn.src[0]); emit_src(nvfx, vpc, hw, 1, insn.src[1]); emit_src(nvfx, vpc, hw, 2, insn.src[2]); + +// if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL) +// hw[3] |= NV40_VP_INST_SCA_RESULT; } static inline struct nvfx_src @@ -328,7 +355,7 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index); break; case TGSI_FILE_CONSTANT: - src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0); + src.reg = vpc->r_const[fsrc->Register.Index]; break; case TGSI_FILE_IMMEDIATE: src.reg = vpc->imm[fsrc->Register.Index]; @@ -339,7 +366,7 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { default: NOUVEAU_ERR("bad src file\n"); src.reg.index = 0; - src.reg.type = 0; + src.reg.type = -1; break; } @@ -349,6 +376,22 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) { src.swz[1] = fsrc->Register.SwizzleY; src.swz[2] = fsrc->Register.SwizzleZ; src.swz[3] = fsrc->Register.SwizzleW; + src.indirect = 0; + + if(fsrc->Register.Indirect) { + if(fsrc->Indirect.File == TGSI_FILE_ADDRESS && + (fsrc->Register.File == TGSI_FILE_CONSTANT || fsrc->Register.File == TGSI_FILE_INPUT)) + { + src.indirect = 1; + src.indirect_reg = fsrc->Indirect.Index; + src.indirect_swz = fsrc->Indirect.SwizzleX; + } + else + { + src.reg.index = 0; + src.reg.type = -1; + } + } return src; } @@ -397,16 +440,16 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, { struct nvfx_src src[3], tmp; struct nvfx_reg dst; + struct nvfx_reg final_dst; struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct nvfx_insn insn; struct nvfx_relocation reloc; struct nvfx_loop_entry loop; + boolean sat = FALSE; int mask; int ai = -1, ci = -1, ii = -1; int i; - - if (finst->Instruction.Opcode == TGSI_OPCODE_END) - return TRUE; + unsigned sub_depth = 0; for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { const struct tgsi_full_src_register *fsrc; @@ -429,7 +472,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_CONSTANT: @@ -439,7 +482,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_IMMEDIATE: @@ -449,7 +492,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, src[i] = tgsi_src(vpc, fsrc); } else { src[i] = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none)); } break; case TGSI_FILE_TEMPORARY: @@ -461,161 +504,178 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, } } - dst = tgsi_dst(vpc, &finst->Dst[0]); + for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { + if(src[i].reg.type < 0) + return FALSE; + } + + if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS && + finst->Instruction.Opcode != TGSI_OPCODE_ARL) + return FALSE; + + final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]); mask = tgsi_mask(finst->Dst[0].Register.WriteMask); + if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE) + { + assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL); + if(nvfx->use_nv4x) + sat = TRUE; + else if(dst.type != NVFXSR_TEMP) + dst = temp(vpc); + } switch (finst->Instruction.Opcode) { case TGSI_OPCODE_ABS: - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none)); break; case TGSI_OPCODE_ADD: - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1])); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); break; case TGSI_OPCODE_ARL: - nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_CMP: - insn = arith(VEC, MOV, none.reg, mask, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); - insn = arith(VEC, MOV, dst, mask, src[2], none, none); + insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); insn.cc_test = NVFX_COND_GE; nvfx_vp_emit(vpc, insn); - insn = arith(VEC, MOV, dst, mask, src[1], none, none); + insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); insn.cc_test = NVFX_COND_LT; nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_COS: - nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_DP2: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none)); - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none)); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y))); break; case TGSI_OPCODE_DP3: - nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DP4: - nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DP4, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DPH: - nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DPH, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_DST: - nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, DST, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_EX2: - nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_EXP: - nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, EXP, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_FLR: - nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, FLR, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_FRC: - nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_LG2: - nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LG2, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LIT: - nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LIT, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LOG: - nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, LOG, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_LRP: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2])); - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp)); + nvfx_vp_emit(vpc, arith(0, VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2])); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], tmp)); break; case TGSI_OPCODE_MAD: - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2])); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], src[2])); break; case TGSI_OPCODE_MAX: - nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MAX, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_MIN: - nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MIN, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_MOV: - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, src[0], none, none)); break; case TGSI_OPCODE_MUL: - nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MUL, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_NOP: break; case TGSI_OPCODE_POW: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X))); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none)); - nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X))); + nvfx_vp_emit(vpc, arith(0, SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X))); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none)); + nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X))); break; case TGSI_OPCODE_RCP: - nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, RCP, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_RSQ: - nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0]))); + nvfx_vp_emit(vpc, arith(sat, SCA, RSQ, dst, mask, none, none, abs(src[0]))); break; case TGSI_OPCODE_SEQ: - nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SFL: - nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SFL, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SGE: - nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SGT: - nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SGT, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SIN: - nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0])); + nvfx_vp_emit(vpc, arith(sat, SCA, SIN, dst, mask, none, none, src[0])); break; case TGSI_OPCODE_SLE: - nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SLE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SLT: - nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SLT, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SNE: - nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SNE, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SSG: - nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_STR: - nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none)); + nvfx_vp_emit(vpc, arith(sat, VEC, STR, dst, mask, src[0], src[1], none)); break; case TGSI_OPCODE_SUB: - nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1]))); + nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, neg(src[1]))); break; case TGSI_OPCODE_TRUNC: tmp = nvfx_src(temp(vpc)); - insn = arith(VEC, MOV, none.reg, mask, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); - nvfx_vp_emit(vpc, arith(VEC, FLR, tmp.reg, mask, abs(src[0]), none, none)); - nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, tmp, none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, abs(src[0]), none, none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, tmp, none, none)); - insn = arith(VEC, MOV, dst, mask, neg(tmp), none, none); + insn = arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none); insn.cc_test = NVFX_COND_LT; nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_XPD: tmp = nvfx_src(temp(vpc)); - nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none)); - nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp))); + nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none)); + nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp))); break; case TGSI_OPCODE_IF: - insn = arith(VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none); + insn = arith(0, VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none); insn.cc_update = 1; nvfx_vp_emit(vpc, insn); @@ -623,7 +683,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = finst->Label.Label + 1; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - insn = arith(SCA, BRA, none.reg, 0, none, none, none); + insn = arith(0, SCA, BRA, none.reg, 0, none, none, none); insn.cc_test = NVFX_COND_EQ; insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0; nvfx_vp_emit(vpc, insn); @@ -637,20 +697,31 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); if(finst->Instruction.Opcode == TGSI_OPCODE_CAL) - insn = arith(SCA, CAL, none.reg, 0, none, none, none); + insn = arith(0, SCA, CAL, none.reg, 0, none, none, none); else - insn = arith(SCA, BRA, none.reg, 0, none, none, none); + insn = arith(0, SCA, BRA, none.reg, 0, none, none, none); nvfx_vp_emit(vpc, insn); break; case TGSI_OPCODE_RET: - tmp = none; - tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0; - nvfx_vp_emit(vpc, arith(SCA, RET, none.reg, 0, none, none, tmp)); + if(sub_depth || !nvfx->use_vp_clipping) { + tmp = none; + tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0; + nvfx_vp_emit(vpc, arith(0, SCA, RET, none.reg, 0, none, none, tmp)); + } else { + reloc.location = vpc->vp->nr_insns; + reloc.target = vpc->info->num_instructions; + util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + } break; case TGSI_OPCODE_BGNSUB: + ++sub_depth; + break; case TGSI_OPCODE_ENDSUB: + --sub_depth; + break; case TGSI_OPCODE_ENDIF: /* nothing to do here */ break; @@ -668,7 +739,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.cont_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); break; case TGSI_OPCODE_CONT: @@ -678,7 +749,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.cont_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); break; case TGSI_OPCODE_BRK: @@ -688,7 +759,24 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, reloc.target = loop.brk_target; util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); - nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none)); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + break; + + case TGSI_OPCODE_END: + assert(!sub_depth); + if(nvfx->use_vp_clipping) { + if(idx != (vpc->info->num_instructions - 1)) { + reloc.location = vpc->vp->nr_insns; + reloc.target = vpc->info->num_instructions; + util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc); + nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none)); + } + } else { + if(vpc->vp->nr_insns) + vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; + nvfx_vp_emit(vpc, arith(0, VEC, NOP, none.reg, 0, none, none, none)); + vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; + } break; default: @@ -696,6 +784,14 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, return FALSE; } + if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE && !nvfx->use_nv4x) + { + if(!vpc->r_0_1.type) + vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0); + nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none)); + nvfx_vp_emit(vpc, arith(0, VEC, MIN, final_dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), Y, Y, Y, Y), none)); + } + release_temps(vpc); return TRUE; } @@ -741,8 +837,13 @@ nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, hw = NVFX_VP(INST_DEST_PSZ); break; case TGSI_SEMANTIC_GENERIC: - hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0); + hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - NVFX_FP_OP_INPUT_SRC_TC(0); + if(hw <= 8) + hw = NVFX_VP(INST_DEST_TC(hw)); + else if(hw == 9) /* TODO: this is correct, but how does this overlapping work exactly? */ + hw = NV40_VP_INST_DEST_PSZ; + else + assert(0); break; case TGSI_SEMANTIC_EDGEFLAG: /* not really an error just a fallback */ @@ -761,22 +862,23 @@ static boolean nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) { struct tgsi_parse_context p; - int high_temp = -1, high_addr = -1, nr_imm = 0, i; + int high_const = -1, high_temp = -1, high_addr = -1, nr_imm = 0, i; struct util_semantic_set set; - unsigned char sem_layout[8]; + unsigned char sem_layout[10]; unsigned num_outputs; + unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8; - num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT); + num_outputs = util_semantic_set_from_program_file(&set, vpc->pipe.tokens, TGSI_FILE_OUTPUT); - if(num_outputs > 8) { + if(num_outputs > num_texcoords) { NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs); return FALSE; } - util_semantic_layout_from_set(sem_layout, &set, 8, 8); + util_semantic_layout_from_set(sem_layout, &set, num_texcoords, num_texcoords); /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */ memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input)); - for(int i = 0; i < 8; ++i) { + for(int i = 0; i < num_texcoords; ++i) { if(sem_layout[i] == 0xff) continue; //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i); @@ -784,7 +886,7 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } vpc->vp->sprite_fp_input = -1; - for(int i = 0; i < 8; ++i) + for(int i = 0; i < num_texcoords; ++i) { if(sem_layout[i] == 0xff) { @@ -793,7 +895,7 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } } - tgsi_parse_init(&p, vpc->vp->pipe.tokens); + tgsi_parse_init(&p, vpc->pipe.tokens); while (!tgsi_parse_end_of_tokens(&p)) { const union tgsi_full_token *tok = &p.FullToken; @@ -814,14 +916,18 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) fdec->Range.Last; } break; -#if 0 /* this would be nice.. except gallium doesn't track it */ case TGSI_FILE_ADDRESS: if (fdec->Range.Last > high_addr) { high_addr = fdec->Range.Last; } break; -#endif + case TGSI_FILE_CONSTANT: + if (fdec->Range.Last > high_const) { + high_const = + fdec->Range.Last; + } + break; case TGSI_FILE_OUTPUT: if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec)) return FALSE; @@ -831,23 +937,6 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) } } break; -#if 1 /* yay, parse instructions looking for address regs instead */ - case TGSI_TOKEN_TYPE_INSTRUCTION: - { - const struct tgsi_full_instruction *finst; - const struct tgsi_full_dst_register *fdst; - - finst = &p.FullToken.FullInstruction; - fdst = &finst->Dst[0]; - - if (fdst->Register.File == TGSI_FILE_ADDRESS) { - if (fdst->Register.Index > high_addr) - high_addr = fdst->Register.Index; - } - - } - break; -#endif default: break; } @@ -868,7 +957,13 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) if (++high_addr) { vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg)); for (i = 0; i < high_addr; i++) - vpc->r_address[i] = temp(vpc); + vpc->r_address[i] = nvfx_reg(NVFXSR_TEMP, i); + } + + if(++high_const) { + vpc->r_const = CALLOC(high_const, sizeof(struct nvfx_reg)); + for (i = 0; i < high_const; i++) + vpc->r_const[i] = constant(vpc, i, 0, 0, 0, 0); } vpc->r_temps_discard = 0; @@ -877,21 +972,36 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc) DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE) -static void -nvfx_vertprog_translate(struct nvfx_context *nvfx, - struct nvfx_vertex_program *vp) +static struct nvfx_vertex_program* +nvfx_vertprog_translate(struct nvfx_context *nvfx, const struct pipe_shader_state* vps, const struct tgsi_shader_info* info) { struct tgsi_parse_context parse; + struct nvfx_vertex_program* vp = NULL; struct nvfx_vpc *vpc = NULL; struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct util_dynarray insns; int i; - vpc = CALLOC(1, sizeof(struct nvfx_vpc)); + tgsi_parse_init(&parse, vps->tokens); + + vp = CALLOC_STRUCT(nvfx_vertex_program); + if(!vp) + goto out_err; + + vpc = CALLOC_STRUCT(nvfx_vpc); if (!vpc) - return; + goto out_err; + vpc->nvfx = nvfx; vpc->vp = vp; + vpc->pipe = *vps; + vpc->info = info; + + { + // TODO: use a 64-bit atomic here! + static unsigned long long id = 0; + vp->id = ++id; + } /* reserve space for ucps */ if(nvfx->use_vp_clipping) @@ -902,7 +1012,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, if (!nvfx_vertprog_prepare(nvfx, vpc)) { FREE(vpc); - return; + return NULL; } /* Redirect post-transform vertex position to a temp if user clip @@ -915,8 +1025,6 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, vpc->r_temps_discard = 0; } - tgsi_parse_init(&parse, vp->pipe.tokens); - util_dynarray_init(&insns); while (!tgsi_parse_end_of_tokens(&parse)) { tgsi_parse_token(&parse); @@ -977,7 +1085,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, NVFX_VP(INST_DEST_POS)); struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]); - nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none)); + nvfx_vp_emit(vpc, arith(0, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none)); } /* Insert code to handle user clip planes */ @@ -1003,22 +1111,14 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, else mask = NVFX_VP_MASK_X; - nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none)); + nvfx_vp_emit(vpc, arith(0, VEC, DP4, cdst, mask, htmp, ceqn, none)); } } - else - { - if(vp->nr_insns) - vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; - - nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none)); - vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST; - } if(debug_get_option_nvfx_dump_vp()) { debug_printf("\n"); - tgsi_dump(vp->pipe.tokens, 0); + tgsi_dump(vpc->pipe.tokens, 0); debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x"); for (i = 0; i < vp->nr_insns; i++) @@ -1028,18 +1128,51 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx, vp->clip_nr = -1; vp->exec_start = -1; - vp->translated = TRUE; -out_err: + +out: tgsi_parse_free(&parse); - util_dynarray_fini(&vpc->label_relocs); - util_dynarray_fini(&vpc->loop_stack); - if (vpc->r_temp) + if(vpc) { + util_dynarray_fini(&vpc->label_relocs); + util_dynarray_fini(&vpc->loop_stack); FREE(vpc->r_temp); - if (vpc->r_address) FREE(vpc->r_address); - if (vpc->imm) + FREE(vpc->r_const); FREE(vpc->imm); - FREE(vpc); + FREE(vpc); + } + return vp; + +out_err: + FREE(vp); + vp = NULL; + goto out; +} + +static struct nvfx_vertex_program* +nvfx_vertprog_translate_draw_vp(struct nvfx_context *nvfx, struct nvfx_pipe_vertex_program* pvp) +{ + struct nvfx_vertex_program* vp = NULL; + struct pipe_shader_state vps; + struct tgsi_shader_info info; + struct ureg_program *ureg = NULL; + unsigned num_outputs = MIN2(pvp->info.num_outputs, 16); + + ureg = ureg_create( TGSI_PROCESSOR_VERTEX ); + if(ureg == NULL) + return 0; + + for (unsigned i = 0; i < num_outputs; i++) + ureg_MOV(ureg, ureg_DECL_output(ureg, pvp->info.output_semantic_name[i], pvp->info.output_semantic_index[i]), ureg_DECL_vs_input(ureg, i)); + + ureg_END( ureg ); + + vps.tokens = ureg_get_tokens(ureg, 0); + tgsi_scan_shader(vps.tokens, &info); + vp = nvfx_vertprog_translate(nvfx, &vps, &info); + ureg_free_tokens(vps.tokens); + ureg_destroy(ureg); + + return vp; } boolean @@ -1047,31 +1180,44 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) { struct nvfx_screen *screen = nvfx->screen; struct nouveau_channel *chan = screen->base.channel; - struct nouveau_grobj *eng3d = screen->eng3d; - struct nvfx_vertex_program *vp; + struct nvfx_pipe_vertex_program *pvp = nvfx->vertprog; + struct nvfx_vertex_program* vp; struct pipe_resource *constbuf; boolean upload_code = FALSE, upload_data = FALSE; int i; if (nvfx->render_mode == HW) { - vp = nvfx->vertprog; - constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX]; - } else { - vp = nvfx->swtnl.vertprog; - constbuf = NULL; - } - - /* Translate TGSI shader into hw bytecode */ - if (!vp->translated) - { nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG; - nvfx_vertprog_translate(nvfx, vp); - if (!vp->translated) { + vp = pvp->vp; + + if(!vp) { + vp = nvfx_vertprog_translate(nvfx, &pvp->pipe, &pvp->info); + if(!vp) + vp = NVFX_VP_FAILED; + pvp->vp = vp; + } + + if(vp == NVFX_VP_FAILED) { nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG; return FALSE; } + + constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX]; + } else { + vp = pvp->draw_vp; + if(!vp) + { + pvp->draw_vp = vp = nvfx_vertprog_translate_draw_vp(nvfx, pvp); + if(!vp) { + _debug_printf("Error: unable to create a swtnl passthrough vertex shader: aborting."); + abort(); + } + } + constbuf = NULL; } + nvfx->hw_vertprog = vp; + /* Allocate hw vtxprog exec slots */ if (!vp->exec) { struct nouveau_resource *heap = nvfx->screen->vp_exec_heap; @@ -1116,6 +1262,8 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) } } + //printf("start at %u nc %u\n", vp->data->start, vp->nr_consts); + /*XXX: handle this some day */ assert(vp->data->start >= vp->data_start_min); @@ -1161,6 +1309,8 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i); struct nvfx_vertex_program_exec *vpi = &vp->insns[reloc->location]; + //printf("reloc %i to %i + %i\n", reloc->location, vp->data->start, reloc->target); + vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK); vpi->data[1] |= (reloc->target + vp->data->start) << @@ -1178,6 +1328,18 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) if (constbuf) map = (float*)nvfx_buffer(constbuf)->data; + /* + * WAIT_RING(chan, 512 * 6); + for (i = 0; i < 512; i++) { + float v[4] = {0.1, 0,2, 0.3, 0.4}; + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, i); + OUT_RINGp(chan, (uint32_t *)v, 4); + printf("frob %i\n", i); + } + */ + + WAIT_RING(chan, 6 * vp->nr_consts); for (i = nvfx->use_vp_clipping ? 6 : 0; i < vp->nr_consts; i++) { struct nvfx_vertex_program_data *vpd = &vp->consts[i]; @@ -1190,19 +1352,23 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) 4 * sizeof(float)); } - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5); - OUT_RING (chan, i + vp->data->start); - OUT_RINGp (chan, (uint32_t *)vpd->value, 4); + //printf("upload into %i + %i: %f %f %f %f\n", vp->data->start, i, vpd->value[0], vpd->value[1], vpd->value[2], vpd->value[3]); + + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5)); + OUT_RING(chan, i + vp->data->start); + OUT_RINGp(chan, (uint32_t *)vpd->value, 4); } } /* Upload vtxprog */ if (upload_code) { - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1); - OUT_RING (chan, vp->exec->start); + WAIT_RING(chan, 2 + 5 * vp->nr_insns); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1)); + OUT_RING(chan, vp->exec->start); for (i = 0; i < vp->nr_insns; i++) { - BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4); - OUT_RINGp (chan, vp->insns[i].data, 4); + OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4)); + //printf("%08x %08x %08x %08x\n", vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]); + OUT_RINGp(chan, vp->insns[i].data, 4); } vp->clip_nr = -1; } @@ -1210,10 +1376,10 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx) if(nvfx->dirty & (NVFX_NEW_VERTPROG)) { WAIT_RING(chan, 6); - OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1)); + OUT_RING(chan, RING_3D(NV30_3D_VP_START_FROM_ID, 1)); OUT_RING(chan, vp->exec->start); if(nvfx->is_nv4x) { - OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 1)); + OUT_RING(chan, RING_3D(NV40_3D_VP_ATTRIB_EN, 1)); OUT_RING(chan, vp->ir); } } @@ -1235,24 +1401,21 @@ nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp) util_dynarray_fini(&vp->branch_relocs); util_dynarray_fini(&vp->const_relocs); + FREE(vp); } static void * -nvfx_vp_state_create(struct pipe_context *pipe, - const struct pipe_shader_state *cso) +nvfx_vp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *cso) { - struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_vertex_program *vp; + struct nvfx_pipe_vertex_program *pvp; - // TODO: use a 64-bit atomic here! - static unsigned long long id = 0; + pvp = CALLOC(1, sizeof(struct nvfx_pipe_vertex_program)); + pvp->pipe.tokens = tgsi_dup_tokens(cso->tokens); + tgsi_scan_shader(pvp->pipe.tokens, &pvp->info); + pvp->draw_elements = MAX2(1, MIN2(pvp->info.num_outputs, 16)); + pvp->draw_no_elements = pvp->info.num_outputs == 0; - vp = CALLOC(1, sizeof(struct nvfx_vertex_program)); - vp->pipe.tokens = tgsi_dup_tokens(cso->tokens); - vp->draw = draw_create_vertex_shader(nvfx->draw, &vp->pipe); - vp->id = ++id; - - return (void *)vp; + return (void *)pvp; } static void @@ -1268,13 +1431,17 @@ nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso) static void nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso) { - struct nvfx_context *nvfx = nvfx_context(pipe); - struct nvfx_vertex_program *vp = hwcso; - - draw_delete_vertex_shader(nvfx->draw, vp->draw); - nvfx_vertprog_destroy(nvfx, vp); - FREE((void*)vp->pipe.tokens); - FREE(vp); + struct nvfx_context *nvfx = nvfx_context(pipe); + struct nvfx_pipe_vertex_program *pvp = hwcso; + + if(pvp->draw_vs) + draw_delete_vertex_shader(nvfx->draw, pvp->draw_vs); + if(pvp->vp && pvp->vp != NVFX_VP_FAILED) + nvfx_vertprog_destroy(nvfx, pvp->vp); + if(pvp->draw_vp) + nvfx_vertprog_destroy(nvfx, pvp->draw_vp); + FREE((void*)pvp->pipe.tokens); + FREE(pvp); } void diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index 47ffc0cb3c6..91a374a5838 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -263,10 +263,6 @@ static void r300_clear(struct pipe_context* pipe, zstex->hiz_in_use[fb->zsbuf->level])) { r300->hyperz_state.dirty = TRUE; } - - /* XXX this flush "fixes" a hardlock in the cubestorm xscreensaver */ - if (r300->flush_counter == 0) - pipe->flush(pipe, 0, NULL); } /* Clear a region of a color surface to a constant value. */ @@ -391,9 +387,6 @@ static void r300_resource_copy_region(struct pipe_context *pipe, r300_flush_depth_stencil(pipe, src, subsrc, srcz); } if (old_format != new_format) { - dst->format = new_format; - src->format = new_format; - r300_texture_reinterpret_format(pipe->screen, dst, new_format); r300_texture_reinterpret_format(pipe->screen, @@ -404,9 +397,6 @@ static void r300_resource_copy_region(struct pipe_context *pipe, src, subsrc, srcx, srcy, srcz, width, height); if (old_format != new_format) { - dst->format = old_format; - src->format = old_format; - r300_texture_reinterpret_format(pipe->screen, dst, old_format); r300_texture_reinterpret_format(pipe->screen, diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 8f0e86fd378..8eddf72b704 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -447,9 +447,17 @@ struct r300_context { struct r300_winsys_cs *cs; /* Screen. */ struct r300_screen *screen; + /* Draw module. Used mostly for SW TCL. */ struct draw_context* draw; + /* Vertex buffer for SW TCL. */ + struct pipe_resource* vbo; + /* Offset and size into the SW TCL VBO. */ + size_t draw_vbo_offset; size_t draw_vbo_size; + /* Whether the VBO must not be flushed. */ + boolean draw_vbo_locked; + /* Accelerated blit support. */ struct blitter_context* blitter; /* Stencil two-sided reference value fallback. */ @@ -457,14 +465,10 @@ struct r300_context { /* For translating vertex buffers having incompatible vertex layout. */ struct r300_translate_context tran; - /* Vertex buffer for rendering. */ - struct pipe_resource* vbo; /* The KIL opcode needs the first texture unit to be enabled * on r3xx-r4xx. In order to calm down the CS checker, we bind this * dummy texture there. */ struct r300_sampler_view *texkill_sampler; - /* Offset into the VBO. */ - size_t vbo_offset; /* The currently active query. */ struct r300_query *query_current; diff --git a/src/gallium/drivers/r300/r300_debug.c b/src/gallium/drivers/r300/r300_debug.c index c3e157e99af..145a7985da3 100644 --- a/src/gallium/drivers/r300/r300_debug.c +++ b/src/gallium/drivers/r300/r300_debug.c @@ -27,24 +27,27 @@ #include <stdio.h> static const struct debug_named_value debug_options[] = { - { "fp", DBG_FP, "Fragment program handling (for debugging)" }, - { "vp", DBG_VP, "Vertex program handling (for debugging)" }, - { "draw", DBG_DRAW, "Draw calls (for debugging)" }, - { "swtcl", DBG_SWTCL, "SWTCL-specific info (for debugging)" }, - { "rsblock", DBG_RS_BLOCK, "Rasterizer registers (for debugging)" }, - { "psc", DBG_PSC, "Vertex stream registers (for debugging)" }, - { "tex", DBG_TEX, "Textures (for debugging)" }, - { "texalloc", DBG_TEXALLOC, "Texture allocation (for debugging)" }, - { "fall", DBG_FALL, "Fallbacks (for debugging)" }, - { "rs", DBG_RS, "Rasterizer (for debugging)" }, - { "fb", DBG_FB, "Framebuffer (for debugging)" }, - { "cbzb", DBG_CBZB, "Fast color clear info (for debugging)" }, - { "fakeocc", DBG_FAKE_OCC, "Use fake occlusion queries (for debugging)" }, - { "anisohq", DBG_ANISOHQ, "High quality anisotropic filtering (for benchmarking)" }, - { "notiling", DBG_NO_TILING, "Disable tiling (for benchmarking)" }, - { "noimmd", DBG_NO_IMMD, "Disable immediate mode (for benchmarking)" }, - { "stats", DBG_STATS, "Gather statistics" }, - { "hyperz", DBG_HYPERZ, "HyperZ (for debugging)" }, + { "fp", DBG_FP, "Log fragment program compilation" }, + { "vp", DBG_VP, "Log vertex program compilation" }, + { "draw", DBG_DRAW, "Log draw calls" }, + { "swtcl", DBG_SWTCL, "Log SWTCL-specific info" }, + { "rsblock", DBG_RS_BLOCK, "Log rasterizer registers" }, + { "psc", DBG_PSC, "Log vertex stream registers" }, + { "tex", DBG_TEX, "Log basic info about textures" }, + { "texalloc", DBG_TEXALLOC, "Log texture mipmap tree info" }, + { "fall", DBG_FALL, "Log fallbacks" }, + { "rs", DBG_RS, "Log rasterizer" }, + { "fb", DBG_FB, "Log framebuffer" }, + { "cbzb", DBG_CBZB, "Log fast color clear info" }, + { "stats", DBG_STATS, "Log emission statistics" }, + { "hyperz", DBG_HYPERZ, "Log HyperZ info" }, + { "scissor", DBG_SCISSOR, "Log scissor info" }, + { "fakeocc", DBG_FAKE_OCC, "Use fake occlusion queries" }, + { "anisohq", DBG_ANISOHQ, "Use high quality anisotropic filtering" }, + { "notiling", DBG_NO_TILING, "Disable tiling" }, + { "noimmd", DBG_NO_IMMD, "Disable immediate mode" }, + { "noopt", DBG_NO_OPT, "Disable shader optimizations" }, + { "nocbzb", DBG_NO_CBZB, "Disable fast color clear" }, /* must be last */ DEBUG_NAMED_VALUE_END diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 232259e21d1..b2b34c3efcb 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -300,6 +300,10 @@ void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state) width = surf->cbzb_width; } + DBG(r300, DBG_SCISSOR, + "r300: Scissor width: %i, height: %i, CBZB clear: %s\n", + width, height, r300->cbzb_clear ? "YES" : "NO"); + BEGIN_CS(size); /* Set up scissors. @@ -843,7 +847,7 @@ void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed) OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); OUT_CS(r300->vertex_info.size | (r300->vertex_info.size << 8)); - OUT_CS(r300->vbo_offset); + OUT_CS(r300->draw_vbo_offset); OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0); END_CS; } @@ -1137,9 +1141,9 @@ void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, voi END_CS; } -void r300_emit_buffer_validate(struct r300_context *r300, - boolean do_validate_vertex_buffers, - struct pipe_resource *index_buffer) +boolean r300_emit_buffer_validate(struct r300_context *r300, + boolean do_validate_vertex_buffers, + struct pipe_resource *index_buffer) { struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)r300->fb_state.state; @@ -1150,7 +1154,6 @@ void r300_emit_buffer_validate(struct r300_context *r300, struct pipe_vertex_element *velem = r300->velems->velem; struct pipe_resource *pbuf; unsigned i; - boolean invalid = FALSE; /* upload buffers first */ if (r300->screen->caps.has_tcl && r300->any_user_vbs) { @@ -1161,7 +1164,6 @@ void r300_emit_buffer_validate(struct r300_context *r300, /* Clean out BOs. */ r300->rws->cs_reset_buffers(r300->cs); -validate: /* Color buffers... */ for (i = 0; i < fb->nr_cbufs; i++) { tex = r300_texture(fb->cbufs[i]->texture); @@ -1208,15 +1210,10 @@ validate: r300_buffer(index_buffer)->domain, 0); if (!r300->rws->cs_validate(r300->cs)) { - r300->context.flush(&r300->context, 0, NULL); - if (invalid) { - /* Well, hell. */ - fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n"); - abort(); - } - invalid = TRUE; - goto validate; + return FALSE; } + + return TRUE; } unsigned r300_get_num_dirty_dwords(struct r300_context *r300) diff --git a/src/gallium/drivers/r300/r300_emit.h b/src/gallium/drivers/r300/r300_emit.h index bae25256346..278dbcb4c7c 100644 --- a/src/gallium/drivers/r300/r300_emit.h +++ b/src/gallium/drivers/r300/r300_emit.h @@ -121,8 +121,8 @@ unsigned r300_get_num_cs_end_dwords(struct r300_context *r300); /* Emit all dirty state. */ void r300_emit_dirty_state(struct r300_context* r300); -void r300_emit_buffer_validate(struct r300_context *r300, - boolean do_validate_vertex_buffers, - struct pipe_resource *index_buffer); +boolean r300_emit_buffer_validate(struct r300_context *r300, + boolean do_validate_vertex_buffers, + struct pipe_resource *index_buffer); #endif /* R300_EMIT_H */ diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c index 2b5d2e42ba5..1afd27f0938 100644 --- a/src/gallium/drivers/r300/r300_flush.c +++ b/src/gallium/drivers/r300/r300_flush.c @@ -43,7 +43,7 @@ static void r300_flush(struct pipe_context* pipe, u_upload_flush(r300->upload_vb); u_upload_flush(r300->upload_ib); - if (r300->draw) + if (r300->draw && !r300->draw_vbo_locked) r300_draw_flush_vbuf(r300); if (r300->dirty_hw) { diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c index 9845e546109..b8dab88ef09 100644 --- a/src/gallium/drivers/r300/r300_fs.c +++ b/src/gallium/drivers/r300/r300_fs.c @@ -385,7 +385,12 @@ static void r300_translate_fragment_shader( compiler.code = &shader->code; compiler.state = shader->compare_state; compiler.Base.is_r500 = r300->screen->caps.is_r500; + compiler.Base.disable_optimizations = DBG_ON(r300, DBG_NO_OPT); + compiler.Base.has_half_swizzles = TRUE; + compiler.Base.has_presub = TRUE; compiler.Base.max_temp_regs = compiler.Base.is_r500 ? 128 : 32; + compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; + compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; compiler.Base.remove_unused_constants = TRUE; compiler.AllocateHwInputs = &allocate_hardware_inputs; compiler.UserData = &shader->inputs; @@ -423,14 +428,6 @@ static void r300_translate_fragment_shader( /* Invoke the compiler */ r3xx_compile_fragment_program(&compiler); - /* Shaders with zero instructions are invalid, - * use the dummy shader instead. */ - if (shader->code.code.r500.inst_end == -1) { - rc_destroy(&compiler.Base); - r300_dummy_fragment_shader(r300, shader); - return; - } - if (compiler.Base.Error) { fprintf(stderr, "r300 FP: Compiler Error:\n%sUsing a dummy shader" " instead.\n", compiler.Base.ErrorMsg); @@ -446,6 +443,14 @@ static void r300_translate_fragment_shader( return; } + /* Shaders with zero instructions are invalid, + * use the dummy shader instead. */ + if (shader->code.code.r500.inst_end == -1) { + rc_destroy(&compiler.Base); + r300_dummy_fragment_shader(r300, shader); + return; + } + /* Initialize numbers of constants for each type. */ shader->externals_count = 0; for (i = 0; diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c index 20bad2c56f5..177850dea2f 100644 --- a/src/gallium/drivers/r300/r300_render.c +++ b/src/gallium/drivers/r300/r300_render.c @@ -179,26 +179,20 @@ enum r300_prepare_flags { /** * Check if the requested number of dwords is available in the CS and - * if not, flush. Then validate buffers and emit dirty state. + * if not, flush. * \param r300 The context. * \param flags See r300_prepare_flags. - * \param index_buffer The index buffer to validate. The parameter may be NULL. * \param cs_dwords The number of dwords to reserve in CS. - * \param aos_offset The offset passed to emit_aos. - * \param index_bias The index bias to emit. + * \return TRUE if the CS was flushed */ -static void r300_prepare_for_rendering(struct r300_context *r300, - enum r300_prepare_flags flags, - struct pipe_resource *index_buffer, - unsigned cs_dwords, - int aos_offset, - int index_bias) +static boolean r300_reserve_cs_dwords(struct r300_context *r300, + enum r300_prepare_flags flags, + unsigned cs_dwords) { boolean flushed = FALSE; boolean first_draw = flags & PREP_FIRST_DRAW; boolean emit_aos = flags & PREP_EMIT_AOS; boolean emit_aos_swtcl = flags & PREP_EMIT_AOS_SWTCL; - boolean indexed = flags & PREP_INDEXED; boolean hw_index_bias = r500_index_bias_supported(r300); /* Add dirty state, index offset, and AOS. */ @@ -223,9 +217,39 @@ static void r300_prepare_for_rendering(struct r300_context *r300, flushed = TRUE; } + return flushed; +} + +/** + * Validate buffers and emit dirty state. + * \param r300 The context. + * \param flags See r300_prepare_flags. + * \param index_buffer The index buffer to validate. The parameter may be NULL. + * \param aos_offset The offset passed to emit_aos. + * \param index_bias The index bias to emit. + * \return TRUE if rendering should be skipped + */ +static boolean r300_emit_states(struct r300_context *r300, + enum r300_prepare_flags flags, + struct pipe_resource *index_buffer, + int aos_offset, + int index_bias) +{ + boolean first_draw = flags & PREP_FIRST_DRAW; + boolean emit_aos = flags & PREP_EMIT_AOS; + boolean emit_aos_swtcl = flags & PREP_EMIT_AOS_SWTCL; + boolean indexed = flags & PREP_INDEXED; + boolean hw_index_bias = r500_index_bias_supported(r300); + /* Validate buffers and emit dirty state if needed. */ - if (first_draw || flushed) { - r300_emit_buffer_validate(r300, flags & PREP_VALIDATE_VBOS, index_buffer); + if (first_draw) { + if (!r300_emit_buffer_validate(r300, flags & PREP_VALIDATE_VBOS, + index_buffer)) { + fprintf(stderr, "r300: CS space validation failed. " + "(not enough memory?) Skipping rendering.\n"); + return FALSE; + } + r300_emit_dirty_state(r300); if (hw_index_bias) { if (r300->screen->caps.has_tcl) @@ -240,6 +264,32 @@ static void r300_prepare_for_rendering(struct r300_context *r300, if (emit_aos_swtcl) r300_emit_aos_swtcl(r300, indexed); } + + return TRUE; +} + +/** + * Check if the requested number of dwords is available in the CS and + * if not, flush. Then validate buffers and emit dirty state. + * \param r300 The context. + * \param flags See r300_prepare_flags. + * \param index_buffer The index buffer to validate. The parameter may be NULL. + * \param cs_dwords The number of dwords to reserve in CS. + * \param aos_offset The offset passed to emit_aos. + * \param index_bias The index bias to emit. + * \return TRUE if rendering should be skipped + */ +static boolean r300_prepare_for_rendering(struct r300_context *r300, + enum r300_prepare_flags flags, + struct pipe_resource *index_buffer, + unsigned cs_dwords, + int aos_offset, + int index_bias) +{ + if (r300_reserve_cs_dwords(r300, flags, cs_dwords)) + flags |= PREP_FIRST_DRAW; + + return r300_emit_states(r300, flags, index_buffer, aos_offset, index_bias); } static boolean immd_is_good_idea(struct r300_context *r300, @@ -300,11 +350,14 @@ static void r300_emit_draw_arrays_immediate(struct r300_context *r300, struct pipe_vertex_element* velem; struct pipe_vertex_buffer* vbuf; unsigned vertex_element_count = r300->velems->count; - unsigned i, v, vbi, dwords; + unsigned i, v, vbi; /* Size of the vertex, in dwords. */ unsigned vertex_size = r300->velems->vertex_size_dwords; + /* The number of dwords for this draw operation. */ + unsigned dwords = 9 + count * vertex_size; + /* Size of the vertex element, in dwords. */ unsigned size[PIPE_MAX_ATTRIBS]; @@ -319,6 +372,9 @@ static void r300_emit_draw_arrays_immediate(struct r300_context *r300, CS_LOCALS(r300); + if (!r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0)) + return; + /* Calculate the vertex size, offsets, strides etc. and map the buffers. */ for (i = 0; i < vertex_element_count; i++) { velem = &r300->velems->velem[i]; @@ -338,10 +394,6 @@ static void r300_emit_draw_arrays_immediate(struct r300_context *r300, mapelem[i] = map[vbi] + (velem->src_offset / 4); } - dwords = 9 + count * vertex_size; - - r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0); - BEGIN_CS(dwords); OUT_CS_REG(R300_GA_COLOR_CONTROL, r300_provoking_vertex_fixes(r300, mode)); @@ -517,10 +569,12 @@ static void r300_draw_range_elements(struct pipe_context* pipe, r300_upload_index_buffer(r300, &indexBuffer, indexSize, start, count, &new_offset); start = new_offset; - /* 15 dwords for emit_draw_elements */ - r300_prepare_for_rendering(r300, - PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS | PREP_INDEXED, - indexBuffer, 15, buffer_offset, indexBias); + + /* 15 dwords for emit_draw_elements. Give up if the function fails. */ + if (!r300_prepare_for_rendering(r300, + PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS | + PREP_INDEXED, indexBuffer, 15, buffer_offset, indexBias)) + goto done; if (alt_num_verts || count <= 65535) { r300_emit_draw_elements(r300, indexBuffer, indexSize, @@ -537,13 +591,15 @@ static void r300_draw_range_elements(struct pipe_context* pipe, /* 15 dwords for emit_draw_elements */ if (count) { - r300_prepare_for_rendering(r300, - PREP_VALIDATE_VBOS | PREP_EMIT_AOS | PREP_INDEXED, - indexBuffer, 15, buffer_offset, indexBias); + if (!r300_prepare_for_rendering(r300, + PREP_VALIDATE_VBOS | PREP_EMIT_AOS | PREP_INDEXED, + indexBuffer, 15, buffer_offset, indexBias)) + goto done; } } while (count); } +done: if (indexBuffer != orgIndexBuffer) { pipe_resource_reference( &indexBuffer, NULL ); } @@ -582,9 +638,11 @@ static void r300_draw_arrays(struct pipe_context* pipe, unsigned mode, if (immd_is_good_idea(r300, count)) { r300_emit_draw_arrays_immediate(r300, mode, start, count); } else { - /* 9 spare dwords for emit_draw_arrays. */ - r300_prepare_for_rendering(r300, PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS, - NULL, 9, start, 0); + /* 9 spare dwords for emit_draw_arrays. Give up if the function fails. */ + if (!r300_prepare_for_rendering(r300, + PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS, + NULL, 9, start, 0)) + goto done; if (alt_num_verts || count <= 65535) { r300_emit_draw_arrays(r300, mode, count); @@ -596,17 +654,18 @@ static void r300_draw_arrays(struct pipe_context* pipe, unsigned mode, start += short_count; count -= short_count; - /* 9 spare dwords for emit_draw_arrays. */ + /* 9 spare dwords for emit_draw_arrays. Give up if the function fails. */ if (count) { - r300_prepare_for_rendering(r300, - PREP_VALIDATE_VBOS | PREP_EMIT_AOS, NULL, 9, - start, 0); + if (!r300_prepare_for_rendering(r300, + PREP_VALIDATE_VBOS | PREP_EMIT_AOS, NULL, 9, + start, 0)) + goto done; } } while (count); } - u_upload_flush(r300->upload_vb); } +done: if (translate) { r300_end_vertex_translate(r300); } @@ -617,6 +676,9 @@ static void r300_draw_vbo(struct pipe_context* pipe, { struct r300_context* r300 = r300_context(pipe); + if (!r300->velems->count || !r300->vertex_buffer_count) + return; + if (info->indexed && r300->index_buffer.buffer) { unsigned offset; @@ -655,7 +717,8 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe, struct pipe_transfer *ib_transfer = NULL; unsigned count = info->count; int i; - void* indices = NULL; + void *indices = NULL; + boolean indexed = info->indexed && r300->index_buffer.buffer; if (r300->skip_rendering) { return; @@ -667,6 +730,11 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe, r300_update_derived_state(r300); + r300_reserve_cs_dwords(r300, + PREP_FIRST_DRAW | PREP_EMIT_AOS_SWTCL | + (indexed ? PREP_INDEXED : 0), + indexed ? 256 : 6); + for (i = 0; i < r300->vertex_buffer_count; i++) { if (r300->vertex_buffer[i].buffer) { void *buf = pipe_buffer_map(pipe, @@ -677,18 +745,17 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe, } } - if (info->indexed && r300->index_buffer.buffer) { + if (indexed) { indices = pipe_buffer_map(pipe, r300->index_buffer.buffer, PIPE_TRANSFER_READ, &ib_transfer); } draw_set_mapped_index_buffer(r300->draw, indices); + r300->draw_vbo_locked = TRUE; draw_vbo(r300->draw, info); - - /* XXX Not sure whether this is the best fix. - * It prevents CS from being rejected and weird assertion failures. */ draw_flush(r300->draw); + r300->draw_vbo_locked = FALSE; for (i = 0; i < r300->vertex_buffer_count; i++) { if (r300->vertex_buffer[i].buffer) { @@ -698,7 +765,7 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe, } } - if (ib_transfer) { + if (indexed) { pipe_buffer_unmap(pipe, r300->index_buffer.buffer, ib_transfer); draw_set_mapped_index_buffer(r300->draw, NULL); } @@ -718,7 +785,6 @@ struct r300_render { unsigned hwprim; /* VBO */ - size_t vbo_offset; size_t vbo_max_used; void * vbo_ptr; @@ -749,18 +815,19 @@ static boolean r300_render_allocate_vertices(struct vbuf_render* render, struct pipe_screen* screen = r300->context.screen; size_t size = (size_t)vertex_size * (size_t)count; - if (size + r300render->vbo_offset > r300->draw_vbo_size) + DBG(r300, DBG_DRAW, "r300: render_allocate_vertices (size: %d)\n", size); + + if (size + r300->draw_vbo_offset > r300->draw_vbo_size) { pipe_resource_reference(&r300->vbo, NULL); r300->vbo = pipe_buffer_create(screen, PIPE_BIND_VERTEX_BUFFER, R300_MAX_DRAW_VBO_SIZE); - r300render->vbo_offset = 0; + r300->draw_vbo_offset = 0; r300->draw_vbo_size = R300_MAX_DRAW_VBO_SIZE; } r300render->vertex_size = vertex_size; - r300->vbo_offset = r300render->vbo_offset; return (r300->vbo) ? TRUE : FALSE; } @@ -772,6 +839,8 @@ static void* r300_render_map_vertices(struct vbuf_render* render) assert(!r300render->vbo_transfer); + DBG(r300, DBG_DRAW, "r300: render_map_vertices\n"); + r300render->vbo_ptr = pipe_buffer_map(&r300render->r300->context, r300->vbo, PIPE_TRANSFER_WRITE, @@ -779,7 +848,7 @@ static void* r300_render_map_vertices(struct vbuf_render* render) assert(r300render->vbo_ptr); - return ((uint8_t*)r300render->vbo_ptr + r300render->vbo_offset); + return ((uint8_t*)r300render->vbo_ptr + r300->draw_vbo_offset); } static void r300_render_unmap_vertices(struct vbuf_render* render, @@ -792,6 +861,8 @@ static void r300_render_unmap_vertices(struct vbuf_render* render, assert(r300render->vbo_transfer); + DBG(r300, DBG_DRAW, "r300: render_unmap_vertices\n"); + r300render->vbo_max_used = MAX2(r300render->vbo_max_used, r300render->vertex_size * (max + 1)); pipe_buffer_unmap(context, r300->vbo, r300render->vbo_transfer); @@ -802,8 +873,11 @@ static void r300_render_unmap_vertices(struct vbuf_render* render, static void r300_render_release_vertices(struct vbuf_render* render) { struct r300_render* r300render = r300_render(render); + struct r300_context* r300 = r300render->r300; + + DBG(r300, DBG_DRAW, "r300: render_release_vertices\n"); - r300render->vbo_offset += r300render->vbo_max_used; + r300->draw_vbo_offset += r300render->vbo_max_used; r300render->vbo_max_used = 0; } @@ -831,11 +905,13 @@ static void r300_render_draw_arrays(struct vbuf_render* render, CS_LOCALS(r300); (void) i; (void) ptr; - r300_prepare_for_rendering(r300, PREP_FIRST_DRAW | PREP_EMIT_AOS_SWTCL, - NULL, dwords, 0, 0); - DBG(r300, DBG_DRAW, "r300: render_draw_arrays (count: %d)\n", count); + if (!r300_emit_states(r300, + PREP_FIRST_DRAW | PREP_EMIT_AOS_SWTCL, + NULL, 0, 0)) + return; + /* Uncomment to dump all VBOs rendered through this interface. * Slow and noisy! ptr = pipe_buffer_map(&r300render->r300->context, @@ -871,7 +947,7 @@ static void r300_render_draw_elements(struct vbuf_render* render, struct r300_context* r300 = r300render->r300; int i; unsigned end_cs_dwords; - unsigned max_index = (r300->draw_vbo_size - r300render->vbo_offset) / + unsigned max_index = (r300->draw_vbo_size - r300->draw_vbo_offset) / (r300render->r300->vertex_info.size * 4) - 1; unsigned short_count; unsigned free_dwords; @@ -879,13 +955,14 @@ static void r300_render_draw_elements(struct vbuf_render* render, CS_LOCALS(r300); DBG(r300, DBG_DRAW, "r300: render_draw_elements (count: %d)\n", count); - /* Reserve at least 256 dwords. - * - * Below we manage the CS space manually because there may be more + if (!r300_emit_states(r300, + PREP_FIRST_DRAW | PREP_EMIT_AOS_SWTCL | PREP_INDEXED, + NULL, 0, 0)) + return; + + /* Below we manage the CS space manually because there may be more * indices than it can fit in CS. */ - r300_prepare_for_rendering(r300, - PREP_FIRST_DRAW | PREP_EMIT_AOS_SWTCL | PREP_INDEXED, - NULL, 256, 0, 0); + end_cs_dwords = r300_get_num_cs_end_dwords(r300); while (count) { @@ -914,9 +991,11 @@ static void r300_render_draw_elements(struct vbuf_render* render, count -= short_count; if (count) { - r300_prepare_for_rendering(r300, - PREP_EMIT_AOS_SWTCL | PREP_INDEXED, - NULL, 256, 0, 0); + if (!r300_prepare_for_rendering(r300, + PREP_EMIT_AOS_SWTCL | PREP_INDEXED, + NULL, 256, 0, 0)) + return; + end_cs_dwords = r300_get_num_cs_end_dwords(r300); } } @@ -947,8 +1026,6 @@ static struct vbuf_render* r300_render_create(struct r300_context* r300) r300render->base.release_vertices = r300_render_release_vertices; r300render->base.destroy = r300_render_destroy; - r300render->vbo_offset = 0; - return &r300render->base; } @@ -985,7 +1062,9 @@ void r300_draw_flush_vbuf(struct r300_context *r300) * End of SW TCL functions * ***************************************************************************/ -/* If we used a quad to draw a rectangle, the pixels on the main diagonal +/* This functions is used to draw a rectangle for the blitter module. + * + * If we rendered a quad, the pixels on the main diagonal * would be computed and stored twice, which makes the clear/copy codepaths * somewhat inefficient. Instead we use a rectangular point sprite. */ static void r300_blitter_draw_rectangle(struct blitter_context *blitter, @@ -1015,7 +1094,8 @@ static void r300_blitter_draw_rectangle(struct blitter_context *blitter, r300->clip_state.dirty = FALSE; r300->viewport_state.dirty = FALSE; - r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0); + if (!r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0)) + goto done; DBG(r300, DBG_DRAW, "r300: draw_rectangle\n"); @@ -1059,6 +1139,7 @@ static void r300_blitter_draw_rectangle(struct blitter_context *blitter, } END_CS; +done: /* Restore the state. */ r300->clip_state.dirty = TRUE; r300->rs_state.dirty = TRUE; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 1e4edcdbc31..7f41ff0e2ec 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -120,7 +120,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Unsupported features (boolean caps). */ case PIPE_CAP_TIMER_QUERY: case PIPE_CAP_DUAL_SOURCE_BLEND: - case PIPE_CAP_TGSI_CONT_SUPPORTED: case PIPE_CAP_INDEP_BLEND_ENABLE: case PIPE_CAP_INDEP_BLEND_FUNC: case PIPE_CAP_DEPTH_CLAMP: /* XXX implemented, but breaks Regnum Online */ @@ -146,11 +145,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* General shader limits and features. */ case PIPE_CAP_SM3: return is_r500 ? 1 : 0; - case PIPE_CAP_MAX_CONST_BUFFERS: - return 1; - case PIPE_CAP_MAX_CONST_BUFFER_SIZE: - return 256; - /* Fragment coordinate conventions. */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: @@ -158,19 +152,39 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; + default: + fprintf(stderr, "r300: Implementation error: Bad param %d\n", + param); + return 0; + } +} - /* Fragment shader limits. */ - case PIPE_CAP_MAX_FS_INSTRUCTIONS: +static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param) +{ + struct r300_screen* r300screen = r300_screen(pscreen); + boolean is_r400 = r300screen->caps.is_r400; + boolean is_r500 = r300screen->caps.is_r500; + + /* XXX extended shader capabilities of r400 unimplemented */ + is_r400 = FALSE; + + switch (shader) + { + case PIPE_SHADER_FRAGMENT: + switch (param) + { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: return is_r500 || is_r400 ? 512 : 96; - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: return is_r500 || is_r400 ? 512 : 64; - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: return is_r500 || is_r400 ? 512 : 32; - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: return is_r500 ? 511 : 4; - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return is_r500 ? 64 : 0; /* Actually unlimited on r500. */ - case PIPE_CAP_MAX_FS_INPUTS: + /* Fragment shader limits. */ + case PIPE_SHADER_CAP_MAX_INPUTS: /* 2 colors + 8 texcoords are always supported * (minus fog and wpos). * @@ -178,42 +192,53 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) * additional texcoords but there is no two-sided color * selection then. However the facing bit can be used instead. */ return 10; - case PIPE_CAP_MAX_FS_CONSTS: + case PIPE_SHADER_CAP_MAX_CONSTS: return is_r500 ? 256 : 32; - case PIPE_CAP_MAX_FS_TEMPS: + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: return is_r500 ? 128 : is_r400 ? 64 : 32; - case PIPE_CAP_MAX_FS_ADDRS: + case PIPE_SHADER_CAP_MAX_ADDRS: return 0; - case PIPE_CAP_MAX_FS_PREDS: + case PIPE_SHADER_CAP_MAX_PREDS: return is_r500 ? 1 : 0; - - /* Vertex shader limits. */ - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + } + break; + case PIPE_SHADER_VERTEX: + switch (param) + { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: return is_r500 ? 1024 : 256; - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: return 0; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */ - case PIPE_CAP_MAX_VS_INPUTS: + case PIPE_SHADER_CAP_MAX_INPUTS: return 16; - case PIPE_CAP_MAX_VS_CONSTS: + case PIPE_SHADER_CAP_MAX_CONSTS: return 256; - case PIPE_CAP_MAX_VS_TEMPS: + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: return 32; - case PIPE_CAP_MAX_VS_ADDRS: + case PIPE_SHADER_CAP_MAX_ADDRS: return 1; /* XXX guessed */ - case PIPE_CAP_MAX_VS_PREDS: + case PIPE_SHADER_CAP_MAX_PREDS: return is_r500 ? 4 : 0; /* XXX guessed. */ - case PIPE_CAP_GEOMETRY_SHADER4: - return 0; - + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; default: - fprintf(stderr, "r300: Implementation error: Bad param %d\n", - param); - return 0; + break; + } + break; + default: + break; } + return 0; } static float r300_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) @@ -410,6 +435,7 @@ struct pipe_screen* r300_screen_create(struct r300_winsys_screen *rws) r300screen->screen.get_name = r300_get_name; r300screen->screen.get_vendor = r300_get_vendor; r300screen->screen.get_param = r300_get_param; + r300screen->screen.get_shader_param = r300_get_shader_param; r300screen->screen.get_paramf = r300_get_paramf; r300screen->screen.is_format_supported = r300_is_format_supported; r300screen->screen.context_create = r300_create_context; diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index 13a3320b992..dc2bc7e8279 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -92,11 +92,14 @@ r300_winsys_screen(struct pipe_screen *screen) { #define DBG_RS_BLOCK (1 << 10) #define DBG_CBZB (1 << 11) #define DBG_HYPERZ (1 << 12) +#define DBG_SCISSOR (1 << 13) /* Features. */ #define DBG_ANISOHQ (1 << 16) #define DBG_NO_TILING (1 << 17) #define DBG_NO_IMMD (1 << 18) #define DBG_FAKE_OCC (1 << 19) +#define DBG_NO_OPT (1 << 20) +#define DBG_NO_CBZB (1 << 21) /* Statistics. */ #define DBG_STATS (1 << 24) /*@}*/ diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c index 960dfdbaf03..f9a516825df 100644 --- a/src/gallium/drivers/r300/r300_state_derived.c +++ b/src/gallium/drivers/r300/r300_state_derived.c @@ -477,6 +477,15 @@ static void r300_update_rs_block(struct r300_context *r300) } } + if (DBG_ON(r300, DBG_RS)) { + for (; i < ATTR_GENERIC_COUNT; i++) { + if (fs_inputs->generic[i] != ATTR_UNUSED) { + DBG(r300, DBG_RS, + "r300: FS input generic %i unassigned.\n", i); + } + } + } + /* Rasterize fog coordinates. */ if (vs_outputs->fog != ATTR_UNUSED && tex_count < 8) { /* Set up the fog coordinates in VAP. */ diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 66f6d80bd0c..34105aa4bcd 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -758,18 +758,6 @@ struct pipe_resource *r300_texture_create(struct pipe_screen *screen, struct r300_screen *rscreen = r300_screen(screen); enum r300_buffer_tiling microtile, macrotile; - /* Refuse to create a texture with size 0. */ - if (!base->width0 || - (!base->height0 && (base->target == PIPE_TEXTURE_2D || - base->target == PIPE_TEXTURE_CUBE || - base->target == PIPE_TEXTURE_RECT)) || - (!base->depth0 && base->target == PIPE_TEXTURE_3D)) { - fprintf(stderr, "r300: texture_create: " - "Got invalid texture dimensions: %ix%ix%i\n", - base->width0, base->height0, base->depth0); - return NULL; - } - if ((base->flags & R300_RESOURCE_FLAG_TRANSFER) || (base->bind & PIPE_BIND_SCANOUT)) { microtile = R300_BUFFER_LINEAR; @@ -893,9 +881,11 @@ struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen, surface->cbzb_format = R300_DEPTHFORMAT_16BIT_INT_Z; SCREEN_DBG(r300_screen(screen), DBG_CBZB, - "CBZB Dim: %ix%i, Misalignment: %i, Macro: %s\n", + "CBZB Allowed: %s, Dim: %ix%i, Misalignment: %i, Micro: %s, Macro: %s\n", + surface->cbzb_allowed ? "YES" : " NO", surface->cbzb_width, surface->cbzb_height, offset & 2047, + tex->desc.microtile ? "YES" : " NO", tex->desc.macrotile[level] ? "YES" : " NO"); } diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c index 2fe5d721881..112282a0a6a 100644 --- a/src/gallium/drivers/r300/r300_texture_desc.c +++ b/src/gallium/drivers/r300/r300_texture_desc.c @@ -339,6 +339,9 @@ static void r300_setup_cbzb_flags(struct r300_screen *rscreen, (bpp == 16 || bpp == 32) && desc->macrotile[0]; + if (SCREEN_DBG_ON(rscreen, DBG_NO_CBZB)) + first_level_valid = FALSE; + for (i = 0; i <= desc->b.b.last_level; i++) desc->cbzb_allowed[i] = first_level_valid && desc->macrotile[i]; } diff --git a/src/gallium/drivers/r300/r300_vs.c b/src/gallium/drivers/r300/r300_vs.c index 5f8dbb28d0c..e2b9af9d018 100644 --- a/src/gallium/drivers/r300/r300_vs.c +++ b/src/gallium/drivers/r300/r300_vs.c @@ -199,13 +199,19 @@ void r300_translate_vertex_shader(struct r300_context *r300, unsigned i; /* Setup the compiler */ + memset(&compiler, 0, sizeof(compiler)); rc_init(&compiler.Base); compiler.Base.Debug = DBG_ON(r300, DBG_VP); compiler.code = &vs->code; compiler.UserData = vs; compiler.Base.is_r500 = r300->screen->caps.is_r500; + compiler.Base.disable_optimizations = DBG_ON(r300, DBG_NO_OPT); + compiler.Base.has_half_swizzles = FALSE; + compiler.Base.has_presub = FALSE; compiler.Base.max_temp_regs = 32; + compiler.Base.max_constants = 256; + compiler.Base.max_alu_insts = r300->screen->caps.is_r500 ? 1024 : 256; compiler.Base.remove_unused_constants = TRUE; if (compiler.Base.Debug) { diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile index fc94ae71f4a..a5249e09aa3 100644 --- a/src/gallium/drivers/r600/Makefile +++ b/src/gallium/drivers/r600/Makefile @@ -19,6 +19,9 @@ C_SOURCES = \ r600_state.c \ r600_texture.c \ r600_asm.c \ - r700_asm.c + r700_asm.c \ + r600_hw_states.c \ + eg_asm.c \ + eg_hw_states.c include ../../Makefile.template diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c new file mode 100644 index 00000000000..bc5dda43ed0 --- /dev/null +++ b/src/gallium/drivers/r600/eg_asm.c @@ -0,0 +1,84 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include "r600_asm.h" +#include "r600_context.h" +#include "util/u_memory.h" +#include "eg_sq.h" +#include "r600_opcodes.h" +#include <stdio.h> +#include <errno.h> + +int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf) +{ + unsigned id = cf->id; + + switch (cf->inst) { + case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3): + case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3): + bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) | + S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode); + bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) | + S_SQ_CF_ALU_WORD1_BARRIER(1) | + S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); + break; + case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX: + bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1); + bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) | + S_SQ_CF_WORD1_BARRIER(1) | + S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1); + break; + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT: + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE: + bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) | + S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) | + S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) | + S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type); + bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) | + S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) | + S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) | + S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program); + break; + case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK: + bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1); + bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) | + S_SQ_CF_WORD1_BARRIER(1) | + S_SQ_CF_WORD1_COND(cf->cond) | + S_SQ_CF_WORD1_POP_COUNT(cf->pop_count); + + break; + default: + R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst); + return -EINVAL; + } + return 0; +} diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c new file mode 100644 index 00000000000..621e36e1bbe --- /dev/null +++ b/src/gallium/drivers/r600/eg_hw_states.c @@ -0,0 +1,1070 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Dave Airlie + */ +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include <util/u_blitter.h> +#include "util/u_pack_color.h" +#include "r600_screen.h" +#include "r600_context.h" +#include "r600_resource.h" +#include "eg_state_inlines.h" +#include "evergreend.h" + +#include "eg_states_inc.h" + +static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + int i; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0); + rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]); + rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]); + rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]); + rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]); + rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000; + rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000; + + for (i = 0; i < 8; i++) { + unsigned eqRGB = state->rt[i].rgb_func; + unsigned srcRGB = state->rt[i].rgb_src_factor; + unsigned dstRGB = state->rt[i].rgb_dst_factor; + + unsigned eqA = state->rt[i].alpha_func; + unsigned srcA = state->rt[i].alpha_src_factor; + unsigned dstA = state->rt[i].alpha_dst_factor; + uint32_t bc = 0; + + if (!state->rt[i].blend_enable) + continue; + + bc |= S_028780_BLEND_CONTROL_ENABLE(1); + + bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); + bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); + bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); + + if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { + bc |= S_028780_SEPARATE_ALPHA_BLEND(1); + bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); + bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); + bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); + } + + rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc; + } + + radeon_state_pm4(rstate); +} + +static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_clip_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0); + + for (int i = 0; i < state->nr; i++) { + rstate->states[i * 4 + 0] = fui(state->ucp[i][0]); + rstate->states[i * 4 + 1] = fui(state->ucp[i][1]); + rstate->states[i * 4 + 2] = fui(state->ucp[i][2]); + rstate->states[i * 4 + 3] = fui(state->ucp[i][3]); + } + radeon_state_pm4(rstate); +} + +static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state, int cb) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_resource_texture *rtex; + struct r600_resource *rbuffer; + unsigned level = state->cbufs[cb]->level; + unsigned pitch, slice; + unsigned color_info; + unsigned format, swap, ntype; + const struct util_format_description *desc; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0); + rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; + rbuffer = &rtex->resource; + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; + rstate->nbo = 1; + pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; + slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1; + + ntype = 0; + desc = util_format_description(rtex->resource.base.b.format); + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) + ntype = V_028C70_NUMBER_SRGB; + + format = r600_translate_colorformat(rtex->resource.base.b.format); + swap = r600_translate_colorswap(rtex->resource.base.b.format); + + color_info = S_028C70_FORMAT(format) | + S_028C70_COMP_SWAP(swap) | + S_028C70_BLEND_CLAMP(1) | + S_028C70_SOURCE_FORMAT(1) | + S_028C70_NUMBER_TYPE(ntype); + + rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8; + rstate->states[EG_CB__CB_COLOR0_INFO] = color_info; + rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch); + rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice); + rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000; + rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1); + + radeon_state_pm4(rstate); +} + +static void eg_db(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_resource_texture *rtex; + struct r600_resource *rbuffer; + unsigned level; + unsigned pitch, slice, format; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0); + if (state->zsbuf == NULL) + return; + + rtex = (struct r600_resource_texture*)state->zsbuf->texture; + rtex->tilled = 1; + rtex->array_mode = 2; + rtex->tile_type = 1; + rtex->depth = 1; + rbuffer = &rtex->resource; + + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->nbo = 1; + rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; + level = state->zsbuf->level; + pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; + slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1; + format = r600_translate_dbformat(state->zsbuf->texture->format); + rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8; + rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8; + rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8; + rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8; + rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8; + rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format); + rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000; + rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch); + rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice); + radeon_state_pm4(rstate); +} + +static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer; + const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; + const struct pipe_clip_state *clip = NULL; + struct r600_screen *rscreen = rctx->screen; + float offset_units = 0, offset_scale = 0; + char depth = 0; + unsigned offset_db_fmt_cntl = 0; + unsigned tmp; + unsigned prov_vtx = 1; + + if (rctx->clip) + clip = &rctx->clip->state.clip; + if (fb->zsbuf) { + offset_units = state->offset_units; + offset_scale = state->offset_scale * 12.0f; + switch (fb->zsbuf->texture->format) { + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + depth = -24; + offset_units *= 2.0f; + break; + case PIPE_FORMAT_Z32_FLOAT: + depth = -23; + offset_units *= 1.0f; + offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); + break; + case PIPE_FORMAT_Z16_UNORM: + depth = -16; + offset_units *= 4.0f; + break; + default: + R600_ERR("unsupported %d\n", fb->zsbuf->texture->format); + return; + } + } + offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); + + if (state->flatshade_first) + prov_vtx = 0; + + rctx->flat_shade = state->flatshade; + radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0); + rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000; + if (rctx->flat_shade) + rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1); + if (state->sprite_coord_enable) { + rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= + S_0286D4_PNT_SPRITE_ENA(1) | + S_0286D4_PNT_SPRITE_OVRD_X(2) | + S_0286D4_PNT_SPRITE_OVRD_Y(3) | + S_0286D4_PNT_SPRITE_OVRD_Z(0) | + S_0286D4_PNT_SPRITE_OVRD_W(1); + if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { + rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= + S_0286D4_PNT_SPRITE_TOP_1(1); + } + } + rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0; + if (clip) { + rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1); + rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp); + rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp); + } + rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] = + S_028814_PROVOKING_VTX_LAST(prov_vtx) | + S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | + S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | + S_028814_FACE(!state->front_ccw) | + S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri); + rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] = + S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | + S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); + rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; + /* point size 12.4 fixed point */ + tmp = (unsigned)(state->point_size * 8.0); + rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp); + rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; + rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; + rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005; + + rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; + rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; + rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; + rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; + rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; + rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl; + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale); + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units); + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale); + rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units); + radeon_state_pm4(rstate); +} + +static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_scissor_state *state = &rctx->scissor->state.scissor; + const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; + struct r600_screen *rscreen = rctx->screen; + unsigned minx, maxx, miny, maxy; + u32 tl, br; + + if (state == NULL) { + minx = 0; + miny = 0; + maxx = fb->cbufs[0]->width; + maxy = fb->cbufs[0]->height; + } else { + minx = state->minx; + miny = state->miny; + maxx = state->maxx; + maxy = state->maxy; + } + tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny); + br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy); + radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0); + /* screen scissor has no WINDOW OFFSET */ + rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; + rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; + rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1); + rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; + rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; + rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1); + rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; + rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1); + rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; + radeon_state_pm4(rstate); +} + +static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0); + rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; + rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; + rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); + rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); + rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); + rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); + rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); + rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); + rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; + radeon_state_pm4(rstate); +} + +static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; + const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref; + struct r600_screen *rscreen = rctx->screen; + unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; + unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control; + struct r600_shader *rshader; + struct r600_query *rquery = NULL; + boolean query_running; + int i; + + if (rctx->ps_shader == NULL) { + return; + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0); + + db_shader_control = 0x210; + rshader = &rctx->ps_shader->shader; + if (rshader->uses_kill) + db_shader_control |= (1 << 6); + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) + db_shader_control |= 1; + } + stencil_ref_mask = 0; + stencil_ref_mask_bf = 0; + db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | + S_028800_Z_WRITE_ENABLE(state->depth.writemask) | + S_028800_ZFUNC(state->depth.func); + /* set stencil enable */ + + if (state->stencil[0].enabled) { + db_depth_control |= S_028800_STENCIL_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); + db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); + db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); + db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); + + stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | + S_028430_STENCILWRITEMASK(state->stencil[0].writemask); + stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); + if (state->stencil[1].enabled) { + db_depth_control |= S_028800_BACKFACE_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); + db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); + db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); + db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); + stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | + S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); + stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); + } + } + + alpha_test_control = 0; + alpha_ref = 0; + if (state->alpha.enabled) { + alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); + alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); + alpha_ref = fui(state->alpha.ref_value); + } + + db_render_control = 0; +/// db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) | +/// S_028D0C_DEPTH_COMPRESS_DISABLE(1); + db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | + S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | + S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); + + query_running = false; + + LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) { + if (rquery->state & R600_QUERY_STATE_STARTED) { + query_running = true; + } + } + + if (query_running) { + db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); + db_render_control |= S_028D0C_PERFECT_ZPASS_COUNTS(1); + } + + rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000; + rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000; + rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control; + rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask; + rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf; + rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref; + // rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; + // rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; + rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000; + rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control; + rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control; + rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control; + rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override; + + rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; + rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000; + rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; + radeon_state_pm4(rstate); +} + + +static INLINE u32 S_FIXED(float value, u32 frac_bits) +{ + return value * (1 << frac_bits); +} + +static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id) +{ + struct r600_screen *rscreen = rctx->screen; + union util_color uc; + + util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + + radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS); + if (uc.ui) { + rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]); + rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]); + rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]); + rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]); + } + radeon_state_pm4(rstate); +} + +static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id) +{ + struct r600_screen *rscreen = rctx->screen; + union util_color uc; + + util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + + radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS); + rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = + S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | + S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | + S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | + S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | + S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | + S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | + S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | + S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); + /* FIXME LOD it depends on texture base level ... */ + rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] = + S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | + S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)); + + rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = + S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) | +S_03C008_TYPE(1); + radeon_state_pm4(rstate); + +} + + +static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate, + const struct pipe_sampler_view *view, unsigned id) +{ + struct r600_context *rctx = r600_context(ctx); + struct r600_screen *rscreen = rctx->screen; + const struct util_format_description *desc; + struct r600_resource_texture *tmp; + struct r600_resource *rbuffer; + unsigned format; + uint32_t word4 = 0, yuv_format = 0, pitch = 0; + unsigned char swizzle[4]; + int r; + + rstate->cpm4 = 0; + swizzle[0] = view->swizzle_r; + swizzle[1] = view->swizzle_g; + swizzle[2] = view->swizzle_b; + swizzle[3] = view->swizzle_a; + format = r600_translate_texformat(view->texture->format, + swizzle, + &word4, &yuv_format); + if (format == ~0) { + return; + } + desc = util_format_description(view->texture->format); + if (desc == NULL) { + R600_ERR("unknow format %d\n", view->texture->format); + return; + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS); + tmp = (struct r600_resource_texture*)view->texture; + rbuffer = &tmp->resource; + if (tmp->depth) { + r = r600_texture_from_depth(ctx, tmp, view->first_level); + if (r) { + return; + } + rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); + rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); + } else { + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + } + rstate->nbo = 2; + rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; + + pitch = (tmp->pitch[0] / tmp->bpt); + pitch = (pitch + 0x7) & ~0x7; + + /* FIXME properly handle first level != 0 */ + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = + S_030000_DIM(r600_tex_dim(view->texture->target)) | + S_030000_PITCH((pitch / 8) - 1) | + S_030000_TEX_WIDTH(view->texture->width0 - 1); + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = + S_030004_TEX_HEIGHT(view->texture->height0 - 1) | + S_030004_TEX_DEPTH(view->texture->depth0 - 1); + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8; + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = + word4 | + S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) | + S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) | + S_030010_REQUEST_SIZE(1) | + S_030010_BASE_LEVEL(view->first_level); + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = + S_030014_LAST_LEVEL(view->last_level) | + S_030014_BASE_ARRAY(0) | + S_030014_LAST_ARRAY(0); + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0; + rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = + S_03001C_DATA_FORMAT(format) | + S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE); + radeon_state_pm4(rstate); +} + +static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) +{ + struct r600_screen *rscreen = rctx->screen; + const struct pipe_blend_state *pbs = &rctx->blend->state.blend; + int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs; + uint32_t color_control, target_mask, shader_mask; + int i; + + target_mask = 0; + shader_mask = 0; + color_control = S_028808_MODE(1); + + for (i = 0; i < nr_cbufs; i++) { + shader_mask |= 0xf << (i * 4); + } + + if (pbs->logicop_enable) { + color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20); + } else { + color_control |= (0xcc << 16); + } + + if (pbs->independent_blend_enable) { + for (i = 0; i < nr_cbufs; i++) { + target_mask |= (pbs->rt[i].colormask << (4 * i)); + } + } else { + for (i = 0; i < nr_cbufs; i++) { + target_mask |= (pbs->rt[0].colormask << (4 * i)); + } + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0); + rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask; + rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask; + rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control; + rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; + rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; + rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; + radeon_state_pm4(rstate); +} + + +static void eg_init_config(struct r600_context *rctx) +{ + int ps_prio; + int vs_prio; + int gs_prio; + int es_prio; + int hs_prio, cs_prio, ls_prio; + int num_ps_gprs; + int num_vs_gprs; + int num_gs_gprs; + int num_es_gprs; + int num_hs_gprs; + int num_ls_gprs; + int num_temp_gprs; + int num_ps_threads; + int num_vs_threads; + int num_gs_threads; + int num_es_threads; + int num_hs_threads; + int num_ls_threads; + int num_ps_stack_entries; + int num_vs_stack_entries; + int num_gs_stack_entries; + int num_es_stack_entries; + int num_hs_stack_entries; + int num_ls_stack_entries; + enum radeon_family family; + + family = radeon_get_family(rctx->rw); + ps_prio = 0; + vs_prio = 1; + gs_prio = 2; + es_prio = 3; + hs_prio = 0; + ls_prio = 0; + cs_prio = 0; + + switch (family) { + case CHIP_CEDAR: + default: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 96; + num_vs_threads = 16; + num_gs_threads = 16; + num_es_threads = 16; + num_hs_threads = 16; + num_ls_threads = 16; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; + case CHIP_REDWOOD: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 42; + num_vs_stack_entries = 42; + num_gs_stack_entries = 42; + num_es_stack_entries = 42; + num_hs_stack_entries = 42; + num_ls_stack_entries = 42; + break; + case CHIP_JUNIPER: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 85; + num_vs_stack_entries = 85; + num_gs_stack_entries = 85; + num_es_stack_entries = 85; + num_hs_stack_entries = 85; + num_ls_stack_entries = 85; + break; + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + num_ps_gprs = 93; + num_vs_gprs = 46; + num_temp_gprs = 4; + num_gs_gprs = 31; + num_es_gprs = 31; + num_hs_gprs = 23; + num_ls_gprs = 23; + num_ps_threads = 128; + num_vs_threads = 20; + num_gs_threads = 20; + num_es_threads = 20; + num_hs_threads = 20; + num_ls_threads = 20; + num_ps_stack_entries = 85; + num_vs_stack_entries = 85; + num_gs_stack_entries = 85; + num_es_stack_entries = 85; + num_hs_stack_entries = 85; + num_ls_stack_entries = 85; + break; + } + + radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0); + + rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000; + switch (family) { + case CHIP_CEDAR: + break; + default: + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1); + break; + } + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio); + rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio); + + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0; + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs); + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs); + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); + + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0; + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs); + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs); + + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0; + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs); + rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs); + + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0; + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads); + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads); + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads); + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads); + + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0; + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads); + rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads); + + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0; + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); + + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0; + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries); + + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0; + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries); + rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries); + + rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4); + + rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000; + + rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000; + rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0; + rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0; + + rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000; + + rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000; + rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000; + + rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000; + rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001; + rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000; +// rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2; +// rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16; + rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1; + + radeon_state_pm4(&rctx->config); +} + +static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset, + uint32_t stride, uint32_t format) +{ + struct radeon_state *vs_resource = &rctx->vs_resource[id]; + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS); + vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + vs_resource->nbo = 1; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) | + S_030008_DATA_FORMAT(format); + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) | + S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) | + S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) | + S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W); + + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000; + vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000; + vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT; + vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(vs_resource); +} + +static int eg_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw, + struct r600_resource *rbuffer, + uint32_t count, int vgt_draw_initiator) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0); + draw->states[EG_DRAW__VGT_NUM_INDICES] = count; + draw->states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; + if (rbuffer) { + draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + draw->placement[0] = RADEON_GEM_DOMAIN_GTT; + draw->placement[1] = RADEON_GEM_DOMAIN_GTT; + draw->nbo = 1; + } + return radeon_state_pm4(draw); +} + +static int eg_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt, + uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type) +{ + struct r600_screen *rscreen = rctx->screen; + radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0); + vgt->states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim; + vgt->states[EG_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; + vgt->states[EG_VGT__VGT_MIN_VTX_INDX] = 0x00000000; + vgt->states[EG_VGT__VGT_INDX_OFFSET] = start; + vgt->states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type; + vgt->states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000; + vgt->states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; + vgt->states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000; + vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000; + vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000; + return radeon_state_pm4(vgt); +} + + +static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader, + struct radeon_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + const struct pipe_rasterizer_state *rasterizer; + struct r600_shader *rshader = &rpshader->shader; + unsigned i, tmp, exports_ps, num_cout; + boolean have_pos = FALSE; + + rasterizer = &rctx->rasterizer->state.rasterizer; + + radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS); + for (i = 0; i < rshader->ninput; i++) { + tmp = S_028644_SEMANTIC(i); + tmp |= S_028644_SEL_CENTROID(1); + if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) + have_pos = TRUE; + if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || + rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || + rshader->input[i].name == TGSI_SEMANTIC_POSITION) { + tmp |= S_028644_FLAT_SHADE(rshader->flat_shade); + } + if (rasterizer->sprite_coord_enable & (1 << i)) { + tmp |= S_028644_PT_SPRITE_TEX(1); + } + state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp; + } + + exports_ps = 0; + num_cout = 0; + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) + exports_ps |= 1; + else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { + exports_ps |= (1 << (num_cout+1)); + num_cout++; + } + } + if (!exports_ps) { + /* always at least export 1 component per pixel */ + exports_ps = 2; + } + state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) | + S_0286CC_PERSP_GRADIENT_ENA(1); + if (have_pos) { + state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1); + state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1; + } + state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000; + state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) | + S_028844_STACK_SIZE(rshader->bc.nstack); + state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps; + state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) | + S_0286E0_LINEAR_CENTROID_ENA(1); + state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->nbo = 1; + state->placement[0] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader, + struct radeon_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_shader *rshader = &rpshader->shader; + unsigned i, tmp; + + radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS); + for (i = 0; i < 10; i++) { + state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0; + } + /* so far never got proper semantic id from tgsi */ + for (i = 0; i < 32; i++) { + tmp = i << ((i & 3) * 8); + state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp; + } + state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2); + state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) | + S_028860_STACK_SIZE(rshader->bc.nstack); + state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->nbo = 2; + state->placement[0] = RADEON_GEM_DOMAIN_GTT; + state->placement[2] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +struct r600_context_hw_state_vtbl eg_hw_state_vtbl = { + .blend = eg_blend, + .ucp = eg_ucp, + .cb = eg_cb, + .db = eg_db, + .rasterizer = eg_rasterizer, + .scissor = eg_scissor, + .viewport = eg_viewport, + .dsa = eg_dsa, + .sampler_border = eg_sampler_border, + .sampler = eg_sampler, + .resource = eg_resource, + .cb_cntl = eg_cb_cntl, + .vs_resource = eg_vs_resource, + .vgt_init = eg_draw_vgt_init, + .vgt_prim = eg_draw_vgt_prim, + .vs_shader = eg_vs_shader, + .ps_shader = eg_ps_shader, + .init_config = eg_init_config, +}; + +void eg_set_constant_buffer(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer) +{ + struct r600_screen *rscreen = r600_screen(ctx->screen); + struct r600_context *rctx = r600_context(ctx); + unsigned nconstant = 0, type, shader_class, size; + struct radeon_state *rstate, *rstates; + struct r600_resource *rbuffer = (struct r600_resource*)buffer; + + type = R600_STATE_CBUF; + + switch (shader) { + case PIPE_SHADER_VERTEX: + shader_class = R600_SHADER_VS; + rstates = rctx->vs_constant; + break; + case PIPE_SHADER_FRAGMENT: + shader_class = R600_SHADER_PS; + rstates = rctx->ps_constant; + break; + default: + R600_ERR("unsupported %d\n", shader); + return; + } + + rstate = &rstates[0]; + +#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) + nconstant = buffer->width0 / 16; + size = ALIGN_DIVUP(nconstant, 16); + + radeon_state_init(rstate, rscreen->rw, type, 0, shader_class); + rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size; + rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0; + + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->nbo = 1; + rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; + if (radeon_state_pm4(rstate)) + return; + radeon_draw_bind(&rctx->draw, rstate); +} diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h new file mode 100644 index 00000000000..f80e8bd3aaf --- /dev/null +++ b/src/gallium/drivers/r600/eg_sq.h @@ -0,0 +1,485 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef EG_SQ_H +#define EG_SQ_H + +#define P_SQ_CF_WORD0 +#define S_SQ_CF_WORD0_ADDR(x) (((x) & 0xFFFFFF) << 0) +#define G_SQ_CF_WORD0_ADDR(x) (((x) >> 0) & 0xFFFFFF) +#define C_SQ_CF_WORD0_ADDR 0x00000000 +#define S_SQ_CF_WORD0_JUMPTABLE_SEL(x) (((x) & 0x7) << 24) +#define G_SQ_CF_WORD0_JUMPTABLE_SEL(x) (((x) >> 24) & 0x7) +#define C_SQ_CF_WORD0_JUMPTABLE_SEL 0xF8FFFFFF +#define P_SQ_CF_WORD1 +#define S_SQ_CF_WORD1_POP_COUNT(x) (((x) & 0x7) << 0) +#define G_SQ_CF_WORD1_POP_COUNT(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_WORD1_POP_COUNT 0xFFFFFFF8 +#define S_SQ_CF_WORD1_CF_CONST(x) (((x) & 0x1F) << 3) +#define G_SQ_CF_WORD1_CF_CONST(x) (((x) >> 3) & 0x1F) +#define C_SQ_CF_WORD1_CF_CONST 0xFFFFFF07 +#define S_SQ_CF_WORD1_COND(x) (((x) & 0x3) << 8) +#define G_SQ_CF_WORD1_COND(x) (((x) >> 8) & 0x3) +#define C_SQ_CF_WORD1_COND 0xFFFFFCFF +#define S_SQ_CF_WORD1_COUNT(x) (((x) & 0x3f) << 10) +#define G_SQ_CF_WORD1_COUNT(x) (((x) >> 10) & 0x3f) +#define C_SQ_CF_WORD1_COUNT 0xFFFF03FF +#define S_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 20) +#define G_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) >> 20) & 0x1) +#define C_SQ_CF_WORD1_VALID_PIXEL_MODE 0xFFEFFFFF +#define S_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_WORD1_END_OF_PROGRAM 0xFFDFFFFF + +#define S_SQ_CF_WORD1_CF_INST(x) (((x) & 0xFF) << 22) +#define G_SQ_CF_WORD1_CF_INST(x) (((x) >> 22) & 0xFF) +#define C_SQ_CF_WORD1_CF_INST 0xC03FFFFF + +#define S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_WORD1_BARRIER 0x7FFFFFFF + +/* done */ +#define P_SQ_CF_ALU_WORD0 +#define S_SQ_CF_ALU_WORD0_ADDR(x) (((x) & 0x3FFFFF) << 0) +#define G_SQ_CF_ALU_WORD0_ADDR(x) (((x) >> 0) & 0x3FFFFF) +#define C_SQ_CF_ALU_WORD0_ADDR 0xFFC00000 +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) & 0xF) << 22) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) >> 22) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK0 0xFC3FFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK1 0xC3FFFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALU_WORD0_KCACHE_MODE0 0x3FFFFFFF +#define P_SQ_CF_ALU_WORD1 +#define S_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) & 0x3) << 0) +#define G_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) >> 0) & 0x3) +#define C_SQ_CF_ALU_WORD1_KCACHE_MODE1 0xFFFFFFFC +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) & 0xFF) << 2) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR0 0xFFFFFC03 +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) & 0xFF) << 10) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR1 0xFFFC03FF +#define S_SQ_CF_ALU_WORD1_COUNT(x) (((x) & 0x7F) << 18) +#define G_SQ_CF_ALU_WORD1_COUNT(x) (((x) >> 18) & 0x7F) +#define C_SQ_CF_ALU_WORD1_COUNT 0xFE03FFFF +#define S_SQ_CF_ALU_WORD1_ALT_CONST(x) (((x) & 0x1) << 25) +#define G_SQ_CF_ALU_WORD1_ALT_CONST(x) (((x) >> 25) & 0x1) +#define C_SQ_CF_ALU_WORD1_ALT_CONST 0xFDFFFFFF +#define S_SQ_CF_ALU_WORD1_CF_INST(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD1_CF_INST(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD1_CF_INST 0xC3FFFFFF +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED 0x0000000C +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F +#define S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALU_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALU_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALU_WORD1_BARRIER 0x7FFFFFFF +/* extended TODO */ +/* done */ +#define P_SQ_CF_ALLOC_EXPORT_WORD0 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) & 0x1FFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE 0xFFFFE000 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) & 0x3) << 13) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) >> 13) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_TYPE 0xFFFF9FFF +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL 0x00000000 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS 0x00000001 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM 0x00000002 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK 0x00000003 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) & 0x7F) << 15) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) >> 15) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR 0xFFC07FFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) & 0x1) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL 0xFFBFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR 0xC07FFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE 0x3FFFFFFF +/* done */ +#define P_SQ_CF_ALLOC_EXPORT_WORD1 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) & 0xF) << 16) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) >> 16) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT 0xFFF0FFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 20) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) >> 20) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE 0xFFEFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM 0xFFDFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) & 0xFF) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) >> 22) & 0xFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST 0xC03FFFFF + +#define S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER 0x7FFFFFFF + +/* done */ +#define P_SQ_CF_ALLOC_EXPORT_WORD1_BUF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) & 0xFFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE 0xFFFFF000 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) & 0xF) << 12) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) >> 12) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK 0xFFFF0FFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) & 0x7) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X 0xFFFFFFF8 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) & 0x7) << 3) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) >> 3) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y 0xFFFFFFC7 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) & 0x7) << 6) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) >> 6) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z 0xFFFFFE3F +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) & 0x7) << 9) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) >> 9) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W 0xFFFFF1FF + +/* done */ +#define P_SQ_ALU_WORD0 +#define S_SQ_ALU_WORD0_SRC0_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD0_SRC0_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC0_SEL 0xFFFFFE00 + +/* + * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+) + * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+) + * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+) + * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+) + * 248 SQ_ALU_SRC_0: special constant 0.0. + * 249 SQ_ALU_SRC_1: special constant 1.0 float. + * 250 SQ_ALU_SRC_1_INT: special constant 1 integer. + * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer. + * 252 SQ_ALU_SRC_0_5: special constant 0.5 float. + * 253 SQ_ALU_SRC_LITERAL: literal constant. + * 254 SQ_ALU_SRC_PV: previous vector result. + * 255 SQ_ALU_SRC_PS: previous scalar result. + */ +#define V_SQ_ALU_SRC_0 0x000000F8 +#define V_SQ_ALU_SRC_1 0x000000F9 +#define V_SQ_ALU_SRC_1_INT 0x000000FA +#define V_SQ_ALU_SRC_M_1_INT 0x000000FB +#define V_SQ_ALU_SRC_0_5 0x000000FC +#define V_SQ_ALU_SRC_LITERAL 0x000000FD +#define S_SQ_ALU_WORD0_SRC0_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD0_SRC0_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD0_SRC0_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD0_SRC0_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD0_SRC0_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD0_SRC1_SEL(x) (((x) & 0x1FF) << 13) +#define G_SQ_ALU_WORD0_SRC1_SEL(x) (((x) >> 13) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC1_SEL 0xFFC01FFF +#define S_SQ_ALU_WORD0_SRC1_REL(x) (((x) & 0x1) << 22) +#define G_SQ_ALU_WORD0_SRC1_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_REL 0xFFBFFFFF +#define S_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) & 0x3) << 23) +#define G_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) >> 23) & 0x3) +#define C_SQ_ALU_WORD0_SRC1_CHAN 0xFE7FFFFF +#define S_SQ_ALU_WORD0_SRC1_NEG(x) (((x) & 0x1) << 25) +#define G_SQ_ALU_WORD0_SRC1_NEG(x) (((x) >> 25) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_NEG 0xFDFFFFFF +#define S_SQ_ALU_WORD0_INDEX_MODE(x) (((x) & 0x7) << 26) +#define G_SQ_ALU_WORD0_INDEX_MODE(x) (((x) >> 26) & 0x7) +#define C_SQ_ALU_WORD0_INDEX_MODE 0xE3FFFFFF +#define S_SQ_ALU_WORD0_PRED_SEL(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD0_PRED_SEL(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD0_PRED_SEL 0x9FFFFFFF +#define S_SQ_ALU_WORD0_LAST(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD0_LAST(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD0_LAST 0x7FFFFFFF +/* same */ +#define P_SQ_ALU_WORD1 +#define S_SQ_ALU_WORD1_ENCODING(x) (((x) & 0x7) << 15) +#define G_SQ_ALU_WORD1_ENCODING(x) (((x) >> 15) & 0x7) +#define C_SQ_ALU_WORD1_ENCODING 0xFFFC7FFF +#define S_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) & 0x7) << 18) +#define G_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) >> 18) & 0x7) +#define C_SQ_ALU_WORD1_BANK_SWIZZLE 0xFFE3FFFF +#define S_SQ_ALU_WORD1_DST_GPR(x) (((x) & 0x7F) << 21) +#define G_SQ_ALU_WORD1_DST_GPR(x) (((x) >> 21) & 0x7F) +#define C_SQ_ALU_WORD1_DST_GPR 0xF01FFFFF +#define S_SQ_ALU_WORD1_DST_REL(x) (((x) & 0x1) << 28) +#define G_SQ_ALU_WORD1_DST_REL(x) (((x) >> 28) & 0x1) +#define C_SQ_ALU_WORD1_DST_REL 0xEFFFFFFF +#define S_SQ_ALU_WORD1_DST_CHAN(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD1_DST_CHAN(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD1_DST_CHAN 0x9FFFFFFF +#define S_SQ_ALU_WORD1_CLAMP(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD1_CLAMP(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD1_CLAMP 0x7FFFFFFF +/* same except maybe encoding */ +#define P_SQ_ALU_WORD1_OP2 +#define S_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) & 0x1) << 0) +#define G_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) >> 0) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC0_ABS 0xFFFFFFFE +#define S_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) & 0x1) << 1) +#define G_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) >> 1) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC1_ABS 0xFFFFFFFD +#define S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) +#define G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK 0xFFFFFFFB +#define S_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) & 0x1) << 3) +#define G_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) >> 3) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_PRED 0xFFFFFFF7 +#define S_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) & 0x1) << 4) +#define G_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) >> 4) & 0x1) +#define C_SQ_ALU_WORD1_OP2_WRITE_MASK 0xFFFFFFEF +#define S_SQ_ALU_WORD1_OP2_OMOD(x) (((x) & 0x3) << 5) +#define G_SQ_ALU_WORD1_OP2_OMOD(x) (((x) >> 5) & 0x3) +#define C_SQ_ALU_WORD1_OP2_OMOD 0xFFFFFF9F +#define S_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) & 0x7FF) << 7) +#define G_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) >> 7) & 0x7FF) +#define C_SQ_ALU_WORD1_OP2_ALU_INST 0xFFFC007F + +#define P_SQ_ALU_WORD1_OP3 +#define S_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD1_OP3_SRC2_SEL 0xFFFFFE00 +#define S_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD1_OP3_SRC2_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) & 0x1F) << 13) +#define G_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) >> 13) & 0x1F) +#define C_SQ_ALU_WORD1_OP3_ALU_INST 0xFFFC1FFF +/* TODO ADD OTHER OP3 */ +/* done */ +#define P_SQ_VTX_WORD0 +#define S_SQ_VTX_WORD0_VTX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_VTX_WORD0_VTX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_VTX_WORD0_VTX_INST 0xFFFFFFE0 +#define S_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) & 0x3) << 5) +#define G_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) >> 5) & 0x3) +#define C_SQ_VTX_WORD0_FETCH_TYPE 0xFFFFFF9F +#define S_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_VTX_WORD0_BUFFER_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_VTX_WORD0_BUFFER_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_VTX_WORD0_BUFFER_ID 0xFFFF00FF +#define S_SQ_VTX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_VTX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_VTX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_VTX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_VTX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_VTX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) & 0x3) << 24) +#define G_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) >> 24) & 0x3) +#define C_SQ_VTX_WORD0_SRC_SEL_X 0xFCFFFFFF +#define S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26) +#define G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F) +#define C_SQ_VTX_WORD0_MEGA_FETCH_COUNT 0x03FFFFFF +/* same WORD 0 */ +#define P_SQ_VTX_WORD1 +#define S_SQ_VTX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_VTX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_VTX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_VTX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) & 0x1) << 21) +#define G_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1) +#define C_SQ_VTX_WORD1_USE_CONST_FIELDS 0xFFDFFFFF +#define S_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) & 0x3F) << 22) +#define G_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) >> 22) & 0x3F) +#define C_SQ_VTX_WORD1_DATA_FORMAT 0xF03FFFFF +#define S_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28) +#define G_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3) +#define C_SQ_VTX_WORD1_NUM_FORMAT_ALL 0xCFFFFFFF +#define S_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30) +#define G_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1) +#define C_SQ_VTX_WORD1_FORMAT_COMP_ALL 0xBFFFFFFF +#define S_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) & 0x1) << 31) +#define G_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) >> 31) & 0x1) +#define C_SQ_VTX_WORD1_SRF_MODE_ALL 0x7FFFFFFF +/* same WORD1 generic */ +#define P_SQ_VTX_WORD1_GPR +#define S_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_VTX_WORD1_GPR_DST_GPR 0xFFFFFF80 +#define S_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD1_GPR_DST_REL 0xFFFFFF7F +#define P_SQ_VTX_WORD1_SEM +#define S_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) & 0xFF) << 0) +#define G_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) >> 0) & 0xFF) +#define C_SQ_VTX_WORD1_SEM_SEMANTIC_ID 0xFFFFFF00 +#define P_SQ_VTX_WORD2 +#define S_SQ_VTX_WORD2_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_SQ_VTX_WORD2_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_SQ_VTX_WORD2_OFFSET 0xFFFF0000 +#define S_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) & 0x3) << 16) +#define G_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) >> 16) & 0x3) +#define C_SQ_VTX_WORD2_ENDIAN_SWAP 0xFFFCFFFF +#define S_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18) +#define G_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1) +#define C_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE 0xFFFBFFFF +#define S_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) & 0x1) << 19) +#define G_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) >> 19) & 0x1) +#define C_SQ_VTX_WORD2_MEGA_FETCH 0xFFF7FFFF +#define S_SQ_VTX_WORD2_ALT_CONST(x) (((x) & 0x1) << 20) +#define G_SQ_VTX_WORD2_ALT_CONST(x) (((x) >> 20) & 0x1) +#define C_SQ_VTX_WORD2_ALT_CONST 0xFFEFFFFF +#define S_SQ_VTX_WORD2_BIM(x) (((x) & 0x3) << 21) +#define G_SQ_VTX_WORD2_BIM(x) (((x) >> 21) & 0x3) +#define C_SQ_VTX_WORD2_BIM 0xFF9FFFFF +/* done */ + +#define P_SQ_TEX_WORD0 +#define S_SQ_TEX_WORD0_TEX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD0_TEX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD0_TEX_INST 0xFFFFFFE0 +#define S_SQ_TEX_WORD0_INST_MOD(x) (((x) & 0x3) << 5) +#define G_SQ_TEX_WORD0_INST_MOD(x) (((x) >> 5) & 0x3) +#define C_SQ_TEX_WORD0_INST_MOD 0xFFFFFF9F +#define S_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_TEX_WORD0_RESOURCE_ID 0xFFFF00FF +#define S_SQ_TEX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_TEX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_TEX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_TEX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_TEX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_TEX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_TEX_WORD0_ALT_CONST(x) (((x) & 0x1) << 24) +#define G_SQ_TEX_WORD0_ALT_CONST(x) (((x) >> 24) & 0x1) +#define C_SQ_TEX_WORD0_ALT_CONST 0xFEFFFFFF +#define S_SQ_TEX_WORD0_RIM(x) (((x) & 0x3) << 25) +#define G_SQ_TEX_WORD0_RIM(x) (((x) >> 25) & 0x3) +#define C_SQ_TEX_WORD0_RIM 0xF9FFFFFF +#define S_SQ_TEX_WORD0_SIM(x) (((x) & 0x3) << 27) +#define G_SQ_TEX_WORD0_SIM(x) (((x) >> 27) & 0x3) +#define C_SQ_TEX_WORD0_SIM 0xE7FFFFFF +#define P_SQ_TEX_WORD1 +#define S_SQ_TEX_WORD1_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_TEX_WORD1_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_TEX_WORD1_DST_GPR 0xFFFFFF80 +#define S_SQ_TEX_WORD1_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD1_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD1_DST_REL 0xFFFFFF7F +#define S_SQ_TEX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_TEX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_TEX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_TEX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_TEX_WORD1_LOD_BIAS(x) (((x) & 0x7F) << 21) +#define G_SQ_TEX_WORD1_LOD_BIAS(x) (((x) >> 21) & 0x7F) +#define C_SQ_TEX_WORD1_LOD_BIAS 0xF01FFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) & 0x1) << 28) +#define G_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) >> 28) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_X 0xEFFFFFFF +#define V_SQ_TEX_WORD1_COORD_UNNORMALIZED 0x00000000 +#define V_SQ_TEX_WORD1_COORD_NORMALIZED 0x00000001 +#define S_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) & 0x1) << 29) +#define G_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) >> 29) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Y 0xDFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) & 0x1) << 30) +#define G_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) >> 30) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Z 0xBFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) & 0x1) << 31) +#define G_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) >> 31) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_W 0x7FFFFFFF +#define P_SQ_TEX_WORD2 +#define S_SQ_TEX_WORD2_OFFSET_X(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD2_OFFSET_X(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_X 0xFFFFFFE0 +#define S_SQ_TEX_WORD2_OFFSET_Y(x) (((x) & 0x1F) << 5) +#define G_SQ_TEX_WORD2_OFFSET_Y(x) (((x) >> 5) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Y 0xFFFFFC1F +#define S_SQ_TEX_WORD2_OFFSET_Z(x) (((x) & 0x1F) << 10) +#define G_SQ_TEX_WORD2_OFFSET_Z(x) (((x) >> 10) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Z 0xFFFF83FF +#define S_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) & 0x1F) << 15) +#define G_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) >> 15) & 0x1F) +#define C_SQ_TEX_WORD2_SAMPLER_ID 0xFFF07FFF +#define S_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) & 0x7) << 20) +#define G_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) >> 20) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_X 0xFF8FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) & 0x7) << 23) +#define G_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) >> 23) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Y 0xFC7FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) & 0x7) << 26) +#define G_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) >> 26) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Z 0xE3FFFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) & 0x7) << 29) +#define G_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) >> 29) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFFFFFF + +#define V_SQ_CF_COND_ACTIVE 0x00 +#define V_SQ_CF_COND_FALSE 0x01 +#define V_SQ_CF_COND_BOOL 0x02 +#define V_SQ_CF_COND_NOT_BOOL 0x03 + +#define V_SQ_REL_ABSOLUTE 0 +#define V_SQ_REL_RELATIVE 1 +#endif diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h new file mode 100644 index 00000000000..4e3514638b7 --- /dev/null +++ b/src/gallium/drivers/r600/eg_state_inlines.h @@ -0,0 +1,434 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef EG_STATE_INLINES_H +#define EG_STATE_INLINES_H + +#include "util/u_format.h" +#include "evergreend.h" + +static INLINE uint32_t r600_translate_blend_function(int blend_func) +{ + switch (blend_func) { + case PIPE_BLEND_ADD: + return V_028780_COMB_DST_PLUS_SRC; + case PIPE_BLEND_SUBTRACT: + return V_028780_COMB_SRC_MINUS_DST; + case PIPE_BLEND_REVERSE_SUBTRACT: + return V_028780_COMB_DST_MINUS_SRC; + case PIPE_BLEND_MIN: + return V_028780_COMB_MIN_DST_SRC; + case PIPE_BLEND_MAX: + return V_028780_COMB_MAX_DST_SRC; + default: + R600_ERR("Unknown blend function %d\n", blend_func); + assert(0); + break; + } + return 0; +} + +static INLINE uint32_t r600_translate_blend_factor(int blend_fact) +{ + switch (blend_fact) { + case PIPE_BLENDFACTOR_ONE: + return V_028780_BLEND_ONE; + case PIPE_BLENDFACTOR_SRC_COLOR: + return V_028780_BLEND_SRC_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA: + return V_028780_BLEND_SRC_ALPHA; + case PIPE_BLENDFACTOR_DST_ALPHA: + return V_028780_BLEND_DST_ALPHA; + case PIPE_BLENDFACTOR_DST_COLOR: + return V_028780_BLEND_DST_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: + return V_028780_BLEND_SRC_ALPHA_SATURATE; + case PIPE_BLENDFACTOR_CONST_COLOR: + return V_028780_BLEND_CONST_COLOR; + case PIPE_BLENDFACTOR_CONST_ALPHA: + return V_028780_BLEND_CONST_ALPHA; + case PIPE_BLENDFACTOR_ZERO: + return V_028780_BLEND_ZERO; + case PIPE_BLENDFACTOR_INV_SRC_COLOR: + return V_028780_BLEND_ONE_MINUS_SRC_COLOR; + case PIPE_BLENDFACTOR_INV_SRC_ALPHA: + return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_ALPHA: + return V_028780_BLEND_ONE_MINUS_DST_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_COLOR: + return V_028780_BLEND_ONE_MINUS_DST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_COLOR: + return V_028780_BLEND_ONE_MINUS_CONST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_ALPHA: + return V_028780_BLEND_ONE_MINUS_CONST_ALPHA; + case PIPE_BLENDFACTOR_SRC1_COLOR: + return V_028780_BLEND_SRC1_COLOR; + case PIPE_BLENDFACTOR_SRC1_ALPHA: + return V_028780_BLEND_SRC1_ALPHA; + case PIPE_BLENDFACTOR_INV_SRC1_COLOR: + return V_028780_BLEND_INV_SRC1_COLOR; + case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: + return V_028780_BLEND_INV_SRC1_ALPHA; + default: + R600_ERR("Bad blend factor %d not supported!\n", blend_fact); + assert(0); + break; + } + return 0; +} + +static INLINE uint32_t r600_translate_stencil_op(int s_op) +{ + switch (s_op) { + case PIPE_STENCIL_OP_KEEP: + return V_028800_STENCIL_KEEP; + case PIPE_STENCIL_OP_ZERO: + return V_028800_STENCIL_ZERO; + case PIPE_STENCIL_OP_REPLACE: + return V_028800_STENCIL_REPLACE; + case PIPE_STENCIL_OP_INCR: + return V_028800_STENCIL_INCR; + case PIPE_STENCIL_OP_DECR: + return V_028800_STENCIL_DECR; + case PIPE_STENCIL_OP_INCR_WRAP: + return V_028800_STENCIL_INCR_WRAP; + case PIPE_STENCIL_OP_DECR_WRAP: + return V_028800_STENCIL_DECR_WRAP; + case PIPE_STENCIL_OP_INVERT: + return V_028800_STENCIL_INVERT; + default: + R600_ERR("Unknown stencil op %d", s_op); + assert(0); + break; + } + return 0; +} + +/* translates straight */ +static INLINE uint32_t r600_translate_ds_func(int func) +{ + return func; +} + +static inline unsigned r600_tex_wrap(unsigned wrap) +{ + switch (wrap) { + default: + case PIPE_TEX_WRAP_REPEAT: + return V_03C000_SQ_TEX_WRAP; + case PIPE_TEX_WRAP_CLAMP: + return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: + return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: + return V_03C000_SQ_TEX_CLAMP_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: + return V_03C000_SQ_TEX_MIRROR; + case PIPE_TEX_WRAP_MIRROR_CLAMP: + return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: + return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: + return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; + } +} + +static inline unsigned r600_tex_filter(unsigned filter) +{ + switch (filter) { + default: + case PIPE_TEX_FILTER_NEAREST: + return V_03C000_SQ_TEX_XY_FILTER_POINT; + case PIPE_TEX_FILTER_LINEAR: + return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; + } +} + +static inline unsigned r600_tex_mipfilter(unsigned filter) +{ + switch (filter) { + case PIPE_TEX_MIPFILTER_NEAREST: + return V_03C000_SQ_TEX_Z_FILTER_POINT; + case PIPE_TEX_MIPFILTER_LINEAR: + return V_03C000_SQ_TEX_Z_FILTER_LINEAR; + default: + case PIPE_TEX_MIPFILTER_NONE: + return V_03C000_SQ_TEX_Z_FILTER_NONE; + } +} + +static inline unsigned r600_tex_compare(unsigned compare) +{ + switch (compare) { + default: + case PIPE_FUNC_NEVER: + return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; + case PIPE_FUNC_LESS: + return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; + case PIPE_FUNC_EQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; + case PIPE_FUNC_LEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; + case PIPE_FUNC_GREATER: + return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; + case PIPE_FUNC_NOTEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; + case PIPE_FUNC_ALWAYS: + return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; + } +} + +static inline unsigned r600_tex_swizzle(unsigned swizzle) +{ + switch (swizzle) { + case PIPE_SWIZZLE_RED: + return V_030010_SQ_SEL_X; + case PIPE_SWIZZLE_GREEN: + return V_030010_SQ_SEL_Y; + case PIPE_SWIZZLE_BLUE: + return V_030010_SQ_SEL_Z; + case PIPE_SWIZZLE_ALPHA: + return V_030010_SQ_SEL_W; + case PIPE_SWIZZLE_ZERO: + return V_030010_SQ_SEL_0; + default: + case PIPE_SWIZZLE_ONE: + return V_030010_SQ_SEL_1; + } +} + +static inline unsigned r600_format_type(unsigned format_type) +{ + switch (format_type) { + default: + case UTIL_FORMAT_TYPE_UNSIGNED: + return V_030010_SQ_FORMAT_COMP_UNSIGNED; + case UTIL_FORMAT_TYPE_SIGNED: + return V_030010_SQ_FORMAT_COMP_SIGNED; + case UTIL_FORMAT_TYPE_FIXED: + return V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED; + } +} + +static inline unsigned r600_tex_dim(unsigned dim) +{ + switch (dim) { + default: + case PIPE_TEXTURE_1D: + return V_030000_SQ_TEX_DIM_1D; + case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_RECT: + return V_030000_SQ_TEX_DIM_2D; + case PIPE_TEXTURE_3D: + return V_030000_SQ_TEX_DIM_3D; + case PIPE_TEXTURE_CUBE: + return V_030000_SQ_TEX_DIM_CUBEMAP; + } +} + +static inline uint32_t r600_translate_dbformat(enum pipe_format format) +{ + switch (format) { + case PIPE_FORMAT_Z16_UNORM: + return V_028040_Z_16; + case PIPE_FORMAT_Z24X8_UNORM: + return V_028040_Z_24; + case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + return V_028040_Z_24; + default: + return ~0; + } +} + +static inline uint32_t r600_translate_colorswap(enum pipe_format format) +{ + switch (format) { + /* 8-bit buffers. */ + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_R8_UNORM: + case PIPE_FORMAT_R8_SNORM: + return V_028C70_SWAP_STD; + + /* 16-bit buffers. */ + case PIPE_FORMAT_B5G6R5_UNORM: + return V_028C70_SWAP_STD_REV; + + case PIPE_FORMAT_B5G5R5A1_UNORM: + case PIPE_FORMAT_B5G5R5X1_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_B4G4R4A4_UNORM: + case PIPE_FORMAT_B4G4R4X4_UNORM: + return V_028C70_SWAP_ALT; + /* 32-bit buffers. */ + + case PIPE_FORMAT_A8B8G8R8_SRGB: + return V_028C70_SWAP_STD_REV; + case PIPE_FORMAT_B8G8R8A8_SRGB: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_B8G8R8A8_UNORM: + case PIPE_FORMAT_B8G8R8X8_UNORM: + return V_028C70_SWAP_ALT; + + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + return V_028C70_SWAP_ALT_REV; + case PIPE_FORMAT_R8G8B8A8_SNORM: + case PIPE_FORMAT_R8G8B8X8_UNORM: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_A8B8G8R8_UNORM: + case PIPE_FORMAT_X8B8G8R8_UNORM: + // case PIPE_FORMAT_R8SG8SB8UX8U_NORM: + return V_028C70_SWAP_STD_REV; + + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + return V_028C70_SWAP_STD; + + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10X2_SNORM: + case PIPE_FORMAT_B10G10R10A2_UNORM: + case PIPE_FORMAT_R10SG10SB10SA2U_NORM: + return V_028C70_SWAP_STD_REV; + + /* 64-bit buffers. */ + case PIPE_FORMAT_R16G16B16A16_UNORM: + case PIPE_FORMAT_R16G16B16A16_SNORM: + // return V_028C70_COLOR_16_16_16_16; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + // return V_028C70_COLOR_16_16_16_16_FLOAT; + + /* 128-bit buffers. */ + case PIPE_FORMAT_R32G32B32A32_FLOAT: + // return V_028C70_COLOR_32_32_32_32_FLOAT; + return 0; + default: + R600_ERR("unsupported colorswap format %d\n", format); + return ~0; + } + return ~0; +} + +static INLINE uint32_t r600_translate_colorformat(enum pipe_format format) +{ + switch (format) { + /* 8-bit buffers. */ + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_R8_UNORM: + case PIPE_FORMAT_R8_SNORM: + return V_028C70_COLOR_8; + + /* 16-bit buffers. */ + case PIPE_FORMAT_B5G6R5_UNORM: + return V_028C70_COLOR_5_6_5; + + case PIPE_FORMAT_B5G5R5A1_UNORM: + case PIPE_FORMAT_B5G5R5X1_UNORM: + return V_028C70_COLOR_1_5_5_5; + + case PIPE_FORMAT_B4G4R4A4_UNORM: + case PIPE_FORMAT_B4G4R4X4_UNORM: + return V_028C70_COLOR_4_4_4_4; + + /* 32-bit buffers. */ + case PIPE_FORMAT_A8B8G8R8_SRGB: + case PIPE_FORMAT_A8B8G8R8_UNORM: + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_B8G8R8A8_SRGB: + case PIPE_FORMAT_B8G8R8A8_UNORM: + case PIPE_FORMAT_B8G8R8X8_UNORM: + case PIPE_FORMAT_R8G8B8A8_SNORM: + case PIPE_FORMAT_R8G8B8A8_UNORM: + case PIPE_FORMAT_R8G8B8X8_UNORM: + case PIPE_FORMAT_R8SG8SB8UX8U_NORM: + case PIPE_FORMAT_X8B8G8R8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + case PIPE_FORMAT_R8G8B8_UNORM: + return V_028C70_COLOR_8_8_8_8; + + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10X2_SNORM: + case PIPE_FORMAT_B10G10R10A2_UNORM: + case PIPE_FORMAT_R10SG10SB10SA2U_NORM: + return V_028C70_COLOR_10_10_10_2; + + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + return V_028C70_COLOR_8_24; + + case PIPE_FORMAT_R32_FLOAT: + return V_028C70_COLOR_32_FLOAT; + + /* 64-bit buffers. */ + case PIPE_FORMAT_R16G16B16A16_UNORM: + case PIPE_FORMAT_R16G16B16A16_SNORM: + return V_028C70_COLOR_16_16_16_16; + case PIPE_FORMAT_R16G16B16A16_FLOAT: + return V_028C70_COLOR_16_16_16_16_FLOAT; + case PIPE_FORMAT_R32G32_FLOAT: + return V_028C70_COLOR_32_32_FLOAT; + + /* 128-bit buffers. */ + case PIPE_FORMAT_R32G32B32_FLOAT: + return V_028C70_COLOR_32_32_32_FLOAT; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + return V_028C70_COLOR_32_32_32_32_FLOAT; + + /* YUV buffers. */ + case PIPE_FORMAT_UYVY: + case PIPE_FORMAT_YUYV: + default: + R600_ERR("unsupported color format %d\n", format); + return ~0; /* Unsupported. */ + } +} + +static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format) +{ + return r600_translate_texformat(format, NULL, NULL, NULL) != ~0; +} + +static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format) +{ + return r600_translate_colorformat(format) != ~0 && + r600_translate_colorswap(format) != ~0; +} + +static INLINE boolean r600_is_zs_format_supported(enum pipe_format format) +{ + return r600_translate_dbformat(format) != ~0; +} + +static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format) +{ + return r600_translate_colorformat(format) != ~0; +} + +#endif diff --git a/src/gallium/drivers/r600/eg_states_inc.h b/src/gallium/drivers/r600/eg_states_inc.h new file mode 100644 index 00000000000..462f31cc798 --- /dev/null +++ b/src/gallium/drivers/r600/eg_states_inc.h @@ -0,0 +1,454 @@ +/* This file is autogenerated from eg_states.h - do not edit directly */ +/* autogenerating script is gen_eg_states.py */ + +/* EG_CONFIG */ +#define EG_CONFIG__SQ_CONFIG 0 +#define EG_CONFIG__SPI_CONFIG_CNTL 1 +#define EG_CONFIG__SPI_CONFIG_CNTL_1 2 +#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1 3 +#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2 4 +#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3 5 +#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1 6 +#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2 7 +#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1 8 +#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2 9 +#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3 10 +#define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 11 +#define EG_CONFIG__PA_CL_ENHANCE 12 +#define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1 13 +#define EG_CONFIG__SQ_LDS_ALLOC_PS 14 +#define EG_CONFIG__SX_MISC 15 +#define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE 16 +#define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE 17 +#define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE 18 +#define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE 19 +#define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE 20 +#define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE 21 +#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE 22 +#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1 23 +#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2 24 +#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3 25 +#define EG_CONFIG__VGT_OUTPUT_PATH_CNTL 26 +#define EG_CONFIG__VGT_HOS_CNTL 27 +#define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL 28 +#define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL 29 +#define EG_CONFIG__VGT_HOS_REUSE_DEPTH 30 +#define EG_CONFIG__VGT_GROUP_PRIM_TYPE 31 +#define EG_CONFIG__VGT_GROUP_FIRST_DECR 32 +#define EG_CONFIG__VGT_GROUP_DECR 33 +#define EG_CONFIG__VGT_GROUP_VECT_0_CNTL 34 +#define EG_CONFIG__VGT_GROUP_VECT_1_CNTL 35 +#define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 36 +#define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 37 +#define EG_CONFIG__VGT_GS_MODE 38 +#define EG_CONFIG__PA_SC_MODE_CNTL_0 39 +#define EG_CONFIG__PA_SC_MODE_CNTL_1 40 +#define EG_CONFIG__VGT_REUSE_OFF 41 +#define EG_CONFIG__VGT_VTX_CNT_EN 42 +#define EG_CONFIG__VGT_SHADER_STAGES_EN 43 +#define EG_CONFIG__VGT_STRMOUT_CONFIG 44 +#define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG 45 +#define EG_CONFIG_SIZE 46 +#define EG_CONFIG_PM4 128 + +/* EG_CB_CNTL */ +#define EG_CB_CNTL__CB_TARGET_MASK 0 +#define EG_CB_CNTL__CB_SHADER_MASK 1 +#define EG_CB_CNTL__CB_COLOR_CONTROL 2 +#define EG_CB_CNTL__PA_SC_AA_CONFIG 3 +#define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 4 +#define EG_CB_CNTL__PA_SC_AA_MASK 5 +#define EG_CB_CNTL_SIZE 6 +#define EG_CB_CNTL_PM4 128 + +/* EG_RASTERIZER */ +#define EG_RASTERIZER__SPI_INTERP_CONTROL_0 0 +#define EG_RASTERIZER__PA_CL_CLIP_CNTL 1 +#define EG_RASTERIZER__PA_SU_SC_MODE_CNTL 2 +#define EG_RASTERIZER__PA_CL_VS_OUT_CNTL 3 +#define EG_RASTERIZER__PA_CL_NANINF_CNTL 4 +#define EG_RASTERIZER__PA_SU_POINT_SIZE 5 +#define EG_RASTERIZER__PA_SU_POINT_MINMAX 6 +#define EG_RASTERIZER__PA_SU_LINE_CNTL 7 +#define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL 8 +#define EG_RASTERIZER__PA_SC_LINE_CNTL 9 +#define EG_RASTERIZER__PA_SU_VTX_CNTL 10 +#define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 +#define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 +#define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 +#define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 +#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 +#define EG_RASTERIZER_SIZE 21 +#define EG_RASTERIZER_PM4 128 + +/* EG_VIEWPORT */ +#define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 +#define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 +#define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 +#define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 +#define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 +#define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 +#define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 +#define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 +#define EG_VIEWPORT__PA_CL_VTE_CNTL 8 +#define EG_VIEWPORT_SIZE 9 +#define EG_VIEWPORT_PM4 128 + +/* EG_SCISSOR */ +#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 +#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 +#define EG_SCISSOR__PA_SC_WINDOW_OFFSET 2 +#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 +#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 +#define EG_SCISSOR__PA_SC_CLIPRECT_RULE 5 +#define EG_SCISSOR__PA_SC_CLIPRECT_0_TL 6 +#define EG_SCISSOR__PA_SC_CLIPRECT_0_BR 7 +#define EG_SCISSOR__PA_SC_CLIPRECT_1_TL 8 +#define EG_SCISSOR__PA_SC_CLIPRECT_1_BR 9 +#define EG_SCISSOR__PA_SC_CLIPRECT_2_TL 10 +#define EG_SCISSOR__PA_SC_CLIPRECT_2_BR 11 +#define EG_SCISSOR__PA_SC_CLIPRECT_3_TL 12 +#define EG_SCISSOR__PA_SC_CLIPRECT_3_BR 13 +#define EG_SCISSOR__PA_SC_EDGERULE 14 +#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 +#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 +#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 +#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 +#define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET 19 +#define EG_SCISSOR_SIZE 20 +#define EG_SCISSOR_PM4 128 + +/* EG_BLEND */ +#define EG_BLEND__CB_BLEND_RED 0 +#define EG_BLEND__CB_BLEND_GREEN 1 +#define EG_BLEND__CB_BLEND_BLUE 2 +#define EG_BLEND__CB_BLEND_ALPHA 3 +#define EG_BLEND__CB_BLEND0_CONTROL 4 +#define EG_BLEND__CB_BLEND1_CONTROL 5 +#define EG_BLEND__CB_BLEND2_CONTROL 6 +#define EG_BLEND__CB_BLEND3_CONTROL 7 +#define EG_BLEND__CB_BLEND4_CONTROL 8 +#define EG_BLEND__CB_BLEND5_CONTROL 9 +#define EG_BLEND__CB_BLEND6_CONTROL 10 +#define EG_BLEND__CB_BLEND7_CONTROL 11 +#define EG_BLEND_SIZE 12 +#define EG_BLEND_PM4 128 + +/* EG_DSA */ +#define EG_DSA__DB_STENCIL_CLEAR 0 +#define EG_DSA__DB_DEPTH_CLEAR 1 +#define EG_DSA__SX_ALPHA_TEST_CONTROL 2 +#define EG_DSA__DB_STENCILREFMASK 3 +#define EG_DSA__DB_STENCILREFMASK_BF 4 +#define EG_DSA__SX_ALPHA_REF 5 +#define EG_DSA__SPI_FOG_CNTL 6 +#define EG_DSA__DB_DEPTH_CONTROL 7 +#define EG_DSA__DB_SHADER_CONTROL 8 +#define EG_DSA__DB_RENDER_CONTROL 9 +#define EG_DSA__DB_RENDER_OVERRIDE 10 +#define EG_DSA__DB_RENDER_OVERRIDE2 11 +#define EG_DSA__DB_SRESULTS_COMPARE_STATE0 12 +#define EG_DSA__DB_SRESULTS_COMPARE_STATE1 13 +#define EG_DSA__DB_PRELOAD_CONTROL 14 +#define EG_DSA__DB_ALPHA_TO_MASK 15 +#define EG_DSA_SIZE 16 +#define EG_DSA_PM4 128 + +/* EG_VS_SHADER */ +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_0 0 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_1 1 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_2 2 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_3 3 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_4 4 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_5 5 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_6 6 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_7 7 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_8 8 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_9 9 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_10 10 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_11 11 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_12 12 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_13 13 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_14 14 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_15 15 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_16 16 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_17 17 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_18 18 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_19 19 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_20 20 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_21 21 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_22 22 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_23 23 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_24 24 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_25 25 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_26 26 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_27 27 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_28 28 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_29 29 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_30 30 +#define EG_VS_SHADER__SQ_VTX_SEMANTIC_31 31 +#define EG_VS_SHADER__SPI_VS_OUT_ID_0 32 +#define EG_VS_SHADER__SPI_VS_OUT_ID_1 33 +#define EG_VS_SHADER__SPI_VS_OUT_ID_2 34 +#define EG_VS_SHADER__SPI_VS_OUT_ID_3 35 +#define EG_VS_SHADER__SPI_VS_OUT_ID_4 36 +#define EG_VS_SHADER__SPI_VS_OUT_ID_5 37 +#define EG_VS_SHADER__SPI_VS_OUT_ID_6 38 +#define EG_VS_SHADER__SPI_VS_OUT_ID_7 39 +#define EG_VS_SHADER__SPI_VS_OUT_ID_8 40 +#define EG_VS_SHADER__SPI_VS_OUT_ID_9 41 +#define EG_VS_SHADER__SPI_VS_OUT_CONFIG 42 +#define EG_VS_SHADER__SQ_PGM_START_VS 43 +#define EG_VS_SHADER__SQ_PGM_RESOURCES_VS 44 +#define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS 45 +#define EG_VS_SHADER__SQ_PGM_START_FS 46 +#define EG_VS_SHADER__SQ_PGM_RESOURCES_FS 47 +#define EG_VS_SHADER_SIZE 48 +#define EG_VS_SHADER_PM4 128 + +/* EG_PS_SHADER */ +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 +#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 +#define EG_PS_SHADER__SPI_THREAD_GROUPING 32 +#define EG_PS_SHADER__SPI_PS_IN_CONTROL_0 33 +#define EG_PS_SHADER__SPI_PS_IN_CONTROL_1 34 +#define EG_PS_SHADER__SPI_INPUT_Z 35 +#define EG_PS_SHADER__SPI_BARYC_CNTL 36 +#define EG_PS_SHADER__SPI_PS_IN_CONTROL_2 37 +#define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL 38 +#define EG_PS_SHADER__SQ_PGM_START_PS 39 +#define EG_PS_SHADER__SQ_PGM_RESOURCES_PS 40 +#define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS 41 +#define EG_PS_SHADER__SQ_PGM_EXPORTS_PS 42 +#define EG_PS_SHADER_SIZE 43 +#define EG_PS_SHADER_PM4 128 + +/* EG_UCP */ +#define EG_UCP__PA_CL_UCP0_X 0 +#define EG_UCP__PA_CL_UCP0_Y 1 +#define EG_UCP__PA_CL_UCP0_Z 2 +#define EG_UCP__PA_CL_UCP0_W 3 +#define EG_UCP__PA_CL_UCP1_X 4 +#define EG_UCP__PA_CL_UCP1_Y 5 +#define EG_UCP__PA_CL_UCP1_Z 6 +#define EG_UCP__PA_CL_UCP1_W 7 +#define EG_UCP__PA_CL_UCP2_X 8 +#define EG_UCP__PA_CL_UCP2_Y 9 +#define EG_UCP__PA_CL_UCP2_Z 10 +#define EG_UCP__PA_CL_UCP2_W 11 +#define EG_UCP__PA_CL_UCP3_X 12 +#define EG_UCP__PA_CL_UCP3_Y 13 +#define EG_UCP__PA_CL_UCP3_Z 14 +#define EG_UCP__PA_CL_UCP3_W 15 +#define EG_UCP__PA_CL_UCP4_X 16 +#define EG_UCP__PA_CL_UCP4_Y 17 +#define EG_UCP__PA_CL_UCP4_Z 18 +#define EG_UCP__PA_CL_UCP4_W 19 +#define EG_UCP__PA_CL_UCP5_X 20 +#define EG_UCP__PA_CL_UCP5_Y 21 +#define EG_UCP__PA_CL_UCP5_Z 22 +#define EG_UCP__PA_CL_UCP5_W 23 +#define EG_UCP_SIZE 24 +#define EG_UCP_PM4 128 + +/* EG_VS_CBUF */ +#define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0 +#define EG_VS_CBUF__ALU_CONST_CACHE_VS_0 1 +#define EG_VS_CBUF_SIZE 2 +#define EG_VS_CBUF_PM4 128 + +/* EG_PS_CBUF */ +#define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0 +#define EG_PS_CBUF__ALU_CONST_CACHE_PS_0 1 +#define EG_PS_CBUF_SIZE 2 +#define EG_PS_CBUF_PM4 128 + +/* EG_PS_RESOURCE */ +#define EG_PS_RESOURCE__RESOURCE0_WORD0 0 +#define EG_PS_RESOURCE__RESOURCE0_WORD1 1 +#define EG_PS_RESOURCE__RESOURCE0_WORD2 2 +#define EG_PS_RESOURCE__RESOURCE0_WORD3 3 +#define EG_PS_RESOURCE__RESOURCE0_WORD4 4 +#define EG_PS_RESOURCE__RESOURCE0_WORD5 5 +#define EG_PS_RESOURCE__RESOURCE0_WORD6 6 +#define EG_PS_RESOURCE__RESOURCE0_WORD7 7 +#define EG_PS_RESOURCE_SIZE 8 +#define EG_PS_RESOURCE_PM4 128 + +/* EG_VS_RESOURCE */ +#define EG_VS_RESOURCE__RESOURCE160_WORD0 0 +#define EG_VS_RESOURCE__RESOURCE160_WORD1 1 +#define EG_VS_RESOURCE__RESOURCE160_WORD2 2 +#define EG_VS_RESOURCE__RESOURCE160_WORD3 3 +#define EG_VS_RESOURCE__RESOURCE160_WORD4 4 +#define EG_VS_RESOURCE__RESOURCE160_WORD5 5 +#define EG_VS_RESOURCE__RESOURCE160_WORD6 6 +#define EG_VS_RESOURCE__RESOURCE160_WORD7 7 +#define EG_VS_RESOURCE_SIZE 8 +#define EG_VS_RESOURCE_PM4 128 + +/* EG_FS_RESOURCE */ +#define EG_FS_RESOURCE__RESOURCE320_WORD0 0 +#define EG_FS_RESOURCE__RESOURCE320_WORD1 1 +#define EG_FS_RESOURCE__RESOURCE320_WORD2 2 +#define EG_FS_RESOURCE__RESOURCE320_WORD3 3 +#define EG_FS_RESOURCE__RESOURCE320_WORD4 4 +#define EG_FS_RESOURCE__RESOURCE320_WORD5 5 +#define EG_FS_RESOURCE__RESOURCE320_WORD6 6 +#define EG_FS_RESOURCE__RESOURCE320_WORD7 7 +#define EG_FS_RESOURCE_SIZE 8 +#define EG_FS_RESOURCE_PM4 128 + +/* EG_GS_RESOURCE */ +#define EG_GS_RESOURCE__RESOURCE336_WORD0 0 +#define EG_GS_RESOURCE__RESOURCE336_WORD1 1 +#define EG_GS_RESOURCE__RESOURCE336_WORD2 2 +#define EG_GS_RESOURCE__RESOURCE336_WORD3 3 +#define EG_GS_RESOURCE__RESOURCE336_WORD4 4 +#define EG_GS_RESOURCE__RESOURCE336_WORD5 5 +#define EG_GS_RESOURCE__RESOURCE336_WORD6 6 +#define EG_GS_RESOURCE__RESOURCE336_WORD7 7 +#define EG_GS_RESOURCE_SIZE 8 +#define EG_GS_RESOURCE_PM4 128 + +/* EG_PS_SAMPLER */ +#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 +#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 +#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 +#define EG_PS_SAMPLER_SIZE 3 +#define EG_PS_SAMPLER_PM4 128 + +/* EG_VS_SAMPLER */ +#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 +#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 +#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 +#define EG_VS_SAMPLER_SIZE 3 +#define EG_VS_SAMPLER_PM4 128 + +/* EG_GS_SAMPLER */ +#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 +#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 +#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 +#define EG_GS_SAMPLER_SIZE 3 +#define EG_GS_SAMPLER_PM4 128 + +/* EG_PS_SAMPLER_BORDER */ +#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 +#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 +#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 +#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 +#define EG_PS_SAMPLER_BORDER_SIZE 4 +#define EG_PS_SAMPLER_BORDER_PM4 128 + +/* EG_VS_SAMPLER_BORDER */ +#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 +#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 +#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 +#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 +#define EG_VS_SAMPLER_BORDER_SIZE 4 +#define EG_VS_SAMPLER_BORDER_PM4 128 + +/* EG_GS_SAMPLER_BORDER */ +#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 +#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 +#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 +#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 +#define EG_GS_SAMPLER_BORDER_SIZE 4 +#define EG_GS_SAMPLER_BORDER_PM4 128 + +/* EG_CB */ +#define EG_CB__CB_COLOR0_BASE 0 +#define EG_CB__CB_COLOR0_PITCH 1 +#define EG_CB__CB_COLOR0_SLICE 2 +#define EG_CB__CB_COLOR0_VIEW 3 +#define EG_CB__CB_COLOR0_INFO 4 +#define EG_CB__CB_COLOR0_ATTRIB 5 +#define EG_CB__CB_COLOR0_DIM 6 +#define EG_CB_SIZE 7 +#define EG_CB_PM4 128 + +/* EG_DB */ +#define EG_DB__DB_HTILE_DATA_BASE 0 +#define EG_DB__DB_Z_INFO 1 +#define EG_DB__DB_STENCIL_INFO 2 +#define EG_DB__DB_DEPTH_SIZE 3 +#define EG_DB__DB_DEPTH_SLICE 4 +#define EG_DB__DB_DEPTH_VIEW 5 +#define EG_DB__DB_HTILE_SURFACE 6 +#define EG_DB__DB_Z_READ_BASE 7 +#define EG_DB__DB_STENCIL_READ_BASE 8 +#define EG_DB__DB_Z_WRITE_BASE 9 +#define EG_DB__DB_STENCIL_WRITE_BASE 10 +#define EG_DB_SIZE 11 +#define EG_DB_PM4 128 + +/* EG_VGT */ +#define EG_VGT__VGT_PRIMITIVE_TYPE 0 +#define EG_VGT__VGT_MAX_VTX_INDX 1 +#define EG_VGT__VGT_MIN_VTX_INDX 2 +#define EG_VGT__VGT_INDX_OFFSET 3 +#define EG_VGT__VGT_DMA_INDEX_TYPE 4 +#define EG_VGT__VGT_PRIMITIVEID_EN 5 +#define EG_VGT__VGT_DMA_NUM_INSTANCES 6 +#define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN 7 +#define EG_VGT__VGT_INSTANCE_STEP_RATE_0 8 +#define EG_VGT__VGT_INSTANCE_STEP_RATE_1 9 +#define EG_VGT_SIZE 10 +#define EG_VGT_PM4 128 + +/* EG_DRAW */ +#define EG_DRAW__VGT_NUM_INDICES 0 +#define EG_DRAW__VGT_DMA_BASE_HI 1 +#define EG_DRAW__VGT_DMA_BASE 2 +#define EG_DRAW__VGT_DRAW_INITIATOR 3 +#define EG_DRAW_SIZE 4 +#define EG_DRAW_PM4 128 + +/* EG_VGT_EVENT */ +#define EG_VGT_EVENT__VGT_EVENT_INITIATOR 0 +#define EG_VGT_EVENT_SIZE 1 +#define EG_VGT_EVENT_PM4 128 + +/* EG_CB_FLUSH */ +#define EG_CB_FLUSH_SIZE 0 +#define EG_CB_FLUSH_PM4 128 + +/* EG_DB_FLUSH */ +#define EG_DB_FLUSH_SIZE 0 +#define EG_DB_FLUSH_PM4 128 + diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h new file mode 100644 index 00000000000..c8e6710605b --- /dev/null +++ b/src/gallium/drivers/r600/evergreend.h @@ -0,0 +1,1442 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef EVERGREEND_H +#define EVERGREEND_H + +#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 + +#define PKT3_NOP 0x10 +#define PKT3_INDIRECT_BUFFER_END 0x17 +#define PKT3_SET_PREDICATION 0x20 +#define PKT3_REG_RMW 0x21 +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define PKT3_DRAW_INDEX_IMMD_BE 0x29 +#define PKT3_INDEX_TYPE 0x2A +#define PKT3_DRAW_INDEX 0x2B +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define PKT3_INDIRECT_BUFFER_MP 0x38 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A +#define PKT3_WAIT_REG_MEM 0x3C +#define PKT3_MEM_WRITE 0x3D +#define PKT3_INDIRECT_BUFFER 0x32 +#define PKT3_CP_INTERRUPT 0x40 +#define PKT3_SURFACE_SYNC 0x43 +#define PKT3_ME_INITIALIZE 0x44 +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_ONE_REG_WRITE 0x57 +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_ALU_CONST 0x6A +#define PKT3_SET_BOOL_CONST 0x6B +#define PKT3_SET_LOOP_CONST 0x6C +#define PKT3_SET_RESOURCE 0x6D +#define PKT3_SET_SAMPLER 0x6E +#define PKT3_SET_CTL_CONST 0x6F +#define PKT3_SURFACE_BASE_UPDATE 0x73 + +#define PKT_TYPE_S(x) (((x) & 0x3) << 30) +#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) +#define PKT_TYPE_C 0x3FFFFFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) +#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) +#define PKT_COUNT_C 0xC000FFFF +#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) +#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) +#define PKT0_BASE_INDEX_C 0xFFFF0000 +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) +#define PKT3_IT_OPCODE_C 0xFFFF00FF +#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count)) + +/* Registers */ +#define R_008C00_SQ_CONFIG 0x00008C00 +#define S_008C00_VC_ENABLE(x) (((x) & 0x1) << 0) +#define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1) +#define C_008C00_VC_ENABLE(x) 0xFFFFFFFE +#define S_008C00_EXPORT_SRC_C(x) (((x) & 0x1) << 1) +#define G_008C00_EXPORT_SRC_C(x) (((x) >> 1) & 0x1) +#define C_008C00_EXPORT_SRC_C(x) 0xFFFFFFFD +/* different */ +#define S_008C00_CS_PRIO(x) (((x) & 0x3) << 18) +#define G_008C00_CS_PRIO(x) (((x) >> 18) & 0x3) +#define C_008C00_CS_PRIO(x) 0xFFF3FFFF +#define S_008C00_LS_PRIO(x) (((x) & 0x3) << 20) +#define G_008C00_LS_PRIO(x) (((x) >> 20) & 0x3) +#define C_008C00_LS_PRIO(x) 0xFFCFFFFF +#define S_008C00_HS_PRIO(x) (((x) & 0x3) << 22) +#define G_008C00_HS_PRIO(x) (((x) >> 22) & 0x3) +#define C_008C00_HS_PRIO(x) 0xFF3FFFFF +#define S_008C00_PS_PRIO(x) (((x) & 0x3) << 24) +#define G_008C00_PS_PRIO(x) (((x) >> 24) & 0x3) +#define C_008C00_PS_PRIO(x) 0xFCFFFFFF +#define S_008C00_VS_PRIO(x) (((x) & 0x3) << 26) +#define G_008C00_VS_PRIO(x) (((x) >> 26) & 0x3) +#define C_008C00_VS_PRIO(x) 0xF3FFFFFF +#define S_008C00_GS_PRIO(x) (((x) & 0x3) << 28) +#define G_008C00_GS_PRIO(x) (((x) >> 28) & 0x3) +#define C_008C00_GS_PRIO(x) 0xCFFFFFFF +#define S_008C00_ES_PRIO(x) (((x) & 0x3) << 30) +#define G_008C00_ES_PRIO(x) (((x) >> 30) & 0x3) +#define C_008C00_ES_PRIO(x) 0x3FFFFFFF +#define R_008C04_SQ_GPR_RESOURCE_MGMT_1 0x00008C04 +#define S_008C04_NUM_PS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C04_NUM_PS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C04_NUM_PS_GPRS(x) 0xFFFFFF00 +#define S_008C04_NUM_VS_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C04_NUM_VS_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C04_NUM_VS_GPRS(x) 0xFF00FFFF +#define S_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) & 0xF) << 28) +#define G_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) >> 28) & 0xF) +#define C_008C04_NUM_CLAUSE_TEMP_GPRS(x) 0x0FFFFFFF +#define R_008C08_SQ_GPR_RESOURCE_MGMT_2 0x00008C08 +#define S_008C08_NUM_GS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C08_NUM_GS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C08_NUM_GS_GPRS(x) 0xFFFFFF00 +#define S_008C08_NUM_ES_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C08_NUM_ES_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C08_NUM_ES_GPRS(x) 0xFF00FFFF +#define R_008C0C_SQ_GPR_RESOURCE_MGMT_3 0x00008C0C +#define S_008C0C_NUM_HS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C0C_NUM_HS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C0C_NUM_HS_GPRS(x) 0xFFFFFF00 +#define S_008C0C_NUM_LS_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C0C_NUM_LS_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C0C_NUM_LS_GPRS(x) 0xFF00FFFF +#define R_008C18_SQ_THREAD_RESOURCE_MGMT_1 0x00008C18 +#define S_008C18_NUM_PS_THREADS(x) (((x) & 0xFF) << 0) +#define G_008C18_NUM_PS_THREADS(x) (((x) >> 0) & 0xFF) +#define C_008C18_NUM_PS_THREADS(x) 0xFFFFFF00 +#define S_008C18_NUM_VS_THREADS(x) (((x) & 0xFF) << 8) +#define G_008C18_NUM_VS_THREADS(x) (((x) >> 8) & 0xFF) +#define C_008C18_NUM_VS_THREADS(x) 0xFFFF00FF +#define S_008C18_NUM_GS_THREADS(x) (((x) & 0xFF) << 16) +#define G_008C18_NUM_GS_THREADS(x) (((x) >> 16) & 0xFF) +#define C_008C18_NUM_GS_THREADS(x) 0xFF00FFFF +#define S_008C18_NUM_ES_THREADS(x) (((x) & 0xFF) << 24) +#define G_008C18_NUM_ES_THREADS(x) (((x) >> 24) & 0xFF) +#define C_008C18_NUM_ES_THREADS(x) 0x00FFFFFF +#define R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 0x00008C1C +#define S_008C1C_NUM_HS_THREADS(x) (((x) & 0xFF) << 0) +#define G_008C1C_NUM_HS_THREADS(x) (((x) >> 0) & 0xFF) +#define C_008C1C_NUM_HS_THREADS(x) 0xFFFFFF00 +#define S_008C1C_NUM_LS_THREADS(x) (((x) & 0xFF) << 8) +#define G_008C1C_NUM_LS_THREADS(x) (((x) >> 8) & 0xFF) +#define C_008C1C_NUM_LS_THREADS(x) 0xFFFF00FF +#define R_008C20_SQ_STACK_RESOURCE_MGMT_1 0x00008C20 +#define S_008C20_NUM_PS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C20_NUM_PS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C20_NUM_PS_STACK_ENTRIES(x) 0xFFFFF000 +#define S_008C20_NUM_VS_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C20_NUM_VS_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C20_NUM_VS_STACK_ENTRIES(x) 0xF000FFFF +#define R_008C24_SQ_STACK_RESOURCE_MGMT_2 0x00008C24 +#define S_008C24_NUM_GS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C24_NUM_GS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C24_NUM_GS_STACK_ENTRIES(x) 0xFFFFF000 +#define S_008C24_NUM_ES_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C24_NUM_ES_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C24_NUM_ES_STACK_ENTRIES(x) 0xF000FFFF +#define R_008C28_SQ_STACK_RESOURCE_MGMT_3 0x00008C28 +#define S_008C28_NUM_HS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C28_NUM_HS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C28_NUM_HS_STACK_ENTRIES(x) 0xFFFFF000 +#define S_008C28_NUM_LS_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C28_NUM_LS_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C28_NUM_LS_STACK_ENTRIES(x) 0xF000FFFF + +#define R_008CF0_SQ_MS_FIFO_SIZES 0x00008CF0 +#define S_008CF0_CACHE_FIFO_SIZE(x) (((x) & 0xFF) << 0) +#define G_008CF0_CACHE_FIFO_SIZE(x) (((x) >> 0) & 0xFF) +#define C_008CF0_CACHE_FIFO_SIZE(x) 0xFFFFFF00 +#define S_008CF0_FETCH_FIFO_HIWATER(x) (((x) & 0x1F) << 8) +#define G_008CF0_FETCH_FIFO_HIWATER(x) (((x) >> 8) & 0x1F) +#define C_008CF0_FETCH_FIFO_HIWATER(x) 0xFFFFE0FF +#define S_008CF0_DONE_FIFO_HIWATER(x) (((x) & 0xFF) << 16) +#define G_008CF0_DONE_FIFO_HIWATER(x) (((x) >> 16) & 0xFF) +#define C_008CF0_DONE_FIFO_HIWATER(x) 0xFF00FFFF +#define S_008CF0_ALU_UPDATE_FIFO_HIWATER(x) (((x) & 0x1F) << 24) +#define G_008CF0_ALU_UPDATE_FIFO_HIWATER(x) (((x) >> 24) & 0x1F) +#define C_008CF0_ALU_UPDATE_FIFO_HIWATER(x) 0xE0FFFFFF + +#define R_009100_SPI_CONFIG_CNTL 0x00009100 +#define R_00913C_SPI_CONFIG_CNTL_1 0x0000913C +#define S_00913C_VTX_DONE_DELAY(x) (((x) & 0xF) << 0) +#define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0xF ) +#define C_00913C_VTX_DONE_DELAY(x) 0xFFFFFFF0 + + +#define R_028C64_CB_COLOR0_PITCH 0x028C64 +#define S_028C64_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) +#define G_028C64_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) +#define C_028C64_PITCH_TILE_MAX 0xFFFFF800 +#define R_028C68_CB_COLOR0_SLICE 0x028C68 +#define S_028C68_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) +#define G_028C68_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) +#define C_028C68_SLICE_TILE_MAX 0xFFC00000 +#define R_028C70_CB_COLOR0_INFO 0x028C70 +#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) +#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) +#define C_028C70_ENDIAN 0xFFFFFFFC +#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) +#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) +#define C_028C70_FORMAT 0xFFFFFF03 +#define V_028C70_COLOR_INVALID 0x00000000 +#define V_028C70_COLOR_8 0x00000001 +#define V_028C70_COLOR_4_4 0x00000002 +#define V_028C70_COLOR_3_3_2 0x00000003 +#define V_028C70_COLOR_16 0x00000005 +#define V_028C70_COLOR_16_FLOAT 0x00000006 +#define V_028C70_COLOR_8_8 0x00000007 +#define V_028C70_COLOR_5_6_5 0x00000008 +#define V_028C70_COLOR_6_5_5 0x00000009 +#define V_028C70_COLOR_1_5_5_5 0x0000000A +#define V_028C70_COLOR_4_4_4_4 0x0000000B +#define V_028C70_COLOR_5_5_5_1 0x0000000C +#define V_028C70_COLOR_32 0x0000000D +#define V_028C70_COLOR_32_FLOAT 0x0000000E +#define V_028C70_COLOR_16_16 0x0000000F +#define V_028C70_COLOR_16_16_FLOAT 0x00000010 +#define V_028C70_COLOR_8_24 0x00000011 +#define V_028C70_COLOR_8_24_FLOAT 0x00000012 +#define V_028C70_COLOR_24_8 0x00000013 +#define V_028C70_COLOR_24_8_FLOAT 0x00000014 +#define V_028C70_COLOR_10_11_11 0x00000015 +#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 +#define V_028C70_COLOR_11_11_10 0x00000017 +#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 +#define V_028C70_COLOR_2_10_10_10 0x00000019 +#define V_028C70_COLOR_8_8_8_8 0x0000001A +#define V_028C70_COLOR_10_10_10_2 0x0000001B +#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_028C70_COLOR_32_32 0x0000001D +#define V_028C70_COLOR_32_32_FLOAT 0x0000001E +#define V_028C70_COLOR_16_16_16_16 0x0000001F +#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_028C70_COLOR_32_32_32_32 0x00000022 +#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 +#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 +#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) +#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) +#define C_028C70_ARRAY_MODE 0xFFFFF0FF +#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 +#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 +#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 +#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 +#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) +#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) +#define C_028C70_NUMBER_TYPE 0xFFFF8FFF +#define V_028C70_NUMBER_UNORM 0x00000000 +#define V_028C70_NUMBER_SNORM 0x00000001 +#define V_028C70_NUMBER_USCALED 0x00000002 +#define V_028C70_NUMBER_SSCALED 0x00000003 +#define V_028C70_NUMBER_UINT 0x00000004 +#define V_028C70_NUMBER_SINT 0x00000005 +#define V_028C70_NUMBER_SRGB 0x00000006 +#define V_028C70_NUMBER_FLOAT 0x00000007 +#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) +#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) +#define C_028C70_COMP_SWAP 0xFFFE7FFF +#define V_028C70_SWAP_STD 0x00000000 +#define V_028C70_SWAP_ALT 0x00000001 +#define V_028C70_SWAP_STD_REV 0x00000002 +#define V_028C70_SWAP_ALT_REV 0x00000003 +#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) +#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) +#define C_028C70_FAST_CLEAR 0xFFFDFFFF +#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) +#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) +#define C_028C70_COMPRESSION 0xFFF3FFFF +#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) +#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) +#define C_028C70_BLEND_CLAMP 0xFFF7FFFF +#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) +#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) +#define C_028C70_BLEND_BYPASS 0xFFEFFFFF +#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) +#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) +#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF +#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) +#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) +#define C_028C70_ROUND_MODE 0xFFBFFFFF +#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) +#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) +#define C_028C70_TILE_COMPACT 0xFF7FFFFF +#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) +#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) +#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF +#define S_028C70_RAT(x) (((x) & 0x1) << 26) +#define G_028C70_RAT(x) (((x) >> 26) & 0x1) +#define C_028C70_RAT 0xFBFFFFFF +#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) +#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) +#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF + +#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 +#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) +#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) +#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF + +#define R_028C78_CB_COLOR0_DIM 0x028C78 +#define S_028C78_WIDTH_MAX(x) (((x) & 0xFFFF) << 0) +#define G_028C78_WIDTH_MAX(x) (((x) >> 0) & 0xFFFF) +#define C_028C78_WIDTH_MAX 0xFFFF0000 +#define S_028C78_HEIGHT_MAX(x) (((x) & 0xFFFF) << 16) +#define G_028C78_HEIGHT_MAX(x) (((x) >> 16) & 0xFFFF) +#define C_028C78_HEIGHT_MAX 0x0000FFFF + +#define R_028C7C_CB_COLOR0_CMASK 0x028C7C +#define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80 +#define R_028C84_CB_COLOR0_FMASK 0x028C84 +#define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88 + +#define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C +#define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90 +#define R_028C94_CB_COLOR0_CLEAR_WORD2 0x028C94 +#define R_028C98_CB_COLOR0_CLEAR_WORD3 0x028C98 + +/* alpha same */ +#define R_028410_SX_ALPHA_TEST_CONTROL 0x028410 +#define S_028410_ALPHA_FUNC(x) (((x) & 0x7) << 0) +#define G_028410_ALPHA_FUNC(x) (((x) >> 0) & 0x7) +#define C_028410_ALPHA_FUNC 0xFFFFFFF8 +#define S_028410_ALPHA_TEST_ENABLE(x) (((x) & 0x1) << 3) +#define G_028410_ALPHA_TEST_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028410_ALPHA_TEST_ENABLE 0xFFFFFFF7 +#define S_028410_ALPHA_TEST_BYPASS(x) (((x) & 0x1) << 8) +#define G_028410_ALPHA_TEST_BYPASS(x) (((x) >> 8) & 0x1) +#define C_028410_ALPHA_TEST_BYPASS 0xFFFFFEFF + +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) +#define C_028800_ZFUNC 0xFFFFFF8F +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define V_028800_STENCILFUNC_NEVER 0x00000000 +#define V_028800_STENCILFUNC_LESS 0x00000001 +#define V_028800_STENCILFUNC_EQUAL 0x00000002 +#define V_028800_STENCILFUNC_LEQUAL 0x00000003 +#define V_028800_STENCILFUNC_GREATER 0x00000004 +#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 +#define V_028800_STENCILFUNC_GEQUAL 0x00000006 +#define V_028800_STENCILFUNC_ALWAYS 0x00000007 +#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) +#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) +#define C_028800_STENCILFAIL 0xFFFFC7FF +#define V_028800_STENCIL_KEEP 0x00000000 +#define V_028800_STENCIL_ZERO 0x00000001 +#define V_028800_STENCIL_REPLACE 0x00000002 +#define V_028800_STENCIL_INCR 0x00000003 +#define V_028800_STENCIL_DECR 0x00000004 +#define V_028800_STENCIL_INVERT 0x00000005 +#define V_028800_STENCIL_INCR_WRAP 0x00000006 +#define V_028800_STENCIL_DECR_WRAP 0x00000007 +#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) +#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) +#define C_028800_STENCILZPASS 0xFFFE3FFF +#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) +#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) +#define C_028800_STENCILZFAIL 0xFFF1FFFF +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) +#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) +#define C_028800_STENCILFAIL_BF 0xFC7FFFFF +#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) +#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) +#define C_028800_STENCILZPASS_BF 0xE3FFFFFF +#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) +#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) +#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF + +#define R_028808_CB_COLOR_CONTROL 0x028808 +#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0) +#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028808_FOG_ENABLE 0xFFFFFFFE +#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1) +#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD +#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2) +#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028808_DITHER_ENABLE 0xFFFFFFFB +#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) +#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 +#define S_028808_MODE(x) (((x) & 0x7) << 4) +#define G_028808_MODE(x) (((x) >> 4) & 0x7) +#define C_028808_MODE 0xFFFFFF8F +#define S_028808_ROP3(x) (((x) & 0xFF) << 16) +#define G_028808_ROP3(x) (((x) >> 16) & 0xFF) +#define C_028808_ROP3 0xFF00FFFF +#define R_028810_PA_CL_CLIP_CNTL 0x028810 +#define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0) +#define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1) +#define C_028810_UCP_ENA_0 0xFFFFFFFE +#define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1) +#define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1) +#define C_028810_UCP_ENA_1 0xFFFFFFFD +#define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2) +#define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1) +#define C_028810_UCP_ENA_2 0xFFFFFFFB +#define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3) +#define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1) +#define C_028810_UCP_ENA_3 0xFFFFFFF7 +#define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4) +#define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1) +#define C_028810_UCP_ENA_4 0xFFFFFFEF +#define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5) +#define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1) +#define C_028810_UCP_ENA_5 0xFFFFFFDF +#define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13) +#define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1) +#define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF +#define S_028810_PS_UCP_MODE(x) (((x) & 0x3) << 14) +#define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x3) +#define C_028810_PS_UCP_MODE 0xFFFF3FFF +#define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16) +#define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1) +#define C_028810_CLIP_DISABLE 0xFFFEFFFF +#define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17) +#define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1) +#define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF +#define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18) +#define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1) +#define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF +#define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19) +#define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1) +#define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF +#define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20) +#define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1) +#define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF +#define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) +#define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) +#define C_028810_VTX_KILL_OR 0xFFDFFFFF +#define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) +#define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) +#define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF +#define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25) +#define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1) +#define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF +#define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26) +#define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1) +#define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF +#define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27) +#define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1) +#define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF + +#define R_028040_DB_Z_INFO 0x028040 +#define S_028040_FORMAT(x) (((x) & 0x3) << 0) +#define G_028040_FORMAT(x) (((x) >> 0) & 0x3) +#define C_028040_FORMAT 0xFFFFFFFC +#define V_028040_Z_INVALID 0x00000000 +#define V_028040_Z_16 0x00000001 +#define V_028040_Z_24 0x00000002 +#define V_028040_Z_32_FLOAT 0x00000003 +#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) +#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) +#define C_028040_ARRAY_MODE 0xFFFFFF0F +#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) +#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) +#define C_028040_READ_SIZE 0xEFFFFFFF +#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) +#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) +#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF +#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF + +#define R_028044_DB_STENCIL_INFO 0x028044 +#define S_028044_FORMAT(x) (((x) & 0x1) << 0) +#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) +#define C_028044_FORMAT 0xFFFFFFFE + +#define R_028058_DB_DEPTH_SIZE 0x028058 +#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) +#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) +#define C_028058_PITCH_TILE_MAX 0xFFFFF800 +#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) +#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) +#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF + +#define R_02805C_DB_DEPTH_SLICE 0x02805C +#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) +#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) +#define C_02805C_SLICE_TILE_MAX 0xFFC00000 + +#define R_028430_DB_STENCILREFMASK 0x028430 +#define S_028430_STENCILREF(x) (((x) & 0xFF) << 0) +#define G_028430_STENCILREF(x) (((x) >> 0) & 0xFF) +#define C_028430_STENCILREF 0xFFFFFF00 +#define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8) +#define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF) +#define C_028430_STENCILMASK 0xFFFF00FF +#define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16) +#define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF) +#define C_028430_STENCILWRITEMASK 0xFF00FFFF +#define R_028434_DB_STENCILREFMASK_BF 0x028434 +#define S_028434_STENCILREF_BF(x) (((x) & 0xFF) << 0) +#define G_028434_STENCILREF_BF(x) (((x) >> 0) & 0xFF) +#define C_028434_STENCILREF_BF 0xFFFFFF00 +#define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8) +#define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF) +#define C_028434_STENCILMASK_BF 0xFFFF00FF +#define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16) +#define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF) +#define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF +#define R_028780_CB_BLEND_CONTROL 0x028780 +#define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0) +#define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F) +#define C_028780_COLOR_SRCBLEND 0xFFFFFFE0 +#define V_028780_BLEND_ZERO 0x00000000 +#define V_028780_BLEND_ONE 0x00000001 +#define V_028780_BLEND_SRC_COLOR 0x00000002 +#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x00000003 +#define V_028780_BLEND_SRC_ALPHA 0x00000004 +#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x00000005 +#define V_028780_BLEND_DST_ALPHA 0x00000006 +#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x00000007 +#define V_028780_BLEND_DST_COLOR 0x00000008 +#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x00000009 +#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0000000A +#define V_028780_BLEND_BOTH_SRC_ALPHA 0x0000000B +#define V_028780_BLEND_BOTH_INV_SRC_ALPHA 0x0000000C +#define V_028780_BLEND_CONST_COLOR 0x0000000D +#define V_028780_BLEND_ONE_MINUS_CONST_COLOR 0x0000000E +#define V_028780_BLEND_SRC1_COLOR 0x0000000F +#define V_028780_BLEND_INV_SRC1_COLOR 0x00000010 +#define V_028780_BLEND_SRC1_ALPHA 0x00000011 +#define V_028780_BLEND_INV_SRC1_ALPHA 0x00000012 +#define V_028780_BLEND_CONST_ALPHA 0x00000013 +#define V_028780_BLEND_ONE_MINUS_CONST_ALPHA 0x00000014 +#define S_028780_COLOR_COMB_FCN(x) (((x) & 0x7) << 5) +#define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x7) +#define C_028780_COLOR_COMB_FCN 0xFFFFFF1F +#define V_028780_COMB_DST_PLUS_SRC 0x00000000 +#define V_028780_COMB_SRC_MINUS_DST 0x00000001 +#define V_028780_COMB_MIN_DST_SRC 0x00000002 +#define V_028780_COMB_MAX_DST_SRC 0x00000003 +#define V_028780_COMB_DST_MINUS_SRC 0x00000004 +#define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8) +#define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F) +#define C_028780_COLOR_DESTBLEND 0xFFFFE0FF +#define S_028780_OPACITY_WEIGHT(x) (((x) & 0x1) << 13) +#define G_028780_OPACITY_WEIGHT(x) (((x) >> 13) & 0x1) +#define C_028780_OPACITY_WEIGHT 0xFFFFDFFF +#define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16) +#define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F) +#define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF +#define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x7) << 21) +#define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x7) +#define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF +#define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24) +#define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F) +#define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF +#define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29) +#define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1) +#define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF +#define S_028780_BLEND_CONTROL_ENABLE(x) (((x) & 0x1) << 30) +#define G_028780_BLEND_CONTROL_ENABLE(x) (((x) >> 30) & 0x1) +#define C_028780_BLEND_CONTROL_ENABLE 0xEFFFFFFF +#define R_028814_PA_SU_SC_MODE_CNTL 0x028814 +#define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0) +#define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1) +#define C_028814_CULL_FRONT 0xFFFFFFFE +#define S_028814_CULL_BACK(x) (((x) & 0x1) << 1) +#define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1) +#define C_028814_CULL_BACK 0xFFFFFFFD +#define S_028814_FACE(x) (((x) & 0x1) << 2) +#define G_028814_FACE(x) (((x) >> 2) & 0x1) +#define C_028814_FACE 0xFFFFFFFB +#define S_028814_POLY_MODE(x) (((x) & 0x3) << 3) +#define G_028814_POLY_MODE(x) (((x) >> 3) & 0x3) +#define C_028814_POLY_MODE 0xFFFFFFE7 +#define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x7) << 5) +#define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x7) +#define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F +#define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x7) << 8) +#define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x7) +#define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF +#define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11) +#define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1) +#define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF +#define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12) +#define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1) +#define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF +#define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13) +#define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1) +#define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF +#define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16) +#define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1) +#define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF +#define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19) +#define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1) +#define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF +#define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20) +#define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1) +#define C_028814_PERSP_CORR_DIS 0xFFEFFFFF +#define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21) +#define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1) +#define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF + +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028004_SLICE_START 0xFFFFF800 +#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028004_SLICE_MAX 0xFF001FFF +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) +#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) +#define C_028D24_HTILE_WIDTH 0xFFFFFFFE +#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) +#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) +#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD +#define S_028D24_LINEAR(x) (((x) & 0x1) << 2) +#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) +#define C_028D24_LINEAR 0xFFFFFFFB +#define S_028D24_FULL_CACHE(x) (((x) & 0x1) << 3) +#define G_028D24_FULL_CACHE(x) (((x) >> 3) & 0x1) +#define C_028D24_FULL_CACHE 0xFFFFFFF7 +#define S_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 4) +#define G_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) >> 4) & 0x1) +#define C_028D24_HTILE_USES_PRELOAD_WIN 0xFFFFFFEF +#define S_028D24_PRELOAD(x) (((x) & 0x1) << 5) +#define G_028D24_PRELOAD(x) (((x) >> 5) & 0x1) +#define C_028D24_PRELOAD 0xFFFFFFDF +#define S_028D24_PREFETCH_WIDTH(x) (((x) & 0x3F) << 6) +#define G_028D24_PREFETCH_WIDTH(x) (((x) >> 6) & 0x3F) +#define C_028D24_PREFETCH_WIDTH 0xFFFFF03F +#define S_028D24_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 12) +#define G_028D24_PREFETCH_HEIGHT(x) (((x) >> 12) & 0x3F) +#define C_028D24_PREFETCH_HEIGHT 0xFFFC0FFF +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00 +#define R_028D0C_DB_RENDER_CONTROL 0x028D0C +#define S_028D0C_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) +#define S_028D0C_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) +#define S_028D0C_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 15) +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define V_028D10_FORCE_OFF 0 +#define V_028D10_FORCE_ENABLE 1 +#define V_028D10_FORCE_DISABLE 2 +#define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0) +#define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3) +#define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC +#define S_028D10_FORCE_HIS_ENABLE0(x) (((x) & 0x3) << 2) +#define G_028D10_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE0 0xFFFFFFF3 +#define S_028D10_FORCE_HIS_ENABLE1(x) (((x) & 0x3) << 4) +#define G_028D10_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE1 0xFFFFFFCF +#define S_028D10_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) +#define G_028D10_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) +#define C_028D10_FORCE_SHADER_Z_ORDER 0xFFFFFFBF +#define S_028D10_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) +#define G_028D10_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) +#define C_028D10_FAST_Z_DISABLE 0xFFFFFF7F +#define S_028D10_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) +#define G_028D10_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) +#define C_028D10_FAST_STENCIL_DISABLE 0xFFFFFEFF +#define S_028D10_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) +#define G_028D10_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) +#define C_028D10_NOOP_CULL_DISABLE 0xFFFFFDFF +#define S_028D10_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) +#define G_028D10_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) +#define C_028D10_FORCE_COLOR_KILL 0xFFFFFBFF +#define S_028D10_FORCE_Z_READ(x) (((x) & 0x1) << 11) +#define G_028D10_FORCE_Z_READ(x) (((x) >> 11) & 0x1) +#define C_028D10_FORCE_Z_READ 0xFFFFF7FF +#define S_028D10_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) +#define G_028D10_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) +#define C_028D10_FORCE_STENCIL_READ 0xFFFFEFFF +#define S_028D10_FORCE_FULL_Z_RANGE(x) (((x) & 0x3) << 13) +#define G_028D10_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x3) +#define C_028D10_FORCE_FULL_Z_RANGE 0xFFFF9FFF +#define S_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) +#define G_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) +#define C_028D10_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF +#define S_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) +#define G_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) +#define C_028D10_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF +#define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) +#define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) +#define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028DF8 +#define S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0) +#define G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF) +#define C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00 +#define S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8) +#define G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1) +#define C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF +#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028E00 +#define S_028E00_SCALE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028E00_SCALE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028E00_SCALE 0x00000000 +#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028E04 +#define S_028E04_OFFSET(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028E04_OFFSET(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028E04_OFFSET 0x00000000 +#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE 0x028E08 +#define S_028E08_SCALE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028E08_SCALE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028E08_SCALE 0x00000000 +#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028E0C +#define S_028E0C_OFFSET(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028E0C_OFFSET(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028E0C_OFFSET 0x00000000 +#define R_028A00_PA_SU_POINT_SIZE 0x028A00 +#define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0) +#define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF) +#define C_028A00_HEIGHT 0xFFFF0000 +#define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16) +#define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF) +#define C_028A00_WIDTH 0x0000FFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF + +/* diff */ +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define S_0286CC_NUM_INTERP(x) (((x) & 0x3F) << 0) +#define G_0286CC_NUM_INTERP(x) (((x) >> 0) & 0x3F) +#define C_0286CC_NUM_INTERP 0xFFFFFFC0 +#define S_0286CC_POSITION_ENA(x) (((x) & 0x1) << 8) +#define G_0286CC_POSITION_ENA(x) (((x) >> 8) & 0x1) +#define C_0286CC_POSITION_ENA 0xFFFFFEFF +#define S_0286CC_POSITION_CENTROID(x) (((x) & 0x1) << 9) +#define G_0286CC_POSITION_CENTROID(x) (((x) >> 9) & 0x1) +#define C_0286CC_POSITION_CENTROID 0xFFFFFDFF +#define S_0286CC_POSITION_ADDR(x) (((x) & 0x1F) << 10) +#define G_0286CC_POSITION_ADDR(x) (((x) >> 10) & 0x1F) +#define C_0286CC_POSITION_ADDR 0xFFFF83FF +#define S_0286CC_PARAM_GEN(x) (((x) & 0xF) << 15) +#define G_0286CC_PARAM_GEN(x) (((x) >> 15) & 0xF) +#define C_0286CC_PARAM_GEN 0xFFF87FFF +#define S_0286CC_PERSP_GRADIENT_ENA(x) (((x) & 0x1) << 28) +#define G_0286CC_PERSP_GRADIENT_ENA(x) (((x) >> 28) & 0x1) +#define C_0286CC_PERSP_GRADIENT_ENA 0xEFFFFFFF +#define S_0286CC_LINEAR_GRADIENT_ENA(x) (((x) & 0x1) << 29) +#define G_0286CC_LINEAR_GRADIENT_ENA(x) (((x) >> 29) & 0x1) +#define C_0286CC_LINEAR_GRADIENT_ENA 0xDFFFFFFF +#define S_0286CC_POSITION_SAMPLE(x) (((x) & 0x1) << 30) +#define G_0286CC_POSITION_SAMPLE(x) (((x) >> 30) & 0x1) +#define C_0286CC_POSITION_SAMPLE 0xBFFFFFFF +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 8) +#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 8) & 0x1) +#define C_0286D0_FRONT_FACE_ENA 0xFFFFFEFF +#define S_0286D0_FRONT_FACE_CHAN(x) (((x) & 0x3) << 9) +#define G_0286D0_FRONT_FACE_CHAN(x) (((x) >> 9) & 0x3) +#define C_0286D0_FRONT_FACE_CHAN 0xFFFFF9FF +#define S_0286D0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 11) +#define G_0286D0_FRONT_FACE_ALL_BITS(x) (((x) >> 11) & 0x1) +#define C_0286D0_FRONT_FACE_ALL_BITS 0xFFFFF7FF +#define S_0286D0_FRONT_FACE_ADDR(x) (((x) & 0x1F) << 12) +#define G_0286D0_FRONT_FACE_ADDR(x) (((x) >> 12) & 0x1F) +#define C_0286D0_FRONT_FACE_ADDR 0xFFFE0FFF +#define S_0286D0_FOG_ADDR(x) (((x) & 0x7F) << 17) +#define G_0286D0_FOG_ADDR(x) (((x) >> 17) & 0x7F) +#define C_0286D0_FOG_ADDR 0xFF01FFFF +#define S_0286D0_FIXED_PT_POSITION_ENA(x) (((x) & 0x1) << 24) +#define G_0286D0_FIXED_PT_POSITION_ENA(x) (((x) >> 24) & 0x1) +#define C_0286D0_FIXED_PT_POSITION_ENA 0xFEFFFFFF +#define S_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) & 0x1F) << 25) +#define G_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) >> 25) & 0x1F) +#define C_0286D0_FIXED_PT_POSITION_ADDR 0xC1FFFFFF +#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 +#define S_0286C4_VS_PER_COMPONENT(x) (((x) & 0x1) << 0) +#define G_0286C4_VS_PER_COMPONENT(x) (((x) >> 0) & 0x1) +#define C_0286C4_VS_PER_COMPONENT 0xFFFFFFFE +#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) +#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) +#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 +#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 8) +#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 8) & 0x1) +#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFEFF +#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 9) +#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 9) & 0x1F) +#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFC1FF + +#define R_0286E0_SPI_BARYC_CNTL 0x0286E0 +#define S_0286E0_PERSP_CENTER_ENA(x) (((x) & 0x3) << 0) +#define G_0286E0_PERSP_CENTER_ENA(x) (((x) >> 0) & 0x3) +#define C_0286E0_PERSP_CENTER_ENA 0xFFFFFFFC +#define S_0286E0_PERSP_CENTROID_ENA(x) (((x) & 0x3) << 4) +#define G_0286E0_PERSP_CENTROID_ENA(x) (((x) >> 4) & 0x3) +#define C_0286E0_PERSP_CENTROID_ENA 0xFFFFFFCF +#define S_0286E0_PERSP_SAMPLE_ENA(x) (((x) & 0x3) << 8) +#define G_0286E0_PERSP_SAMPLE_ENA(x) (((x) >> 8) & 0x3) +#define C_0286E0_PERSP_SAMPLE_ENA 0xFFFFFCFF +#define S_0286E0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x3) << 12) +#define G_0286E0_PERSP_PULL_MODEL_ENA(x) (((x) >> 12) & 0x3) +#define C_0286E0_PERSP_PULL_MODEL_ENA 0xFFFFCFFF +#define S_0286E0_LINEAR_CENTER_ENA(x) (((x) & 0x3) << 16) +#define G_0286E0_LINEAR_CENTER_ENA(x) (((x) >> 16) & 0x3) +#define C_0286E0_LINEAR_CENTER_ENA 0xFFFCFFFF +#define S_0286E0_LINEAR_CENTROID_ENA(x) (((x) & 0x3) << 20) +#define G_0286E0_LINEAR_CENTROID_ENA(x) (((x) >> 20) & 0x3) +#define C_0286E0_LINEAR_CENTROID_ENA 0xFFCFFFFF +#define S_0286E0_LINEAR_SAMPLE_ENA(x) (((x) & 0x3) << 24) +#define G_0286E0_LINEAR_SAMPLE_ENA(x) (((x) >> 24) & 0x3) +#define C_0286E0_LINEAR_SAMPLE_ENA 0xFCFFFFFF + + +/* new - diff */ +#define R_028250_PA_SC_VPORT_SCISSOR_TL 0x028250 +#define S_028250_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028250_TL_X 0xFFFF8000 +#define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028250_TL_Y 0x8000FFFF +#define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028254_PA_SC_VPORT_SCISSOR_BR 0x028254 +#define S_028254_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028254_BR_X 0xFFFF8000 +#define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028254_BR_Y 0x8000FFFF +/* diff */ +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028240_TL_X 0xFFFF8000 +#define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028240_TL_Y 0x8000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028244_BR_X 0xFFFF8000 +#define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028244_BR_Y 0x8000FFFF +/* diff */ +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0xFFFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF) +#define C_028030_TL_X 0xFFFF0000 +#define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF) +#define C_028030_TL_Y 0x0000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0xFFFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF) +#define C_028034_BR_X 0xFFFF0000 +#define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF) +#define C_028034_BR_Y 0x0000FFFF +/* diff */ +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028204_TL_X 0xFFFF8000 +#define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028204_TL_Y 0x8000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028208_BR_X 0xFFFF8000 +#define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028208_BR_Y 0x8000FFFF + +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x3) << 0) +#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3) +#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC +#define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2) +#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3) +#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 +#define S_0287F0_SPRITE_EN(x) (((x) & 0x1) << 4) +#define G_0287F0_SPRITE_EN(x) (((x) >> 4) & 0x1) +#define C_0287F0_SPRITE_EN 0xFFFFFFEF +#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) +#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) +#define C_0287F0_NOT_EOP 0xFFFFFFDF +#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) +#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) +#define C_0287F0_USE_OPAQUE 0xFFFFFFBF + +#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 +#define S_030000_DIM(x) (((x) & 0x7) << 0) +#define G_030000_DIM(x) (((x) >> 0) & 0x7) +#define C_030000_DIM 0xFFFFFFF8 +#define V_030000_SQ_TEX_DIM_1D 0x00000000 +#define V_030000_SQ_TEX_DIM_2D 0x00000001 +#define V_030000_SQ_TEX_DIM_3D 0x00000002 +#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 +#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 +#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 +#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 +#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 +#define S_030000_PITCH(x) (((x) & 0xFFF) << 6) +#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) +#define C_030000_PITCH 0xFFFC003F +#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) +#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) +#define C_030000_TEX_WIDTH 0x0003FFFF +#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 +#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) +#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) +#define C_030004_TEX_HEIGHT 0xFFFFC000 +#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) +#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) +#define C_030004_TEX_DEPTH 0xF8003FFF +#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) +#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) +#define C_030004_ARRAY_MODE 0x0FFFFFFF +#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 +#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030008_BASE_ADDRESS 0x00000000 +#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C +#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_03000C_MIP_ADDRESS 0x00000000 +#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 +#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) +#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) +#define C_030010_FORMAT_COMP_X 0xFFFFFFFC +#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 +#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 +#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 +#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) +#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) +#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 +#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) +#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) +#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF +#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) +#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) +#define C_030010_FORMAT_COMP_W 0xFFFFFF3F +#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) +#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) +#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF +#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 +#define V_030010_SQ_NUM_FORMAT_INT 0x00000001 +#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 +#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) +#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) +#define C_030010_SRF_MODE_ALL 0xFFFFFBFF +#define V_030010_SFR_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 +#define V_030010_SFR_MODE_NO_ZERO 0x00000001 +#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) +#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) +#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF +#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) +#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) +#define C_030010_ENDIAN_SWAP 0xFFFFCFFF +#define S_030010_REQUEST_SIZE(x) (((x) & 0x3) << 14) +#define G_030010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) +#define C_030010_REQUEST_SIZE 0xFFFF3FFF +#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) +#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) +#define C_030010_DST_SEL_X 0xFFF8FFFF +#define V_030010_SQ_SEL_X 0x00000000 +#define V_030010_SQ_SEL_Y 0x00000001 +#define V_030010_SQ_SEL_Z 0x00000002 +#define V_030010_SQ_SEL_W 0x00000003 +#define V_030010_SQ_SEL_0 0x00000004 +#define V_030010_SQ_SEL_1 0x00000005 +#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) +#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) +#define C_030010_DST_SEL_Y 0xFFC7FFFF +#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) +#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) +#define C_030010_DST_SEL_Z 0xFE3FFFFF +#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) +#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) +#define C_030010_DST_SEL_W 0xF1FFFFFF +#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) +#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) +#define C_030010_BASE_LEVEL 0x0FFFFFFF +#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 +#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) +#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) +#define C_030014_LAST_LEVEL 0xFFFFFFF0 +#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) +#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) +#define C_030014_BASE_ARRAY 0xFFFE000F +#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) +#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) +#define C_030014_LAST_ARRAY 0xC001FFFF +#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 +#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) +#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) +#define C_030018_PERF_MODULATION 0xFFFFFFC7 +#define S_030018_INTERLACED(x) (((x) & 0x1) << 6) +#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) +#define C_030018_INTERLACED 0xFFFFFFBF +#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C +#define S_03001C_TYPE(x) (((x) & 0x3) << 30) +#define G_03001C_TYPE(x) (((x) >> 30) & 0x3) +#define C_03001C_TYPE 0x3FFFFFFF +#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 +#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 +#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 +#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 +#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) +#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) +#define C_03001C_DATA_FORMAT 0xFFFFFFC0 + +#define R_030008_SQ_VTX_CONSTANT_WORD2_0 0x030008 +#define S_030008_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) +#define G_030008_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) +#define C_030008_BASE_ADDRESS_HI 0xFFFFFF00 +#define S_030008_STRIDE(x) (((x) & 0x7FF) << 8) +#define G_030008_STRIDE(x) (((x) >> 8) & 0x7FF) +#define C_030008_STRIDE 0xFFF800FF +#define S_030008_CLAMP_X(x) (((x) & 0x1) << 19) +#define G_030008_CLAMP_X(x) (((x) >> 19) & 0x1) +#define C_030008_CLAMP_X 0xFFF7FFFF +#define S_030008_DATA_FORMAT(x) (((x) & 0x3F) << 20) +#define G_030008_DATA_FORMAT(x) (((x) >> 20) & 0x3F) +#define C_030008_DATA_FORMAT 0xFC0FFFFF +#define V_030008_COLOR_INVALID 0x00000000 +#define V_030008_COLOR_8 0x00000001 +#define V_030008_COLOR_4_4 0x00000002 +#define V_030008_COLOR_3_3_2 0x00000003 +#define V_030008_COLOR_16 0x00000005 +#define V_030008_COLOR_16_FLOAT 0x00000006 +#define V_030008_COLOR_8_8 0x00000007 +#define V_030008_COLOR_5_6_5 0x00000008 +#define V_030008_COLOR_6_5_5 0x00000009 +#define V_030008_COLOR_1_5_5_5 0x0000000A +#define V_030008_COLOR_4_4_4_4 0x0000000B +#define V_030008_COLOR_5_5_5_1 0x0000000C +#define V_030008_COLOR_32 0x0000000D +#define V_030008_COLOR_32_FLOAT 0x0000000E +#define V_030008_COLOR_16_16 0x0000000F +#define V_030008_COLOR_16_16_FLOAT 0x00000010 +#define V_030008_COLOR_8_24 0x00000011 +#define V_030008_COLOR_8_24_FLOAT 0x00000012 +#define V_030008_COLOR_24_8 0x00000013 +#define V_030008_COLOR_24_8_FLOAT 0x00000014 +#define V_030008_COLOR_10_11_11 0x00000015 +#define V_030008_COLOR_10_11_11_FLOAT 0x00000016 +#define V_030008_COLOR_11_11_10 0x00000017 +#define V_030008_COLOR_11_11_10_FLOAT 0x00000018 +#define V_030008_COLOR_2_10_10_10 0x00000019 +#define V_030008_COLOR_8_8_8_8 0x0000001A +#define V_030008_COLOR_10_10_10_2 0x0000001B +#define V_030008_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_030008_COLOR_32_32 0x0000001D +#define V_030008_COLOR_32_32_FLOAT 0x0000001E +#define V_030008_COLOR_16_16_16_16 0x0000001F +#define V_030008_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_030008_COLOR_32_32_32_32 0x00000022 +#define V_030008_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_030008_NUM_FORMAT_ALL(x) (((x) & 0x3) << 26) +#define G_030008_NUM_FORMAT_ALL(x) (((x) >> 26) & 0x3) +#define C_030008_NUM_FORMAT_ALL 0xF3FFFFFF +#define S_030008_FORMAT_COMP_ALL(x) (((x) & 0x1) << 28) +#define G_030008_FORMAT_COMP_ALL(x) (((x) >> 28) & 0x1) +#define C_030008_FORMAT_COMP_ALL 0xEFFFFFFF +#define S_030008_SRF_MODE_ALL(x) (((x) & 0x1) << 29) +#define G_030008_SRF_MODE_ALL(x) (((x) >> 29) & 0x1) +#define C_030008_SRF_MODE_ALL 0xDFFFFFFF +#define S_030008_ENDIAN_SWAP(x) (((x) & 0x3) << 30) +#define G_030008_ENDIAN_SWAP(x) (((x) >> 30) & 0x3) +#define C_030008_ENDIAN_SWAP 0x3FFFFFFF + +#define R_03000C_SQ_VTX_CONSTANT_WORD3_0 0x03000C +#define S_03000C_DST_SEL_X(x) (((x) & 0x7) << 3) +#define G_03000C_DST_SEL_X(x) (((x) >> 3) & 0x7) +#define V_03000C_SQ_SEL_X 0x00000000 +#define V_03000C_SQ_SEL_Y 0x00000001 +#define V_03000C_SQ_SEL_Z 0x00000002 +#define V_03000C_SQ_SEL_W 0x00000003 +#define V_03000C_SQ_SEL_0 0x00000004 +#define V_03000C_SQ_SEL_1 0x00000005 +#define S_03000C_DST_SEL_Y(x) (((x) & 0x7) << 6) +#define G_03000C_DST_SEL_Y(x) (((x) >> 6) & 0x7) +#define S_03000C_DST_SEL_Z(x) (((x) & 0x7) << 9) +#define G_03000C_DST_SEL_Z(x) (((x) >> 9) & 0x7) +#define S_03000C_DST_SEL_W(x) (((x) & 0x7) << 12) +#define G_03000C_DST_SEL_W(x) (((x) >> 12) & 0x7) + +#define R_03C000_SQ_TEX_SAMPLER_WORD0_0 0x03C000 +#define S_03C000_CLAMP_X(x) (((x) & 0x7) << 0) +#define G_03C000_CLAMP_X(x) (((x) >> 0) & 0x7) +#define C_03C000_CLAMP_X 0xFFFFFFF8 +#define V_03C000_SQ_TEX_WRAP 0x00000000 +#define V_03C000_SQ_TEX_MIRROR 0x00000001 +#define V_03C000_SQ_TEX_CLAMP_LAST_TEXEL 0x00000002 +#define V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x00000003 +#define V_03C000_SQ_TEX_CLAMP_HALF_BORDER 0x00000004 +#define V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x00000005 +#define V_03C000_SQ_TEX_CLAMP_BORDER 0x00000006 +#define V_03C000_SQ_TEX_MIRROR_ONCE_BORDER 0x00000007 +#define S_03C000_CLAMP_Y(x) (((x) & 0x7) << 3) +#define G_03C000_CLAMP_Y(x) (((x) >> 3) & 0x7) +#define C_03C000_CLAMP_Y 0xFFFFFFC7 +#define S_03C000_CLAMP_Z(x) (((x) & 0x7) << 6) +#define G_03C000_CLAMP_Z(x) (((x) >> 6) & 0x7) +#define C_03C000_CLAMP_Z 0xFFFFFE3F +#define S_03C000_XY_MAG_FILTER(x) (((x) & 0x3) << 9) +#define G_03C000_XY_MAG_FILTER(x) (((x) >> 9) & 0x3) +#define C_03C000_XY_MAG_FILTER 0xFFFFF9FF +#define V_03C000_SQ_TEX_XY_FILTER_POINT 0x00000000 +#define V_03C000_SQ_TEX_XY_FILTER_BILINEAR 0x00000001 +#define S_03C000_XY_MIN_FILTER(x) (((x) & 0x3) << 11) +#define G_03C000_XY_MIN_FILTER(x) (((x) >> 11) & 0x3) +#define C_03C000_XY_MIN_FILTER 0xFFFFE7FF +#define S_03C000_Z_FILTER(x) (((x) & 0x3) << 13) +#define G_03C000_Z_FILTER(x) (((x) >> 13) & 0x3) +#define C_03C000_Z_FILTER 0xFFFF9FFF +#define V_03C000_SQ_TEX_Z_FILTER_NONE 0x00000000 +#define V_03C000_SQ_TEX_Z_FILTER_POINT 0x00000001 +#define V_03C000_SQ_TEX_Z_FILTER_LINEAR 0x00000002 +#define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 15) +#define G_03C000_MIP_FILTER(x) (((x) >> 15) & 0x3) +#define C_03C000_MIP_FILTER 0xFFFE7FFF +#define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 20) +#define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 20) & 0x3) +#define C_03C000_BORDER_COLOR_TYPE 0xFFCFFFFF +#define V_03C000_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00000000 +#define V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x00000001 +#define V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x00000002 +#define V_03C000_SQ_TEX_BORDER_COLOR_REGISTER 0x00000003 +#define S_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) & 0x7) << 22) +#define G_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) >> 22) & 0x7) +#define C_03C000_DEPTH_COMPARE_FUNCTION 0xFE3FFFFF +#define V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER 0x00000000 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_LESS 0x00000001 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL 0x00000002 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x00000003 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER 0x00000004 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x00000005 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x00000006 +#define V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x00000007 +#define S_03C000_CHROMA_KEY(x) (((x) & 0x3) << 25) +#define G_03C000_CHROMA_KEY(x) (((x) >> 25) & 0x3) +#define C_03C000_CHROMA_KEY 0xF9FFFFFF +#define V_03C000_SQ_TEX_CHROMA_KEY_DISABLE 0x00000000 +#define V_03C000_SQ_TEX_CHROMA_KEY_KILL 0x00000001 +#define V_03C000_SQ_TEX_CHROMA_KEY_BLEND 0x00000002 + +#define R_03C004_SQ_TEX_SAMPLER_WORD1_0 0x03C004 +#define S_03C004_MIN_LOD(x) (((x) & 0xFFF) << 0) +#define G_03C004_MIN_LOD(x) (((x) >> 0) & 0xFFF) +#define C_03C004_MIN_LOD 0xFFFFF000 +#define S_03C004_MAX_LOD(x) (((x) & 0xFFF) << 12) +#define G_03C004_MAX_LOD(x) (((x) >> 12) & 0xFFF) +#define C_03C004_MAX_LOD 0xFF000FFF + +#define S_03C004_PERF_MIP(x) (((x) & 0xF) << 24) +#define G_03C004_PERF_MIP(x) (((x) >> 24) & 0xF) +#define C_03C004_PERF_MIP 0xF0FFFFFF +#define S_03C004_PERF_Z(x) (((x) & 0xF) << 28) +#define G_03C004_PERF_Z(x) (((x) >> 24) & 0xF) +#define C_03C004_PERF_Z 0x0FFFFFFF + +#define R_03C008_SQ_TEX_SAMPLER_WORD2_0 0x03C008 +#define S_03C008_LOD_BIAS(x) (((x) & 0x3FFF) << 0) +#define G_03C008_LOD_BIAS(x) (((x) >> 0) & 0x3FFF) +#define C_03C008_LOD_BIAS 0xFFFFC000 +#define S_03C008_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14) +#define G_03C008_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F) +#define C_03C008_LOD_BIAS_SEC 0xFFF03FFF +#define S_03C008_MC_COORD_TRUNCATE(x) (((x) & 0x1) << 20) +#define G_03C008_MC_COORD_TRUNCATE(x) (((x) >> 20) & 0x1) +#define C_03C008_MC_COORD_TRUNCATE 0xFFEFFFFF +#define S_03C008_FORCE_DEGAMMA(x) (((x) & 0x1) << 21) +#define G_03C008_FORCE_DEGAMMA(x) (((x) >> 21) & 0x1) +#define C_03C008_FORCE_DEGAMMA 0xFFDFFFFF +#define S_03C008_TYPE(x) (((x) & 0x1) << 31) +#define G_03C008_TYPE(x) (((x) >> 31) & 0x1) +#define C_03C008_TYPE 0x7FFFFFFF + +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_008958_PRIM_TYPE 0xFFFFFFC0 +#define V_008958_DI_PT_NONE 0x00000000 +#define V_008958_DI_PT_POINTLIST 0x00000001 +#define V_008958_DI_PT_LINELIST 0x00000002 +#define V_008958_DI_PT_LINESTRIP 0x00000003 +#define V_008958_DI_PT_TRILIST 0x00000004 +#define V_008958_DI_PT_TRIFAN 0x00000005 +#define V_008958_DI_PT_TRISTRIP 0x00000006 +#define V_008958_DI_PT_UNUSED_0 0x00000007 +#define V_008958_DI_PT_UNUSED_1 0x00000008 +#define V_008958_DI_PT_UNUSED_2 0x00000009 +#define V_008958_DI_PT_LINELIST_ADJ 0x0000000A +#define V_008958_DI_PT_LINESTRIP_ADJ 0x0000000B +#define V_008958_DI_PT_TRILIST_ADJ 0x0000000C +#define V_008958_DI_PT_TRISTRIP_ADJ 0x0000000D +#define V_008958_DI_PT_UNUSED_3 0x0000000E +#define V_008958_DI_PT_UNUSED_4 0x0000000F +#define V_008958_DI_PT_TRI_WITH_WFLAGS 0x00000010 +#define V_008958_DI_PT_RECTLIST 0x00000011 +#define V_008958_DI_PT_LINELOOP 0x00000012 +#define V_008958_DI_PT_QUADLIST 0x00000013 +#define V_008958_DI_PT_QUADSTRIP 0x00000014 +#define V_008958_DI_PT_POLYGON 0x00000015 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x00000016 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x00000017 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x00000018 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x00000019 +#define V_008958_DI_PT_2D_FILL_RECT_LIST 0x0000001A +#define V_008958_DI_PT_2D_LINE_STRIP 0x0000001B +#define V_008958_DI_PT_2D_TRI_STRIP 0x0000001C +#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C +#define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0) +#define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1) +#define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE +#define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1) +#define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1) +#define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD +#define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2) +#define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1) +#define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB +#define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3) +#define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1) +#define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7 +#define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4) +#define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1) +#define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF +#define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5) +#define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1) +#define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF +#define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6) +#define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1) +#define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF +#define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7) +#define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1) +#define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F +#define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8) +#define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1) +#define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF +#define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9) +#define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1) +#define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF +#define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10) +#define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1) +#define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF +#define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11) +#define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1) +#define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF +#define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12) +#define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1) +#define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF +#define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13) +#define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1) +#define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF +#define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14) +#define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1) +#define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF +#define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15) +#define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1) +#define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF +#define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16) +#define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1) +#define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF +#define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17) +#define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1) +#define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF +#define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18) +#define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1) +#define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF +#define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19) +#define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1) +#define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF +#define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20) +#define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1) +#define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF +#define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21) +#define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1) +#define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF +#define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22) +#define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1) +#define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF +#define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23) +#define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1) +#define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF +/* diff */ +#define R_028860_SQ_PGM_RESOURCES_VS 0x028860 +#define S_028860_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_028860_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_028860_NUM_GPRS 0xFFFFFF00 +#define S_028860_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_028860_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_028860_STACK_SIZE 0xFFFF00FF +#define S_028860_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_028860_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_028860_DX10_CLAMP 0xFFDFFFFF +#define S_028860_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28) +#define G_028860_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1) +#define C_028860_UNCACHED_FIRST_INST 0xEFFFFFFF +#define R_028864_SQ_PGM_RESOURCES_2_VS 0x028864 + +#define R_028844_SQ_PGM_RESOURCES_PS 0x028844 +#define S_028844_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_028844_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_028844_NUM_GPRS 0xFFFFFF00 +#define S_028844_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_028844_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_028844_STACK_SIZE 0xFFFF00FF +#define S_028844_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_028844_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_028844_DX10_CLAMP 0xFFDFFFFF +#define S_028844_PRIME_CACHE_ON_DRAW(x) (((x) & 0x1) << 23) +#define G_028844_PRIME_CACHE_ON_DRAW(x) (((x) >> 23) & 0x1) + +#define S_028844_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28) +#define G_028844_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1) +#define C_028844_UNCACHED_FIRST_INST 0xEFFFFFFF +#define S_028844_CLAMP_CONSTS(x) (((x) & 0x1) << 31) +#define G_028844_CLAMP_CONSTS(x) (((x) >> 31) & 0x1) +#define C_028844_CLAMP_CONSTS 0x7FFFFFFF +#define R_028848_SQ_PGM_RESOURCES_2_PS 0x028848 + +#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 +#define S_028644_SEMANTIC(x) (((x) & 0xFF) << 0) +#define G_028644_SEMANTIC(x) (((x) >> 0) & 0xFF) +#define C_028644_SEMANTIC 0xFFFFFF00 +#define S_028644_DEFAULT_VAL(x) (((x) & 0x3) << 8) +#define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x3) +#define C_028644_DEFAULT_VAL 0xFFFFFCFF +#define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) +#define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) +#define C_028644_FLAT_SHADE 0xFFFFFBFF +#define S_028644_SEL_CENTROID(x) (((x) & 0x1) << 11) +#define G_028644_SEL_CENTROID(x) (((x) >> 11) & 0x1) +#define C_028644_SEL_CENTROID 0xFFFFF7FF +#define S_028644_SEL_LINEAR(x) (((x) & 0x1) << 12) +#define G_028644_SEL_LINEAR(x) (((x) >> 12) & 0x1) +#define C_028644_SEL_LINEAR 0xFFFFEFFF +#define S_028644_CYL_WRAP(x) (((x) & 0xF) << 13) +#define G_028644_CYL_WRAP(x) (((x) >> 13) & 0xF) +#define C_028644_CYL_WRAP 0xFFFE1FFF +#define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) +#define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) +#define C_028644_PT_SPRITE_TEX 0xFFFDFFFF +#define S_028644_SEL_SAMPLE(x) (((x) & 0x1) << 18) +#define G_028644_SEL_SAMPLE(x) (((x) >> 18) & 0x1) +#define C_028644_SEL_SAMPLE 0xFFFBFFFF +#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 +#define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) +#define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) +#define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE +#define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) +#define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) +#define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD +#define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x7) << 2) +#define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 +#define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x7) << 5) +#define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F +#define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x7) << 8) +#define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF +#define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x7) << 11) +#define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF +#define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) +#define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) +#define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF + +#define SQ_TEX_INST_LD 0x03 +#define SQ_TEX_INST_GET_GRADIENTS_H 0x7 +#define SQ_TEX_INST_GET_GRADIENTS_V 0x8 + +#define SQ_TEX_INST_SAMPLE 0x10 +#define SQ_TEX_INST_SAMPLE_L 0x11 +#define SQ_TEX_INST_SAMPLE_C 0x18 +#endif diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 6483dac7039..662b9b9115d 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -24,9 +24,61 @@ #include "r600_context.h" #include "util/u_memory.h" #include "r600_sq.h" +#include "r600_opcodes.h" #include <stdio.h> #include <errno.h> +static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu) +{ + if(alu->is_op3) + return 3; + + switch (alu->inst) { + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP: + return 0; + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE: + return 2; + + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS: + return 1; + + default: R600_ERR( + "Need instruction operand number for 0x%x.\n", alu->inst); + }; + + return 3; +} + int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id); static struct r600_bc_cf *r600_bc_cf(void) @@ -49,6 +101,7 @@ static struct r600_bc_alu *r600_bc_alu(void) if (alu == NULL) return NULL; LIST_INITHEAD(&alu->list); + LIST_INITHEAD(&alu->bs_list); return alu; } @@ -93,6 +146,13 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family) case CHIP_RV740: bc->chiprev = 1; break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + bc->chiprev = 2; + break; default: R600_ERR("unknown family %d\n", bc->family); return -EINVAL; @@ -128,6 +188,224 @@ int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output) return 0; } +const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000 + SQ_ALU_VEC_120, //001 + SQ_ALU_VEC_102, //010 + + SQ_ALU_VEC_201, //011 + SQ_ALU_VEC_012, //100 + SQ_ALU_VEC_021, //101 + + SQ_ALU_VEC_012, //110 + SQ_ALU_VEC_012}; //111 + +const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000 + SQ_ALU_SCL_122, //001 + SQ_ALU_SCL_122, //010 + + SQ_ALU_SCL_221, //011 + SQ_ALU_SCL_212, //100 + SQ_ALU_SCL_122, //101 + + SQ_ALU_SCL_122, //110 + SQ_ALU_SCL_122}; //111 + +static int init_gpr(struct r600_bc_alu *alu) +{ + int cycle, component; + /* set up gpr use */ + for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++) + for (component = 0; component < NUM_OF_COMPONENTS; component++) + alu->hw_gpr[cycle][component] = -1; + return 0; +} + +#if 0 +static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle) +{ + if (alu->hw_gpr[cycle][chan] < 0) + alu->hw_gpr[cycle][chan] = sel; + else if (alu->hw_gpr[cycle][chan] != (int)sel) { + R600_ERR("Another scalar operation has already used GPR read port for channel\n"); + return -1; + } + return 0; +} + +static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle) +{ + int table[3]; + int ret = 0; + switch (swiz) { + case SQ_ALU_SCL_210: + table[0] = 2; table[1] = 1; table[2] = 0; + *p_cycle = table[sel]; + break; + case SQ_ALU_SCL_122: + table[0] = 1; table[1] = 2; table[2] = 2; + *p_cycle = table[sel]; + break; + case SQ_ALU_SCL_212: + table[0] = 2; table[1] = 1; table[2] = 2; + *p_cycle = table[sel]; + break; + case SQ_ALU_SCL_221: + table[0] = 2; table[1] = 2; table[2] = 1; + *p_cycle = table[sel]; + break; + break; + default: + R600_ERR("bad scalar bank swizzle value\n"); + ret = -1; + break; + } + return ret; +} + +static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle) +{ + int table[3]; + int ret; + + switch (swiz) { + case SQ_ALU_VEC_012: + table[0] = 0; table[1] = 1; table[2] = 2; + *p_cycle = table[sel]; + break; + case SQ_ALU_VEC_021: + table[0] = 0; table[1] = 2; table[2] = 1; + *p_cycle = table[sel]; + break; + case SQ_ALU_VEC_120: + table[0] = 1; table[1] = 2; table[2] = 0; + *p_cycle = table[sel]; + break; + case SQ_ALU_VEC_102: + table[0] = 1; table[1] = 0; table[2] = 2; + *p_cycle = table[sel]; + break; + case SQ_ALU_VEC_201: + table[0] = 2; table[1] = 0; table[2] = 1; + *p_cycle = table[sel]; + break; + case SQ_ALU_VEC_210: + table[0] = 2; table[1] = 1; table[2] = 0; + *p_cycle = table[sel]; + break; + default: + R600_ERR("bad vector bank swizzle value\n"); + ret = -1; + break; + } + return ret; +} + + + +static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter) +{ + int num_src; + int i; + int channel_swizzle; + + num_src = r600_bc_get_num_operands(alu); + + for (i = 0; i < num_src; i++) { + channel_swizzle = alu->src[i].chan; + if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3) + chan_counter[channel_swizzle]++; + } +} + +/* we need something like this I think - but this is bogus */ +int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first) +{ + struct r600_bc_alu *alu; + int chan_counter[4] = { 0 }; + + update_chan_counter(alu_first, chan_counter); + + LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) { + update_chan_counter(alu, chan_counter); + } + + if (chan_counter[0] > 3 || + chan_counter[1] > 3 || + chan_counter[2] > 3 || + chan_counter[3] > 3) { + R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n", + alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]); + return -1; + } + return 0; +} +#endif + +static int is_const(int sel) +{ + if (sel > 255 && sel < 512) + return 1; + if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL) + return 1; + return 0; +} + +static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu) +{ + unsigned swizzle_key; + + if (alu->bank_swizzle_force) { + alu->bank_swizzle = alu->bank_swizzle_force; + return 0; + } + swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + + (is_const(alu->src[1].sel) ? 2 : 0 ) + + (is_const(alu->src[2].sel) ? 1 : 0 ); + + alu->bank_swizzle = bank_swizzle_scl[swizzle_key]; + return 0; +} + +static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu) +{ + unsigned swizzle_key; + + if (alu->bank_swizzle_force) { + alu->bank_swizzle = alu->bank_swizzle_force; + return 0; + } + swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + + (is_const(alu->src[1].sel) ? 2 : 0 ) + + (is_const(alu->src[2].sel) ? 1 : 0 ); + + alu->bank_swizzle = bank_swizzle_vec[swizzle_key]; + return 0; +} + +static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first) +{ + struct r600_bc_alu *alu = NULL; + int num_instr = 1; + + init_gpr(alu_first); + + LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) { + num_instr++; + } + + if (num_instr == 1) { + check_scalar(bc, alu_first); + + } else { +/* check_read_slots(bc, bc->cf_last->curr_bs_head);*/ + check_vector(bc, alu_first); + LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) { + check_vector(bc, alu); + } + } + return 0; +} + int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type) { struct r600_bc_alu *nalu = r600_bc_alu(); @@ -150,6 +428,12 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int } bc->cf_last->inst = (type << 3); } + if (!bc->cf_last->curr_bs_head) { + bc->cf_last->curr_bs_head = nalu; + LIST_INITHEAD(&nalu->bs_list); + } else { + LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list); + } if (alu->last && (bc->cf_last->ndw >> 1) >= 124) { bc->force_add_cf = 1; } @@ -180,12 +464,21 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int /* each alu use 2 dwords */ bc->cf_last->ndw += 2; bc->ndw += 2; + + if (bc->use_mem_constant) + bc->cf_last->kcache0_mode = 2; + + /* process cur ALU instructions for bank swizzle */ + if (alu->last) { + check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head); + bc->cf_last->curr_bs_head = NULL; + } return 0; } int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu) { - return r600_bc_add_alu_type(bc, alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU); + return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU)); } int r600_bc_add_literal(struct r600_bc *bc, const u32 *value) @@ -198,6 +491,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value) if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) { return 0; } + /* all same on EG */ if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP || bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE || bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL || @@ -207,6 +501,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value) bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) { return 0; } + /* same on EG */ if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) && (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) || LIST_IS_EMPTY(&bc->cf_last->alu)) { @@ -289,6 +584,7 @@ int r600_bc_add_cfinst(struct r600_bc *bc, int inst) return 0; } +/* common to all 3 families */ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id) { bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) | @@ -306,6 +602,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign return 0; } +/* common to all 3 families */ static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id) { bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) | @@ -335,6 +632,7 @@ static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsign return 0; } +/* r600 only, r700/eg bits in r700_asm.c */ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id) { unsigned i; @@ -360,7 +658,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) | - S_SQ_ALU_WORD1_BANK_SWIZZLE(0); + S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); } else { bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | @@ -370,13 +668,13 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) | - S_SQ_ALU_WORD1_BANK_SWIZZLE(0) | + S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) | S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate); } if (alu->last) { if (alu->nliteral && !alu->literal_added) { - R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n"); + R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst); } for (i = 0; i < alu->nliteral; i++) { bc->bytecode[id++] = alu->value[i]; @@ -385,6 +683,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign return 0; } +/* common for r600/r700 - eg in eg_asm.c */ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf) { unsigned id = cf->id; @@ -392,7 +691,9 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf) switch (cf->inst) { case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3): case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3): - bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1); + bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) | + S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode); + bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) | S_SQ_CF_ALU_WORD1_BARRIER(1) | S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); @@ -469,6 +770,8 @@ int r600_bc_build(struct r600_bc *bc) break; case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT: case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE: + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT: + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE: break; case V_SQ_CF_WORD1_SQ_CF_INST_JUMP: case V_SQ_CF_WORD1_SQ_CF_INST_ELSE: @@ -492,7 +795,10 @@ int r600_bc_build(struct r600_bc *bc) return -ENOMEM; LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) { addr = cf->addr; - r = r600_bc_cf_build(bc, cf); + if (bc->chiprev == 2) + r = eg_bc_cf_build(bc, cf); + else + r = r600_bc_cf_build(bc, cf); if (r) return r; switch (cf->inst) { @@ -504,6 +810,7 @@ int r600_bc_build(struct r600_bc *bc) r = r600_bc_alu_build(bc, alu, addr); break; case 1: + case 2: /* eg alu is same encoding as r700 */ r = r700_bc_alu_build(bc, alu, addr); break; default: @@ -537,6 +844,8 @@ int r600_bc_build(struct r600_bc *bc) break; case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT: case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE: + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT: + case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE: case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL: case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END: case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE: diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h index 9e65fcdd4fa..cc62535e5cd 100644 --- a/src/gallium/drivers/r600/r600_asm.h +++ b/src/gallium/drivers/r600/r600_asm.h @@ -26,6 +26,9 @@ #include "radeon.h" #include "util/u_double_list.h" +#define NUM_OF_CYCLES 3 +#define NUM_OF_COMPONENTS 4 + struct r600_bc_alu_src { unsigned sel; unsigned chan; @@ -44,6 +47,7 @@ struct r600_bc_alu_dst { struct r600_bc_alu { struct list_head list; + struct list_head bs_list; /* bank swizzle list */ struct r600_bc_alu_src src[3]; struct r600_bc_alu_dst dst; unsigned inst; @@ -52,7 +56,10 @@ struct r600_bc_alu { unsigned predicate; unsigned nliteral; unsigned literal_added; + unsigned bank_swizzle; + unsigned bank_swizzle_force; u32 value[4]; + int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS]; }; struct r600_bc_tex { @@ -120,10 +127,12 @@ struct r600_bc_cf { unsigned cond; unsigned pop_count; unsigned cf_addr; /* control flow addr */ + unsigned kcache0_mode; struct list_head alu; struct list_head tex; struct list_head vtx; struct r600_bc_output output; + struct r600_bc_alu *curr_bs_head; }; #define FC_NONE 0 @@ -151,6 +160,7 @@ struct r600_cf_callstack { struct r600_bc { enum radeon_family family; int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */ + unsigned use_mem_constant; struct list_head cf; struct r600_bc_cf *cf_last; unsigned ndw; diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c index 7829a479c2e..06197d3d7d9 100644 --- a/src/gallium/drivers/r600/r600_buffer.c +++ b/src/gallium/drivers/r600/r600_buffer.c @@ -56,6 +56,9 @@ u32 r600_domain_from_usage(unsigned usage) if (usage & PIPE_BIND_INDEX_BUFFER) { domain |= RADEON_GEM_DOMAIN_GTT; } + if (usage & PIPE_BIND_CONSTANT_BUFFER) { + domain |= RADEON_GEM_DOMAIN_VRAM; + } return domain; } @@ -79,7 +82,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, rbuffer->base.b.screen = screen; rbuffer->base.vtbl = &r600_buffer_vtbl; - if (rbuffer->base.b.bind & PIPE_BIND_CONSTANT_BUFFER) { + if ((rscreen->use_mem_constant == FALSE) && (rbuffer->base.b.bind & PIPE_BIND_CONSTANT_BUFFER)) { desc.alignment = alignment; desc.usage = rbuffer->base.b.bind; rbuffer->pb = pb_malloc_buffer_create(rbuffer->base.b.width0, @@ -153,7 +156,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe, int write = 0; if (rbuffer->pb) { - return (uint8_t*)pb_map(rbuffer->pb, transfer->usage) + transfer->box.x; + return (uint8_t*)pb_map(rbuffer->pb, transfer->usage, NULL) + transfer->box.x; } if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) { /* FIXME */ diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c index 7a0e5b4049f..00df4dcd428 100644 --- a/src/gallium/drivers/r600/r600_context.c +++ b/src/gallium/drivers/r600/r600_context.c @@ -32,8 +32,6 @@ #include "r600_screen.h" #include "r600_context.h" #include "r600_resource.h" -#include "r600d.h" - static void r600_destroy_context(struct pipe_context *context) { @@ -53,6 +51,11 @@ static void r600_destroy_context(struct pipe_context *context) rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref); rctx->viewport = r600_context_state_decref(rctx->viewport); rctx->framebuffer = r600_context_state_decref(rctx->framebuffer); + + free(rctx->ps_constant); + free(rctx->vs_constant); + free(rctx->vs_resource); + radeon_ctx_fini(&rctx->ctx); FREE(rctx); } @@ -61,9 +64,11 @@ void r600_flush(struct pipe_context *ctx, unsigned flags, struct pipe_fence_handle **fence) { struct r600_context *rctx = r600_context(ctx); - struct r600_query *rquery; + struct r600_query *rquery = NULL; static int dc = 0; +#if 0 char dname[256]; +#endif /* suspend queries */ r600_queries_suspend(ctx); @@ -92,237 +97,6 @@ out: r600_queries_resume(ctx); } -static void r600_init_config(struct r600_context *rctx) -{ - int ps_prio; - int vs_prio; - int gs_prio; - int es_prio; - int num_ps_gprs; - int num_vs_gprs; - int num_gs_gprs; - int num_es_gprs; - int num_temp_gprs; - int num_ps_threads; - int num_vs_threads; - int num_gs_threads; - int num_es_threads; - int num_ps_stack_entries; - int num_vs_stack_entries; - int num_gs_stack_entries; - int num_es_stack_entries; - enum radeon_family family; - - family = radeon_get_family(rctx->rw); - ps_prio = 0; - vs_prio = 1; - gs_prio = 2; - es_prio = 3; - switch (family) { - case CHIP_R600: - num_ps_gprs = 192; - num_vs_gprs = 56; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 136; - num_vs_threads = 48; - num_gs_threads = 4; - num_es_threads = 4; - num_ps_stack_entries = 128; - num_vs_stack_entries = 128; - num_gs_stack_entries = 0; - num_es_stack_entries = 0; - break; - case CHIP_RV630: - case CHIP_RV635: - num_ps_gprs = 84; - num_vs_gprs = 36; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 144; - num_vs_threads = 40; - num_gs_threads = 4; - num_es_threads = 4; - num_ps_stack_entries = 40; - num_vs_stack_entries = 40; - num_gs_stack_entries = 32; - num_es_stack_entries = 16; - break; - case CHIP_RV610: - case CHIP_RV620: - case CHIP_RS780: - case CHIP_RS880: - default: - num_ps_gprs = 84; - num_vs_gprs = 36; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 136; - num_vs_threads = 48; - num_gs_threads = 4; - num_es_threads = 4; - num_ps_stack_entries = 40; - num_vs_stack_entries = 40; - num_gs_stack_entries = 32; - num_es_stack_entries = 16; - break; - case CHIP_RV670: - num_ps_gprs = 144; - num_vs_gprs = 40; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 136; - num_vs_threads = 48; - num_gs_threads = 4; - num_es_threads = 4; - num_ps_stack_entries = 40; - num_vs_stack_entries = 40; - num_gs_stack_entries = 32; - num_es_stack_entries = 16; - break; - case CHIP_RV770: - num_ps_gprs = 192; - num_vs_gprs = 56; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 188; - num_vs_threads = 60; - num_gs_threads = 0; - num_es_threads = 0; - num_ps_stack_entries = 256; - num_vs_stack_entries = 256; - num_gs_stack_entries = 0; - num_es_stack_entries = 0; - break; - case CHIP_RV730: - case CHIP_RV740: - num_ps_gprs = 84; - num_vs_gprs = 36; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 188; - num_vs_threads = 60; - num_gs_threads = 0; - num_es_threads = 0; - num_ps_stack_entries = 128; - num_vs_stack_entries = 128; - num_gs_stack_entries = 0; - num_es_stack_entries = 0; - break; - case CHIP_RV710: - num_ps_gprs = 192; - num_vs_gprs = 56; - num_temp_gprs = 4; - num_gs_gprs = 0; - num_es_gprs = 0; - num_ps_threads = 144; - num_vs_threads = 48; - num_gs_threads = 0; - num_es_threads = 0; - num_ps_stack_entries = 128; - num_vs_stack_entries = 128; - num_gs_stack_entries = 0; - num_es_stack_entries = 0; - break; - } - radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0); - - rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000; - switch (family) { - case CHIP_RV610: - case CHIP_RV620: - case CHIP_RS780: - case CHIP_RS880: - case CHIP_RV710: - break; - default: - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1); - break; - } - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1); - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1); - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio); - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio); - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio); - rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio); - - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0; - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs); - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs); - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); - - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0; - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs); - rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs); - - rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0; - rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads); - rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads); - rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads); - rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads); - - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0; - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); - - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0; - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); - rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); - - rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000; - rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000; - - if (family >= CHIP_RV770) { - rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000; - rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002; - rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000; - rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204; - rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000; - rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000; - } else { - rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000; - rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003; - rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000; - rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204; - rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001; - rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010; - } - rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003; - rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001; - rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000; - rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000; - radeon_state_pm4(&rctx->config); -} - struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) { struct r600_context *rctx = CALLOC_STRUCT(r600_context); @@ -341,6 +115,11 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) rctx->screen = rscreen; rctx->rw = rscreen->rw; + if (rscreen->chip_class == EVERGREEN) + rctx->vtbl = &eg_hw_state_vtbl; + else + rctx->vtbl = &r600_hw_state_vtbl; + r600_init_blit_functions(rctx); r600_init_query_functions(rctx); r600_init_state_functions(rctx); @@ -352,7 +131,25 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) return NULL; } - r600_init_config(rctx); + rctx->vtbl->init_config(rctx); + + rctx->vs_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state)); + if (!rctx->vs_constant) { + FREE(rctx); + return NULL; + } + + rctx->ps_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state)); + if (!rctx->ps_constant) { + FREE(rctx); + return NULL; + } + + rctx->vs_resource = (struct radeon_state *)calloc(R600_MAX_RESOURCE, sizeof(struct radeon_state)); + if (!rctx->vs_resource) { + FREE(rctx); + return NULL; + } radeon_ctx_init(&rctx->ctx, rscreen->rw); radeon_draw_init(&rctx->draw, rscreen->rw); diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h index cea08130545..58f6d0232b0 100644 --- a/src/gallium/drivers/r600/r600_context.h +++ b/src/gallium/drivers/r600/r600_context.h @@ -119,7 +119,63 @@ struct r600_context_hw_states { struct radeon_state scissor; struct radeon_state dsa; struct radeon_state cb_cntl; + + struct radeon_state db_flush; + struct radeon_state cb_flush; +}; + +#define R600_MAX_CONSTANT 256 /* magic */ +#define R600_MAX_RESOURCE 160 /* magic */ + +struct r600_shader_sampler_states { + unsigned nsampler; + unsigned nview; + unsigned nborder; + struct radeon_state *sampler[PIPE_MAX_ATTRIBS]; + struct radeon_state *view[PIPE_MAX_ATTRIBS]; + struct radeon_state *border[PIPE_MAX_ATTRIBS]; +}; + +struct r600_context; +struct r600_resource; + +struct r600_context_hw_state_vtbl { + void (*blend)(struct r600_context *rctx, + struct radeon_state *rstate, + const struct pipe_blend_state *state); + void (*ucp)(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_clip_state *state); + void (*cb)(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state, int cb); + void (*db)(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state); + void (*rasterizer)(struct r600_context *rctx, struct radeon_state *rstate); + void (*scissor)(struct r600_context *rctx, struct radeon_state *rstate); + void (*viewport)(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state); + void (*dsa)(struct r600_context *rctx, struct radeon_state *rstate); + void (*sampler_border)(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id); + void (*sampler)(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id); + void (*resource)(struct pipe_context *ctx, struct radeon_state *rstate, + const struct pipe_sampler_view *view, unsigned id); + void (*cb_cntl)(struct r600_context *rctx, struct radeon_state *rstate); + int (*vs_resource)(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset, + uint32_t stride, uint32_t format); + int (*vgt_init)(struct r600_context *rctx, struct radeon_state *draw, + struct r600_resource *rbuffer, + uint32_t count, int vgt_draw_initiator); + int (*vgt_prim)(struct r600_context *rctx, struct radeon_state *vgt, + uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type); + + int (*ps_shader)(struct r600_context *rctx, struct r600_context_state *rshader, + struct radeon_state *state); + int (*vs_shader)(struct r600_context *rctx, struct r600_context_state *rpshader, + struct radeon_state *state); + void (*init_config)(struct r600_context *rctx); }; +extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl; +extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl; struct r600_context { struct pipe_context context; @@ -128,20 +184,19 @@ struct r600_context { struct radeon_ctx ctx; struct blitter_context *blitter; struct radeon_draw draw; + struct r600_context_hw_state_vtbl *vtbl; struct radeon_state config; + boolean use_mem_constant; /* FIXME get rid of those vs_resource,vs/ps_constant */ - struct radeon_state vs_resource[160]; + struct radeon_state *vs_resource; unsigned vs_nresource; - struct radeon_state vs_constant[256]; - struct radeon_state ps_constant[256]; + struct radeon_state *vs_constant; + struct radeon_state *ps_constant; /* hw states */ struct r600_context_hw_states hw_states; /* pipe states */ unsigned flat_shade; - unsigned ps_nsampler; - unsigned vs_nsampler; - unsigned ps_nsampler_view; - unsigned vs_nsampler_view; + unsigned nvertex_buffer; struct r600_context_state *rasterizer; struct r600_context_state *poly_stipple; @@ -157,10 +212,9 @@ struct r600_context { struct r600_context_state *stencil_ref; struct r600_context_state *viewport; struct r600_context_state *framebuffer; - struct radeon_state *ps_sampler[PIPE_MAX_ATTRIBS]; - struct radeon_state *vs_sampler[PIPE_MAX_ATTRIBS]; - struct radeon_state *ps_sampler_view[PIPE_MAX_ATTRIBS]; - struct radeon_state *vs_sampler_view[PIPE_MAX_ATTRIBS]; + struct r600_shader_sampler_states vs_sampler; + struct r600_shader_sampler_states ps_sampler; + /* can add gs later */ struct r600_vertex_element *vertex_elements; struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; struct pipe_index_buffer index_buffer; @@ -179,7 +233,6 @@ static INLINE struct r600_query* r600_query(struct pipe_query* q) return (struct r600_query*)q; } -struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state); struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate); struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate); void r600_flush(struct pipe_context *ctx, unsigned flags, @@ -212,5 +265,16 @@ uint32_t r600_translate_texformat(enum pipe_format format, extern void r600_queries_resume(struct pipe_context *ctx); extern void r600_queries_suspend(struct pipe_context *ctx); +int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf); + +void r600_set_constant_buffer_file(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer); +void r600_set_constant_buffer_mem(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer); +void eg_set_constant_buffer(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer); #endif diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c index fabd337d239..f24f30f6ffd 100644 --- a/src/gallium/drivers/r600/r600_draw.c +++ b/src/gallium/drivers/r600/r600_draw.c @@ -104,59 +104,17 @@ static int r600_draw_common(struct r600_draw *draw) rbuffer = (struct r600_resource*)vertex_buffer->buffer; offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset; format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format); - radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS); - vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - vs_resource->nbo = 1; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) | - S_038008_DATA_FORMAT(format); - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000; - vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000; - vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT; - vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT; - r = radeon_state_pm4(vs_resource); - if (r) { - return r; - } + + rctx->vtbl->vs_resource(rctx, i, rbuffer, offset, vertex_buffer->stride, format); radeon_draw_bind(&rctx->draw, vs_resource); } rctx->vs_nresource = rctx->vertex_elements->count; /* FIXME start need to change winsys */ - radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0); - draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count; - draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; - if (draw->index_buffer) { - rbuffer = (struct r600_resource*)draw->index_buffer; - draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT; - draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT; - draw->draw.nbo = 1; - } - r = radeon_state_pm4(&draw->draw); - if (r) { - return r; - } + rctx->vtbl->vgt_init(rctx, &draw->draw, (struct r600_resource *)draw->index_buffer, + draw->count, vgt_draw_initiator); radeon_draw_bind(&rctx->draw, &draw->draw); - radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0); - draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim; - draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; - draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000; - draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start; - draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000; - draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type; - draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000; - draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; - draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000; - draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000; - draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000; - r = radeon_state_pm4(&draw->vgt); - if (r) { - return r; - } + rctx->vtbl->vgt_prim(rctx, &draw->vgt, prim, draw->start, vgt_dma_index_type); radeon_draw_bind(&rctx->draw, &draw->vgt); r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw); @@ -164,6 +122,9 @@ static int r600_draw_common(struct r600_draw *draw) r600_flush(draw->ctx, 0, NULL); r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw); } + + radeon_state_fini(&draw->draw); + return r; } @@ -175,6 +136,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) assert(info->index_bias == 0); + memset(&draw, 0, sizeof(draw)); + draw.ctx = ctx; draw.mode = info->mode; draw.start = info->start; diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c new file mode 100644 index 00000000000..de9491d4060 --- /dev/null +++ b/src/gallium/drivers/r600/r600_hw_states.c @@ -0,0 +1,1125 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Dave Airlie + */ + +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include <util/u_blitter.h> +#include "util/u_pack_color.h" +#include "r600_screen.h" +#include "r600_context.h" +#include "r600_resource.h" +#include "r600_state_inlines.h" +#include "r600d.h" + +static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + int i; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0); + rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]); + rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]); + rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]); + rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]); + rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; + + for (i = 0; i < 8; i++) { + unsigned eqRGB = state->rt[i].rgb_func; + unsigned srcRGB = state->rt[i].rgb_src_factor; + unsigned dstRGB = state->rt[i].rgb_dst_factor; + + unsigned eqA = state->rt[i].alpha_func; + unsigned srcA = state->rt[i].alpha_src_factor; + unsigned dstA = state->rt[i].alpha_dst_factor; + uint32_t bc = 0; + + if (!state->rt[i].blend_enable) + continue; + + bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); + bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); + bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); + + if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { + bc |= S_028804_SEPARATE_ALPHA_BLEND(1); + bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); + bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); + bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); + } + + rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc; + if (i == 0) + rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc; + } + + radeon_state_pm4(rstate); +} + +static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_clip_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0); + + for (int i = 0; i < state->nr; i++) { + rstate->states[i * 4 + 0] = fui(state->ucp[i][0]); + rstate->states[i * 4 + 1] = fui(state->ucp[i][1]); + rstate->states[i * 4 + 2] = fui(state->ucp[i][2]); + rstate->states[i * 4 + 3] = fui(state->ucp[i][3]); + } + radeon_state_pm4(rstate); +} + +static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state, int cb) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_resource_texture *rtex; + struct r600_resource *rbuffer; + unsigned level = state->cbufs[cb]->level; + unsigned pitch, slice; + unsigned color_info; + unsigned format, swap, ntype; + const struct util_format_description *desc; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0); + rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; + rbuffer = &rtex->resource; + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; + rstate->nbo = 1; + pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; + slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1; + + ntype = 0; + desc = util_format_description(rtex->resource.base.b.format); + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) + ntype = V_0280A0_NUMBER_SRGB; + + format = r600_translate_colorformat(rtex->resource.base.b.format); + swap = r600_translate_colorswap(rtex->resource.base.b.format); + + color_info = S_0280A0_FORMAT(format) | + S_0280A0_COMP_SWAP(swap) | + S_0280A0_BLEND_CLAMP(1) | + S_0280A0_SOURCE_FORMAT(1) | + S_0280A0_NUMBER_TYPE(ntype); + + rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8; + rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info; + rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | + S_028060_SLICE_TILE_MAX(slice); + rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; + radeon_state_pm4(rstate); +} + +static void r600_db(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_framebuffer_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_resource_texture *rtex; + struct r600_resource *rbuffer; + unsigned level; + unsigned pitch, slice, format; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0); + if (state->zsbuf == NULL) + return; + + rtex = (struct r600_resource_texture*)state->zsbuf->texture; + rtex->tilled = 1; + rtex->array_mode = 2; + rtex->tile_type = 1; + rtex->depth = 1; + rbuffer = &rtex->resource; + + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->nbo = 1; + rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; + level = state->zsbuf->level; + pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; + slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1; + format = r600_translate_dbformat(state->zsbuf->texture->format); + rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8; + rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) | + S_028010_FORMAT(format); + rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000; + rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1; + rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | + S_028000_SLICE_TILE_MAX(slice); + radeon_state_pm4(rstate); +} + +static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer; + const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; + const struct pipe_clip_state *clip = NULL; + struct r600_screen *rscreen = rctx->screen; + float offset_units = 0, offset_scale = 0; + char depth = 0; + unsigned offset_db_fmt_cntl = 0; + unsigned tmp; + unsigned prov_vtx = 1; + + if (rctx->clip) + clip = &rctx->clip->state.clip; + if (fb->zsbuf) { + offset_units = state->offset_units; + offset_scale = state->offset_scale * 12.0f; + switch (fb->zsbuf->texture->format) { + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + depth = -24; + offset_units *= 2.0f; + break; + case PIPE_FORMAT_Z32_FLOAT: + depth = -23; + offset_units *= 1.0f; + offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); + break; + case PIPE_FORMAT_Z16_UNORM: + depth = -16; + offset_units *= 4.0f; + break; + default: + R600_ERR("unsupported %d\n", fb->zsbuf->texture->format); + return; + } + } + offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); + + if (state->flatshade_first) + prov_vtx = 0; + + rctx->flat_shade = state->flatshade; + radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0); + rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; + if (state->sprite_coord_enable) { + rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |= + S_0286D4_PNT_SPRITE_ENA(1) | + S_0286D4_PNT_SPRITE_OVRD_X(2) | + S_0286D4_PNT_SPRITE_OVRD_Y(3) | + S_0286D4_PNT_SPRITE_OVRD_Z(0) | + S_0286D4_PNT_SPRITE_OVRD_W(1); + if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { + rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |= + S_0286D4_PNT_SPRITE_TOP_1(1); + } + } + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0; + if (clip) { + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1); + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp); + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp); + } + rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = + S_028814_PROVOKING_VTX_LAST(prov_vtx) | + S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | + S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | + S_028814_FACE(!state->front_ccw) | + S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri); + rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = + S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | + S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); + rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; + /* point size 12.4 fixed point */ + tmp = (unsigned)(state->point_size * 8.0); + rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp); + rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; + rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; + rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; + rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale); + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units); + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale); + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units); + radeon_state_pm4(rstate); +} + +static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_scissor_state *state = &rctx->scissor->state.scissor; + const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; + struct r600_screen *rscreen = rctx->screen; + unsigned minx, maxx, miny, maxy; + u32 tl, br; + + if (state == NULL) { + minx = 0; + miny = 0; + maxx = fb->cbufs[0]->width; + maxy = fb->cbufs[0]->height; + } else { + minx = state->minx; + miny = state->miny; + maxx = state->maxx; + maxy = state->maxy; + } + tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1); + br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy); + radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0); + rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; + rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; + radeon_state_pm4(rstate); +} + +static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0); + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); + rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; + radeon_state_pm4(rstate); +} + +static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) +{ + const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; + const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref; + struct r600_screen *rscreen = rctx->screen; + unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; + unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control; + struct r600_shader *rshader; + struct r600_query *rquery = NULL; + boolean query_running; + int i; + + if (rctx->ps_shader == NULL) { + return; + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0); + + db_shader_control = 0x210; + rshader = &rctx->ps_shader->shader; + if (rshader->uses_kill) + db_shader_control |= (1 << 6); + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) + db_shader_control |= 1; + } + stencil_ref_mask = 0; + stencil_ref_mask_bf = 0; + db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | + S_028800_Z_WRITE_ENABLE(state->depth.writemask) | + S_028800_ZFUNC(state->depth.func); + /* set stencil enable */ + + if (state->stencil[0].enabled) { + db_depth_control |= S_028800_STENCIL_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); + db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); + db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); + db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); + + stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | + S_028430_STENCILWRITEMASK(state->stencil[0].writemask); + stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); + if (state->stencil[1].enabled) { + db_depth_control |= S_028800_BACKFACE_ENABLE(1); + db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); + db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); + db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); + db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); + stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | + S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); + stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); + } + } + + alpha_test_control = 0; + alpha_ref = 0; + if (state->alpha.enabled) { + alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); + alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); + alpha_ref = fui(state->alpha.ref_value); + } + + db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) | + S_028D0C_DEPTH_COMPRESS_DISABLE(1); + db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | + S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | + S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); + + query_running = false; + + LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) { + if (rquery->state & R600_QUERY_STATE_STARTED) { + query_running = true; + } + } + + if (query_running) { + db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); + if (rscreen->chip_class == R700) + db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); + } + + rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; + rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; + rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control; + rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask; + rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf; + rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref; + rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; + rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; + rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; + rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control; + rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control; + rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control; + rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override; + + rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; + rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; + rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; + radeon_state_pm4(rstate); +} + + +static INLINE u32 S_FIXED(float value, u32 frac_bits) +{ + return value * (1 << frac_bits); +} + +static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id) +{ + struct r600_screen *rscreen = rctx->screen; + union util_color uc; + + util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + + radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS); + if (uc.ui) { + rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]); + rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]); + rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]); + rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]); + } + radeon_state_pm4(rstate); +} + +static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, + const struct pipe_sampler_state *state, unsigned id) +{ + struct r600_screen *rscreen = rctx->screen; + union util_color uc; + + util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + + radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS); + rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = + S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | + S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | + S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | + S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | + S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | + S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | + S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | + S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); + /* FIXME LOD it depends on texture base level ... */ + rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] = + S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | + S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | + S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); + rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1); + radeon_state_pm4(rstate); + +} + + +static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, + const struct pipe_sampler_view *view, unsigned id) +{ + struct r600_context *rctx = r600_context(ctx); + struct r600_screen *rscreen = rctx->screen; + const struct util_format_description *desc; + struct r600_resource_texture *tmp; + struct r600_resource *rbuffer; + unsigned format; + uint32_t word4 = 0, yuv_format = 0, pitch = 0; + unsigned char swizzle[4], array_mode = 0, tile_type = 0; + int r; + + rstate->cpm4 = 0; + swizzle[0] = view->swizzle_r; + swizzle[1] = view->swizzle_g; + swizzle[2] = view->swizzle_b; + swizzle[3] = view->swizzle_a; + format = r600_translate_texformat(view->texture->format, + swizzle, + &word4, &yuv_format); + if (format == ~0) { + return; + } + desc = util_format_description(view->texture->format); + if (desc == NULL) { + R600_ERR("unknow format %d\n", view->texture->format); + return; + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS); + tmp = (struct r600_resource_texture*)view->texture; + rbuffer = &tmp->resource; + if (tmp->depth) { + r = r600_texture_from_depth(ctx, tmp, view->first_level); + if (r) { + return; + } + rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); + rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); + } else { + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + } + rstate->nbo = 2; + rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; + + pitch = (tmp->pitch[0] / tmp->bpt); + pitch = (pitch + 0x7) & ~0x7; + + /* FIXME properly handle first level != 0 */ + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = + S_038000_DIM(r600_tex_dim(view->texture->target)) | + S_038000_TILE_MODE(array_mode) | + S_038000_TILE_TYPE(tile_type) | + S_038000_PITCH((pitch / 8) - 1) | + S_038000_TEX_WIDTH(view->texture->width0 - 1); + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = + S_038004_TEX_HEIGHT(view->texture->height0 - 1) | + S_038004_TEX_DEPTH(view->texture->depth0 - 1) | + S_038004_DATA_FORMAT(format); + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = + word4 | + S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | + S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | + S_038010_REQUEST_SIZE(1) | + S_038010_BASE_LEVEL(view->first_level); + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = + S_038014_LAST_LEVEL(view->last_level) | + S_038014_BASE_ARRAY(0) | + S_038014_LAST_ARRAY(0); + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = + S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE); + radeon_state_pm4(rstate); +} + +static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) +{ + struct r600_screen *rscreen = rctx->screen; + const struct pipe_blend_state *pbs = &rctx->blend->state.blend; + int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs; + uint32_t color_control, target_mask, shader_mask; + int i; + + target_mask = 0; + shader_mask = 0; + color_control = S_028808_PER_MRT_BLEND(1); + + for (i = 0; i < nr_cbufs; i++) { + shader_mask |= 0xf << (i * 4); + } + + if (pbs->logicop_enable) { + color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20); + } else { + color_control |= (0xcc << 16); + } + + if (pbs->independent_blend_enable) { + for (i = 0; i < nr_cbufs; i++) { + if (pbs->rt[i].blend_enable) { + color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); + } + target_mask |= (pbs->rt[i].colormask << (4 * i)); + } + } else { + for (i = 0; i < nr_cbufs; i++) { + if (pbs->rt[0].blend_enable) { + color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); + } + target_mask |= (pbs->rt[0].colormask << (4 * i)); + } + } + radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0); + rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask; + rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask; + rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control; + rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; + rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; + rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000; + rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; + rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000; + rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; + rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; + rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; + radeon_state_pm4(rstate); +} + +static void r600_init_config(struct r600_context *rctx) +{ + int ps_prio; + int vs_prio; + int gs_prio; + int es_prio; + int num_ps_gprs; + int num_vs_gprs; + int num_gs_gprs; + int num_es_gprs; + int num_temp_gprs; + int num_ps_threads; + int num_vs_threads; + int num_gs_threads; + int num_es_threads; + int num_ps_stack_entries; + int num_vs_stack_entries; + int num_gs_stack_entries; + int num_es_stack_entries; + enum radeon_family family; + + family = radeon_get_family(rctx->rw); + ps_prio = 0; + vs_prio = 1; + gs_prio = 2; + es_prio = 3; + switch (family) { + case CHIP_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV630: + case CHIP_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV730: + case CHIP_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0); + + rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000; + switch (family) { + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV710: + break; + default: + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1); + break; + } + + if (!rctx->screen->use_mem_constant) + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1); + + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1); + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio); + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio); + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio); + rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio); + + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0; + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs); + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs); + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); + + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0; + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs); + rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs); + + rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0; + rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads); + rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads); + rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads); + rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads); + + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0; + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); + + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0; + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); + rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); + + rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000; + rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000; + + if (family >= CHIP_RV770) { + rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000; + rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002; + rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000; + rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204; + rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000; + rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000; + } else { + rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000; + rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003; + rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000; + rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204; + rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001; + rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010; + } + rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003; + rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001; + rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000; + rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000; + radeon_state_pm4(&rctx->config); +} + +static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset, + uint32_t stride, uint32_t format) +{ + struct radeon_state *vs_resource = &rctx->vs_resource[id]; + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS); + vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + vs_resource->nbo = 1; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) | + S_038008_DATA_FORMAT(format); + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000; + vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT; + vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(vs_resource); +} + +static int r600_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw, + struct r600_resource *rbuffer, + uint32_t count, int vgt_draw_initiator) +{ + struct r600_screen *rscreen = rctx->screen; + + radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0); + draw->states[R600_DRAW__VGT_NUM_INDICES] = count; + draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; + if (rbuffer) { + draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + draw->placement[0] = RADEON_GEM_DOMAIN_GTT; + draw->placement[1] = RADEON_GEM_DOMAIN_GTT; + draw->nbo = 1; + } + return radeon_state_pm4(draw); +} + +static int r600_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt, + uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type) +{ + struct r600_screen *rscreen = rctx->screen; + radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0); + vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim; + vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; + vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000; + vgt->states[R600_VGT__VGT_INDX_OFFSET] = start; + vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000; + vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type; + vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000; + vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; + vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000; + vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000; + vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000; + return radeon_state_pm4(vgt); +} + +static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader, + struct radeon_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + const struct pipe_rasterizer_state *rasterizer; + struct r600_shader *rshader = &rpshader->shader; + unsigned i, tmp, exports_ps, num_cout; + boolean have_pos = FALSE; + + rasterizer = &rctx->rasterizer->state.rasterizer; + + radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS); + for (i = 0; i < rshader->ninput; i++) { + tmp = S_028644_SEMANTIC(i); + tmp |= S_028644_SEL_CENTROID(1); + if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) + have_pos = TRUE; + if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || + rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || + rshader->input[i].name == TGSI_SEMANTIC_POSITION) { + tmp |= S_028644_FLAT_SHADE(rshader->flat_shade); + } + if (rasterizer->sprite_coord_enable & (1 << i)) { + tmp |= S_028644_PT_SPRITE_TEX(1); + } + state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp; + } + + exports_ps = 0; + num_cout = 0; + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) + exports_ps |= 1; + else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { + exports_ps |= (1 << (num_cout+1)); + num_cout++; + } + } + if (!exports_ps) { + /* always at least export 1 component per pixel */ + exports_ps = 2; + } + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) | + S_0286CC_PERSP_GRADIENT_ENA(1); + if (have_pos) { + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) | + S_0286CC_BARYC_SAMPLE_CNTL(1); + state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1; + } + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000; + state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | + S_028868_STACK_SIZE(rshader->bc.nstack); + state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps; + state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->nbo = 1; + state->placement[0] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader, + struct radeon_state *state) +{ + struct r600_screen *rscreen = rctx->screen; + struct r600_shader *rshader = &rpshader->shader; + unsigned i, tmp; + + radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS); + for (i = 0; i < 10; i++) { + state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0; + } + /* so far never got proper semantic id from tgsi */ + for (i = 0; i < 32; i++) { + tmp = i << ((i & 3) * 8); + state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp; + } + state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2); + state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | + S_028868_STACK_SIZE(rshader->bc.nstack); + state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo); + state->nbo = 2; + state->placement[0] = RADEON_GEM_DOMAIN_GTT; + state->placement[2] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +struct r600_context_hw_state_vtbl r600_hw_state_vtbl = { + .blend = r600_blend, + .ucp = r600_ucp, + .cb = r600_cb, + .db = r600_db, + .rasterizer = r600_rasterizer, + .scissor = r600_scissor, + .viewport = r600_viewport, + .dsa = r600_dsa, + .sampler_border = r600_sampler_border, + .sampler = r600_sampler, + .resource = r600_resource, + .cb_cntl = r600_cb_cntl, + .vs_resource = r600_vs_resource, + .vgt_init = r600_draw_vgt_init, + .vgt_prim = r600_draw_vgt_prim, + .vs_shader = r600_vs_shader, + .ps_shader = r600_ps_shader, + .init_config = r600_init_config, +}; + +void r600_set_constant_buffer_file(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer) +{ + struct r600_screen *rscreen = r600_screen(ctx->screen); + struct r600_context *rctx = r600_context(ctx); + unsigned nconstant = 0, i, type, shader_class; + struct radeon_state *rstate, *rstates; + struct pipe_transfer *transfer; + u32 *ptr; + + type = R600_STATE_CONSTANT; + + switch (shader) { + case PIPE_SHADER_VERTEX: + shader_class = R600_SHADER_VS; + rstates = rctx->vs_constant; + break; + case PIPE_SHADER_FRAGMENT: + shader_class = R600_SHADER_PS; + rstates = rctx->ps_constant; + break; + default: + R600_ERR("unsupported %d\n", shader); + return; + } + if (buffer && buffer->width0 > 0) { + nconstant = buffer->width0 / 16; + ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer); + if (ptr == NULL) + return; + for (i = 0; i < nconstant; i++) { + rstate = &rstates[i]; + radeon_state_init(rstate, rscreen->rw, type, i, shader_class); + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; + if (radeon_state_pm4(rstate)) + return; + radeon_draw_bind(&rctx->draw, rstate); + } + pipe_buffer_unmap(ctx, buffer, transfer); + } +} + +void r600_set_constant_buffer_mem(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_resource *buffer) +{ + struct r600_screen *rscreen = r600_screen(ctx->screen); + struct r600_context *rctx = r600_context(ctx); + unsigned nconstant = 0, type, shader_class, size; + struct radeon_state *rstate, *rstates; + struct r600_resource *rbuffer = (struct r600_resource*)buffer; + + type = R600_STATE_CBUF; + + switch (shader) { + case PIPE_SHADER_VERTEX: + shader_class = R600_SHADER_VS; + rstates = rctx->vs_constant; + break; + case PIPE_SHADER_FRAGMENT: + shader_class = R600_SHADER_PS; + rstates = rctx->ps_constant; + break; + default: + R600_ERR("unsupported %d\n", shader); + return; + } + + rstate = &rstates[0]; + +#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) + + nconstant = buffer->width0 / 16; + size = ALIGN_DIVUP(nconstant, 16); + + radeon_state_init(rstate, rscreen->rw, type, 0, shader_class); + rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size; + rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0; + + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->nbo = 1; + rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; + if (radeon_state_pm4(rstate)) + return; + radeon_draw_bind(&rctx->draw, rstate); +} + diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h new file mode 100644 index 00000000000..0cf9c1c401c --- /dev/null +++ b/src/gallium/drivers/r600/r600_opcodes.h @@ -0,0 +1,396 @@ + +#ifndef R600_OPCODES_H +#define R600_OPCODES_H + +#define V_SQ_CF_WORD1_SQ_CF_INST_NOP 0x00000000 +#define V_SQ_CF_WORD1_SQ_CF_INST_TEX 0x00000001 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX 0x00000002 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC 0x00000003 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START 0x00000004 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END 0x00000005 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define V_SQ_CF_WORD1_SQ_CF_INST_JUMP 0x0000000A +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH 0x0000000B +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH_ELSE 0x0000000C +#define V_SQ_CF_WORD1_SQ_CF_INST_ELSE 0x0000000D +#define V_SQ_CF_WORD1_SQ_CF_INST_POP 0x0000000E +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_JUMP 0x0000000F +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH 0x00000010 +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL 0x00000012 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS 0x00000013 +#define V_SQ_CF_WORD1_SQ_CF_INST_RETURN 0x00000014 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define V_SQ_CF_WORD1_SQ_CF_INST_KILL 0x00000018 + +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F + +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD 0x00000000 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL 0x00000001 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE 0x00000002 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX 0x00000003 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN 0x00000004 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10 0x00000005 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10 0x00000006 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE 0x00000008 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT 0x00000009 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE 0x0000000A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE 0x0000000B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10 0x0000000C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10 0x0000000D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10 0x0000000E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10 0x0000000F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT 0x00000010 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC 0x00000011 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL 0x00000012 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE 0x00000013 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR 0x00000014 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA 0x00000015 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR 0x00000016 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT 0x00000018 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV 0x00000019 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP 0x0000001A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT 0x0000001E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT 0x0000001F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE 0x00000020 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT 0x00000021 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE 0x00000022 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE 0x00000023 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV 0x00000024 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP 0x00000025 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR 0x00000026 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE 0x00000027 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH 0x00000028 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH 0x00000029 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH 0x0000002A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH 0x0000002B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE 0x0000002C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT 0x0000002D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE 0x0000002E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE 0x0000002F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT 0x00000030 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT 0x00000031 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT 0x00000032 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT 0x00000033 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT 0x00000034 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT 0x00000035 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT 0x00000036 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT 0x00000037 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT 0x00000038 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT 0x00000039 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT 0x0000003A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT 0x0000003B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT 0x0000003C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT 0x0000003D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT 0x0000003E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT 0x0000003F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT 0x00000040 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT 0x00000041 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT 0x00000042 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT 0x00000043 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT 0x00000044 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT 0x00000045 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT 0x00000046 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT 0x00000047 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT 0x00000048 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT 0x00000049 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT 0x0000004A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT 0x0000004B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT 0x0000004C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT 0x0000004D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT 0x0000004E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT 0x0000004F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 0x00000050 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE 0x00000051 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE 0x00000052 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4 0x00000053 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT 0x00000060 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE 0x00000061 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED 0x00000062 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE 0x00000063 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED 0x00000064 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF 0x00000065 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE 0x00000066 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED 0x00000067 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF 0x00000068 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE 0x00000069 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE 0x0000006A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT 0x0000006B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT 0x0000006C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT 0x0000006D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN 0x0000006E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS 0x0000006F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT 0x00000070 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT 0x00000071 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT 0x00000072 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT 0x00000073 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT 0x00000074 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT 0x00000075 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT 0x00000076 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT 0x00000077 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT 0x00000078 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT 0x00000079 + +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT 0x0000000C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 0x0000000D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4 0x0000000E +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 0x0000000F +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD 0x00000010 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2 0x00000011 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4 0x00000012 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2 0x00000013 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE 0x00000014 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M2 0x00000015 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M4 0x00000016 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_D2 0x00000017 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE 0x00000018 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT 0x00000019 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE 0x0000001A +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT 0x0000001C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT 0x0000001D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT 0x0000001E + +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0 0x00000020 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1 0x00000021 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2 0x00000022 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3 0x00000023 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH 0x00000024 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION 0x00000025 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING 0x00000026 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT 0x00000027 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE 0x00000028 + +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_NOP 0x00000000 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX 0x00000001 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX 0x00000002 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_GDS 0x00000003 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START 0x00000004 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END 0x00000005 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP 0x0000000A +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_PUSH 0x0000000B +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_12 0x0000000C /* resvd */ +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE 0x0000000D +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_POP 0x0000000E +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_15 0x0000000F +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_16 0x00000010 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_17 0x00000011 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL 0x00000012 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS 0x00000013 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN 0x00000014 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_KILL 0x00000018 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_25 0x00000019 +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_WAIT_ACK 0x0000001a +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_TC_ACK 0x0000001b +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_VC_ACK 0x0000001c +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMPTABLE 0x0000001d +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_GLOBAL_WAVE_SYNC 0x0000001e +#define EG_V_SQ_CF_WORD1_SQ_CF_INST_HALT 0x0000001f + +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED 0x0000000C +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E +#define EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F + +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD 0x00000000 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL 0x00000001 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE 0x00000002 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX 0x00000003 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN 0x00000004 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10 0x00000005 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10 0x00000006 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE 0x00000008 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT 0x00000009 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE 0x0000000A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE 0x0000000B +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10 0x0000000C +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10 0x0000000D +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10 0x0000000E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10 0x0000000F +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT 0x00000010 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC 0x00000011 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL 0x00000012 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE 0x00000013 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR 0x00000014 +/* same up to here */ +/* +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA 0x00000015 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR 0x00000016 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT 0x00000018 +*/ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT 0x00000015 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT 0x00000016 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT 0x00000017 +/* same again from here */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV 0x00000019 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP 0x0000001A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64 0x0000001B /* new EG */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT64_TO_FLT32 0x0000001C /* new EG */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64 0x0000001D /* new EG */ +/* same */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT 0x0000001E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT 0x0000001F +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE 0x00000020 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT 0x00000021 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE 0x00000022 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE 0x00000023 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV 0x00000024 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP 0x00000025 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR 0x00000026 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE 0x00000027 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH 0x00000028 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH 0x00000029 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH 0x0000002A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH 0x0000002B +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE 0x0000002C +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT 0x0000002D +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE 0x0000002E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE 0x0000002F +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT 0x00000030 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT 0x00000031 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT 0x00000032 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT 0x00000033 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT 0x00000034 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT 0x00000035 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT 0x00000036 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT 0x00000037 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT 0x00000038 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT 0x00000039 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT 0x0000003A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT 0x0000003B +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT 0x0000003C +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT 0x0000003D +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT 0x0000003E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT 0x0000003F +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT 0x00000040 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT 0x00000041 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT 0x00000042 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT 0x00000043 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT 0x00000044 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT 0x00000045 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT 0x00000046 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT 0x00000047 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT 0x00000048 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT 0x00000049 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT 0x0000004A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT 0x0000004B +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT 0x0000004C +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT 0x0000004D +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT 0x0000004E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT 0x0000004F +/* same up to here */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT 0x00000050 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFREV_INT 0x00000051 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADDC_UINT 0x00000052 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUBB_UINT 0x00000053 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_BARRIER 0x00000054 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_BEGIN 0x00000055 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_END 0x00000056 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_MODE 0x00000057 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX0 0x00000058 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX1 0x00000059 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_LDS_SIZE 0x0000005A + +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE 0x00000081 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED 0x00000082 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE 0x00000083 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED 0x00000084 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF 0x00000085 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE 0x00000086 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED 0x00000087 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF 0x00000088 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE 0x00000089 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE 0x0000008A +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN 0x0000008D +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS 0x0000008E +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT 0x0000008F +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT 0x00000090 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT 0x00000091 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT 0x00000092 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT 0x00000093 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT 0x00000094 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_64 0x00000095 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED_64 0x00000096 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_64 0x00000097 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED_64 0x00000098 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_64 0x00000099 +/* TODO Fill in more ALU */ +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 0x000000BE +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE 0x000000BF +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE 0x000000C0 + +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY 0x000000D6 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW 0x000000D7 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_X 0x000000D8 +#define EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_Z 0x000000D9 + + +/* TODO ADD OTHER OP3 */ +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD 0x00000014 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2 0x00000015 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4 0x00000016 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2 0x00000017 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE 0x00000018 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE 0x00000019 +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT 0x0000001A +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE 0x0000001B +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT 0x0000001C +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT 0x0000001D +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT 0x0000001E +#define EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT 0x0000001F + +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0 0x00000040 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1 0x00000041 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2 0x00000042 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3 0x00000043 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0 0x00000044 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1 0x00000045 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2 0x00000046 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3 0x00000047 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0 0x00000048 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1 0x00000049 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2 0x0000004A +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3 0x0000004B +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0 0x0000004C +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1 0x0000004D +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2 0x0000004E +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3 0x0000004F +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH 0x00000050 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING 0x00000052 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT 0x00000053 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE 0x00000054 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT 0x00000055 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT 0x00000056 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_CACHELESS 0x00000057 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING1 0x00000058 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING2 0x00000059 +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING3 0x0000005A +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED 0x0000005B +#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS 0x0000005C + +#define BC_INST(bc, x) ((bc)->chiprev == 2 ? EG_##x : x) + +#define CTX_INST(x) (ctx->bc->chiprev == 2 ? EG_##x : x) + +#endif diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 530940ed843..0073072b4af 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -77,7 +77,6 @@ static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned q return NULL; q->type = query_type; - LIST_ADDTAIL(&q->list, &rctx->query_list); q->buffer_size = 4096; q->buffer = radeon_bo(rscreen->rw, 0, q->buffer_size, 1, NULL); @@ -85,6 +84,9 @@ static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned q FREE(q); return NULL; } + + LIST_ADDTAIL(&q->list, &rctx->query_list); + return (struct pipe_query *)q; } diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c index a047a49a6c5..19d1005e771 100644 --- a/src/gallium/drivers/r600/r600_screen.c +++ b/src/gallium/drivers/r600/r600_screen.c @@ -46,8 +46,10 @@ static const char* r600_get_name(struct pipe_screen* pscreen) if (family >= CHIP_R600 && family < CHIP_RV770) return "R600 (HD2XXX,HD3XXX)"; - else + else if (family < CHIP_CEDAR) return "R700 (HD4XXX)"; + else + return "EVERGREEN"; } static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) @@ -74,10 +76,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Unsupported features (boolean caps). */ case PIPE_CAP_TIMER_QUERY: - case PIPE_CAP_TGSI_CONT_SUPPORTED: case PIPE_CAP_STREAM_OUTPUT: case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */ - case PIPE_CAP_GEOMETRY_SHADER4: return 0; /* Texturing. */ @@ -104,55 +104,59 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; - - /* Shader limits. */ - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - return 16384; //max native instructions, not greater than max instructions - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - return 16384; - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - return 16384; //max program native instructions - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - return 16384; //max program native ALU instructions - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - return 16384; //max program native texture instructions - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - return 2048; //max program native texture indirections - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - return 8; /* FIXME */ - case PIPE_CAP_MAX_VS_INPUTS: - return 16; //max native attributes - case PIPE_CAP_MAX_FS_INPUTS: - return 10; //max native attributes - case PIPE_CAP_MAX_VS_TEMPS: - return 256; //max native temporaries - case PIPE_CAP_MAX_FS_TEMPS: - return 256; //max native temporaries - case PIPE_CAP_MAX_VS_ADDRS: - case PIPE_CAP_MAX_FS_ADDRS: - return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */ - case PIPE_CAP_MAX_VS_CONSTS: - return 256; //max native parameters - case PIPE_CAP_MAX_FS_CONSTS: - return 256; //max program native parameters - case PIPE_CAP_MAX_CONST_BUFFERS: - return 1; - case PIPE_CAP_MAX_CONST_BUFFER_SIZE: /* in bytes */ - return 4096; - case PIPE_CAP_MAX_PREDICATE_REGISTERS: - case PIPE_CAP_MAX_VS_PREDS: - case PIPE_CAP_MAX_FS_PREDS: - return 0; /* FIXME */ - default: R600_ERR("r600: unknown param %d\n", param); return 0; } } +static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) + { + case PIPE_SHADER_FRAGMENT: + case PIPE_SHADER_VERTEX: + break; + case PIPE_SHADER_GEOMETRY: + /* TODO: support and enable geometry programs */ + return 0; + default: + /* TODO: support tessellation on Evergreen */ + return 0; + } + + /* TODO: all these should be fixed, since r600 surely supports much more! */ + switch (param) { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return 16384; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return 8; /* FIXME */ + case PIPE_SHADER_CAP_MAX_INPUTS: + if(shader == PIPE_SHADER_FRAGMENT) + return 10; + else + return 16; + case PIPE_SHADER_CAP_MAX_TEMPS: + return 256; //max native temporaries + case PIPE_SHADER_CAP_MAX_ADDRS: + return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */ + case PIPE_SHADER_CAP_MAX_CONSTS: + return 256; //max native parameters + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_PREDS: + return 0; /* FIXME */ + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + /* TODO: support this! */ + return 0; + default: + return 0; + } +} + static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) { switch (param) { @@ -240,6 +244,9 @@ struct pipe_screen *r600_screen_create(struct radeon *rw) if (rscreen == NULL) { return NULL; } + + /* don't enable mem constant for r600 yet */ + rscreen->use_mem_constant = FALSE; switch (family) { case CHIP_R600: @@ -258,6 +265,14 @@ struct pipe_screen *r600_screen_create(struct radeon *rw) case CHIP_RV740: rscreen->chip_class = R700; break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + rscreen->chip_class = EVERGREEN; + rscreen->use_mem_constant = TRUE; + break; default: FREE(rscreen); return NULL; @@ -268,6 +283,7 @@ struct pipe_screen *r600_screen_create(struct radeon *rw) rscreen->screen.get_name = r600_get_name; rscreen->screen.get_vendor = r600_get_vendor; rscreen->screen.get_param = r600_get_param; + rscreen->screen.get_shader_param = r600_get_shader_param; rscreen->screen.get_paramf = r600_get_paramf; rscreen->screen.is_format_supported = r600_is_format_supported; rscreen->screen.context_create = r600_create_context; diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h index b9938f117a8..4be77865fbd 100644 --- a/src/gallium/drivers/r600/r600_screen.h +++ b/src/gallium/drivers/r600/r600_screen.h @@ -52,6 +52,7 @@ struct r600_screen { struct pipe_screen screen; struct radeon *rw; enum chip_class chip_class; + boolean use_mem_constant; }; static INLINE struct r600_screen *r600_screen(struct pipe_screen *screen) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 0ba26a23112..f12dbd37d38 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -30,6 +30,7 @@ #include "r600_shader.h" #include "r600_asm.h" #include "r600_sq.h" +#include "r600_opcodes.h" #include "r600d.h" #include <stdio.h> #include <errno.h> @@ -60,8 +61,9 @@ struct r600_shader_tgsi_instruction { int (*process)(struct r600_shader_ctx *ctx); }; -static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]; +static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[]; static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader); +static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx); static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader) { @@ -113,6 +115,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, if (rpshader == NULL) return -ENOMEM; rpshader->shader.family = radeon_get_family(rscreen->rw); + rpshader->shader.use_mem_constant = rscreen->use_mem_constant; r = r600_shader_from_tgsi(tokens, &rpshader->shader); if (r) { R600_ERR("translation from TGSI failed !\n"); @@ -129,92 +132,24 @@ int r600_pipe_shader_create(struct pipe_context *ctx, static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader) { - struct r600_screen *rscreen = r600_screen(ctx->screen); - struct r600_shader *rshader = &rpshader->shader; + struct r600_context *rctx = r600_context(ctx); struct radeon_state *state; - unsigned i, tmp; state = &rpshader->rstate[0]; radeon_state_fini(&rpshader->rstate[0]); - radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS); - for (i = 0; i < 10; i++) { - state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0; - } - /* so far never got proper semantic id from tgsi */ - for (i = 0; i < 32; i++) { - tmp = i << ((i & 3) * 8); - state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp; - } - state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2); - state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | - S_028868_STACK_SIZE(rshader->bc.nstack); - state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); - state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo); - state->nbo = 2; - state->placement[0] = RADEON_GEM_DOMAIN_GTT; - state->placement[2] = RADEON_GEM_DOMAIN_GTT; - return radeon_state_pm4(state); + + return rctx->vtbl->vs_shader(rctx, rpshader, state); } static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader) { - const struct pipe_rasterizer_state *rasterizer; - struct r600_screen *rscreen = r600_screen(ctx->screen); - struct r600_shader *rshader = &rpshader->shader; struct r600_context *rctx = r600_context(ctx); struct radeon_state *state; - unsigned i, tmp, exports_ps, num_cout; - boolean have_pos = FALSE; state = &rpshader->rstate[0]; - rasterizer = &rctx->rasterizer->state.rasterizer; radeon_state_fini(state); - radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS); - for (i = 0; i < rshader->ninput; i++) { - tmp = S_028644_SEMANTIC(i); - tmp |= S_028644_SEL_CENTROID(1); - if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) - have_pos = TRUE; - if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || - rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || - rshader->input[i].name == TGSI_SEMANTIC_POSITION) { - tmp |= S_028644_FLAT_SHADE(rshader->flat_shade); - } - if (rasterizer->sprite_coord_enable & (1 << i)) { - tmp |= S_028644_PT_SPRITE_TEX(1); - } - state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp; - } - exports_ps = 0; - num_cout = 0; - for (i = 0; i < rshader->noutput; i++) { - if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) - exports_ps |= 1; - else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { - exports_ps |= (1 << (num_cout+1)); - num_cout++; - } - } - if (!exports_ps) { - /* always at least export 1 component per pixel */ - exports_ps = 2; - } - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) | - S_0286CC_PERSP_GRADIENT_ENA(1); - if (have_pos) { - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1) | - S_0286CC_BARYC_SAMPLE_CNTL(1); - state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1; - } - state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000; - state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) | - S_028868_STACK_SIZE(rshader->bc.nstack); - state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps; - state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); - state->nbo = 1; - state->placement[0] = RADEON_GEM_DOMAIN_GTT; - return radeon_state_pm4(state); + return rctx->vtbl->ps_shader(rctx, rpshader, state); } static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader) @@ -307,6 +242,39 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx) return 0; } +static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr) +{ + int i, r; + struct r600_bc_alu alu; + + for (i = 0; i < 8; i++) { + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + if (i < 4) + alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW; + else + alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY; + + if ((i > 1) && (i < 6)) { + alu.dst.sel = ctx->shader->input[gpr].gpr; + alu.dst.write = 1; + } + + alu.dst.chan = i % 4; + alu.src[0].chan = (1 - (i % 2)); + alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr; + + alu.bank_swizzle_force = SQ_ALU_VEC_210; + if ((i % 4) == 3) + alu.last = 1; + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + } + return 0; +} + + static int tgsi_declaration(struct r600_shader_ctx *ctx) { struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration; @@ -340,6 +308,10 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) if (r) return r; } + if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) { + /* turn input into interpolate on EG */ + evergreen_interp_alu(ctx, i); + } break; case TGSI_FILE_OUTPUT: i = ctx->shader->noutput++; @@ -379,6 +351,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s r = r600_bc_init(ctx.bc, shader->family); if (r) return r; + ctx.bc->use_mem_constant = shader->use_mem_constant; ctx.tokens = tokens; tgsi_scan_shader(tokens, &ctx.info); tgsi_parse_init(&ctx.parse, tokens); @@ -414,7 +387,11 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s ctx.info.file_count[TGSI_FILE_INPUT]; ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] + ctx.info.file_count[TGSI_FILE_OUTPUT]; - ctx.file_offset[TGSI_FILE_CONSTANT] = 256; + if (ctx.shader->use_mem_constant) + ctx.file_offset[TGSI_FILE_CONSTANT] = 128; + else + ctx.file_offset[TGSI_FILE_CONSTANT] = 256; + ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253; ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] + ctx.info.file_count[TGSI_FILE_TEMPORARY]; @@ -451,7 +428,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s /* reserve first tmp for everyone */ r600_get_temp(&ctx); opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode; - ctx.inst_info = &r600_shader_tgsi_instruction[opcode]; + if (ctx.bc->chiprev == 2) + ctx.inst_info = &eg_shader_tgsi_instruction[opcode]; + else + ctx.inst_info = &r600_shader_tgsi_instruction[opcode]; r = ctx.inst_info->process(&ctx); if (r) goto out_err; @@ -478,7 +458,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s output[i].barrier = 1; output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM; output[i].array_base = i - pos0; - output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT; + output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT); switch (ctx.type) { case TGSI_PROCESSOR_VERTEX: if (shader->output[i].name == TGSI_SEMANTIC_POSITION) { @@ -550,7 +530,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s output[0].barrier = 1; output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL; output[0].array_base = 0; - output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT; + output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT); noutput++; } /* set export done on last export of each type */ @@ -560,7 +540,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s } if (!(output_done & (1 << output[i].type))) { output_done |= (1 << output[i].type); - output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE; + output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE); } } /* add output to bytecode */ @@ -666,7 +646,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s int treg = r600_get_temp(ctx); for (k = 0; k < 4; k++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = r600_src[j].sel; alu.src[0].chan = k; alu.dst.sel = treg; @@ -702,7 +682,7 @@ static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_ int treg = r600_get_temp(ctx); for (k = 0; k < 4; k++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = r600_src[j].sel; alu.src[0].chan = k; alu.dst.sel = treg; @@ -820,7 +800,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx, lit_vals[1] = fui(0.5f); memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.dst.chan = 0; @@ -843,7 +823,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx, return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT); alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; @@ -865,7 +845,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx, } memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.dst.chan = 0; @@ -924,7 +904,7 @@ static int tgsi_trig(struct r600_shader_ctx *ctx) continue; memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = ctx->temp_reg; r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); @@ -953,7 +933,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx) /* dst.x = COS */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS); r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst); if (r) return r; @@ -967,7 +947,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx) /* dst.y = SIN */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN); r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst); if (r) return r; @@ -1037,7 +1017,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) /* dst.x, <- 1.0 */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/ alu.src[0].chan = 0; r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst); @@ -1050,7 +1030,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) /* dst.y = max(src.x, 0.0) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX); alu.src[0] = r600_src[0]; alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/ alu.src[1].chan = 0; @@ -1064,7 +1044,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) /* dst.w, <- 1.0 */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst); @@ -1087,7 +1067,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) /* dst.z = log(src.y) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED); alu.src[0] = r600_src[0]; alu.src[0].chan = tgsi_chan(&inst->Src[0], 1); r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst); @@ -1107,7 +1087,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT); alu.src[0] = r600_src[0]; alu.src[0].chan = tgsi_chan(&inst->Src[0], 3); alu.src[1].sel = sel; @@ -1129,7 +1109,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) return r; /* dst.z = exp(tmp.x) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst); @@ -1143,6 +1123,34 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) return 0; } +static int tgsi_rsq(struct r600_shader_ctx *ctx) +{ + struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; + struct r600_bc_alu alu; + int i, r; + + memset(&alu, 0, sizeof(struct r600_bc_alu)); + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE); + for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { + r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]); + if (r) + return r; + alu.src[i].chan = tgsi_chan(&inst->Src[i], 0); + alu.src[i].abs = 1; + } + alu.dst.sel = ctx->temp_reg; + alu.dst.write = 1; + alu.last = 1; + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + /* replicate result */ + return tgsi_helper_tempx_replicate(ctx); +} + static int tgsi_trans(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; @@ -1180,7 +1188,7 @@ static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx) for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.src[0].sel = ctx->temp_reg; - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.dst.chan = i; r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (r) @@ -1230,7 +1238,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx) /* LOG2(a) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); if (r) return r; @@ -1246,7 +1254,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx) return r; /* b * LOG2(a) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE); r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]); if (r) return r; @@ -1263,7 +1271,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx) return r; /* POW(a,b) = EXP2(b * LOG2(a))*/ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; @@ -1291,7 +1299,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx) /* tmp = (src > 0 ? 1 : src) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT); alu.is_op3 = 1; alu.dst.sel = ctx->temp_reg; @@ -1317,7 +1325,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx) /* dst = (-tmp > 0 ? -1 : tmp) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT); alu.is_op3 = 1; r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (r) @@ -1353,10 +1361,10 @@ static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instru for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); if (!(inst->Dst[0].Register.WriteMask & (1 << i))) { - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP); alu.dst.chan = i; } else { - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (r) return r; @@ -1475,7 +1483,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) { /* Add perspective divide */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); if (r) return r; @@ -1491,7 +1499,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 3; r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]); @@ -1506,7 +1514,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) return r; } memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.dst.sel = ctx->temp_reg; @@ -1526,7 +1534,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE); switch (i) { case 0: src_chan = 2; @@ -1565,7 +1573,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) /* tmp1.z = RCP_e(|tmp1.z|) */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 2; alu.src[0].abs = 1; @@ -1582,7 +1590,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) * muladd has no writemask, have to use another temp */ memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.src[0].sel = ctx->temp_reg; @@ -1602,7 +1610,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.src[0].sel = ctx->temp_reg; @@ -1634,7 +1642,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) if (src_not_temp) { for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = src_gpr; alu.src[0].chan = i; alu.dst.sel = ctx->temp_reg; @@ -1709,7 +1717,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx) /* 1 - src0 */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; alu.src[1] = r600_src[0]; @@ -1732,7 +1740,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx) /* (1 - src0) * src2 */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = i; alu.src[1] = r600_src[2]; @@ -1754,7 +1762,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx) /* src0 * src1 + (1 - src0) * src2 */ for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.is_op3 = 1; alu.src[0] = r600_src[0]; alu.src[0].chan = tgsi_chan(&inst->Src[0], i); @@ -1791,7 +1799,7 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx) for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE); alu.src[0] = r600_src[0]; alu.src[0].chan = tgsi_chan(&inst->Src[0], i); @@ -1839,7 +1847,7 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx) for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); alu.src[0] = r600_src[0]; switch (i) { @@ -1882,11 +1890,15 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx) r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; } for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD); alu.src[0] = r600_src[0]; switch (i) { @@ -1939,6 +1951,10 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx) r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; } if (use_temp) return tgsi_helper_copy(ctx, inst); @@ -1956,7 +1972,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) if (inst->Dst[0].Register.WriteMask & 1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); if (r) return r; @@ -1975,7 +1991,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) if (r) return r; - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; @@ -1996,7 +2012,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) if ((inst->Dst[0].Register.WriteMask >> 1) & 1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT); alu.src[0] = r600_src[0]; r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); if (r) @@ -2023,7 +2039,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) /* result.z = RoughApprox2ToX(tmp);*/ if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); if (r) return r; @@ -2047,7 +2063,209 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); + alu.src[0].sel = V_SQ_ALU_SRC_1; + alu.src[0].chan = 0; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 3; + alu.dst.write = 1; + alu.last = 1; + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + } + return tgsi_helper_copy(ctx, inst); +} + +static int tgsi_log(struct r600_shader_ctx *ctx) +{ + struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; + struct r600_bc_alu alu; + int r; + + /* result.x = floor(log2(src)); */ + if (inst->Dst[0].Register.WriteMask & 1) { + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); + r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); + if (r) + return r; + + alu.src[0].chan = tgsi_chan(&inst->Src[0], 0); + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 0; + alu.dst.write = 1; + alu.last = 1; + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); + alu.src[0].sel = ctx->temp_reg; + alu.src[0].chan = 0; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 0; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + } + + /* result.y = src.x / (2 ^ floor(log2(src.x))); */ + if ((inst->Dst[0].Register.WriteMask >> 1) & 1) { + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); + r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); + if (r) + return r; + + alu.src[0].chan = tgsi_chan(&inst->Src[0], 0); + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 1; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR); + alu.src[0].sel = ctx->temp_reg; + alu.src[0].chan = 1; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 1; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE); + alu.src[0].sel = ctx->temp_reg; + alu.src[0].chan = 1; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 1; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE); + alu.src[0].sel = ctx->temp_reg; + alu.src[0].chan = 1; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 1; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); + + r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); + if (r) + return r; + + alu.src[0].chan = tgsi_chan(&inst->Src[0], 0); + + alu.src[1].sel = ctx->temp_reg; + alu.src[1].chan = 1; + + alu.dst.sel = ctx->temp_reg; + alu.dst.chan = 1; + alu.dst.write = 1; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + } + + /* result.z = log2(src);*/ + if ((inst->Dst[0].Register.WriteMask >> 2) & 1) { + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE); + r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); + if (r) + return r; + + alu.src[0].chan = tgsi_chan(&inst->Src[0], 0); + + alu.dst.sel = ctx->temp_reg; + alu.dst.write = 1; + alu.dst.chan = 2; + alu.last = 1; + + r = r600_bc_add_alu(ctx->bc, &alu); + if (r) + return r; + + r = r600_bc_add_literal(ctx->bc, ctx->value); + if (r) + return r; + } + + /* result.w = 1.0; */ + if ((inst->Dst[0].Register.WriteMask >> 3) & 1) { + memset(&alu, 0, sizeof(struct r600_bc_alu)); + + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); alu.src[0].sel = V_SQ_ALU_SRC_1; alu.src[0].chan = 0; @@ -2055,16 +2273,20 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) alu.dst.chan = 3; alu.dst.write = 1; alu.last = 1; + r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; + r = r600_bc_add_literal(ctx->bc, ctx->value); if (r) return r; } + return tgsi_helper_copy(ctx, inst); } +/* r6/7 only for now */ static int tgsi_arl(struct r600_shader_ctx *ctx) { /* TODO from r600c, ar values don't persist between clauses */ @@ -2082,7 +2304,7 @@ static int tgsi_arl(struct r600_shader_ctx *ctx) alu.last = 1; - r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU); + r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU)); if (r) return r; return 0; @@ -2097,7 +2319,7 @@ static int tgsi_opdst(struct r600_shader_ctx *ctx) for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL; + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); if (r) return r; @@ -2151,7 +2373,7 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode) alu.last = 1; - r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE); + r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)); if (r) return r; return 0; @@ -2159,7 +2381,7 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode) static int pops(struct r600_shader_ctx *ctx, int pops) { - r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_POP); + r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP)); ctx->bc->cf_last->pop_count = pops; return 0; } @@ -2192,6 +2414,9 @@ static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned r case FC_PUSH_WQM: diff = 4; break; + default: + assert(0); + diff = 0; } if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) > ctx->bc->callstack[ctx->bc->call_sp].max) { @@ -2300,9 +2525,9 @@ static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp) static int tgsi_if(struct r600_shader_ctx *ctx) { - emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE); + emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE)); - r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP); + r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP)); fc_pushlevel(ctx, FC_IF); @@ -2312,7 +2537,7 @@ static int tgsi_if(struct r600_shader_ctx *ctx) static int tgsi_else(struct r600_shader_ctx *ctx) { - r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE); + r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE)); ctx->bc->cf_last->pop_count = 1; fc_set_mid(ctx, ctx->bc->fc_sp); @@ -2342,7 +2567,7 @@ static int tgsi_endif(struct r600_shader_ctx *ctx) static int tgsi_bgnloop(struct r600_shader_ctx *ctx) { - r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL); + r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL)); fc_pushlevel(ctx, FC_LOOP); @@ -2355,7 +2580,7 @@ static int tgsi_endloop(struct r600_shader_ctx *ctx) { int i; - r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END); + r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END)); if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) { R600_ERR("loop/endloop in shader code are not paired.\n"); @@ -2410,9 +2635,9 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate}, - {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq}, {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp}, - {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log}, {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2}, {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, @@ -2562,3 +2787,161 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, }; + +static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { + {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, + {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, + {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp}, + {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2}, + {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, + {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, + {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, + {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst}, + {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2}, + {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2}, + {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap}, + {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2}, + {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3}, + {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2}, + {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp}, + {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + /* gap */ + {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + /* gap */ + {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2}, + {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2}, + {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow}, + {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd}, + /* gap */ + {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, + {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, + {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig}, + {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex}, + {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex}, + {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */ + {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2}, + {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2}, + {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig}, + {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap}, + {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2}, + {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, + {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex}, + {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg}, + {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp}, + {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs}, + {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex}, + {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp}, + {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont}, + {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if}, + /* gap */ + {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else}, + {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif}, + /* gap */ + {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate}, + {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + /* gap */ + {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont}, + {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop}, + {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop}, + {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + /* gap */ + {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + /* gap */ + {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */ + {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */ + /* gap */ + {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, + {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, +}; diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h index 7c722c07cbe..fba4a2b3b8a 100644 --- a/src/gallium/drivers/r600/r600_shader.h +++ b/src/gallium/drivers/r600/r600_shader.h @@ -43,6 +43,7 @@ struct r600_shader { struct r600_shader_io output[32]; enum radeon_family family; boolean uses_kill; + boolean use_mem_constant; }; #endif diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h index fa7a31742af..0573e63dc82 100644 --- a/src/gallium/drivers/r600/r600_sq.h +++ b/src/gallium/drivers/r600/r600_sq.h @@ -55,31 +55,6 @@ #define S_SQ_CF_WORD1_CF_INST(x) (((x) & 0x7F) << 23) #define G_SQ_CF_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) #define C_SQ_CF_WORD1_CF_INST 0xC07FFFFF -#define V_SQ_CF_WORD1_SQ_CF_INST_NOP 0x00000000 -#define V_SQ_CF_WORD1_SQ_CF_INST_TEX 0x00000001 -#define V_SQ_CF_WORD1_SQ_CF_INST_VTX 0x00000002 -#define V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC 0x00000003 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START 0x00000004 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END 0x00000005 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10 0x00000006 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE 0x00000008 -#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK 0x00000009 -#define V_SQ_CF_WORD1_SQ_CF_INST_JUMP 0x0000000A -#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH 0x0000000B -#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH_ELSE 0x0000000C -#define V_SQ_CF_WORD1_SQ_CF_INST_ELSE 0x0000000D -#define V_SQ_CF_WORD1_SQ_CF_INST_POP 0x0000000E -#define V_SQ_CF_WORD1_SQ_CF_INST_POP_JUMP 0x0000000F -#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH 0x00000010 -#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 -#define V_SQ_CF_WORD1_SQ_CF_INST_CALL 0x00000012 -#define V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS 0x00000013 -#define V_SQ_CF_WORD1_SQ_CF_INST_RETURN 0x00000014 -#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX 0x00000015 -#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 -#define V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX 0x00000017 -#define V_SQ_CF_WORD1_SQ_CF_INST_KILL 0x00000018 #define S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) #define G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) #define C_SQ_CF_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF @@ -118,13 +93,6 @@ #define S_SQ_CF_ALU_WORD1_CF_INST(x) (((x) & 0xF) << 26) #define G_SQ_CF_ALU_WORD1_CF_INST(x) (((x) >> 26) & 0xF) #define C_SQ_CF_ALU_WORD1_CF_INST 0xC3FFFFFF -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E -#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F #define S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) #define G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) #define C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF @@ -167,15 +135,7 @@ #define S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) & 0x7F) << 23) #define G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) #define C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST 0xC07FFFFF -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0 0x00000020 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1 0x00000021 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2 0x00000022 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3 0x00000023 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH 0x00000024 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION 0x00000025 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING 0x00000026 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT 0x00000027 -#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE 0x00000028 + #define S_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) #define G_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) #define C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF @@ -219,6 +179,7 @@ * 253 SQ_ALU_SRC_LITERAL: literal constant. * 254 SQ_ALU_SRC_PV: previous vector result. * 255 SQ_ALU_SRC_PS: previous scalar result. + * 448 EG - INTERP SRC BASE */ #define V_SQ_ALU_SRC_0 0x000000F8 #define V_SQ_ALU_SRC_1 0x000000F9 @@ -226,6 +187,7 @@ #define V_SQ_ALU_SRC_M_1_INT 0x000000FB #define V_SQ_ALU_SRC_0_5 0x000000FC #define V_SQ_ALU_SRC_LITERAL 0x000000FD +#define V_SQ_ALU_SRC_PARAM_BASE 0x000001C0 #define S_SQ_ALU_WORD0_SRC0_REL(x) (((x) & 0x1) << 9) #define G_SQ_ALU_WORD0_SRC0_REL(x) (((x) >> 9) & 0x1) #define C_SQ_ALU_WORD0_SRC0_REL 0xFFFFFDFF @@ -300,111 +262,6 @@ #define S_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) & 0x3FF) << 8) #define G_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) >> 8) & 0x3FF) #define C_SQ_ALU_WORD1_OP2_ALU_INST 0xFFFC00FF -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD 0x00000000 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL 0x00000001 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE 0x00000002 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX 0x00000003 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN 0x00000004 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10 0x00000005 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10 0x00000006 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE 0x00000008 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT 0x00000009 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE 0x0000000A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE 0x0000000B -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10 0x0000000C -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10 0x0000000D -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10 0x0000000E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10 0x0000000F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT 0x00000010 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC 0x00000011 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL 0x00000012 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE 0x00000013 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR 0x00000014 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA 0x00000015 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR 0x00000016 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT 0x00000018 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV 0x00000019 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP 0x0000001A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT 0x0000001E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT 0x0000001F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE 0x00000020 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT 0x00000021 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE 0x00000022 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE 0x00000023 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV 0x00000024 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP 0x00000025 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR 0x00000026 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE 0x00000027 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH 0x00000028 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH 0x00000029 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH 0x0000002A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH 0x0000002B -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE 0x0000002C -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT 0x0000002D -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE 0x0000002E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE 0x0000002F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT 0x00000030 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT 0x00000031 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT 0x00000032 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT 0x00000033 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT 0x00000034 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT 0x00000035 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT 0x00000036 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT 0x00000037 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT 0x00000038 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT 0x00000039 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT 0x0000003A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT 0x0000003B -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT 0x0000003C -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT 0x0000003D -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT 0x0000003E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT 0x0000003F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT 0x00000040 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT 0x00000041 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT 0x00000042 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT 0x00000043 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT 0x00000044 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT 0x00000045 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT 0x00000046 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT 0x00000047 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT 0x00000048 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT 0x00000049 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT 0x0000004A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT 0x0000004B -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT 0x0000004C -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT 0x0000004D -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT 0x0000004E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT 0x0000004F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 0x00000050 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE 0x00000051 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE 0x00000052 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4 0x00000053 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT 0x00000060 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE 0x00000061 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED 0x00000062 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE 0x00000063 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED 0x00000064 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF 0x00000065 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE 0x00000066 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED 0x00000067 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF 0x00000068 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE 0x00000069 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE 0x0000006A -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT 0x0000006B -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT 0x0000006C -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT 0x0000006D -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN 0x0000006E -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS 0x0000006F -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT 0x00000070 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT 0x00000071 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT 0x00000072 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT 0x00000073 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT 0x00000074 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT 0x00000075 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT 0x00000076 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT 0x00000077 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT 0x00000078 -#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT 0x00000079 #define P_SQ_ALU_WORD1_OP3 #define S_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) & 0x1FF) << 0) #define G_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) >> 0) & 0x1FF) @@ -421,24 +278,6 @@ #define S_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) & 0x1F) << 13) #define G_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) >> 13) & 0x1F) #define C_SQ_ALU_WORD1_OP3_ALU_INST 0xFFFC1FFF -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT 0x0000000C -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 0x0000000D -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4 0x0000000E -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 0x0000000F -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD 0x00000010 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2 0x00000011 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4 0x00000012 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2 0x00000013 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE 0x00000014 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M2 0x00000015 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M4 0x00000016 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_D2 0x00000017 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE 0x00000018 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT 0x00000019 -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE 0x0000001A -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT 0x0000001C -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT 0x0000001D -#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT 0x0000001E #define P_SQ_VTX_WORD0 #define S_SQ_VTX_WORD0_VTX_INST(x) (((x) & 0x1F) << 0) #define G_SQ_VTX_WORD0_VTX_INST(x) (((x) >> 0) & 0x1F) @@ -610,4 +449,16 @@ #define V_SQ_REL_ABSOLUTE 0 #define V_SQ_REL_RELATIVE 1 + +#define SQ_ALU_VEC_012 0x00 +#define SQ_ALU_VEC_021 0x01 +#define SQ_ALU_VEC_120 0x02 +#define SQ_ALU_VEC_102 0x03 +#define SQ_ALU_VEC_201 0x04 +#define SQ_ALU_VEC_210 0x05 + +#define SQ_ALU_SCL_210 0x00000000 +#define SQ_ALU_SCL_122 0x00000001 +#define SQ_ALU_SCL_212 0x00000002 +#define SQ_ALU_SCL_221 0x00000003 #endif diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 66cab7d7a6e..5a4a72d64f6 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -28,60 +28,88 @@ #include "util/u_inlines.h" #include "util/u_format.h" #include "util/u_memory.h" +#include "util/u_pack_color.h" #include "r600_screen.h" #include "r600_context.h" #include "r600_resource.h" -#include "r600d.h" -#include "r600_state_inlines.h" - -static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state); -static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state); -static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state); -static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id); -static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id); -static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_framebuffer_state *state, int cb); -static void r600_db(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_framebuffer_state *state); +static struct r600_context_state *r600_new_context_state(unsigned type) +{ + struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state); + if (rstate == NULL) + return NULL; + rstate->type = type; + rstate->refcount = 1; + return rstate; +} static void *r600_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state) { struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; - return r600_context_state(rctx, pipe_blend_type, state); + rstate = r600_new_context_state(pipe_blend_type); + rstate->state.blend = *state; + rctx->vtbl->blend(rctx, &rstate->rstate[0], &rstate->state.blend); + + return rstate; } static void *r600_create_dsa_state(struct pipe_context *ctx, - const struct pipe_depth_stencil_alpha_state *state) + const struct pipe_depth_stencil_alpha_state *state) { - struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; - return r600_context_state(rctx, pipe_dsa_type, state); + rstate = r600_new_context_state(pipe_dsa_type); + rstate->state.dsa = *state; + return rstate; } static void *r600_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state) { - struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; - return r600_context_state(rctx, pipe_rasterizer_type, state); + rstate = r600_new_context_state(pipe_rasterizer_type); + rstate->state.rasterizer = *state; + return rstate; } static void *r600_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; - return r600_context_state(rctx, pipe_sampler_type, state); + rstate = r600_new_context_state(pipe_sampler_type); + rstate->state.sampler = *state; + rctx->vtbl->sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0); + rctx->vtbl->sampler_border(rctx, &rstate->rstate[1], &rstate->state.sampler, 0); + return rstate; } +static void r600_remove_sampler_view(struct r600_shader_sampler_states *sampler, + struct r600_context_state *rstate) +{ + int i, j; + + for (i = 0; i < sampler->nview; i++) { + for (j = 0; j < rstate->nrstate; j++) { + if (sampler->view[i] == &rstate->rstate[j]) + sampler->view[i] = NULL; + } + } +} static void r600_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state) { struct r600_context_state *rstate = (struct r600_context_state *)state; + struct r600_context *rctx = r600_context(ctx); + /* need to search list of vs/ps sampler views and remove it from any - uggh */ + r600_remove_sampler_view(&rctx->ps_sampler, rstate); + r600_remove_sampler_view(&rctx->vs_sampler, rstate); r600_context_state_decref(rstate); } @@ -89,24 +117,87 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c struct pipe_resource *texture, const struct pipe_sampler_view *state) { - struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; + struct r600_context *rctx = r600_context(ctx); - rstate = r600_context_state(rctx, pipe_sampler_view_type, state); + rstate = r600_new_context_state(pipe_sampler_view_type); + rstate->state.sampler_view = *state; + rstate->state.sampler_view.texture = NULL; pipe_reference(NULL, &texture->reference); rstate->state.sampler_view.texture = texture; rstate->state.sampler_view.reference.count = 1; rstate->state.sampler_view.context = ctx; - r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0); + rctx->vtbl->resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0); return &rstate->state.sampler_view; } +static void r600_set_sampler_view(struct pipe_context *ctx, + unsigned count, + struct pipe_sampler_view **views, + struct r600_shader_sampler_states *sampler, + unsigned shader_id) +{ + struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; + unsigned i; + + for (i = 0; i < sampler->nview; i++) { + radeon_draw_unbind(&rctx->draw, sampler->view[i]); + } + + for (i = 0; i < count; i++) { + rstate = (struct r600_context_state *)views[i]; + if (rstate) { + rstate->nrstate = 0; + } + } + for (i = 0; i < count; i++) { + rstate = (struct r600_context_state *)views[i]; + if (rstate) { + if (rstate->nrstate >= R600_MAX_RSTATE) + continue; + if (rstate->nrstate) { + memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state)); + } + radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, shader_id); + sampler->view[i] = &rstate->rstate[rstate->nrstate]; + rstate->nrstate++; + } + } + sampler->nview = count; +} + +static void r600_set_ps_sampler_view(struct pipe_context *ctx, + unsigned count, + struct pipe_sampler_view **views) +{ + struct r600_context *rctx = r600_context(ctx); + r600_set_sampler_view(ctx, count, views, &rctx->ps_sampler, R600_SHADER_PS); +} + +static void r600_set_vs_sampler_view(struct pipe_context *ctx, + unsigned count, + struct pipe_sampler_view **views) +{ + struct r600_context *rctx = r600_context(ctx); + r600_set_sampler_view(ctx, count, views, &rctx->vs_sampler, R600_SHADER_VS); +} + static void *r600_create_shader_state(struct pipe_context *ctx, const struct pipe_shader_state *state) { struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate; + int r; - return r600_context_state(rctx, pipe_shader_type, state); + rstate = r600_new_context_state(pipe_shader_type); + rstate->state.shader = *state; + r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens); + if (r) { + r600_context_state_decref(rstate); + return NULL; + } + return rstate; } static void *r600_create_vertex_elements(struct pipe_context *ctx, @@ -122,119 +213,95 @@ static void *r600_create_vertex_elements(struct pipe_context *ctx, return v; } -static void r600_bind_state(struct pipe_context *ctx, void *state) +static void r600_delete_vertex_element(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = r600_context(ctx); - struct r600_context_state *rstate = (struct r600_context_state *)state; + struct r600_vertex_element *v = (struct r600_vertex_element*)state; - if (state == NULL) + if (v == NULL) return; - switch (rstate->type) { - case pipe_rasterizer_type: - rctx->rasterizer = r600_context_state_decref(rctx->rasterizer); - rctx->rasterizer = r600_context_state_incref(rstate); - break; - case pipe_poly_stipple_type: - rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple); - rctx->poly_stipple = r600_context_state_incref(rstate); - break; - case pipe_scissor_type: - rctx->scissor = r600_context_state_decref(rctx->scissor); - rctx->scissor = r600_context_state_incref(rstate); - break; - case pipe_clip_type: - rctx->clip = r600_context_state_decref(rctx->clip); - rctx->clip = r600_context_state_incref(rstate); - break; - case pipe_depth_type: - rctx->depth = r600_context_state_decref(rctx->depth); - rctx->depth = r600_context_state_incref(rstate); - break; - case pipe_stencil_type: - rctx->stencil = r600_context_state_decref(rctx->stencil); - rctx->stencil = r600_context_state_incref(rstate); - break; - case pipe_alpha_type: - rctx->alpha = r600_context_state_decref(rctx->alpha); - rctx->alpha = r600_context_state_incref(rstate); - break; - case pipe_dsa_type: - rctx->dsa = r600_context_state_decref(rctx->dsa); - rctx->dsa = r600_context_state_incref(rstate); - break; - case pipe_blend_type: - rctx->blend = r600_context_state_decref(rctx->blend); - rctx->blend = r600_context_state_incref(rstate); - break; - case pipe_framebuffer_type: - rctx->framebuffer = r600_context_state_decref(rctx->framebuffer); - rctx->framebuffer = r600_context_state_incref(rstate); - break; - case pipe_stencil_ref_type: - rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref); - rctx->stencil_ref = r600_context_state_incref(rstate); - break; - case pipe_viewport_type: - rctx->viewport = r600_context_state_decref(rctx->viewport); - rctx->viewport = r600_context_state_incref(rstate); - break; - case pipe_shader_type: - case pipe_sampler_type: - case pipe_sampler_view_type: - default: - R600_ERR("invalid type %d\n", rstate->type); + if (--v->refcount) return; + free(v); +} + +static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = r600_context(ctx); + struct r600_vertex_element *v = (struct r600_vertex_element*)state; + + r600_delete_vertex_element(ctx, rctx->vertex_elements); + rctx->vertex_elements = v; + if (v) { + v->refcount++; } } -static void r600_bind_ps_shader(struct pipe_context *ctx, void *state) +static void r600_bind_rasterizer_state(struct pipe_context *ctx, void *state) { struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate = (struct r600_context_state *)state; - rctx->ps_shader = r600_context_state_decref(rctx->ps_shader); - rctx->ps_shader = r600_context_state_incref(rstate); + if (state == NULL) + return; + rctx->rasterizer = r600_context_state_decref(rctx->rasterizer); + rctx->rasterizer = r600_context_state_incref(rstate); } -static void r600_bind_vs_shader(struct pipe_context *ctx, void *state) +static void r600_bind_blend_state(struct pipe_context *ctx, void *state) { struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate = (struct r600_context_state *)state; - rctx->vs_shader = r600_context_state_decref(rctx->vs_shader); - rctx->vs_shader = r600_context_state_incref(rstate); + if (state == NULL) + return; + rctx->blend = r600_context_state_decref(rctx->blend); + rctx->blend = r600_context_state_incref(rstate); + } -static void r600_delete_vertex_element(struct pipe_context *ctx, void *state) +static void r600_bind_dsa_state(struct pipe_context *ctx, void *state) { - struct r600_vertex_element *v = (struct r600_vertex_element*)state; + struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate = (struct r600_context_state *)state; - if (v == NULL) - return; - if (--v->refcount) + if (state == NULL) return; - free(v); + rctx->dsa = r600_context_state_decref(rctx->dsa); + rctx->dsa = r600_context_state_incref(rstate); } -static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) +static void r600_bind_ps_shader(struct pipe_context *ctx, void *state) { struct r600_context *rctx = r600_context(ctx); - struct r600_vertex_element *v = (struct r600_vertex_element*)state; + struct r600_context_state *rstate = (struct r600_context_state *)state; - r600_delete_vertex_element(ctx, rctx->vertex_elements); - rctx->vertex_elements = v; - if (v) { - v->refcount++; - } + rctx->ps_shader = r600_context_state_decref(rctx->ps_shader); + rctx->ps_shader = r600_context_state_incref(rstate); } -static void r600_bind_ps_sampler(struct pipe_context *ctx, - unsigned count, void **states) +static void r600_bind_vs_shader(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = r600_context(ctx); + struct r600_context_state *rstate = (struct r600_context_state *)state; + + rctx->vs_shader = r600_context_state_decref(rctx->vs_shader); + rctx->vs_shader = r600_context_state_incref(rstate); +} + +static void r600_bind_sampler_shader(struct pipe_context *ctx, + unsigned count, void **states, + struct r600_shader_sampler_states *sampler, unsigned shader_id) { struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; unsigned i; + for (i = 0; i < sampler->nsampler; i++) { + radeon_draw_unbind(&rctx->draw, sampler->sampler[i]); + } + for (i = 0; i < sampler->nborder; i++) { + radeon_draw_unbind(&rctx->draw, sampler->border[i]); + } for (i = 0; i < count; i++) { rstate = (struct r600_context_state *)states[i]; if (rstate) { @@ -248,42 +315,31 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx, continue; if (rstate->nrstate) { memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state)); + memcpy(&rstate->rstate[rstate->nrstate+1], &rstate->rstate[1], sizeof(struct radeon_state)); } - radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS); - rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate]; - rstate->nrstate++; + radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, shader_id); + radeon_state_convert(&rstate->rstate[rstate->nrstate + 1], R600_STATE_SAMPLER_BORDER, i, shader_id); + sampler->sampler[i] = &rstate->rstate[rstate->nrstate]; + sampler->border[i] = &rstate->rstate[rstate->nrstate + 1]; + rstate->nrstate += 2; } } - rctx->ps_nsampler = count; + sampler->nsampler = count; + sampler->nborder = count; } -static void r600_bind_vs_sampler(struct pipe_context *ctx, +static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) { struct r600_context *rctx = r600_context(ctx); - struct r600_context_state *rstate; - unsigned i; + r600_bind_sampler_shader(ctx, count, states, &rctx->ps_sampler, R600_SHADER_PS); +} - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)states[i]; - if (rstate) { - rstate->nrstate = 0; - } - } - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)states[i]; - if (rstate) { - if (rstate->nrstate >= R600_MAX_RSTATE) - continue; - if (rstate->nrstate) { - memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state)); - } - radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS); - rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate]; - rstate->nrstate++; - } - } - rctx->vs_nsampler = count; +static void r600_bind_vs_sampler(struct pipe_context *ctx, + unsigned count, void **states) +{ + struct r600_context *rctx = r600_context(ctx); + r600_bind_sampler_shader(ctx, count, states, &rctx->vs_sampler, R600_SHADER_VS); } static void r600_delete_state(struct pipe_context *ctx, void *state) @@ -307,116 +363,12 @@ static void r600_set_clip_state(struct pipe_context *ctx, struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; - rstate = r600_context_state(rctx, pipe_clip_type, state); - r600_bind_state(ctx, rstate); - /* refcount is taken care of this */ - r600_delete_state(ctx, rstate); -} - -static void r600_set_constant_buffer(struct pipe_context *ctx, - uint shader, uint index, - struct pipe_resource *buffer) -{ - struct r600_screen *rscreen = r600_screen(ctx->screen); - struct r600_context *rctx = r600_context(ctx); - unsigned nconstant = 0, i, type, shader_class; - struct radeon_state *rstate, *rstates; - struct pipe_transfer *transfer; - u32 *ptr; + r600_context_state_decref(rctx->clip); - type = R600_STATE_CONSTANT; - - switch (shader) { - case PIPE_SHADER_VERTEX: - shader_class = R600_SHADER_VS; - rstates = rctx->vs_constant; - break; - case PIPE_SHADER_FRAGMENT: - shader_class = R600_SHADER_PS; - rstates = rctx->ps_constant; - break; - default: - R600_ERR("unsupported %d\n", shader); - return; - } - if (buffer && buffer->width0 > 0) { - nconstant = buffer->width0 / 16; - ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer); - if (ptr == NULL) - return; - for (i = 0; i < nconstant; i++) { - rstate = &rstates[i]; - radeon_state_init(rstate, rscreen->rw, type, i, shader_class); - rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; - rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; - rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; - rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; - if (radeon_state_pm4(rstate)) - return; - radeon_draw_bind(&rctx->draw, rstate); - } - pipe_buffer_unmap(ctx, buffer, transfer); - } -} - -static void r600_set_ps_sampler_view(struct pipe_context *ctx, - unsigned count, - struct pipe_sampler_view **views) -{ - struct r600_context *rctx = r600_context(ctx); - struct r600_context_state *rstate; - unsigned i; - - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)views[i]; - if (rstate) { - rstate->nrstate = 0; - } - } - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)views[i]; - if (rstate) { - if (rstate->nrstate >= R600_MAX_RSTATE) - continue; - if (rstate->nrstate) { - memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state)); - } - radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS); - rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate]; - rstate->nrstate++; - } - } - rctx->ps_nsampler_view = count; -} - -static void r600_set_vs_sampler_view(struct pipe_context *ctx, - unsigned count, - struct pipe_sampler_view **views) -{ - struct r600_context *rctx = r600_context(ctx); - struct r600_context_state *rstate; - unsigned i; - - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)views[i]; - if (rstate) { - rstate->nrstate = 0; - } - } - for (i = 0; i < count; i++) { - rstate = (struct r600_context_state *)views[i]; - if (rstate) { - if (rstate->nrstate >= R600_MAX_RSTATE) - continue; - if (rstate->nrstate) { - memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state)); - } - radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS); - rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate]; - rstate->nrstate++; - } - } - rctx->vs_nsampler_view = count; + rstate = r600_new_context_state(pipe_clip_type); + rstate->state.clip = *state; + rctx->vtbl->ucp(rctx, &rstate->rstate[0], &rstate->state.clip); + rctx->clip = rstate; } static void r600_set_framebuffer_state(struct pipe_context *ctx, @@ -424,15 +376,24 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, { struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; + int i; + + r600_context_state_decref(rctx->framebuffer); - rstate = r600_context_state(rctx, pipe_framebuffer_type, state); - r600_bind_state(ctx, rstate); - for (int i = 0; i < state->nr_cbufs; i++) { - r600_cb(rctx, &rstate->rstate[i+1], state, i); + rstate = r600_new_context_state(pipe_framebuffer_type); + rstate->state.framebuffer = *state; + for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { + pipe_reference(NULL, &state->cbufs[i]->reference); + } + pipe_reference(NULL, &state->zsbuf->reference); + rctx->framebuffer = rstate; + for (i = 0; i < state->nr_cbufs; i++) { + rctx->vtbl->cb(rctx, &rstate->rstate[i+1], state, i); } if (state->zsbuf) { - r600_db(rctx, &rstate->rstate[0], state); + rctx->vtbl->db(rctx, &rstate->rstate[0], state); } + return; } static void r600_set_polygon_stipple(struct pipe_context *ctx, @@ -450,10 +411,11 @@ static void r600_set_scissor_state(struct pipe_context *ctx, struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; - rstate = r600_context_state(rctx, pipe_scissor_type, state); - r600_bind_state(ctx, rstate); - /* refcount is taken care of this */ - r600_delete_state(ctx, rstate); + r600_context_state_decref(rctx->scissor); + + rstate = r600_new_context_state(pipe_scissor_type); + rstate->state.scissor = *state; + rctx->scissor = rstate; } static void r600_set_stencil_ref(struct pipe_context *ctx, @@ -462,10 +424,11 @@ static void r600_set_stencil_ref(struct pipe_context *ctx, struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; - rstate = r600_context_state(rctx, pipe_stencil_ref_type, state); - r600_bind_state(ctx, rstate); - /* refcount is taken care of this */ - r600_delete_state(ctx, rstate); + r600_context_state_decref(rctx->stencil_ref); + + rstate = r600_new_context_state(pipe_stencil_ref_type); + rstate->state.stencil_ref = *state; + rctx->stencil_ref = rstate; } static void r600_set_vertex_buffers(struct pipe_context *ctx, @@ -508,9 +471,12 @@ static void r600_set_viewport_state(struct pipe_context *ctx, struct r600_context *rctx = r600_context(ctx); struct r600_context_state *rstate; - rstate = r600_context_state(rctx, pipe_viewport_type, state); - r600_bind_state(ctx, rstate); - r600_delete_state(ctx, rstate); + r600_context_state_decref(rctx->viewport); + + rstate = r600_new_context_state(pipe_viewport_type); + rstate->state.viewport = *state; + rctx->vtbl->viewport(rctx, &rstate->rstate[0], &rstate->state.viewport); + rctx->viewport = rstate; } void r600_init_state_functions(struct r600_context *rctx) @@ -523,11 +489,11 @@ void r600_init_state_functions(struct r600_context *rctx) rctx->context.create_sampler_view = r600_create_sampler_view; rctx->context.create_vertex_elements_state = r600_create_vertex_elements; rctx->context.create_vs_state = r600_create_shader_state; - rctx->context.bind_blend_state = r600_bind_state; - rctx->context.bind_depth_stencil_alpha_state = r600_bind_state; + rctx->context.bind_blend_state = r600_bind_blend_state; + rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler; rctx->context.bind_fs_state = r600_bind_ps_shader; - rctx->context.bind_rasterizer_state = r600_bind_state; + rctx->context.bind_rasterizer_state = r600_bind_rasterizer_state; rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler; rctx->context.bind_vs_state = r600_bind_vs_shader; @@ -540,7 +506,14 @@ void r600_init_state_functions(struct r600_context *rctx) rctx->context.delete_vs_state = r600_delete_state; rctx->context.set_blend_color = r600_set_blend_color; rctx->context.set_clip_state = r600_set_clip_state; - rctx->context.set_constant_buffer = r600_set_constant_buffer; + + if (rctx->screen->chip_class == EVERGREEN) + rctx->context.set_constant_buffer = eg_set_constant_buffer; + else if (rctx->screen->use_mem_constant) + rctx->context.set_constant_buffer = r600_set_constant_buffer_mem; + else + rctx->context.set_constant_buffer = r600_set_constant_buffer_file; + rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view; rctx->context.set_framebuffer_state = r600_set_framebuffer_state; rctx->context.set_polygon_stipple = r600_set_polygon_stipple; @@ -603,775 +576,101 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state * return NULL; } -struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state) +static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shader_sampler_states *sampler) { - struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state); - const union pipe_states *states = state; - unsigned i; - int r; - - if (rstate == NULL) - return NULL; - rstate->type = type; - rstate->refcount = 1; - - switch (rstate->type) { - case pipe_sampler_view_type: - rstate->state.sampler_view = (*states).sampler_view; - rstate->state.sampler_view.texture = NULL; - break; - case pipe_framebuffer_type: - rstate->state.framebuffer = (*states).framebuffer; - for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { - pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], - (*states).framebuffer.cbufs[i]); - } - pipe_surface_reference(&rstate->state.framebuffer.zsbuf, - (*states).framebuffer.zsbuf); - break; - case pipe_viewport_type: - rstate->state.viewport = (*states).viewport; - r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport); - break; - case pipe_depth_type: - rstate->state.depth = (*states).depth; - break; - case pipe_rasterizer_type: - rstate->state.rasterizer = (*states).rasterizer; - break; - case pipe_poly_stipple_type: - rstate->state.poly_stipple = (*states).poly_stipple; - break; - case pipe_scissor_type: - rstate->state.scissor = (*states).scissor; - break; - case pipe_clip_type: - rstate->state.clip = (*states).clip; - r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip); - break; - case pipe_stencil_type: - rstate->state.stencil = (*states).stencil; - break; - case pipe_alpha_type: - rstate->state.alpha = (*states).alpha; - break; - case pipe_dsa_type: - rstate->state.dsa = (*states).dsa; - break; - case pipe_blend_type: - rstate->state.blend = (*states).blend; - r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend); - break; - case pipe_stencil_ref_type: - rstate->state.stencil_ref = (*states).stencil_ref; - break; - case pipe_shader_type: - rstate->state.shader = (*states).shader; - r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens); - if (r) { - r600_context_state_decref(rstate); - return NULL; - } - break; - case pipe_sampler_type: - rstate->state.sampler = (*states).sampler; - r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0); - break; - default: - R600_ERR("invalid type %d\n", rstate->type); - FREE(rstate); - return NULL; - } - return rstate; -} - -static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state) -{ - struct r600_screen *rscreen = rctx->screen; int i; - radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0); - rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]); - rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]); - rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]); - rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]); - rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; - rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; - - for (i = 0; i < 8; i++) { - unsigned eqRGB = state->rt[i].rgb_func; - unsigned srcRGB = state->rt[i].rgb_src_factor; - unsigned dstRGB = state->rt[i].rgb_dst_factor; - - unsigned eqA = state->rt[i].alpha_func; - unsigned srcA = state->rt[i].alpha_src_factor; - unsigned dstA = state->rt[i].alpha_dst_factor; - uint32_t bc = 0; - - if (!state->rt[i].blend_enable) - continue; - - bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); - bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); - bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); - - if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { - bc |= S_028804_SEPARATE_ALPHA_BLEND(1); - bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); - bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); - bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); - } - - rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc; - if (i == 0) - rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc; + for (i = 0; i < sampler->nsampler; i++) { + if (sampler->sampler[i]) + radeon_draw_bind(&rctx->draw, sampler->sampler[i]); } - radeon_state_pm4(rstate); -} - -static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_clip_state *state) -{ - struct r600_screen *rscreen = rctx->screen; - - radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0); + for (i = 0; i < sampler->nborder; i++) { + if (sampler->border[i]) + radeon_draw_bind(&rctx->draw, sampler->border[i]); + } - for (int i = 0; i < state->nr; i++) { - rstate->states[i * 4 + 0] = fui(state->ucp[i][0]); - rstate->states[i * 4 + 1] = fui(state->ucp[i][1]); - rstate->states[i * 4 + 2] = fui(state->ucp[i][2]); - rstate->states[i * 4 + 3] = fui(state->ucp[i][3]); + for (i = 0; i < sampler->nview; i++) { + if (sampler->view[i]) + radeon_draw_bind(&rctx->draw, sampler->view[i]); } - radeon_state_pm4(rstate); } -static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_framebuffer_state *state, int cb) -{ - struct r600_screen *rscreen = rctx->screen; - struct r600_resource_texture *rtex; - struct r600_resource *rbuffer; - unsigned level = state->cbufs[cb]->level; - unsigned pitch, slice; - unsigned color_info; - unsigned format, swap, ntype; - const struct util_format_description *desc; - - radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0); - rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; - rbuffer = &rtex->resource; - rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; - rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; - rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; - rstate->nbo = 3; - pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; - slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1; - - ntype = 0; - desc = util_format_description(rtex->resource.base.b.format); - if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) - ntype = V_0280A0_NUMBER_SRGB; - - format = r600_translate_colorformat(rtex->resource.base.b.format); - swap = r600_translate_colorswap(rtex->resource.base.b.format); - - color_info = S_0280A0_FORMAT(format) | - S_0280A0_COMP_SWAP(swap) | - S_0280A0_BLEND_CLAMP(1) | - S_0280A0_SOURCE_FORMAT(1) | - S_0280A0_NUMBER_TYPE(ntype); - - rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8; - rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info; - rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | - S_028060_SLICE_TILE_MAX(slice); - rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; - rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; - rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; - rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; - radeon_state_pm4(rstate); -} -static void r600_db(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_framebuffer_state *state) +static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush) { struct r600_screen *rscreen = rctx->screen; struct r600_resource_texture *rtex; struct r600_resource *rbuffer; - unsigned level; - unsigned pitch, slice, format; - - radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0); - if (state->zsbuf == NULL) - return; - - rtex = (struct r600_resource_texture*)state->zsbuf->texture; - rtex->tilled = 1; - rtex->array_mode = 2; - rtex->tile_type = 1; - rtex->depth = 1; - rbuffer = &rtex->resource; - - rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - rstate->nbo = 1; - rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; - level = state->zsbuf->level; - pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; - slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1; - format = r600_translate_dbformat(state->zsbuf->texture->format); - rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8; - rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) | - S_028010_FORMAT(format); - rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000; - rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1; - rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | - S_028000_SLICE_TILE_MAX(slice); - radeon_state_pm4(rstate); -} - -static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate) -{ - const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer; - const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; - const struct pipe_clip_state *clip = NULL; - struct r600_screen *rscreen = rctx->screen; - float offset_units = 0, offset_scale = 0; - char depth = 0; - unsigned offset_db_fmt_cntl = 0; - unsigned tmp; - unsigned prov_vtx = 1; - - if (rctx->clip) - clip = &rctx->clip->state.clip; - if (fb->zsbuf) { - offset_units = state->offset_units; - offset_scale = state->offset_scale * 12.0f; - switch (fb->zsbuf->texture->format) { - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: - depth = -24; - offset_units *= 2.0f; - break; - case PIPE_FORMAT_Z32_FLOAT: - depth = -23; - offset_units *= 1.0f; - offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); - break; - case PIPE_FORMAT_Z16_UNORM: - depth = -16; - offset_units *= 4.0f; - break; - default: - R600_ERR("unsupported %d\n", fb->zsbuf->texture->format); - return; - } - } - offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); - - if (state->flatshade_first) - prov_vtx = 0; - - rctx->flat_shade = state->flatshade; - radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0); - rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; - if (state->sprite_coord_enable) { - rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |= - S_0286D4_PNT_SPRITE_ENA(1) | - S_0286D4_PNT_SPRITE_OVRD_X(2) | - S_0286D4_PNT_SPRITE_OVRD_Y(3) | - S_0286D4_PNT_SPRITE_OVRD_Z(0) | - S_0286D4_PNT_SPRITE_OVRD_W(1); - if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { - rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |= - S_0286D4_PNT_SPRITE_TOP_1(1); - } - } - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0; - if (clip) { - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1); - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp); - rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp); - } - rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = - S_028814_PROVOKING_VTX_LAST(prov_vtx) | - S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | - S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | - S_028814_FACE(!state->front_ccw) | - S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri); - rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = - S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | - S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); - rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; - /* point size 12.4 fixed point */ - tmp = (unsigned)(state->point_size * 8.0); - rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp); - rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; - rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; - rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; - rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; - rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; - rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl; - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale); - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units); - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale); - rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units); - radeon_state_pm4(rstate); -} - -static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate) -{ - const struct pipe_scissor_state *state = &rctx->scissor->state.scissor; - const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; - struct r600_screen *rscreen = rctx->screen; - unsigned minx, maxx, miny, maxy; - u32 tl, br; - - if (state == NULL) { - minx = 0; - miny = 0; - maxx = fb->cbufs[0]->width; - maxy = fb->cbufs[0]->height; - } else { - minx = state->minx; - miny = state->miny; - maxx = state->maxx; - maxy = state->maxy; - } - tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1); - br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy); - radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0); - rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; - rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; - rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; - rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; - rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; - radeon_state_pm4(rstate); -} - -static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state) -{ - struct r600_screen *rscreen = rctx->screen; - - radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0); - rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; - rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; - rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); - rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); - rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; - radeon_state_pm4(rstate); -} - -static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) -{ - const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; - const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref; - struct r600_screen *rscreen = rctx->screen; - unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; - unsigned stencil_ref_mask, stencil_ref_mask_bf; - struct r600_shader *rshader; + struct pipe_surface *surf; int i; - if (rctx->ps_shader == NULL) { - return; - } - radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0); - - db_shader_control = 0x210; - rshader = &rctx->ps_shader->shader; - if (rshader->uses_kill) - db_shader_control |= (1 << 6); - for (i = 0; i < rshader->noutput; i++) { - if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) - db_shader_control |= 1; - } - stencil_ref_mask = 0; - stencil_ref_mask_bf = 0; - db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | - S_028800_Z_WRITE_ENABLE(state->depth.writemask) | - S_028800_ZFUNC(state->depth.func); - /* set stencil enable */ - - if (state->stencil[0].enabled) { - db_depth_control |= S_028800_STENCIL_ENABLE(1); - db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); - db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); - db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); - db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); - - stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | - S_028430_STENCILWRITEMASK(state->stencil[0].writemask); - stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); - if (state->stencil[1].enabled) { - db_depth_control |= S_028800_BACKFACE_ENABLE(1); - db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); - db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); - db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); - db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); - stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | - S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); - stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); - } - } - - alpha_test_control = 0; - alpha_ref = 0; - if (state->alpha.enabled) { - alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); - alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); - alpha_ref = fui(state->alpha.ref_value); - } - - rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; - rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; - rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control; - rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask; - rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf; - rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref; - rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; - rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; - rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; - rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control; - rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control; - rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; - rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; - rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; - rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; - rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; - radeon_state_pm4(rstate); -} - -static inline unsigned r600_tex_wrap(unsigned wrap) -{ - switch (wrap) { - default: - case PIPE_TEX_WRAP_REPEAT: - return V_03C000_SQ_TEX_WRAP; - case PIPE_TEX_WRAP_CLAMP: - return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; - case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; - case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - return V_03C000_SQ_TEX_CLAMP_BORDER; - case PIPE_TEX_WRAP_MIRROR_REPEAT: - return V_03C000_SQ_TEX_MIRROR; - case PIPE_TEX_WRAP_MIRROR_CLAMP: - return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: - return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: - return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; - } -} - -static inline unsigned r600_tex_filter(unsigned filter) -{ - switch (filter) { - default: - case PIPE_TEX_FILTER_NEAREST: - return V_03C000_SQ_TEX_XY_FILTER_POINT; - case PIPE_TEX_FILTER_LINEAR: - return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; - } -} - -static inline unsigned r600_tex_mipfilter(unsigned filter) -{ - switch (filter) { - case PIPE_TEX_MIPFILTER_NEAREST: - return V_03C000_SQ_TEX_Z_FILTER_POINT; - case PIPE_TEX_MIPFILTER_LINEAR: - return V_03C000_SQ_TEX_Z_FILTER_LINEAR; - default: - case PIPE_TEX_MIPFILTER_NONE: - return V_03C000_SQ_TEX_Z_FILTER_NONE; - } -} - -static inline unsigned r600_tex_compare(unsigned compare) -{ - switch (compare) { - default: - case PIPE_FUNC_NEVER: - return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; - case PIPE_FUNC_LESS: - return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; - case PIPE_FUNC_EQUAL: - return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; - case PIPE_FUNC_LEQUAL: - return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; - case PIPE_FUNC_GREATER: - return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; - case PIPE_FUNC_NOTEQUAL: - return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; - case PIPE_FUNC_GEQUAL: - return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; - case PIPE_FUNC_ALWAYS: - return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; - } -} - -static INLINE u32 S_FIXED(float value, u32 frac_bits) -{ - return value * (1 << frac_bits); -} - -static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, - const struct pipe_sampler_state *state, unsigned id) -{ - struct r600_screen *rscreen = rctx->screen; - - radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS); - rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = - S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | - S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | - S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | - S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | - S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | - S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | - S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)); - /* FIXME LOD it depends on texture base level ... */ - rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] = - S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | - S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | - S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); - rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1); - radeon_state_pm4(rstate); -} - -static inline unsigned r600_tex_swizzle(unsigned swizzle) -{ - switch (swizzle) { - case PIPE_SWIZZLE_RED: - return V_038010_SQ_SEL_X; - case PIPE_SWIZZLE_GREEN: - return V_038010_SQ_SEL_Y; - case PIPE_SWIZZLE_BLUE: - return V_038010_SQ_SEL_Z; - case PIPE_SWIZZLE_ALPHA: - return V_038010_SQ_SEL_W; - case PIPE_SWIZZLE_ZERO: - return V_038010_SQ_SEL_0; - default: - case PIPE_SWIZZLE_ONE: - return V_038010_SQ_SEL_1; - } -} - -static inline unsigned r600_format_type(unsigned format_type) -{ - switch (format_type) { - default: - case UTIL_FORMAT_TYPE_UNSIGNED: - return V_038010_SQ_FORMAT_COMP_UNSIGNED; - case UTIL_FORMAT_TYPE_SIGNED: - return V_038010_SQ_FORMAT_COMP_SIGNED; - case UTIL_FORMAT_TYPE_FIXED: - return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED; - } -} + radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0); -static inline unsigned r600_tex_dim(unsigned dim) -{ - switch (dim) { - default: - case PIPE_TEXTURE_1D: - return V_038000_SQ_TEX_DIM_1D; - case PIPE_TEXTURE_2D: - case PIPE_TEXTURE_RECT: - return V_038000_SQ_TEX_DIM_2D; - case PIPE_TEXTURE_3D: - return V_038000_SQ_TEX_DIM_3D; - case PIPE_TEXTURE_CUBE: - return V_038000_SQ_TEX_DIM_CUBEMAP; + for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) { + surf = rctx->framebuffer->state.framebuffer.cbufs[i]; + + rtex = (struct r600_resource_texture*)surf->texture; + rbuffer = &rtex->resource; + /* just need to the bo to the flush list */ + flush->bo[i] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + flush->placement[i] = RADEON_GEM_DOMAIN_VRAM; } + flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs; + return radeon_state_pm4(flush); } -static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, - const struct pipe_sampler_view *view, unsigned id) +static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush) { - struct r600_context *rctx = r600_context(ctx); struct r600_screen *rscreen = rctx->screen; - const struct util_format_description *desc; - struct r600_resource_texture *tmp; + struct r600_resource_texture *rtex; struct r600_resource *rbuffer; - unsigned format; - uint32_t word4 = 0, yuv_format = 0, pitch = 0; - unsigned char swizzle[4], array_mode = 0, tile_type = 0; - int r; - - rstate->cpm4 = 0; - swizzle[0] = view->swizzle_r; - swizzle[1] = view->swizzle_g; - swizzle[2] = view->swizzle_b; - swizzle[3] = view->swizzle_a; - format = r600_translate_texformat(view->texture->format, - swizzle, - &word4, &yuv_format); - if (format == ~0) { - return; - } - desc = util_format_description(view->texture->format); - if (desc == NULL) { - R600_ERR("unknow format %d\n", view->texture->format); - return; - } - radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS); - tmp = (struct r600_resource_texture*)view->texture; - rbuffer = &tmp->resource; - if (tmp->depth) { - r = r600_texture_from_depth(ctx, tmp, view->first_level); - if (r) { - return; - } - rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); - rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed); - } else { - rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); - } - rstate->nbo = 2; - rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; - rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; - rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; - rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; - - pitch = (tmp->pitch[0] / tmp->bpt); - pitch = (pitch + 0x7) & ~0x7; - - /* FIXME properly handle first level != 0 */ - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = - S_038000_DIM(r600_tex_dim(view->texture->target)) | - S_038000_TILE_MODE(array_mode) | - S_038000_TILE_TYPE(tile_type) | - S_038000_PITCH((pitch / 8) - 1) | - S_038000_TEX_WIDTH(view->texture->width0 - 1); - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = - S_038004_TEX_HEIGHT(view->texture->height0 - 1) | - S_038004_TEX_DEPTH(view->texture->depth0 - 1) | - S_038004_DATA_FORMAT(format); - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8; - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = - word4 | - S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | - S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | - S_038010_REQUEST_SIZE(1) | - S_038010_BASE_LEVEL(view->first_level); - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = - S_038014_LAST_LEVEL(view->last_level) | - S_038014_BASE_ARRAY(0) | - S_038014_LAST_ARRAY(0); - rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = - S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE); - radeon_state_pm4(rstate); -} + struct pipe_surface *surf; -static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) -{ - struct r600_screen *rscreen = rctx->screen; - const struct pipe_blend_state *pbs = &rctx->blend->state.blend; - int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs; - uint32_t color_control, target_mask, shader_mask; - int i; - - target_mask = 0; - shader_mask = 0; - color_control = S_028808_PER_MRT_BLEND(1); - - for (i = 0; i < nr_cbufs; i++) { - shader_mask |= 0xf << (i * 4); - } + surf = rctx->framebuffer->state.framebuffer.zsbuf; - if (pbs->logicop_enable) { - color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20); - } else { - color_control |= (0xcc << 16); - } + if (!surf) + return 0; + + radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0); + rtex = (struct r600_resource_texture*)surf->texture; + rbuffer = &rtex->resource; + /* just need to the bo to the flush list */ + flush->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + flush->placement[0] = RADEON_GEM_DOMAIN_VRAM; - if (pbs->independent_blend_enable) { - for (i = 0; i < nr_cbufs; i++) { - if (pbs->rt[i].blend_enable) { - color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); - } - target_mask |= (pbs->rt[i].colormask << (4 * i)); - } - } else { - for (i = 0; i < nr_cbufs; i++) { - if (pbs->rt[0].blend_enable) { - color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); - } - target_mask |= (pbs->rt[0].colormask << (4 * i)); - } - } - radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0); - rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask; - rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask; - rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control; - rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; - rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; - rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000; - rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; - rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000; - rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; - rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; - rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; - radeon_state_pm4(rstate); + flush->nbo = 1; + return radeon_state_pm4(flush); } int r600_context_hw_states(struct pipe_context *ctx) { struct r600_context *rctx = r600_context(ctx); unsigned i; - + /* build new states */ - r600_rasterizer(rctx, &rctx->hw_states.rasterizer); - r600_scissor(rctx, &rctx->hw_states.scissor); - r600_dsa(rctx, &rctx->hw_states.dsa); - r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl); + rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer); + rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor); + rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa); + rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl); + + /* setup flushes */ + setup_db_flush(rctx, &rctx->hw_states.db_flush); + setup_cb_flush(rctx, &rctx->hw_states.cb_flush); /* bind states */ + radeon_draw_bind(&rctx->draw, &rctx->config); + radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer); radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor); radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa); radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl); - radeon_draw_bind(&rctx->draw, &rctx->config); + radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush); + radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush); + + radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush); + radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush); if (rctx->viewport) { radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]); @@ -1388,15 +687,9 @@ int r600_context_hw_states(struct pipe_context *ctx) if (rctx->framebuffer->state.framebuffer.zsbuf) { radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]); } - for (i = 0; i < rctx->ps_nsampler; i++) { - if (rctx->ps_sampler[i]) { - radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]); - } - } - for (i = 0; i < rctx->ps_nsampler_view; i++) { - if (rctx->ps_sampler_view[i]) { - radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]); - } - } + + r600_bind_shader_sampler(rctx, &rctx->vs_sampler); + r600_bind_shader_sampler(rctx, &rctx->ps_sampler); + return 0; } diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h index 84866825aab..b4c21d9e126 100644 --- a/src/gallium/drivers/r600/r600_state_inlines.h +++ b/src/gallium/drivers/r600/r600_state_inlines.h @@ -129,7 +129,125 @@ static INLINE uint32_t r600_translate_ds_func(int func) return func; } -static uint32_t r600_translate_dbformat(enum pipe_format format) +static inline unsigned r600_tex_wrap(unsigned wrap) +{ + switch (wrap) { + default: + case PIPE_TEX_WRAP_REPEAT: + return V_03C000_SQ_TEX_WRAP; + case PIPE_TEX_WRAP_CLAMP: + return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: + return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: + return V_03C000_SQ_TEX_CLAMP_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: + return V_03C000_SQ_TEX_MIRROR; + case PIPE_TEX_WRAP_MIRROR_CLAMP: + return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: + return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: + return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; + } +} + +static inline unsigned r600_tex_filter(unsigned filter) +{ + switch (filter) { + default: + case PIPE_TEX_FILTER_NEAREST: + return V_03C000_SQ_TEX_XY_FILTER_POINT; + case PIPE_TEX_FILTER_LINEAR: + return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; + } +} + +static inline unsigned r600_tex_mipfilter(unsigned filter) +{ + switch (filter) { + case PIPE_TEX_MIPFILTER_NEAREST: + return V_03C000_SQ_TEX_Z_FILTER_POINT; + case PIPE_TEX_MIPFILTER_LINEAR: + return V_03C000_SQ_TEX_Z_FILTER_LINEAR; + default: + case PIPE_TEX_MIPFILTER_NONE: + return V_03C000_SQ_TEX_Z_FILTER_NONE; + } +} + +static inline unsigned r600_tex_compare(unsigned compare) +{ + switch (compare) { + default: + case PIPE_FUNC_NEVER: + return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; + case PIPE_FUNC_LESS: + return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; + case PIPE_FUNC_EQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; + case PIPE_FUNC_LEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; + case PIPE_FUNC_GREATER: + return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; + case PIPE_FUNC_NOTEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; + case PIPE_FUNC_ALWAYS: + return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; + } +} + +static inline unsigned r600_tex_swizzle(unsigned swizzle) +{ + switch (swizzle) { + case PIPE_SWIZZLE_RED: + return V_038010_SQ_SEL_X; + case PIPE_SWIZZLE_GREEN: + return V_038010_SQ_SEL_Y; + case PIPE_SWIZZLE_BLUE: + return V_038010_SQ_SEL_Z; + case PIPE_SWIZZLE_ALPHA: + return V_038010_SQ_SEL_W; + case PIPE_SWIZZLE_ZERO: + return V_038010_SQ_SEL_0; + default: + case PIPE_SWIZZLE_ONE: + return V_038010_SQ_SEL_1; + } +} + +static inline unsigned r600_format_type(unsigned format_type) +{ + switch (format_type) { + default: + case UTIL_FORMAT_TYPE_UNSIGNED: + return V_038010_SQ_FORMAT_COMP_UNSIGNED; + case UTIL_FORMAT_TYPE_SIGNED: + return V_038010_SQ_FORMAT_COMP_SIGNED; + case UTIL_FORMAT_TYPE_FIXED: + return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED; + } +} + +static inline unsigned r600_tex_dim(unsigned dim) +{ + switch (dim) { + default: + case PIPE_TEXTURE_1D: + return V_038000_SQ_TEX_DIM_1D; + case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_RECT: + return V_038000_SQ_TEX_DIM_2D; + case PIPE_TEXTURE_3D: + return V_038000_SQ_TEX_DIM_3D; + case PIPE_TEXTURE_CUBE: + return V_038000_SQ_TEX_DIM_CUBEMAP; + } +} + +static inline uint32_t r600_translate_dbformat(enum pipe_format format) { switch (format) { case PIPE_FORMAT_Z16_UNORM: @@ -143,7 +261,7 @@ static uint32_t r600_translate_dbformat(enum pipe_format format) } } -static uint32_t r600_translate_colorswap(enum pipe_format format) +static inline uint32_t r600_translate_colorswap(enum pipe_format format) { switch (format) { /* 8-bit buffers. */ diff --git a/src/gallium/drivers/r600/r600_states_inc.h b/src/gallium/drivers/r600/r600_states_inc.h new file mode 100644 index 00000000000..de717f35368 --- /dev/null +++ b/src/gallium/drivers/r600/r600_states_inc.h @@ -0,0 +1,543 @@ +/* This file is autogenerated from r600_states.h - do not edit directly */ +/* autogenerating script is gen_r600_states.py */ + +/* R600_CONFIG */ +#define R600_CONFIG__SQ_CONFIG 0 +#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 +#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2 +#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3 +#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4 +#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5 +#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 +#define R600_CONFIG__TA_CNTL_AUX 7 +#define R600_CONFIG__VC_ENHANCE 8 +#define R600_CONFIG__DB_DEBUG 9 +#define R600_CONFIG__DB_WATERMARKS 10 +#define R600_CONFIG__SX_MISC 11 +#define R600_CONFIG__SPI_THREAD_GROUPING 12 +#define R600_CONFIG__CB_SHADER_CONTROL 13 +#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14 +#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15 +#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16 +#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17 +#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18 +#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19 +#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20 +#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21 +#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22 +#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23 +#define R600_CONFIG__VGT_HOS_CNTL 24 +#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25 +#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26 +#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27 +#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28 +#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29 +#define R600_CONFIG__VGT_GROUP_DECR 30 +#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31 +#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32 +#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33 +#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34 +#define R600_CONFIG__VGT_GS_MODE 35 +#define R600_CONFIG__PA_SC_MODE_CNTL 36 +#define R600_CONFIG__VGT_STRMOUT_EN 37 +#define R600_CONFIG__VGT_REUSE_OFF 38 +#define R600_CONFIG__VGT_VTX_CNT_EN 39 +#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40 +#define R600_CONFIG_SIZE 41 +#define R600_CONFIG_PM4 128 + +/* R600_CB_CNTL */ +#define R600_CB_CNTL__CB_CLEAR_RED 0 +#define R600_CB_CNTL__CB_CLEAR_GREEN 1 +#define R600_CB_CNTL__CB_CLEAR_BLUE 2 +#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 +#define R600_CB_CNTL__CB_SHADER_MASK 4 +#define R600_CB_CNTL__CB_TARGET_MASK 5 +#define R600_CB_CNTL__CB_FOG_RED 6 +#define R600_CB_CNTL__CB_FOG_GREEN 7 +#define R600_CB_CNTL__CB_FOG_BLUE 8 +#define R600_CB_CNTL__CB_COLOR_CONTROL 9 +#define R600_CB_CNTL__PA_SC_AA_CONFIG 10 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12 +#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13 +#define R600_CB_CNTL__CB_CLRCMP_SRC 14 +#define R600_CB_CNTL__CB_CLRCMP_DST 15 +#define R600_CB_CNTL__CB_CLRCMP_MSK 16 +#define R600_CB_CNTL__PA_SC_AA_MASK 17 +#define R600_CB_CNTL_SIZE 18 +#define R600_CB_CNTL_PM4 128 + +/* R600_RASTERIZER */ +#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0 +#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1 +#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2 +#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3 +#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4 +#define R600_RASTERIZER__PA_SU_POINT_SIZE 5 +#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6 +#define R600_RASTERIZER__PA_SU_LINE_CNTL 7 +#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8 +#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9 +#define R600_RASTERIZER__PA_SC_LINE_CNTL 10 +#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 +#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 +#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 +#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 +#define R600_RASTERIZER_SIZE 21 +#define R600_RASTERIZER_PM4 128 + +/* R600_VIEWPORT */ +#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 +#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 +#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 +#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 +#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 +#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 +#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 +#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 +#define R600_VIEWPORT__PA_CL_VTE_CNTL 8 +#define R600_VIEWPORT_SIZE 9 +#define R600_VIEWPORT_PM4 128 + +/* R600_SCISSOR */ +#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 +#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 +#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 +#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13 +#define R600_SCISSOR__PA_SC_EDGERULE 14 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 +#define R600_SCISSOR_SIZE 19 +#define R600_SCISSOR_PM4 128 + +/* R600_BLEND */ +#define R600_BLEND__CB_BLEND_RED 0 +#define R600_BLEND__CB_BLEND_GREEN 1 +#define R600_BLEND__CB_BLEND_BLUE 2 +#define R600_BLEND__CB_BLEND_ALPHA 3 +#define R600_BLEND__CB_BLEND0_CONTROL 4 +#define R600_BLEND__CB_BLEND1_CONTROL 5 +#define R600_BLEND__CB_BLEND2_CONTROL 6 +#define R600_BLEND__CB_BLEND3_CONTROL 7 +#define R600_BLEND__CB_BLEND4_CONTROL 8 +#define R600_BLEND__CB_BLEND5_CONTROL 9 +#define R600_BLEND__CB_BLEND6_CONTROL 10 +#define R600_BLEND__CB_BLEND7_CONTROL 11 +#define R600_BLEND__CB_BLEND_CONTROL 12 +#define R600_BLEND_SIZE 13 +#define R600_BLEND_PM4 128 + +/* R600_DSA */ +#define R600_DSA__DB_STENCIL_CLEAR 0 +#define R600_DSA__DB_DEPTH_CLEAR 1 +#define R600_DSA__SX_ALPHA_TEST_CONTROL 2 +#define R600_DSA__DB_STENCILREFMASK 3 +#define R600_DSA__DB_STENCILREFMASK_BF 4 +#define R600_DSA__SX_ALPHA_REF 5 +#define R600_DSA__SPI_FOG_FUNC_SCALE 6 +#define R600_DSA__SPI_FOG_FUNC_BIAS 7 +#define R600_DSA__SPI_FOG_CNTL 8 +#define R600_DSA__DB_DEPTH_CONTROL 9 +#define R600_DSA__DB_SHADER_CONTROL 10 +#define R600_DSA__DB_RENDER_CONTROL 11 +#define R600_DSA__DB_RENDER_OVERRIDE 12 +#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13 +#define R600_DSA__DB_PRELOAD_CONTROL 14 +#define R600_DSA__DB_ALPHA_TO_MASK 15 +#define R600_DSA_SIZE 16 +#define R600_DSA_PM4 128 + +/* R600_VS_SHADER */ +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31 +#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32 +#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33 +#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34 +#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35 +#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36 +#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37 +#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38 +#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39 +#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40 +#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41 +#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42 +#define R600_VS_SHADER__SQ_PGM_START_VS 43 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44 +#define R600_VS_SHADER__SQ_PGM_START_FS 45 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48 +#define R600_VS_SHADER_SIZE 49 +#define R600_VS_SHADER_PM4 128 + +/* R600_PS_SHADER */ +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33 +#define R600_PS_SHADER__SPI_INPUT_Z 34 +#define R600_PS_SHADER__SQ_PGM_START_PS 35 +#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36 +#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37 +#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38 +#define R600_PS_SHADER_SIZE 39 +#define R600_PS_SHADER_PM4 128 + +/* R600_VS_CBUF */ +#define R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0 +#define R600_VS_CBUF__ALU_CONST_CACHE_VS_0 1 +#define R600_VS_CBUF_SIZE 2 +#define R600_VS_CBUF_PM4 128 + +/* R600_PS_CBUF */ +#define R600_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0 +#define R600_PS_CBUF__ALU_CONST_CACHE_PS_0 1 +#define R600_PS_CBUF_SIZE 2 +#define R600_PS_CBUF_PM4 128 + +/* R600_PS_CONSTANT */ +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3 +#define R600_PS_CONSTANT_SIZE 4 +#define R600_PS_CONSTANT_PM4 128 + +/* R600_VS_CONSTANT */ +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3 +#define R600_VS_CONSTANT_SIZE 4 +#define R600_VS_CONSTANT_PM4 128 + +/* R600_UCP */ +#define R600_UCP__PA_CL_UCP0_X 0 +#define R600_UCP__PA_CL_UCP0_Y 1 +#define R600_UCP__PA_CL_UCP0_Z 2 +#define R600_UCP__PA_CL_UCP0_W 3 +#define R600_UCP__PA_CL_UCP1_X 4 +#define R600_UCP__PA_CL_UCP1_Y 5 +#define R600_UCP__PA_CL_UCP1_Z 6 +#define R600_UCP__PA_CL_UCP1_W 7 +#define R600_UCP__PA_CL_UCP2_X 8 +#define R600_UCP__PA_CL_UCP2_Y 9 +#define R600_UCP__PA_CL_UCP2_Z 10 +#define R600_UCP__PA_CL_UCP2_W 11 +#define R600_UCP__PA_CL_UCP3_X 12 +#define R600_UCP__PA_CL_UCP3_Y 13 +#define R600_UCP__PA_CL_UCP3_Z 14 +#define R600_UCP__PA_CL_UCP3_W 15 +#define R600_UCP__PA_CL_UCP4_X 16 +#define R600_UCP__PA_CL_UCP4_Y 17 +#define R600_UCP__PA_CL_UCP4_Z 18 +#define R600_UCP__PA_CL_UCP4_W 19 +#define R600_UCP__PA_CL_UCP5_X 20 +#define R600_UCP__PA_CL_UCP5_Y 21 +#define R600_UCP__PA_CL_UCP5_Z 22 +#define R600_UCP__PA_CL_UCP5_W 23 +#define R600_UCP_SIZE 24 +#define R600_UCP_PM4 128 + +/* R600_PS_RESOURCE */ +#define R600_PS_RESOURCE__RESOURCE0_WORD0 0 +#define R600_PS_RESOURCE__RESOURCE0_WORD1 1 +#define R600_PS_RESOURCE__RESOURCE0_WORD2 2 +#define R600_PS_RESOURCE__RESOURCE0_WORD3 3 +#define R600_PS_RESOURCE__RESOURCE0_WORD4 4 +#define R600_PS_RESOURCE__RESOURCE0_WORD5 5 +#define R600_PS_RESOURCE__RESOURCE0_WORD6 6 +#define R600_PS_RESOURCE_SIZE 7 +#define R600_PS_RESOURCE_PM4 128 + +/* R600_VS_RESOURCE */ +#define R600_VS_RESOURCE__RESOURCE160_WORD0 0 +#define R600_VS_RESOURCE__RESOURCE160_WORD1 1 +#define R600_VS_RESOURCE__RESOURCE160_WORD2 2 +#define R600_VS_RESOURCE__RESOURCE160_WORD3 3 +#define R600_VS_RESOURCE__RESOURCE160_WORD4 4 +#define R600_VS_RESOURCE__RESOURCE160_WORD5 5 +#define R600_VS_RESOURCE__RESOURCE160_WORD6 6 +#define R600_VS_RESOURCE_SIZE 7 +#define R600_VS_RESOURCE_PM4 128 + +/* R600_FS_RESOURCE */ +#define R600_FS_RESOURCE__RESOURCE320_WORD0 0 +#define R600_FS_RESOURCE__RESOURCE320_WORD1 1 +#define R600_FS_RESOURCE__RESOURCE320_WORD2 2 +#define R600_FS_RESOURCE__RESOURCE320_WORD3 3 +#define R600_FS_RESOURCE__RESOURCE320_WORD4 4 +#define R600_FS_RESOURCE__RESOURCE320_WORD5 5 +#define R600_FS_RESOURCE__RESOURCE320_WORD6 6 +#define R600_FS_RESOURCE_SIZE 7 +#define R600_FS_RESOURCE_PM4 128 + +/* R600_GS_RESOURCE */ +#define R600_GS_RESOURCE__RESOURCE336_WORD0 0 +#define R600_GS_RESOURCE__RESOURCE336_WORD1 1 +#define R600_GS_RESOURCE__RESOURCE336_WORD2 2 +#define R600_GS_RESOURCE__RESOURCE336_WORD3 3 +#define R600_GS_RESOURCE__RESOURCE336_WORD4 4 +#define R600_GS_RESOURCE__RESOURCE336_WORD5 5 +#define R600_GS_RESOURCE__RESOURCE336_WORD6 6 +#define R600_GS_RESOURCE_SIZE 7 +#define R600_GS_RESOURCE_PM4 128 + +/* R600_PS_SAMPLER */ +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 +#define R600_PS_SAMPLER_SIZE 3 +#define R600_PS_SAMPLER_PM4 128 + +/* R600_VS_SAMPLER */ +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 +#define R600_VS_SAMPLER_SIZE 3 +#define R600_VS_SAMPLER_PM4 128 + +/* R600_GS_SAMPLER */ +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 +#define R600_GS_SAMPLER_SIZE 3 +#define R600_GS_SAMPLER_PM4 128 + +/* R600_PS_SAMPLER_BORDER */ +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 +#define R600_PS_SAMPLER_BORDER_SIZE 4 +#define R600_PS_SAMPLER_BORDER_PM4 128 + +/* R600_VS_SAMPLER_BORDER */ +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 +#define R600_VS_SAMPLER_BORDER_SIZE 4 +#define R600_VS_SAMPLER_BORDER_PM4 128 + +/* R600_GS_SAMPLER_BORDER */ +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 +#define R600_GS_SAMPLER_BORDER_SIZE 4 +#define R600_GS_SAMPLER_BORDER_PM4 128 + +/* R600_CB0 */ +#define R600_CB0__CB_COLOR0_BASE 0 +#define R600_CB0__CB_COLOR0_INFO 1 +#define R600_CB0__CB_COLOR0_SIZE 2 +#define R600_CB0__CB_COLOR0_VIEW 3 +#define R600_CB0__CB_COLOR0_FRAG 4 +#define R600_CB0__CB_COLOR0_TILE 5 +#define R600_CB0__CB_COLOR0_MASK 6 +#define R600_CB0_SIZE 7 +#define R600_CB0_PM4 128 + +/* R600_CB1 */ +#define R600_CB1__CB_COLOR1_BASE 0 +#define R600_CB1__CB_COLOR1_INFO 1 +#define R600_CB1__CB_COLOR1_SIZE 2 +#define R600_CB1__CB_COLOR1_VIEW 3 +#define R600_CB1__CB_COLOR1_FRAG 4 +#define R600_CB1__CB_COLOR1_TILE 5 +#define R600_CB1__CB_COLOR1_MASK 6 +#define R600_CB1_SIZE 7 +#define R600_CB1_PM4 128 + +/* R600_CB2 */ +#define R600_CB2__CB_COLOR2_BASE 0 +#define R600_CB2__CB_COLOR2_INFO 1 +#define R600_CB2__CB_COLOR2_SIZE 2 +#define R600_CB2__CB_COLOR2_VIEW 3 +#define R600_CB2__CB_COLOR2_FRAG 4 +#define R600_CB2__CB_COLOR2_TILE 5 +#define R600_CB2__CB_COLOR2_MASK 6 +#define R600_CB2_SIZE 7 +#define R600_CB2_PM4 128 + +/* R600_CB3 */ +#define R600_CB3__CB_COLOR3_BASE 0 +#define R600_CB3__CB_COLOR3_INFO 1 +#define R600_CB3__CB_COLOR3_SIZE 2 +#define R600_CB3__CB_COLOR3_VIEW 3 +#define R600_CB3__CB_COLOR3_FRAG 4 +#define R600_CB3__CB_COLOR3_TILE 5 +#define R600_CB3__CB_COLOR3_MASK 6 +#define R600_CB3_SIZE 7 +#define R600_CB3_PM4 128 + +/* R600_CB4 */ +#define R600_CB4__CB_COLOR4_BASE 0 +#define R600_CB4__CB_COLOR4_INFO 1 +#define R600_CB4__CB_COLOR4_SIZE 2 +#define R600_CB4__CB_COLOR4_VIEW 3 +#define R600_CB4__CB_COLOR4_FRAG 4 +#define R600_CB4__CB_COLOR4_TILE 5 +#define R600_CB4__CB_COLOR4_MASK 6 +#define R600_CB4_SIZE 7 +#define R600_CB4_PM4 128 + +/* R600_CB5 */ +#define R600_CB5__CB_COLOR5_BASE 0 +#define R600_CB5__CB_COLOR5_INFO 1 +#define R600_CB5__CB_COLOR5_SIZE 2 +#define R600_CB5__CB_COLOR5_VIEW 3 +#define R600_CB5__CB_COLOR5_FRAG 4 +#define R600_CB5__CB_COLOR5_TILE 5 +#define R600_CB5__CB_COLOR5_MASK 6 +#define R600_CB5_SIZE 7 +#define R600_CB5_PM4 128 + +/* R600_CB6 */ +#define R600_CB6__CB_COLOR6_BASE 0 +#define R600_CB6__CB_COLOR6_INFO 1 +#define R600_CB6__CB_COLOR6_SIZE 2 +#define R600_CB6__CB_COLOR6_VIEW 3 +#define R600_CB6__CB_COLOR6_FRAG 4 +#define R600_CB6__CB_COLOR6_TILE 5 +#define R600_CB6__CB_COLOR6_MASK 6 +#define R600_CB6_SIZE 7 +#define R600_CB6_PM4 128 + +/* R600_CB7 */ +#define R600_CB7__CB_COLOR7_BASE 0 +#define R600_CB7__CB_COLOR7_INFO 1 +#define R600_CB7__CB_COLOR7_SIZE 2 +#define R600_CB7__CB_COLOR7_VIEW 3 +#define R600_CB7__CB_COLOR7_FRAG 4 +#define R600_CB7__CB_COLOR7_TILE 5 +#define R600_CB7__CB_COLOR7_MASK 6 +#define R600_CB7_SIZE 7 +#define R600_CB7_PM4 128 + +/* R600_DB */ +#define R600_DB__DB_DEPTH_BASE 0 +#define R600_DB__DB_DEPTH_SIZE 1 +#define R600_DB__DB_DEPTH_VIEW 2 +#define R600_DB__DB_DEPTH_INFO 3 +#define R600_DB__DB_HTILE_SURFACE 4 +#define R600_DB__DB_PREFETCH_LIMIT 5 +#define R600_DB_SIZE 6 +#define R600_DB_PM4 128 + +/* R600_VGT */ +#define R600_VGT__VGT_PRIMITIVE_TYPE 0 +#define R600_VGT__VGT_MAX_VTX_INDX 1 +#define R600_VGT__VGT_MIN_VTX_INDX 2 +#define R600_VGT__VGT_INDX_OFFSET 3 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4 +#define R600_VGT__VGT_DMA_INDEX_TYPE 5 +#define R600_VGT__VGT_PRIMITIVEID_EN 6 +#define R600_VGT__VGT_DMA_NUM_INSTANCES 7 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10 +#define R600_VGT_SIZE 11 +#define R600_VGT_PM4 128 + +/* R600_DRAW */ +#define R600_DRAW__VGT_NUM_INDICES 0 +#define R600_DRAW__VGT_DMA_BASE_HI 1 +#define R600_DRAW__VGT_DMA_BASE 2 +#define R600_DRAW__VGT_DRAW_INITIATOR 3 +#define R600_DRAW_SIZE 4 +#define R600_DRAW_PM4 128 + +/* R600_VGT_EVENT */ +#define R600_VGT_EVENT__VGT_EVENT_INITIATOR 0 +#define R600_VGT_EVENT_SIZE 1 +#define R600_VGT_EVENT_PM4 128 + +/* R600_CB_FLUSH */ +#define R600_CB_FLUSH_SIZE 0 +#define R600_CB_FLUSH_PM4 128 + +/* R600_DB_FLUSH */ +#define R600_DB_FLUSH_SIZE 0 +#define R600_DB_FLUSH_PM4 128 + diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index b6698e3885c..37907ef0e9a 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -199,11 +199,6 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, struct r600_resource *resource; struct radeon_bo *bo = NULL; - bo = radeon_bo(rw, whandle->handle, 0, 0, NULL); - if (bo == NULL) { - return NULL; - } - /* Support only 2D textures without mipmaps */ if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || templ->depth0 != 1 || templ->last_level != 0) @@ -213,6 +208,12 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, if (rtex == NULL) return NULL; + bo = radeon_bo(rw, whandle->handle, 0, 0, NULL); + if (bo == NULL) { + FREE(rtex); + return NULL; + } + resource = &rtex->resource; resource->base.b = *templ; resource->base.vtbl = &r600_texture_vtbl; @@ -523,7 +524,7 @@ uint32_t r600_translate_texformat(enum pipe_format format, if (desc->channel[0].size == 5 && desc->channel[1].size == 6 && desc->channel[2].size == 5) { - result |= V_0280A0_COLOR_5_6_5; + result = V_0280A0_COLOR_5_6_5; goto out_word4; } goto out_unknown; @@ -532,14 +533,14 @@ uint32_t r600_translate_texformat(enum pipe_format format, desc->channel[1].size == 5 && desc->channel[2].size == 5 && desc->channel[3].size == 1) { - result |= V_0280A0_COLOR_1_5_5_5; + result = V_0280A0_COLOR_1_5_5_5; goto out_word4; } if (desc->channel[0].size == 10 && desc->channel[1].size == 10 && desc->channel[2].size == 10 && desc->channel[3].size == 2) { - result |= V_0280A0_COLOR_10_10_10_2; + result = V_0280A0_COLOR_10_10_10_2; goto out_word4; } goto out_unknown; @@ -560,36 +561,36 @@ uint32_t r600_translate_texformat(enum pipe_format format, case 4: switch (desc->nr_channels) { case 2: - result |= V_0280A0_COLOR_4_4; + result = V_0280A0_COLOR_4_4; goto out_word4; case 4: - result |= V_0280A0_COLOR_4_4_4_4; + result = V_0280A0_COLOR_4_4_4_4; goto out_word4; } goto out_unknown; case 8: switch (desc->nr_channels) { case 1: - result |= V_0280A0_COLOR_8; + result = V_0280A0_COLOR_8; goto out_word4; case 2: - result |= V_0280A0_COLOR_8_8; + result = V_0280A0_COLOR_8_8; goto out_word4; case 4: - result |= V_0280A0_COLOR_8_8_8_8; + result = V_0280A0_COLOR_8_8_8_8; goto out_word4; } goto out_unknown; case 16: switch (desc->nr_channels) { case 1: - result |= V_0280A0_COLOR_16; + result = V_0280A0_COLOR_16; goto out_word4; case 2: - result |= V_0280A0_COLOR_16_16; + result = V_0280A0_COLOR_16_16; goto out_word4; case 4: - result |= V_0280A0_COLOR_16_16_16_16; + result = V_0280A0_COLOR_16_16_16_16; goto out_word4; } } @@ -600,26 +601,26 @@ uint32_t r600_translate_texformat(enum pipe_format format, case 16: switch (desc->nr_channels) { case 1: - result |= V_0280A0_COLOR_16_FLOAT; + result = V_0280A0_COLOR_16_FLOAT; goto out_word4; case 2: - result |= V_0280A0_COLOR_16_16_FLOAT; + result = V_0280A0_COLOR_16_16_FLOAT; goto out_word4; case 4: - result |= V_0280A0_COLOR_16_16_16_16_FLOAT; + result = V_0280A0_COLOR_16_16_16_16_FLOAT; goto out_word4; } goto out_unknown; case 32: switch (desc->nr_channels) { case 1: - result |= V_0280A0_COLOR_32_FLOAT; + result = V_0280A0_COLOR_32_FLOAT; goto out_word4; case 2: - result |= V_0280A0_COLOR_32_32_FLOAT; + result = V_0280A0_COLOR_32_32_FLOAT; goto out_word4; case 4: - result |= V_0280A0_COLOR_32_32_32_32_FLOAT; + result = V_0280A0_COLOR_32_32_32_32_FLOAT; goto out_word4; } } diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index 7b9a983d53b..259927e5fa0 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -589,7 +589,14 @@ #define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0) #define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF) #define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00 +#define R_028D0C_DB_RENDER_CONTROL 0x028D0C +#define S_028D0C_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) +#define S_028D0C_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) +#define S_028D0C_R700_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 15) #define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define V_028D10_FORCE_OFF 0 +#define V_028D10_FORCE_ENABLE 1 +#define V_028D10_FORCE_DISABLE 2 #define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0) #define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3) #define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c index 1ebe20d6ab0..e754d733afc 100644 --- a/src/gallium/drivers/r600/r700_asm.c +++ b/src/gallium/drivers/r600/r700_asm.c @@ -26,41 +26,50 @@ #include "r700_sq.h" #include <stdio.h> + int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id) { unsigned i; + bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | + S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | + S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | + S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | + S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | + S_SQ_ALU_WORD0_SRC0_REL(alu->src[1].rel) | + S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | + S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | + S_SQ_ALU_WORD0_LAST(alu->last); + /* don't replace gpr by pv or ps for destination register */ if (alu->is_op3) { - bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | - S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | - S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | - S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | - S_SQ_ALU_WORD0_LAST(alu->last); bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | + S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | + S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | + S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) | - S_SQ_ALU_WORD1_BANK_SWIZZLE(0); + S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); } else { - bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | - S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | - S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | - S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | - S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | - S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | - S_SQ_ALU_WORD0_LAST(alu->last); bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | + S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | + S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) | S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) | - S_SQ_ALU_WORD1_BANK_SWIZZLE(0); + S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | + S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) | + S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate); } if (alu->last) { + if (alu->nliteral && !alu->literal_added) { + R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst); + } for (i = 0; i < alu->nliteral; i++) { bc->bytecode[id++] = alu->value[i]; } diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h index aaac8de5283..7991821ddab 100644 --- a/src/gallium/drivers/r600/radeon.h +++ b/src/gallium/drivers/r600/radeon.h @@ -194,6 +194,7 @@ enum r600_stype { R600_STATE_DSA, R600_STATE_SHADER, /* has PS,VS,GS,FS variants */ R600_STATE_CONSTANT, /* has PS,VS,GS,FS variants */ + R600_STATE_CBUF, /* has PS,VS,GS,FS variants */ R600_STATE_RESOURCE, /* has PS,VS,GS,FS variants */ R600_STATE_SAMPLER, /* has PS,VS,GS,FS variants */ R600_STATE_SAMPLER_BORDER, /* has PS,VS,GS,FS variants */ @@ -211,420 +212,14 @@ enum r600_stype { R600_STATE_UCP, R600_STATE_VGT, R600_STATE_DRAW, + R600_STATE_CB_FLUSH, + R600_STATE_DB_FLUSH, + R600_STATE_MAX, }; -/* R600_CONFIG */ -#define R600_CONFIG__SQ_CONFIG 0 -#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 -#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2 -#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3 -#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4 -#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5 -#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 -#define R600_CONFIG__TA_CNTL_AUX 7 -#define R600_CONFIG__VC_ENHANCE 8 -#define R600_CONFIG__DB_DEBUG 9 -#define R600_CONFIG__DB_WATERMARKS 10 -#define R600_CONFIG__SX_MISC 11 -#define R600_CONFIG__SPI_THREAD_GROUPING 12 -#define R600_CONFIG__CB_SHADER_CONTROL 13 -#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14 -#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15 -#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16 -#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17 -#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18 -#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19 -#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20 -#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21 -#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22 -#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23 -#define R600_CONFIG__VGT_HOS_CNTL 24 -#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25 -#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26 -#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27 -#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28 -#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29 -#define R600_CONFIG__VGT_GROUP_DECR 30 -#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31 -#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32 -#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33 -#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34 -#define R600_CONFIG__VGT_GS_MODE 35 -#define R600_CONFIG__PA_SC_MODE_CNTL 36 -#define R600_CONFIG__VGT_STRMOUT_EN 37 -#define R600_CONFIG__VGT_REUSE_OFF 38 -#define R600_CONFIG__VGT_VTX_CNT_EN 39 -#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40 -#define R600_CONFIG_SIZE 41 -#define R600_CONFIG_PM4 128 -/* R600_CB_CNTL */ -#define R600_CB_CNTL__CB_CLEAR_RED 0 -#define R600_CB_CNTL__CB_CLEAR_GREEN 1 -#define R600_CB_CNTL__CB_CLEAR_BLUE 2 -#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 -#define R600_CB_CNTL__CB_SHADER_MASK 4 -#define R600_CB_CNTL__CB_TARGET_MASK 5 -#define R600_CB_CNTL__CB_FOG_RED 6 -#define R600_CB_CNTL__CB_FOG_GREEN 7 -#define R600_CB_CNTL__CB_FOG_BLUE 8 -#define R600_CB_CNTL__CB_COLOR_CONTROL 9 -#define R600_CB_CNTL__PA_SC_AA_CONFIG 10 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12 -#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13 -#define R600_CB_CNTL__CB_CLRCMP_SRC 14 -#define R600_CB_CNTL__CB_CLRCMP_DST 15 -#define R600_CB_CNTL__CB_CLRCMP_MSK 16 -#define R600_CB_CNTL__PA_SC_AA_MASK 17 -#define R600_CB_CNTL_SIZE 18 -#define R600_CB_CNTL_PM4 128 -/* R600_RASTERIZER */ -#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0 -#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1 -#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2 -#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3 -#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4 -#define R600_RASTERIZER__PA_SU_POINT_SIZE 5 -#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6 -#define R600_RASTERIZER__PA_SU_LINE_CNTL 7 -#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8 -#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9 -#define R600_RASTERIZER__PA_SC_LINE_CNTL 10 -#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 -#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 -#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 -#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 -#define R600_RASTERIZER_SIZE 21 -#define R600_RASTERIZER_PM4 128 -/* R600_VIEWPORT */ -#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 -#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 -#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 -#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 -#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 -#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 -#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 -#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 -#define R600_VIEWPORT__PA_CL_VTE_CNTL 8 -#define R600_VIEWPORT_SIZE 9 -#define R600_VIEWPORT_PM4 128 -/* R600_SCISSOR */ -#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 -#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 -#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 -#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13 -#define R600_SCISSOR__PA_SC_EDGERULE 14 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 -#define R600_SCISSOR_SIZE 19 -#define R600_SCISSOR_PM4 128 -/* R600_BLEND */ -#define R600_BLEND__CB_BLEND_RED 0 -#define R600_BLEND__CB_BLEND_GREEN 1 -#define R600_BLEND__CB_BLEND_BLUE 2 -#define R600_BLEND__CB_BLEND_ALPHA 3 -#define R600_BLEND__CB_BLEND0_CONTROL 4 -#define R600_BLEND__CB_BLEND1_CONTROL 5 -#define R600_BLEND__CB_BLEND2_CONTROL 6 -#define R600_BLEND__CB_BLEND3_CONTROL 7 -#define R600_BLEND__CB_BLEND4_CONTROL 8 -#define R600_BLEND__CB_BLEND5_CONTROL 9 -#define R600_BLEND__CB_BLEND6_CONTROL 10 -#define R600_BLEND__CB_BLEND7_CONTROL 11 -#define R600_BLEND__CB_BLEND_CONTROL 12 -#define R600_BLEND_SIZE 13 -#define R600_BLEND_PM4 128 -/* R600_DSA */ -#define R600_DSA__DB_STENCIL_CLEAR 0 -#define R600_DSA__DB_DEPTH_CLEAR 1 -#define R600_DSA__SX_ALPHA_TEST_CONTROL 2 -#define R600_DSA__DB_STENCILREFMASK 3 -#define R600_DSA__DB_STENCILREFMASK_BF 4 -#define R600_DSA__SX_ALPHA_REF 5 -#define R600_DSA__SPI_FOG_FUNC_SCALE 6 -#define R600_DSA__SPI_FOG_FUNC_BIAS 7 -#define R600_DSA__SPI_FOG_CNTL 8 -#define R600_DSA__DB_DEPTH_CONTROL 9 -#define R600_DSA__DB_SHADER_CONTROL 10 -#define R600_DSA__DB_RENDER_CONTROL 11 -#define R600_DSA__DB_RENDER_OVERRIDE 12 -#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13 -#define R600_DSA__DB_PRELOAD_CONTROL 14 -#define R600_DSA__DB_ALPHA_TO_MASK 15 -#define R600_DSA_SIZE 16 -#define R600_DSA_PM4 128 -/* R600_VS_SHADER */ -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31 -#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32 -#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33 -#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34 -#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35 -#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36 -#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37 -#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38 -#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39 -#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40 -#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41 -#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42 -#define R600_VS_SHADER__SQ_PGM_START_VS 43 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44 -#define R600_VS_SHADER__SQ_PGM_START_FS 45 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48 -#define R600_VS_SHADER_SIZE 49 -#define R600_VS_SHADER_PM4 128 -/* R600_PS_SHADER */ -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33 -#define R600_PS_SHADER__SPI_INPUT_Z 34 -#define R600_PS_SHADER__SQ_PGM_START_PS 35 -#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36 -#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37 -#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38 -#define R600_PS_SHADER_SIZE 39 -#define R600_PS_SHADER_PM4 128 -/* R600_PS_CONSTANT */ -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3 -#define R600_PS_CONSTANT_SIZE 4 -#define R600_PS_CONSTANT_PM4 128 -/* R600_VS_CONSTANT */ -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3 -#define R600_VS_CONSTANT_SIZE 4 -#define R600_VS_CONSTANT_PM4 128 -/* R600_PS_RESOURCE */ -#define R600_PS_RESOURCE__RESOURCE0_WORD0 0 -#define R600_PS_RESOURCE__RESOURCE0_WORD1 1 -#define R600_PS_RESOURCE__RESOURCE0_WORD2 2 -#define R600_PS_RESOURCE__RESOURCE0_WORD3 3 -#define R600_PS_RESOURCE__RESOURCE0_WORD4 4 -#define R600_PS_RESOURCE__RESOURCE0_WORD5 5 -#define R600_PS_RESOURCE__RESOURCE0_WORD6 6 -#define R600_PS_RESOURCE_SIZE 7 -#define R600_PS_RESOURCE_PM4 128 -/* R600_VS_RESOURCE */ -#define R600_VS_RESOURCE__RESOURCE160_WORD0 0 -#define R600_VS_RESOURCE__RESOURCE160_WORD1 1 -#define R600_VS_RESOURCE__RESOURCE160_WORD2 2 -#define R600_VS_RESOURCE__RESOURCE160_WORD3 3 -#define R600_VS_RESOURCE__RESOURCE160_WORD4 4 -#define R600_VS_RESOURCE__RESOURCE160_WORD5 5 -#define R600_VS_RESOURCE__RESOURCE160_WORD6 6 -#define R600_VS_RESOURCE_SIZE 7 -#define R600_VS_RESOURCE_PM4 128 -/* R600_FS_RESOURCE */ -#define R600_FS_RESOURCE__RESOURCE320_WORD0 0 -#define R600_FS_RESOURCE__RESOURCE320_WORD1 1 -#define R600_FS_RESOURCE__RESOURCE320_WORD2 2 -#define R600_FS_RESOURCE__RESOURCE320_WORD3 3 -#define R600_FS_RESOURCE__RESOURCE320_WORD4 4 -#define R600_FS_RESOURCE__RESOURCE320_WORD5 5 -#define R600_FS_RESOURCE__RESOURCE320_WORD6 6 -#define R600_FS_RESOURCE_SIZE 7 -#define R600_FS_RESOURCE_PM4 128 -/* R600_GS_RESOURCE */ -#define R600_GS_RESOURCE__RESOURCE336_WORD0 0 -#define R600_GS_RESOURCE__RESOURCE336_WORD1 1 -#define R600_GS_RESOURCE__RESOURCE336_WORD2 2 -#define R600_GS_RESOURCE__RESOURCE336_WORD3 3 -#define R600_GS_RESOURCE__RESOURCE336_WORD4 4 -#define R600_GS_RESOURCE__RESOURCE336_WORD5 5 -#define R600_GS_RESOURCE__RESOURCE336_WORD6 6 -#define R600_GS_RESOURCE_SIZE 7 -#define R600_GS_RESOURCE_PM4 128 -/* R600_PS_SAMPLER */ -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 -#define R600_PS_SAMPLER_SIZE 3 -#define R600_PS_SAMPLER_PM4 128 -/* R600_VS_SAMPLER */ -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 -#define R600_VS_SAMPLER_SIZE 3 -#define R600_VS_SAMPLER_PM4 128 -/* R600_GS_SAMPLER */ -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 -#define R600_GS_SAMPLER_SIZE 3 -#define R600_GS_SAMPLER_PM4 128 -/* R600_PS_SAMPLER_BORDER */ -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 -#define R600_PS_SAMPLER_BORDER_SIZE 4 -#define R600_PS_SAMPLER_BORDER_PM4 128 -/* R600_VS_SAMPLER_BORDER */ -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 -#define R600_VS_SAMPLER_BORDER_SIZE 4 -#define R600_VS_SAMPLER_BORDER_PM4 128 -/* R600_GS_SAMPLER_BORDER */ -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 -#define R600_GS_SAMPLER_BORDER_SIZE 4 -#define R600_GS_SAMPLER_BORDER_PM4 128 -/* R600_CB0 */ -#define R600_CB0__CB_COLOR0_BASE 0 -#define R600_CB0__CB_COLOR0_INFO 1 -#define R600_CB0__CB_COLOR0_SIZE 2 -#define R600_CB0__CB_COLOR0_VIEW 3 -#define R600_CB0__CB_COLOR0_FRAG 4 -#define R600_CB0__CB_COLOR0_TILE 5 -#define R600_CB0__CB_COLOR0_MASK 6 -#define R600_CB0_SIZE 7 -#define R600_CB0_PM4 128 -/* R600_DB */ -#define R600_DB__DB_DEPTH_BASE 0 -#define R600_DB__DB_DEPTH_SIZE 1 -#define R600_DB__DB_DEPTH_VIEW 2 -#define R600_DB__DB_DEPTH_INFO 3 -#define R600_DB__DB_HTILE_SURFACE 4 -#define R600_DB__DB_PREFETCH_LIMIT 5 -#define R600_DB_SIZE 6 -#define R600_DB_PM4 128 -/* R600_VGT */ -#define R600_VGT__VGT_PRIMITIVE_TYPE 0 -#define R600_VGT__VGT_MAX_VTX_INDX 1 -#define R600_VGT__VGT_MIN_VTX_INDX 2 -#define R600_VGT__VGT_INDX_OFFSET 3 -#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4 -#define R600_VGT__VGT_DMA_INDEX_TYPE 5 -#define R600_VGT__VGT_PRIMITIVEID_EN 6 -#define R600_VGT__VGT_DMA_NUM_INSTANCES 7 -#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8 -#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9 -#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10 -#define R600_VGT_SIZE 11 -#define R600_VGT_PM4 128 -/* R600_DRAW */ -#define R600_DRAW__VGT_NUM_INDICES 0 -#define R600_DRAW__VGT_DMA_BASE_HI 1 -#define R600_DRAW__VGT_DMA_BASE 2 -#define R600_DRAW__VGT_DRAW_INITIATOR 3 -#define R600_DRAW_SIZE 4 -#define R600_DRAW_PM4 128 -/* R600_CLIP */ -#define R600_CLIP__PA_CL_UCP_X_0 0 -#define R600_CLIP__PA_CL_UCP_Y_0 1 -#define R600_CLIP__PA_CL_UCP_Z_0 2 -#define R600_CLIP__PA_CL_UCP_W_0 3 -#define R600_CLIP__PA_CL_UCP_X_1 4 -#define R600_CLIP__PA_CL_UCP_Y_1 5 -#define R600_CLIP__PA_CL_UCP_Z_1 6 -#define R600_CLIP__PA_CL_UCP_W_1 7 -#define R600_CLIP__PA_CL_UCP_X_2 8 -#define R600_CLIP__PA_CL_UCP_Y_2 9 -#define R600_CLIP__PA_CL_UCP_Z_2 10 -#define R600_CLIP__PA_CL_UCP_W_2 11 -#define R600_CLIP__PA_CL_UCP_X_3 12 -#define R600_CLIP__PA_CL_UCP_Y_3 13 -#define R600_CLIP__PA_CL_UCP_Z_3 14 -#define R600_CLIP__PA_CL_UCP_W_3 15 -#define R600_CLIP__PA_CL_UCP_X_4 16 -#define R600_CLIP__PA_CL_UCP_Y_4 17 -#define R600_CLIP__PA_CL_UCP_Z_4 18 -#define R600_CLIP__PA_CL_UCP_W_4 19 -#define R600_CLIP__PA_CL_UCP_X_5 20 -#define R600_CLIP__PA_CL_UCP_Y_5 21 -#define R600_CLIP__PA_CL_UCP_Z_5 22 -#define R600_CLIP__PA_CL_UCP_W_5 23 -#define R600_CLIP_SIZE 24 -#define R600_CLIP_PM4 128 +#include "r600_states_inc.h" +#include "eg_states_inc.h" + /* R600 QUERY BEGIN/END */ #define R600_QUERY__OFFSET 0 #define R600_QUERY_SIZE 1 diff --git a/src/gallium/drivers/rbug/rbug_screen.c b/src/gallium/drivers/rbug/rbug_screen.c index b9f32ee6a9b..961df482c29 100644 --- a/src/gallium/drivers/rbug/rbug_screen.c +++ b/src/gallium/drivers/rbug/rbug_screen.c @@ -79,6 +79,17 @@ rbug_screen_get_param(struct pipe_screen *_screen, param); } +static int +rbug_screen_get_shader_param(struct pipe_screen *_screen, + unsigned shader, enum pipe_shader_cap param) +{ + struct rbug_screen *rb_screen = rbug_screen(_screen); + struct pipe_screen *screen = rb_screen->screen; + + return screen->get_shader_param(screen, shader, + param); +} + static float rbug_screen_get_paramf(struct pipe_screen *_screen, enum pipe_cap param) @@ -317,6 +328,7 @@ rbug_screen_create(struct pipe_screen *screen) rb_screen->base.get_name = rbug_screen_get_name; rb_screen->base.get_vendor = rbug_screen_get_vendor; rb_screen->base.get_param = rbug_screen_get_param; + rb_screen->base.get_shader_param = rbug_screen_get_shader_param; rb_screen->base.get_paramf = rbug_screen_get_paramf; rb_screen->base.is_format_supported = rbug_screen_is_format_supported; rb_screen->base.context_create = rbug_screen_context_create; diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c index 73ae2dea561..2053d02f628 100644 --- a/src/gallium/drivers/softpipe/sp_screen.c +++ b/src/gallium/drivers/softpipe/sp_screen.c @@ -31,6 +31,7 @@ #include "util/u_format_s3tc.h" #include "pipe/p_defines.h" #include "pipe/p_screen.h" +#include "draw/draw_context.h" #include "state_tracker/sw_winsys.h" #include "tgsi/tgsi_exec.h" @@ -98,14 +99,8 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return SP_MAX_TEXTURE_3D_LEVELS; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return SP_MAX_TEXTURE_2D_LEVELS; - case PIPE_CAP_TGSI_CONT_SUPPORTED: - return 1; case PIPE_CAP_BLEND_EQUATION_SEPARATE: return 1; - case PIPE_CAP_MAX_CONST_BUFFERS: - return PIPE_MAX_CONSTANT_BUFFERS; - case PIPE_CAP_MAX_CONST_BUFFER_SIZE: - return 4096 * 4 * sizeof(float); case PIPE_CAP_INDEP_BLEND_ENABLE: return 1; case PIPE_CAP_INDEP_BLEND_FUNC: @@ -117,46 +112,27 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 1; case PIPE_CAP_STREAM_OUTPUT: return 1; - - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - /* There is no limit in number of instructions beyond available memory */ - return 32768; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - return TGSI_EXEC_MAX_NESTING; - case PIPE_CAP_MAX_VS_INPUTS: - case PIPE_CAP_MAX_FS_INPUTS: - return TGSI_EXEC_MAX_INPUT_ATTRIBS; - case PIPE_CAP_MAX_FS_CONSTS: - case PIPE_CAP_MAX_VS_CONSTS: - return TGSI_EXEC_MAX_CONST_BUFFER; - case PIPE_CAP_MAX_VS_TEMPS: - case PIPE_CAP_MAX_FS_TEMPS: - return TGSI_EXEC_NUM_TEMPS; - case PIPE_CAP_MAX_VS_ADDRS: - case PIPE_CAP_MAX_FS_ADDRS: - return TGSI_EXEC_NUM_ADDRS; - case PIPE_CAP_MAX_VS_PREDS: - case PIPE_CAP_MAX_FS_PREDS: - return TGSI_EXEC_NUM_PREDS; - case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: return 0; - - case PIPE_CAP_GEOMETRY_SHADER4: - return 1; default: return 0; } } +static int +softpipe_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + switch(shader) + { + case PIPE_SHADER_FRAGMENT: + return tgsi_exec_get_shader_param(param); + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_GEOMETRY: + return draw_get_shader_param(shader, param); + default: + return 0; + } +} static float softpipe_get_paramf(struct pipe_screen *screen, enum pipe_cap param) @@ -320,6 +296,7 @@ softpipe_create_screen(struct sw_winsys *winsys) screen->base.get_name = softpipe_get_name; screen->base.get_vendor = softpipe_get_vendor; screen->base.get_param = softpipe_get_param; + screen->base.get_shader_param = softpipe_get_shader_param; screen->base.get_paramf = softpipe_get_paramf; screen->base.is_format_supported = softpipe_is_format_supported; screen->base.context_create = softpipe_create_context; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index 077ff9a2cf6..b5fae94f783 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -180,57 +180,6 @@ svga_get_paramf(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; - /* - * Fragment shader limits - */ - - case PIPE_CAP_MAX_FS_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: - return svgascreen->use_ps30 ? 512 : 96; - case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: - return SVGA3D_MAX_NESTING_LEVEL; - case PIPE_CAP_MAX_FS_INPUTS: - return 10; - case PIPE_CAP_MAX_FS_CONSTS: - return svgascreen->use_vs30 ? 224 : 16; - case PIPE_CAP_MAX_FS_TEMPS: - if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, &result)) - return svgascreen->use_ps30 ? 32 : 12; - return result.u; - case PIPE_CAP_MAX_FS_ADDRS: - return svgascreen->use_ps30 ? 1 : 0; - case PIPE_CAP_MAX_FS_PREDS: - return svgascreen->use_ps30 ? 1 : 0; - - /* - * Vertex shader limits - */ - case PIPE_CAP_MAX_VS_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS: - if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS, &result)) - return svgascreen->use_vs30 ? 512 : 256; - return result.u; - case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS: - case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS: - /* XXX: until we have vertex texture support */ - return 0; - case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH: - return SVGA3D_MAX_NESTING_LEVEL; - case PIPE_CAP_MAX_VS_INPUTS: - return 16; - case PIPE_CAP_MAX_VS_CONSTS: - return 256; - case PIPE_CAP_MAX_VS_TEMPS: - if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, &result)) - return svgascreen->use_vs30 ? 32 : 12; - return result.u; - case PIPE_CAP_MAX_VS_ADDRS: - return svgascreen->use_vs30 ? 1 : 0; - case PIPE_CAP_MAX_VS_PREDS: - return svgascreen->use_vs30 ? 1 : 0; - case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: return 1; @@ -248,6 +197,81 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param) return (int) svga_get_paramf( screen, param ); } +static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) +{ + struct svga_screen *svgascreen = svga_screen(screen); + struct svga_winsys_screen *sws = svgascreen->sws; + SVGA3dDevCapResult result; + + switch (shader) + { + case PIPE_SHADER_FRAGMENT: + switch (param) + { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + return svgascreen->use_ps30 ? 512 : 96; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return SVGA3D_MAX_NESTING_LEVEL; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 10; + case PIPE_SHADER_CAP_MAX_CONSTS: + return svgascreen->use_ps30 ? 224 : 16; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, &result)) + return svgascreen->use_ps30 ? 32 : 12; + return result.u; + case PIPE_SHADER_CAP_MAX_ADDRS: + return svgascreen->use_ps30 ? 1 : 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return svgascreen->use_ps30 ? 1 : 0; + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + } + break; + case PIPE_SHADER_VERTEX: + switch (param) + { + case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: + if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS, &result)) + return svgascreen->use_vs30 ? 512 : 256; + return result.u; + case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: + case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: + /* XXX: until we have vertex texture support */ + return 0; + case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: + return SVGA3D_MAX_NESTING_LEVEL; + case PIPE_SHADER_CAP_MAX_INPUTS: + return 16; + case PIPE_SHADER_CAP_MAX_CONSTS: + return 256; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + return 1; + case PIPE_SHADER_CAP_MAX_TEMPS: + if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, &result)) + return svgascreen->use_vs30 ? 32 : 12; + return result.u; + case PIPE_SHADER_CAP_MAX_ADDRS: + return svgascreen->use_vs30 ? 1 : 0; + case PIPE_SHADER_CAP_MAX_PREDS: + return svgascreen->use_vs30 ? 1 : 0; + case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: + return 1; + default: + break; + } + break; + default: + break; + } + return 0; +} static INLINE SVGA3dDevCapIndex svga_translate_format_cap(enum pipe_format format) @@ -449,6 +473,7 @@ svga_screen_create(struct svga_winsys_screen *sws) screen->get_name = svga_get_name; screen->get_vendor = svga_get_vendor; screen->get_param = svga_get_param; + screen->get_shader_param = svga_get_shader_param; screen->get_paramf = svga_get_paramf; screen->is_format_supported = svga_is_format_supported; screen->context_create = svga_context_create; diff --git a/src/gallium/drivers/trace/tr_screen.c b/src/gallium/drivers/trace/tr_screen.c index 32e519a68a0..935831071e6 100644 --- a/src/gallium/drivers/trace/tr_screen.c +++ b/src/gallium/drivers/trace/tr_screen.c @@ -106,6 +106,30 @@ trace_screen_get_param(struct pipe_screen *_screen, } +static int +trace_screen_get_shader_param(struct pipe_screen *_screen, unsigned shader, + enum pipe_shader_cap param) +{ + struct trace_screen *tr_scr = trace_screen(_screen); + struct pipe_screen *screen = tr_scr->screen; + int result; + + trace_dump_call_begin("pipe_screen", "get_shader_param"); + + trace_dump_arg(ptr, screen); + trace_dump_arg(int, shader); + trace_dump_arg(int, param); + + result = screen->get_shader_param(screen, shader, param); + + trace_dump_ret(int, result); + + trace_dump_call_end(); + + return result; +} + + static float trace_screen_get_paramf(struct pipe_screen *_screen, enum pipe_cap param) @@ -547,6 +571,7 @@ trace_screen_create(struct pipe_screen *screen) tr_scr->base.get_name = trace_screen_get_name; tr_scr->base.get_vendor = trace_screen_get_vendor; tr_scr->base.get_param = trace_screen_get_param; + tr_scr->base.get_shader_param = trace_screen_get_shader_param; tr_scr->base.get_paramf = trace_screen_get_paramf; tr_scr->base.is_format_supported = trace_screen_is_format_supported; assert(screen->context_create); |