diff options
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/compiler.h | 24 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/disassemble.c | 104 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/helpers.h | 20 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_compile.c | 216 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_emit.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_ops.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_ra.c | 30 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c | 10 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_schedule.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/mir.c | 2 |
11 files changed, 213 insertions, 212 deletions
diff --git a/src/gallium/drivers/panfrost/midgard/compiler.h b/src/gallium/drivers/panfrost/midgard/compiler.h index 5692467c565..79fe7dfc78a 100644 --- a/src/gallium/drivers/panfrost/midgard/compiler.h +++ b/src/gallium/drivers/panfrost/midgard/compiler.h @@ -312,31 +312,31 @@ mir_next_op(struct midgard_instruction *ins) } #define mir_foreach_block(ctx, v) \ - list_for_each_entry(struct midgard_block, v, &ctx->blocks, link) + list_for_each_entry(struct midgard_block, v, &ctx->blocks, link) #define mir_foreach_block_from(ctx, from, v) \ list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link) #define mir_foreach_instr(ctx, v) \ - list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link) + list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link) #define mir_foreach_instr_safe(ctx, v) \ - list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link) + list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link) #define mir_foreach_instr_in_block(block, v) \ - list_for_each_entry(struct midgard_instruction, v, &block->instructions, link) + list_for_each_entry(struct midgard_instruction, v, &block->instructions, link) #define mir_foreach_instr_in_block_safe(block, v) \ - list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link) + list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link) #define mir_foreach_instr_in_block_safe_rev(block, v) \ - list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link) + list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link) #define mir_foreach_instr_in_block_from(block, v, from) \ - list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link) + list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link) #define mir_foreach_instr_in_block_from_rev(block, v, from) \ - list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link) + list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link) #define mir_foreach_bundle_in_block(block, v) \ util_dynarray_foreach(&block->bundles, midgard_bundle, v) @@ -443,10 +443,10 @@ void mir_create_pipeline_registers(compiler_context *ctx); /* Final emission */ void emit_binary_bundle( - compiler_context *ctx, - midgard_bundle *bundle, - struct util_dynarray *emission, - int next_tag); + compiler_context *ctx, + midgard_bundle *bundle, + struct util_dynarray *emission, + int next_tag); /* NIR stuff */ diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c b/src/gallium/drivers/panfrost/midgard/disassemble.c index f82f3497821..bed803162f3 100644 --- a/src/gallium/drivers/panfrost/midgard/disassemble.c +++ b/src/gallium/drivers/panfrost/midgard/disassemble.c @@ -49,21 +49,21 @@ static void print_tag_short(unsigned tag) { switch (midgard_word_types[tag]) { - case midgard_word_type_texture: - printf("tex/%X", tag); - break; + case midgard_word_type_texture: + printf("tex/%X", tag); + break; - case midgard_word_type_load_store: - printf("ldst"); - break; + case midgard_word_type_load_store: + printf("ldst"); + break; - case midgard_word_type_alu: - printf("alu%d/%X", midgard_word_size[tag], tag); - break; + case midgard_word_type_alu: + printf("alu%d/%X", midgard_word_size[tag], tag); + break; - default: - printf("%s%X", (tag > 0) ? "" : "unk", tag); - break; + default: + printf("%s%X", (tag > 0) ? "" : "unk", tag); + break; } } @@ -99,14 +99,14 @@ static char prefix_for_bits(unsigned bits) { switch (bits) { - case 8: - return 'q'; - case 16: - return 'h'; - case 64: - return 'd'; - default: - return 0; + case 8: + return 'q'; + case 16: + return 'h'; + case 64: + return 'd'; + default: + return 0; } } @@ -153,7 +153,7 @@ static void print_outmod(unsigned outmod, bool is_int) { printf("%s", is_int ? outmod_names_int[outmod] : - outmod_names_float[outmod]); + outmod_names_float[outmod]); } static void @@ -194,7 +194,7 @@ print_swizzle_helper_8(unsigned swizzle, bool upper) static void print_swizzle_vec16(unsigned swizzle, bool rep_high, bool rep_low, - midgard_dest_override override) + midgard_dest_override override) { printf("."); @@ -270,16 +270,16 @@ static int bits_for_mode(midgard_reg_mode mode) { switch (mode) { - case midgard_reg_mode_8: - return 8; - case midgard_reg_mode_16: - return 16; - case midgard_reg_mode_32: - return 32; - case midgard_reg_mode_64: - return 64; - default: - return 0; + case midgard_reg_mode_8: + return 8; + case midgard_reg_mode_16: + return 16; + case midgard_reg_mode_32: + return 32; + case midgard_reg_mode_64: + return 64; + default: + return 0; } } @@ -334,7 +334,7 @@ print_vector_src(unsigned src_binary, if (is_int && int_mod == midgard_int_shift) printf(") << %d", bits); else if ((is_int && (int_mod != midgard_int_normal)) - || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS)) + || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS)) printf(")"); } @@ -383,8 +383,8 @@ print_mask_vec16(uint8_t mask, midgard_dest_override override) for (unsigned i = 0; i < 8; i++) { if (mask & (1 << i)) printf("%c%c", - components[i*2 + 0], - components[i*2 + 1]); + components[i*2 + 0], + components[i*2 + 1]); } } else { bool upper = (override == midgard_dest_override_upper); @@ -493,7 +493,7 @@ print_vector_field(const char *name, uint16_t *words, uint16_t reg_word, /* Print the outmod, if there is one */ print_outmod(alu_field->outmod, - midgard_is_integer_out_op(alu_field->op)); + midgard_is_integer_out_op(alu_field->op)); printf(" "); @@ -512,7 +512,7 @@ print_vector_field(const char *name, uint16_t *words, uint16_t reg_word, else if (override == midgard_dest_override_upper) mask &= 0xF0; } else if (mode == midgard_reg_mode_16 - && override == midgard_dest_override_lower) { + && override == midgard_dest_override_lower) { /* stub */ } @@ -596,7 +596,7 @@ print_scalar_field(const char *name, uint16_t *words, uint16_t reg_word, printf("%s.", name); print_alu_opcode(alu_field->op); print_outmod(alu_field->outmod, - midgard_is_integer_out_op(alu_field->op)); + midgard_is_integer_out_op(alu_field->op)); printf(" "); bool full = alu_field->output_full; @@ -1087,14 +1087,14 @@ static char sampler_type_name(enum mali_sampler_type t) { switch (t) { - case MALI_SAMPLER_FLOAT: - return 'f'; - case MALI_SAMPLER_UNSIGNED: - return 'u'; - case MALI_SAMPLER_SIGNED: - return 'i'; - default: - return '?'; + case MALI_SAMPLER_FLOAT: + return 'f'; + case MALI_SAMPLER_UNSIGNED: + return 'u'; + case MALI_SAMPLER_SIGNED: + return 'i'; + default: + return '?'; } } @@ -1188,9 +1188,9 @@ print_texture_word(uint32_t *word, unsigned tabs) /* Regardless, just print the immediate offset */ printf(" + <%d, %d, %d>, ", - texture->offset_x, - texture->offset_y, - texture->offset_z); + texture->offset_x, + texture->offset_y, + texture->offset_z); } else { printf(", "); } @@ -1243,9 +1243,9 @@ print_texture_word(uint32_t *word, unsigned tabs) * following unknowns are zero, so we don't include them */ if (texture->unknown2 || - texture->unknown4 || - texture->unknownA || - texture->unknown8) { + texture->unknown4 || + texture->unknownA || + texture->unknown8) { printf("// unknown2 = 0x%x\n", texture->unknown2); printf("// unknown4 = 0x%x\n", texture->unknown4); printf("// unknownA = 0x%x\n", texture->unknownA); diff --git a/src/gallium/drivers/panfrost/midgard/helpers.h b/src/gallium/drivers/panfrost/midgard/helpers.h index 4a395a4c8cd..ef854dc60c1 100644 --- a/src/gallium/drivers/panfrost/midgard/helpers.h +++ b/src/gallium/drivers/panfrost/midgard/helpers.h @@ -163,16 +163,16 @@ static inline unsigned swizzle_of(unsigned comp) { switch (comp) { - case 1: - return SWIZZLE_XXXX; - case 2: - return SWIZZLE_XYXX; - case 3: - return SWIZZLE_XYZX; - case 4: - return SWIZZLE_XYZW; - default: - unreachable("Invalid component count"); + case 1: + return SWIZZLE_XXXX; + case 2: + return SWIZZLE_XYXX; + case 3: + return SWIZZLE_XYZX; + case 4: + return SWIZZLE_XYZW; + default: + unreachable("Invalid component count"); } } diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h b/src/gallium/drivers/panfrost/midgard/midgard.h index ab10b9b8cb1..5953214c599 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard.h +++ b/src/gallium/drivers/panfrost/midgard/midgard.h @@ -539,7 +539,8 @@ __attribute__((__packed__)) /* Padding to make this 8-bit */ unsigned zero : 3; -} midgard_tex_register_select; +} +midgard_tex_register_select; /* Texture pipeline results are in r28-r29 */ #define REG_TEX_BASE 28 diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c index a06318a5d93..9c1349094bd 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c @@ -52,10 +52,10 @@ #include "disassemble.h" static const struct debug_named_value debug_options[] = { - {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"}, - {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"}, + {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"}, + {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"}, {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"}, - DEBUG_NAMED_VALUE_END + DEBUG_NAMED_VALUE_END }; DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0) @@ -115,7 +115,7 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor) static midgard_vector_alu_src vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count, - bool half, bool sext) + bool half, bool sext) { if (!src) return blank_alu_src; @@ -146,8 +146,8 @@ vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count, if (half) { alu_src.mod = sext ? - midgard_int_sign_extend - : midgard_int_zero_extend; + midgard_int_sign_extend + : midgard_int_zero_extend; } /* These should have been lowered away */ @@ -272,9 +272,9 @@ midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu) nir_ssa_def *product = nir_fmul(b, src0, src1); - nir_ssa_def *sum = nir_fadd(b, - nir_channel(b, product, 0), - nir_channel(b, product, 1)); + nir_ssa_def *sum = nir_fadd(b, + nir_channel(b, product, 0), + nir_channel(b, product, 1)); /* Replace the fdot2 with this sum */ nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum)); @@ -324,10 +324,10 @@ static int sysval_for_instr(compiler_context *ctx, nir_instr *instr, break; sysval = PAN_SYSVAL(TEXTURE_SIZE, - PAN_TXS_SYSVAL_ID(tex->texture_index, - nir_tex_instr_dest_size(tex) - - (tex->is_array ? 1 : 0), - tex->is_array)); + PAN_TXS_SYSVAL_ID(tex->texture_index, + nir_tex_instr_dest_size(tex) - + (tex->is_array ? 1 : 0), + tex->is_array)); dst = &tex->dest; break; default: @@ -429,7 +429,7 @@ optimise_nir(nir_shader *nir) nir_lower_tex_options lower_tex_2nd_pass_options = { .lower_txs_lod = true, - }; + }; NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_1st_pass_options); NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_2nd_pass_options); @@ -729,16 +729,16 @@ reg_mode_for_nir(nir_alu_instr *instr) unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); switch (src_bitsize) { - case 8: - return midgard_reg_mode_8; - case 16: - return midgard_reg_mode_16; - case 32: - return midgard_reg_mode_32; - case 64: - return midgard_reg_mode_64; - default: - unreachable("Invalid bit size"); + case 8: + return midgard_reg_mode_8; + case 16: + return midgard_reg_mode_16; + case 32: + return midgard_reg_mode_32; + case 64: + return midgard_reg_mode_64; + default: + unreachable("Invalid bit size"); } } @@ -935,7 +935,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) reg_mode++; break; } - + /* For greater-or-equal, we lower to less-or-equal and flip the * arguments */ @@ -1159,11 +1159,11 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) static void emit_ubo_read( - compiler_context *ctx, - unsigned dest, - unsigned offset, - nir_src *indirect_offset, - unsigned index) + compiler_context *ctx, + unsigned dest, + unsigned offset, + nir_src *indirect_offset, + unsigned index) { /* TODO: half-floats */ @@ -1201,10 +1201,10 @@ emit_ubo_read( static void emit_varying_read( - compiler_context *ctx, - unsigned dest, unsigned offset, - unsigned nr_comp, unsigned component, - nir_src *indirect_offset, nir_alu_type type) + compiler_context *ctx, + unsigned dest, unsigned offset, + unsigned nr_comp, unsigned component, + nir_src *indirect_offset, nir_alu_type type) { /* XXX: Half-floats? */ /* TODO: swizzle, mask */ @@ -1234,19 +1234,19 @@ emit_varying_read( /* Use the type appropriate load */ switch (type) { - case nir_type_uint: - case nir_type_bool: - ins.load_store.op = midgard_op_ld_vary_32u; - break; - case nir_type_int: - ins.load_store.op = midgard_op_ld_vary_32i; - break; - case nir_type_float: - ins.load_store.op = midgard_op_ld_vary_32; - break; - default: - unreachable("Attempted to load unknown type"); - break; + case nir_type_uint: + case nir_type_bool: + ins.load_store.op = midgard_op_ld_vary_32u; + break; + case nir_type_int: + ins.load_store.op = midgard_op_ld_vary_32i; + break; + case nir_type_float: + ins.load_store.op = midgard_op_ld_vary_32; + break; + default: + unreachable("Attempted to load unknown type"); + break; } emit_mir_instruction(ctx, ins); @@ -1315,7 +1315,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) /* We may need to apply a fractional offset */ int component = instr->intrinsic == nir_intrinsic_load_input ? - nir_intrinsic_component(instr) : 0; + nir_intrinsic_component(instr) : 0; reg = nir_dest_index(ctx, &instr->dest); if (is_uniform && !ctx->is_blend) { @@ -1353,19 +1353,19 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) /* Use the type appropriate load */ switch (t) { - case nir_type_uint: - case nir_type_bool: - ins.load_store.op = midgard_op_ld_attr_32u; - break; - case nir_type_int: - ins.load_store.op = midgard_op_ld_attr_32i; - break; - case nir_type_float: - ins.load_store.op = midgard_op_ld_attr_32; - break; - default: - unreachable("Attempted to load unknown type"); - break; + case nir_type_uint: + case nir_type_bool: + ins.load_store.op = midgard_op_ld_attr_32u; + break; + case nir_type_int: + ins.load_store.op = midgard_op_ld_attr_32i; + break; + case nir_type_float: + ins.load_store.op = midgard_op_ld_attr_32; + break; + default: + unreachable("Attempted to load unknown type"); + break; } emit_mir_instruction(ctx, ins); @@ -1375,7 +1375,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) } break; - } + } /* Reads 128-bit value raw off the tilebuffer during blending, tasty */ @@ -1515,9 +1515,9 @@ midgard_tex_format(enum glsl_sampler_dim dim) static bool pan_attach_constant_bias( - compiler_context *ctx, - nir_src lod, - midgard_texture_word *word) + compiler_context *ctx, + nir_src lod, + midgard_texture_word *word) { /* To attach as constant, it has to *be* constant */ @@ -1544,23 +1544,23 @@ pan_attach_constant_bias( } static enum mali_sampler_type -midgard_sampler_type(nir_alu_type t) -{ - switch (nir_alu_type_get_base_type(t)) { - case nir_type_float: - return MALI_SAMPLER_FLOAT; - case nir_type_int: - return MALI_SAMPLER_SIGNED; - case nir_type_uint: - return MALI_SAMPLER_UNSIGNED; - default: - unreachable("Unknown sampler type"); +midgard_sampler_type(nir_alu_type t) { + switch (nir_alu_type_get_base_type(t)) + { + case nir_type_float: + return MALI_SAMPLER_FLOAT; + case nir_type_int: + return MALI_SAMPLER_SIGNED; + case nir_type_uint: + return MALI_SAMPLER_UNSIGNED; + default: + unreachable("Unknown sampler type"); } } static void emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, - unsigned midgard_texop) + unsigned midgard_texop) { /* TODO */ //assert (!instr->sampler); @@ -1699,7 +1699,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, ins.texture.bias = packed; break; - }; + }; default: unreachable("Unknown texture source type\n"); @@ -1746,7 +1746,7 @@ emit_tex(compiler_context *ctx, nir_tex_instr *instr) emit_sysval_read(ctx, &instr->instr); break; default: - unreachable("Unhanlded texture op"); + unreachable("Unhanlded texture op"); } } @@ -1754,20 +1754,20 @@ static void emit_jump(compiler_context *ctx, nir_jump_instr *instr) { switch (instr->type) { - case nir_jump_break: { - /* Emit a branch out of the loop */ - struct midgard_instruction br = v_branch(false, false); - br.branch.target_type = TARGET_BREAK; - br.branch.target_break = ctx->current_loop_depth; - emit_mir_instruction(ctx, br); - - DBG("break..\n"); - break; - } + case nir_jump_break: { + /* Emit a branch out of the loop */ + struct midgard_instruction br = v_branch(false, false); + br.branch.target_type = TARGET_BREAK; + br.branch.target_break = ctx->current_loop_depth; + emit_mir_instruction(ctx, br); + + DBG("break..\n"); + break; + } - default: - DBG("Unknown jump type %d\n", instr->type); - break; + default: + DBG("Unknown jump type %d\n", instr->type); + break; } } @@ -2549,7 +2549,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl { struct util_dynarray *compiled = &program->compiled; - midgard_debug = debug_get_option_midgard_debug(); + midgard_debug = debug_get_option_midgard_debug(); compiler_context ictx = { .nir = nir, @@ -2577,7 +2577,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl /* Record the varying mapping for the command stream's bookkeeping */ struct exec_list *varyings = - ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs; + ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs; unsigned max_varying = 0; nir_foreach_variable(var, varyings) { @@ -2613,9 +2613,9 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl optimise_nir(nir); - if (midgard_debug & MIDGARD_DBG_SHADERS) { - nir_print_shader(nir, stdout); - } + if (midgard_debug & MIDGARD_DBG_SHADERS) { + nir_print_shader(nir, stdout); + } /* Assign sysvals and counts, now that we're sure * (post-optimisation) */ @@ -2855,8 +2855,8 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl program->blend_patch_offset = ctx->blend_constant_offset; - if (midgard_debug & MIDGARD_DBG_SHADERS) - disassemble_midgard(program->compiled.data, program->compiled.size); + if (midgard_debug & MIDGARD_DBG_SHADERS) + disassemble_midgard(program->compiled.data, program->compiled.size); if (midgard_debug & MIDGARD_DBG_SHADERDB) { unsigned nr_bundles = 0, nr_ins = 0, nr_quadwords = 0; @@ -2869,7 +2869,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl mir_foreach_block(ctx, block) { nr_bundles += util_dynarray_num_elements( - &block->bundles, midgard_bundle); + &block->bundles, midgard_bundle); nr_quadwords += block->quadword_count; } @@ -2882,18 +2882,18 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl unsigned nr_threads = (nr_registers <= 4) ? 4 : (nr_registers <= 8) ? 2 : - 1; + 1; /* Dump stats */ fprintf(stderr, "shader%d - %s shader: " - "%u inst, %u bundles, %u quadwords, " - "%u registers, %u threads, %u loops\n", - SHADER_DB_COUNT++, - gl_shader_stage_name(ctx->stage), - nr_ins, nr_bundles, nr_quadwords, - nr_registers, nr_threads, - ctx->loop_count); + "%u inst, %u bundles, %u quadwords, " + "%u registers, %u threads, %u loops\n", + SHADER_DB_COUNT++, + gl_shader_stage_name(ctx->stage), + nr_ins, nr_bundles, nr_quadwords, + nr_registers, nr_threads, + ctx->loop_count); } diff --git a/src/gallium/drivers/panfrost/midgard/midgard_emit.c b/src/gallium/drivers/panfrost/midgard/midgard_emit.c index f5d2d7212b3..3522e77d5b1 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_emit.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_emit.c @@ -198,9 +198,9 @@ emit_alu_bundle(compiler_context *ctx, void emit_binary_bundle(compiler_context *ctx, - midgard_bundle *bundle, - struct util_dynarray *emission, - int next_tag) + midgard_bundle *bundle, + struct util_dynarray *emission, + int next_tag) { int lookahead = next_tag << 4; diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ops.c b/src/gallium/drivers/panfrost/midgard/midgard_ops.c index d1e9b27a393..ccd750cff83 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_ops.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_ops.c @@ -122,7 +122,7 @@ struct mir_op_props alu_opcode_props[256] = { [midgard_alu_op_fcos] = {"fcos", UNIT_VLUT}, /* XXX: Test case where it's right on smul but not sadd */ - [midgard_alu_op_iand] = {"iand", UNITS_MOST | OP_COMMUTES}, + [midgard_alu_op_iand] = {"iand", UNITS_MOST | OP_COMMUTES}, [midgard_alu_op_iandnot] = {"iandnot", UNITS_MOST}, [midgard_alu_op_ior] = {"ior", UNITS_MOST | OP_COMMUTES}, @@ -145,7 +145,7 @@ struct mir_op_props alu_opcode_props[256] = { [midgard_alu_op_ibany_neq] = {"ibany_neq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES}, /* These instructions are not yet emitted by the compiler, so - * don't speculate about units yet */ + * don't speculate about units yet */ [midgard_alu_op_ishladd] = {"ishladd", 0}, [midgard_alu_op_uball_lt] = {"uball_lt", 0}, diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra.c b/src/gallium/drivers/panfrost/midgard/midgard_ra.c index 9dae43dfff0..cfe091326ed 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_ra.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_ra.c @@ -49,8 +49,8 @@ static unsigned reg_type_to_mask[WORK_STRIDE] = { 0xF, /* xyzw */ 0x7, 0x7 << 1, /* xyz */ - 0x3, 0x3 << 1, 0x3 << 2, /* xy */ - 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */ + 0x3, 0x3 << 1, 0x3 << 2, /* xy */ + 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */ }; static unsigned reg_type_to_swizzle[WORK_STRIDE] = { @@ -123,7 +123,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash) return hash; unsigned temp = (uintptr_t) _mesa_hash_table_u64_search( - ctx->hash_to_temp, hash + 1); + ctx->hash_to_temp, hash + 1); if (temp) return temp - 1; @@ -133,7 +133,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash) ctx->max_hash = MAX2(ctx->max_hash, hash); _mesa_hash_table_u64_insert(ctx->hash_to_temp, - hash + 1, (void *) ((uintptr_t) temp + 1)); + hash + 1, (void *) ((uintptr_t) temp + 1)); return temp; } @@ -251,7 +251,7 @@ allocate_registers(compiler_context *ctx) if (mask1 & mask2) ra_add_reg_conflict(regs, - base + a, base + b); + base + a, base + b); } } } @@ -408,9 +408,9 @@ allocate_registers(compiler_context *ctx) static void install_registers_instr( - compiler_context *ctx, - struct ra_graph *g, - midgard_instruction *ins) + compiler_context *ctx, + struct ra_graph *g, + midgard_instruction *ins) { ssa_args args = ins->ssa_args; @@ -421,7 +421,7 @@ install_registers_instr( struct phys_reg src2 = index_to_reg(ctx, g, adjusted_src); struct phys_reg dest = index_to_reg(ctx, g, args.dest); - unsigned uncomposed_mask = ins->mask; + unsigned uncomposed_mask = ins->mask; ins->mask = compose_writemask(uncomposed_mask, dest); /* Adjust the dest mask if necessary. Mostly this is a no-op @@ -445,14 +445,14 @@ install_registers_instr( int lower_11 = ins->inline_constant & ((1 << 12) - 1); uint16_t imm = ((lower_11 >> 8) & 0x7) | - ((lower_11 & 0xFF) << 3); + ((lower_11 & 0xFF) << 3); ins->alu.src2 = imm << 2; } else { midgard_vector_alu_src mod2 = vector_alu_from_unsigned(ins->alu.src2); mod2.swizzle = compose_swizzle( - mod2.swizzle, uncomposed_mask, src2, dest); + mod2.swizzle, uncomposed_mask, src2, dest); ins->alu.src2 = vector_alu_srco_unsigned(mod2); ins->registers.src2_reg = src2.reg; @@ -472,17 +472,17 @@ install_registers_instr( * logical dataflow */ unsigned r = OP_IS_STORE(ins->load_store.op) ? - args.src0 : args.dest; + args.src0 : args.dest; struct phys_reg src = index_to_reg(ctx, g, r); ins->load_store.reg = src.reg; ins->load_store.swizzle = compose_swizzle( - ins->load_store.swizzle, 0xF, - default_phys_reg(0), src); + ins->load_store.swizzle, 0xF, + default_phys_reg(0), src); ins->mask = compose_writemask( - ins->mask, src); + ins->mask, src); } break; diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c b/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c index 6622c2bc534..cd64bdf29e5 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c @@ -40,10 +40,10 @@ static bool mir_pipeline_ins( - compiler_context *ctx, - midgard_block *block, - midgard_bundle *bundle, unsigned i, - unsigned pipeline_count) + compiler_context *ctx, + midgard_block *block, + midgard_bundle *bundle, unsigned i, + unsigned pipeline_count) { midgard_instruction *ins = bundle->instructions[i]; unsigned dest = ins->ssa_args.dest; @@ -68,7 +68,7 @@ mir_pipeline_ins( * we're live after the last instruction of the bundle */ midgard_instruction *end = bundle->instructions[ - bundle->instruction_count - 1]; + bundle->instruction_count - 1]; if (mir_is_live_after(ctx, block, end, ins->ssa_args.dest)) return false; diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c index f4156d6b730..7a3841e4d44 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c @@ -105,8 +105,8 @@ can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second) static bool midgard_has_hazard( - midgard_instruction **segment, unsigned segment_size, - midgard_instruction *ains) + midgard_instruction **segment, unsigned segment_size, + midgard_instruction *ains) { for (int s = 0; s < segment_size; ++s) if (!can_run_concurrent_ssa(segment[s], ains)) @@ -228,7 +228,7 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction assert(units & UNITS_SCALAR); if (!scalar) { - if (last_unit >= UNIT_VADD) { + if (last_unit >= UNIT_VADD) { if (units & UNIT_VLUT) unit = UNIT_VLUT; else diff --git a/src/gallium/drivers/panfrost/midgard/mir.c b/src/gallium/drivers/panfrost/midgard/mir.c index 263aafadec0..6adc1350c0a 100644 --- a/src/gallium/drivers/panfrost/midgard/mir.c +++ b/src/gallium/drivers/panfrost/midgard/mir.c @@ -31,7 +31,7 @@ mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new) ins->ssa_args.src0 = new; if (ins->ssa_args.src1 == old && - !ins->ssa_args.inline_constant) + !ins->ssa_args.inline_constant) ins->ssa_args.src1 = new; } } |