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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c8
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h4
2 files changed, 5 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 877f5552bd5..77e9becda6a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -193,8 +193,8 @@ static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
/* Each texture is an array of slices. Each slice is an array
* of mipmap levels. */
return box->z * rtex->surface.u.gfx9.surf_slice_size +
- ((rtex->surface.u.gfx9.surf_ymip_offset[level] +
- box->y / rtex->surface.blk_h) *
+ rtex->surface.u.gfx9.offset[level] +
+ (box->y / rtex->surface.blk_h *
rtex->surface.u.gfx9.surf_pitch +
box->x / rtex->surface.blk_w) * rtex->surface.bpe;
} else {
@@ -1623,9 +1623,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
* Use the staging texture for uploads if the underlying BO
* is busy.
*/
- /* TODO: Linear CPU mipmap addressing is broken on GFX9: */
- if (!rtex->surface.is_linear ||
- (rctx->chip_class == GFX9 && level))
+ if (!rtex->surface.is_linear)
use_staging_texture = true;
else if (usage & PIPE_TRANSFER_READ)
use_staging_texture =
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 43f74f653e4..a19ece6634d 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -364,8 +364,8 @@ struct gfx9_surf_layout {
uint64_t surf_slice_size;
uint16_t surf_pitch; /* in blocks */
uint16_t surf_height;
- /* Y mipmap level offset in blocks. Only valid for LINEAR. */
- uint16_t surf_ymip_offset[RADEON_SURF_MAX_LEVELS];
+ /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
+ uint32_t offset[RADEON_SURF_MAX_LEVELS];
uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */