diff options
Diffstat (limited to 'src/gallium/drivers')
30 files changed, 236 insertions, 1144 deletions
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index b6919a5c6d3..21e8012d46a 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -151,7 +151,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_INDEP_BLEND_ENABLE: return 1; case PIPE_CAP_INDEP_BLEND_FUNC: - return 0; + return 1; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 1; diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c index 5d83a1e3579..7b7b2721ba8 100644 --- a/src/gallium/drivers/llvmpipe/lp_setup.c +++ b/src/gallium/drivers/llvmpipe/lp_setup.c @@ -1064,6 +1064,8 @@ lp_setup_begin_query(struct lp_setup_context *setup, { /* init the query to its beginning state */ assert(setup->active_query == NULL); + + set_scene_state(setup, SETUP_ACTIVE, "begin_query"); if (setup->scene) { if (!lp_scene_bin_everywhere(setup->scene, @@ -1093,6 +1095,8 @@ lp_setup_end_query(struct lp_setup_context *setup, struct llvmpipe_query *pq) { union lp_rast_cmd_arg dummy = { 0 }; + set_scene_state(setup, SETUP_ACTIVE, "end_query"); + assert(setup->active_query == pq); setup->active_query = NULL; diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c index 1b9119eda00..6243a96f454 100644 --- a/src/gallium/drivers/llvmpipe/lp_state_fs.c +++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c @@ -546,6 +546,7 @@ generate_fragment(struct llvmpipe_context *lp, unsigned i; unsigned chan; unsigned cbuf; + boolean cbuf0_write_all; /* Adjust color input interpolation according to flatshade state: */ @@ -559,6 +560,15 @@ generate_fragment(struct llvmpipe_context *lp, } } + /* check if writes to cbuf[0] are to be copied to all cbufs */ + cbuf0_write_all = FALSE; + for (i = 0;i < shader->info.base.num_properties; i++) { + if (shader->info.base.properties[i].name == + TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) { + cbuf0_write_all = TRUE; + break; + } + } /* TODO: actually pick these based on the fs and color buffer * characteristics. */ @@ -697,9 +707,10 @@ generate_fragment(struct llvmpipe_context *lp, mask_input, counter); - for(cbuf = 0; cbuf < key->nr_cbufs; cbuf++) - for(chan = 0; chan < NUM_CHANNELS; ++chan) - fs_out_color[cbuf][chan][i] = out_color[cbuf][chan]; + for (cbuf = 0; cbuf < key->nr_cbufs; cbuf++) + for (chan = 0; chan < NUM_CHANNELS; ++chan) + fs_out_color[cbuf][chan][i] = + out_color[cbuf * !cbuf0_write_all][chan]; } sampler->destroy(sampler); diff --git a/src/gallium/drivers/nouveau/Makefile b/src/gallium/drivers/nouveau/Makefile index db591b756c4..a33bf5ebc28 100644 --- a/src/gallium/drivers/nouveau/Makefile +++ b/src/gallium/drivers/nouveau/Makefile @@ -4,6 +4,7 @@ include $(TOP)/configs/current LIBNAME = nouveau LIBRARY_INCLUDES = \ + $(LIBDRM_CFLAGS) \ -I$(TOP)/src/gallium/drivers/nouveau/include C_SOURCES = nouveau_screen.c diff --git a/src/gallium/drivers/nv50/Makefile b/src/gallium/drivers/nv50/Makefile index bf1e8201a08..b3535c0976e 100644 --- a/src/gallium/drivers/nv50/Makefile +++ b/src/gallium/drivers/nv50/Makefile @@ -29,4 +29,7 @@ C_SOURCES = \ nv50_pc_optimize.c \ nv50_pc_regalloc.c +LIBRARY_INCLUDES = \ + $(LIBDRM_CFLAGS) + include ../../Makefile.template diff --git a/src/gallium/drivers/nvc0/Makefile b/src/gallium/drivers/nvc0/Makefile index da8f9a2ab4d..54f1ab7fa93 100644 --- a/src/gallium/drivers/nvc0/Makefile +++ b/src/gallium/drivers/nvc0/Makefile @@ -31,4 +31,7 @@ C_SOURCES = \ nvc0_mm.c \ nvc0_query.c +LIBRARY_INCLUDES = \ + $(LIBDRM_CFLAGS) + include ../../Makefile.template diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nvc0/nvc0_3d.xml.h index 31302949d5e..61932ff2b6a 100644 --- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h +++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h @@ -843,7 +843,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES_ADJACENCY 0x0000000c #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLE_STRIP_ADJACENCY 0x0000000d #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_PATCHES 0x0000000e -#define NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT 0x10000000 +#define NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT 0x04000000 +#define NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_CONT 0x08000000 #define NVC0_3D_VERTEX_DATA 0x00001640 diff --git a/src/gallium/drivers/nvc0/nvc0_context.h b/src/gallium/drivers/nvc0/nvc0_context.h index eeb5beff7a7..94117988e50 100644 --- a/src/gallium/drivers/nvc0/nvc0_context.h +++ b/src/gallium/drivers/nvc0/nvc0_context.h @@ -71,7 +71,7 @@ struct nvc0_context { uint32_t dirty; struct { - uint32_t instance_bits; + uint32_t instance_elts; /* bitmask of per-instance elements */ uint32_t instance_base; int32_t index_bias; boolean prim_restart; diff --git a/src/gallium/drivers/nvc0/nvc0_program.c b/src/gallium/drivers/nvc0/nvc0_program.c index 57a0874e679..aefaf7b98ad 100644 --- a/src/gallium/drivers/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nvc0/nvc0_program.c @@ -132,15 +132,17 @@ nvc0_indirect_outputs(struct nvc0_translation_info *ti, int id) } static INLINE unsigned -nvc0_system_value_location(unsigned sn, unsigned si) +nvc0_system_value_location(unsigned sn, unsigned si, boolean *is_input) { /* NOTE: locations 0xfxx indicate special regs */ switch (sn) { /* case TGSI_SEMANTIC_VERTEXID: + *is_input = TRUE; return 0x2fc; */ case TGSI_SEMANTIC_PRIMID: + *is_input = TRUE; return 0x60; /* case TGSI_SEMANTIC_LAYER_INDEX: @@ -149,8 +151,10 @@ nvc0_system_value_location(unsigned sn, unsigned si) return 0x68; */ case TGSI_SEMANTIC_INSTANCEID: + *is_input = TRUE; return 0x2f8; case TGSI_SEMANTIC_FACE: + *is_input = TRUE; return 0x3fc; /* case TGSI_SEMANTIC_INVOCATIONID: @@ -281,7 +285,7 @@ prog_decl(struct nvc0_translation_info *ti, } break; case TGSI_FILE_SYSTEM_VALUE: - ti->sysval_loc[i] = nvc0_system_value_location(sn, si); + ti->sysval_loc[i] = nvc0_system_value_location(sn, si, &ti->sysval_in[i]); assert(first == last); break; case TGSI_FILE_NULL: @@ -414,6 +418,12 @@ nvc0_vp_gp_gen_header(struct nvc0_program *vp, struct nvc0_translation_info *ti) } } + for (i = 0; i < TGSI_SEMANTIC_COUNT; ++i) { + a = ti->sysval_loc[i] / 4; + if (a > 0 && a < (0xf00 / 4)) + vp->hdr[(ti->sysval_in[i] ? 5 : 13) + a / 32] |= 1 << (a % 32); + } + return 0; } @@ -520,6 +530,12 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nvc0_translation_info *ti) fp->hdr[18] |= 0xf << ti->output_loc[i][0]; } + for (i = 0; i < TGSI_SEMANTIC_COUNT; ++i) { + a = ti->sysval_loc[i] / 2; + if ((a > 0) && (a < 0xf00 / 2)) + fp->hdr[4 + a / 32] |= NVC0_INTERP_FLAT << (a % 32); + } + return 0; } diff --git a/src/gallium/drivers/nvc0/nvc0_program.h b/src/gallium/drivers/nvc0/nvc0_program.h index 2e84caecc9e..e6b210d1355 100644 --- a/src/gallium/drivers/nvc0/nvc0_program.h +++ b/src/gallium/drivers/nvc0/nvc0_program.h @@ -63,6 +63,7 @@ struct nvc0_translation_info { uint16_t input_loc[PIPE_MAX_SHADER_INPUTS][4]; uint16_t output_loc[PIPE_MAX_SHADER_OUTPUTS][4]; uint16_t sysval_loc[TGSI_SEMANTIC_COUNT]; + boolean sysval_in[TGSI_SEMANTIC_COUNT]; int input_access[PIPE_MAX_SHADER_INPUTS][4]; int output_access[PIPE_MAX_SHADER_OUTPUTS][4]; ubyte interp_mode[PIPE_MAX_SHADER_INPUTS]; diff --git a/src/gallium/drivers/nvc0/nvc0_push.c b/src/gallium/drivers/nvc0/nvc0_push.c index 941be678586..74c3451c19a 100644 --- a/src/gallium/drivers/nvc0/nvc0_push.c +++ b/src/gallium/drivers/nvc0/nvc0_push.c @@ -26,6 +26,7 @@ struct push_context { boolean primitive_restart; uint32_t prim; uint32_t restart_index; + uint32_t instance_id; }; static INLINE unsigned @@ -75,7 +76,8 @@ emit_vertices_i08(struct push_context *ctx, unsigned start, unsigned count) BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size); - ctx->translate->run_elts8(ctx->translate, elts, nr, 0, ctx->chan->cur); + ctx->translate->run_elts8(ctx->translate, elts, nr, ctx->instance_id, + ctx->chan->cur); ctx->chan->cur += size; count -= nr; @@ -86,7 +88,8 @@ emit_vertices_i08(struct push_context *ctx, unsigned start, unsigned count) elts++; BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2); OUT_RING (ctx->chan, 0); - OUT_RING (ctx->chan, ctx->prim); + OUT_RING (ctx->chan, NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_CONT | + (ctx->prim & ~NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT)); } } } @@ -108,7 +111,8 @@ emit_vertices_i16(struct push_context *ctx, unsigned start, unsigned count) BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size); - ctx->translate->run_elts16(ctx->translate, elts, nr, 0, ctx->chan->cur); + ctx->translate->run_elts16(ctx->translate, elts, nr, ctx->instance_id, + ctx->chan->cur); ctx->chan->cur += size; count -= nr; @@ -119,7 +123,8 @@ emit_vertices_i16(struct push_context *ctx, unsigned start, unsigned count) elts++; BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2); OUT_RING (ctx->chan, 0); - OUT_RING (ctx->chan, ctx->prim); + OUT_RING (ctx->chan, NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_CONT | + (ctx->prim & ~NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT)); } } } @@ -141,7 +146,8 @@ emit_vertices_i32(struct push_context *ctx, unsigned start, unsigned count) BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size); - ctx->translate->run_elts(ctx->translate, elts, nr, 0, ctx->chan->cur); + ctx->translate->run_elts(ctx->translate, elts, nr, ctx->instance_id, + ctx->chan->cur); ctx->chan->cur += size; count -= nr; @@ -152,7 +158,8 @@ emit_vertices_i32(struct push_context *ctx, unsigned start, unsigned count) elts++; BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2); OUT_RING (ctx->chan, 0); - OUT_RING (ctx->chan, ctx->prim); + OUT_RING (ctx->chan, NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_CONT | + (ctx->prim & ~NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT)); } } } @@ -166,7 +173,8 @@ emit_vertices_seq(struct push_context *ctx, unsigned start, unsigned count) BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size); - ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur); + ctx->translate->run(ctx->translate, start, push, ctx->instance_id, + ctx->chan->cur); ctx->chan->cur += size; count -= push; start += push; @@ -244,6 +252,7 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) ctx.restart_index = 0; } + ctx.instance_id = info->start_instance; ctx.prim = nvc0_prim_gl(info->mode); while (inst--) { @@ -268,6 +277,7 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) } IMMED_RING(ctx.chan, RING_3D(VERTEX_END_GL), 0); + ctx.instance_id++; ctx.prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; } diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 54eec660b2a..f608b32e1cb 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -110,6 +110,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SHADER_STENCIL_EXPORT: return 0; case PIPE_CAP_PRIMITIVE_RESTART: + case PIPE_CAP_INSTANCED_DRAWING: return 1; default: NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); diff --git a/src/gallium/drivers/nvc0/nvc0_stateobj.h b/src/gallium/drivers/nvc0/nvc0_stateobj.h index ee788c5bb9c..6c8028aba13 100644 --- a/src/gallium/drivers/nvc0/nvc0_stateobj.h +++ b/src/gallium/drivers/nvc0/nvc0_stateobj.h @@ -65,7 +65,8 @@ struct nvc0_vertex_element { struct nvc0_vertex_stateobj { struct translate *translate; unsigned num_elements; - uint32_t instance_bits; + uint32_t instance_elts; + uint32_t instance_bufs; unsigned vtx_size; unsigned vtx_per_packet_max; struct nvc0_vertex_element element[1]; diff --git a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c index fecfc76fb79..950bee2eda4 100644 --- a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c +++ b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c @@ -1085,6 +1085,20 @@ emit_fetch(struct bld_context *bld, const struct tgsi_full_instruction *insn, case TGSI_FILE_PREDICATE: res = bld_fetch_global(bld, &bld->pvs[idx][swz]); break; + case TGSI_FILE_SYSTEM_VALUE: + assert(bld->ti->sysval_loc[idx] < 0xf00); /* >= would mean special reg */ + res = new_value(bld->pc, + bld->pc->is_fragprog ? NV_FILE_MEM_V : NV_FILE_MEM_A, 4); + res->reg.address = bld->ti->sysval_loc[idx]; + + if (res->reg.file == NV_FILE_MEM_A) + res = bld_insn_1(bld, NV_OP_VFETCH, res); + else + res = bld_interp(bld, NVC0_INTERP_FLAT, res); + + /* mesa doesn't do real integers yet :-(and in GL this should be S32) */ + res = bld_cvt(bld, NV_TYPE_F32, NV_TYPE_U32, res); + break; default: NOUVEAU_ERR("illegal/unhandled src reg file: %d\n", src->Register.File); abort(); diff --git a/src/gallium/drivers/nvc0/nvc0_vbo.c b/src/gallium/drivers/nvc0/nvc0_vbo.c index a14e9557382..a51a887ed89 100644 --- a/src/gallium/drivers/nvc0/nvc0_vbo.c +++ b/src/gallium/drivers/nvc0/nvc0_vbo.c @@ -58,7 +58,8 @@ nvc0_vertex_state_create(struct pipe_context *pipe, if (!so) return NULL; so->num_elements = num_elements; - so->instance_bits = 0; + so->instance_elts = 0; + so->instance_bufs = 0; transkey.nr_elements = 0; transkey.output_stride = 0; @@ -85,7 +86,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe, } so->element[i].state |= i; - if (likely(!ve->instance_divisor)) { + if (1) { unsigned j = transkey.nr_elements++; transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL; @@ -97,8 +98,11 @@ nvc0_vertex_state_create(struct pipe_context *pipe, transkey.element[j].output_format = fmt; transkey.element[j].output_offset = transkey.output_stride; transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3; - } else { - so->instance_bits |= 1 << i; + + if (unlikely(ve->instance_divisor)) { + so->instance_elts |= 1 << i; + so->instance_bufs |= 1 << vbi; + } } } @@ -141,6 +145,22 @@ nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb, OUT_RINGf(chan, v[i]); } +static INLINE void +nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi, + uint32_t *base, uint32_t *size) +{ + if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) { + /* TODO: use min and max instance divisor to get a proper range */ + *base = 0; + *size = (nvc0->vtxbuf[vbi].max_index + 1) * nvc0->vtxbuf[vbi].stride; + } else { + assert(nvc0->vbo_max_index != ~0); + *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride; + *size = (nvc0->vbo_max_index - + nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride; + } +} + static void nvc0_prevalidate_vbufs(struct nvc0_context *nvc0) { @@ -165,9 +185,7 @@ nvc0_prevalidate_vbufs(struct nvc0_context *nvc0) if (buf->status & NVC0_BUFFER_STATUS_USER_MEMORY) { nvc0->vbo_user |= 1 << i; assert(vb->stride > vb->buffer_offset); - size = vb->stride * (nvc0->vbo_max_index - - nvc0->vbo_min_index + 1); - base = vb->stride * nvc0->vbo_min_index; + nvc0_vbuf_range(nvc0, i, &base, &size); nvc0_user_buffer_upload(buf, base, size); } else { nvc0_buffer_migrate(nvc0, buf, NOUVEAU_BO_GART); @@ -184,7 +202,6 @@ static void nvc0_update_user_vbufs(struct nvc0_context *nvc0) { struct nouveau_channel *chan = nvc0->screen->base.channel; - const uint32_t vertex_count = nvc0->vbo_max_index - nvc0->vbo_min_index + 1; uint32_t base, offset, size; int i; uint32_t written = 0; @@ -202,8 +219,7 @@ nvc0_update_user_vbufs(struct nvc0_context *nvc0) nvc0_emit_vtxattr(nvc0, vb, ve, i); continue; } - size = vb->stride * vertex_count; - base = vb->stride * nvc0->vbo_min_index; + nvc0_vbuf_range(nvc0, b, &base, &size); if (!(written & (1 << b))) { written |= 1 << b; @@ -253,13 +269,13 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0) vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index]; if (unlikely(ve->pipe.instance_divisor)) { - if (!(nvc0->state.instance_bits & (1 << i))) { + if (!(nvc0->state.instance_elts & (1 << i))) { IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); } BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1); OUT_RING (chan, ve->pipe.instance_divisor); } else - if (unlikely(nvc0->state.instance_bits & (1 << i))) { + if (unlikely(nvc0->state.instance_elts & (1 << i))) { IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0); } @@ -293,7 +309,7 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0) } nvc0->state.num_vtxelts = vertex->num_elements; - nvc0->state.instance_bits = vertex->instance_bits; + nvc0->state.instance_elts = vertex->instance_elts; } #define NVC0_PRIM_GL_CASE(n) \ @@ -600,17 +616,18 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) nvc0_state_validate(nvc0); + if (nvc0->vbo_fifo) { + nvc0_push_vbo(nvc0, info); + return; + } + if (nvc0->state.instance_base != info->start_instance) { nvc0->state.instance_base = info->start_instance; + /* NOTE: this does not affect the shader input, should it ? */ BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1); OUT_RING (chan, info->start_instance); } - if (nvc0->vbo_fifo) { - nvc0_push_vbo(nvc0, info); - return; - } - if (nvc0->vbo_dirty) { BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1); OUT_RING (chan, 0); diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile index 95da7782256..cd37f0111e2 100644 --- a/src/gallium/drivers/nvfx/Makefile +++ b/src/gallium/drivers/nvfx/Makefile @@ -28,6 +28,7 @@ C_SOURCES = \ nvfx_video_context.c LIBRARY_INCLUDES = \ + $(LIBDRM_CFLAGS) \ -I$(TOP)/src/gallium/drivers/nouveau/include include ../../Makefile.template diff --git a/src/gallium/drivers/r600/SConscript b/src/gallium/drivers/r600/SConscript index 64980140963..e51f50c5df5 100644 --- a/src/gallium/drivers/r600/SConscript +++ b/src/gallium/drivers/r600/SConscript @@ -9,7 +9,7 @@ except OSError: Return() env.Append(CPPPATH = [ - '#/include', + '#/include', '#/src/mesa', ]) diff --git a/src/gallium/drivers/r600/eg_states_inc.h b/src/gallium/drivers/r600/eg_states_inc.h deleted file mode 100644 index 1379c11291f..00000000000 --- a/src/gallium/drivers/r600/eg_states_inc.h +++ /dev/null @@ -1,458 +0,0 @@ -/* This file is autogenerated from eg_states.h - do not edit directly */ -/* autogenerating script is gen_eg_states.py */ - -/* EG_CONFIG */ -#define EG_CONFIG__SQ_CONFIG 0 -#define EG_CONFIG__SPI_CONFIG_CNTL 1 -#define EG_CONFIG__SPI_CONFIG_CNTL_1 2 -#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1 3 -#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2 4 -#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3 5 -#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1 6 -#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2 7 -#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1 8 -#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2 9 -#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3 10 -#define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 11 -#define EG_CONFIG__PA_CL_ENHANCE 12 -#define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1 13 -#define EG_CONFIG__SQ_LDS_ALLOC_PS 14 -#define EG_CONFIG__SX_MISC 15 -#define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE 16 -#define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE 17 -#define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE 18 -#define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE 19 -#define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE 20 -#define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE 21 -#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE 22 -#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1 23 -#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2 24 -#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3 25 -#define EG_CONFIG__VGT_OUTPUT_PATH_CNTL 26 -#define EG_CONFIG__VGT_HOS_CNTL 27 -#define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL 28 -#define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL 29 -#define EG_CONFIG__VGT_HOS_REUSE_DEPTH 30 -#define EG_CONFIG__VGT_GROUP_PRIM_TYPE 31 -#define EG_CONFIG__VGT_GROUP_FIRST_DECR 32 -#define EG_CONFIG__VGT_GROUP_DECR 33 -#define EG_CONFIG__VGT_GROUP_VECT_0_CNTL 34 -#define EG_CONFIG__VGT_GROUP_VECT_1_CNTL 35 -#define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 36 -#define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 37 -#define EG_CONFIG__VGT_GS_MODE 38 -#define EG_CONFIG__PA_SC_MODE_CNTL_0 39 -#define EG_CONFIG__PA_SC_MODE_CNTL_1 40 -#define EG_CONFIG__VGT_REUSE_OFF 41 -#define EG_CONFIG__VGT_VTX_CNT_EN 42 -#define EG_CONFIG__VGT_SHADER_STAGES_EN 43 -#define EG_CONFIG__VGT_STRMOUT_CONFIG 44 -#define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG 45 -#define EG_CONFIG_SIZE 46 -#define EG_CONFIG_PM4 128 - -/* EG_CB_CNTL */ -#define EG_CB_CNTL__CB_TARGET_MASK 0 -#define EG_CB_CNTL__CB_SHADER_MASK 1 -#define EG_CB_CNTL__CB_COLOR_CONTROL 2 -#define EG_CB_CNTL__PA_SC_AA_CONFIG 3 -#define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 4 -#define EG_CB_CNTL__PA_SC_AA_MASK 5 -#define EG_CB_CNTL_SIZE 6 -#define EG_CB_CNTL_PM4 128 - -/* EG_RASTERIZER */ -#define EG_RASTERIZER__SPI_INTERP_CONTROL_0 0 -#define EG_RASTERIZER__PA_CL_CLIP_CNTL 1 -#define EG_RASTERIZER__PA_SU_SC_MODE_CNTL 2 -#define EG_RASTERIZER__PA_CL_VS_OUT_CNTL 3 -#define EG_RASTERIZER__PA_CL_NANINF_CNTL 4 -#define EG_RASTERIZER__PA_SU_POINT_SIZE 5 -#define EG_RASTERIZER__PA_SU_POINT_MINMAX 6 -#define EG_RASTERIZER__PA_SU_LINE_CNTL 7 -#define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL 8 -#define EG_RASTERIZER__PA_SC_LINE_CNTL 9 -#define EG_RASTERIZER__PA_SU_VTX_CNTL 10 -#define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 -#define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 -#define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 -#define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 -#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 -#define EG_RASTERIZER_SIZE 21 -#define EG_RASTERIZER_PM4 128 - -/* EG_VIEWPORT */ -#define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 -#define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 -#define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 -#define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 -#define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 -#define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 -#define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 -#define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 -#define EG_VIEWPORT__PA_CL_VTE_CNTL 8 -#define EG_VIEWPORT_SIZE 9 -#define EG_VIEWPORT_PM4 128 - -/* EG_SCISSOR */ -#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 -#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 -#define EG_SCISSOR__PA_SC_WINDOW_OFFSET 2 -#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 -#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 -#define EG_SCISSOR__PA_SC_CLIPRECT_RULE 5 -#define EG_SCISSOR__PA_SC_CLIPRECT_0_TL 6 -#define EG_SCISSOR__PA_SC_CLIPRECT_0_BR 7 -#define EG_SCISSOR__PA_SC_CLIPRECT_1_TL 8 -#define EG_SCISSOR__PA_SC_CLIPRECT_1_BR 9 -#define EG_SCISSOR__PA_SC_CLIPRECT_2_TL 10 -#define EG_SCISSOR__PA_SC_CLIPRECT_2_BR 11 -#define EG_SCISSOR__PA_SC_CLIPRECT_3_TL 12 -#define EG_SCISSOR__PA_SC_CLIPRECT_3_BR 13 -#define EG_SCISSOR__PA_SC_EDGERULE 14 -#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 -#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 -#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 -#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 -#define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET 19 -#define EG_SCISSOR_SIZE 20 -#define EG_SCISSOR_PM4 128 - -/* EG_BLEND */ -#define EG_BLEND__CB_BLEND_RED 0 -#define EG_BLEND__CB_BLEND_GREEN 1 -#define EG_BLEND__CB_BLEND_BLUE 2 -#define EG_BLEND__CB_BLEND_ALPHA 3 -#define EG_BLEND__CB_BLEND0_CONTROL 4 -#define EG_BLEND__CB_BLEND1_CONTROL 5 -#define EG_BLEND__CB_BLEND2_CONTROL 6 -#define EG_BLEND__CB_BLEND3_CONTROL 7 -#define EG_BLEND__CB_BLEND4_CONTROL 8 -#define EG_BLEND__CB_BLEND5_CONTROL 9 -#define EG_BLEND__CB_BLEND6_CONTROL 10 -#define EG_BLEND__CB_BLEND7_CONTROL 11 -#define EG_BLEND_SIZE 12 -#define EG_BLEND_PM4 128 - -/* EG_DSA */ -#define EG_DSA__DB_STENCIL_CLEAR 0 -#define EG_DSA__DB_DEPTH_CLEAR 1 -#define EG_DSA__SX_ALPHA_TEST_CONTROL 2 -#define EG_DSA__DB_STENCILREFMASK 3 -#define EG_DSA__DB_STENCILREFMASK_BF 4 -#define EG_DSA__SX_ALPHA_REF 5 -#define EG_DSA__SPI_FOG_CNTL 6 -#define EG_DSA__DB_DEPTH_CONTROL 7 -#define EG_DSA__DB_SHADER_CONTROL 8 -#define EG_DSA__DB_RENDER_CONTROL 9 -#define EG_DSA__DB_COUNT_CONTROL 10 -#define EG_DSA__DB_RENDER_OVERRIDE 11 -#define EG_DSA__DB_RENDER_OVERRIDE2 12 -#define EG_DSA__DB_SRESULTS_COMPARE_STATE0 13 -#define EG_DSA__DB_SRESULTS_COMPARE_STATE1 14 -#define EG_DSA__DB_PRELOAD_CONTROL 15 -#define EG_DSA__DB_ALPHA_TO_MASK 16 -#define EG_DSA_SIZE 17 -#define EG_DSA_PM4 128 - -/* EG_VS_SHADER */ -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_0 0 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_1 1 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_2 2 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_3 3 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_4 4 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_5 5 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_6 6 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_7 7 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_8 8 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_9 9 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_10 10 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_11 11 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_12 12 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_13 13 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_14 14 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_15 15 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_16 16 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_17 17 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_18 18 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_19 19 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_20 20 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_21 21 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_22 22 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_23 23 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_24 24 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_25 25 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_26 26 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_27 27 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_28 28 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_29 29 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_30 30 -#define EG_VS_SHADER__SQ_VTX_SEMANTIC_31 31 -#define EG_VS_SHADER__SPI_VS_OUT_ID_0 32 -#define EG_VS_SHADER__SPI_VS_OUT_ID_1 33 -#define EG_VS_SHADER__SPI_VS_OUT_ID_2 34 -#define EG_VS_SHADER__SPI_VS_OUT_ID_3 35 -#define EG_VS_SHADER__SPI_VS_OUT_ID_4 36 -#define EG_VS_SHADER__SPI_VS_OUT_ID_5 37 -#define EG_VS_SHADER__SPI_VS_OUT_ID_6 38 -#define EG_VS_SHADER__SPI_VS_OUT_ID_7 39 -#define EG_VS_SHADER__SPI_VS_OUT_ID_8 40 -#define EG_VS_SHADER__SPI_VS_OUT_ID_9 41 -#define EG_VS_SHADER__SPI_VS_OUT_CONFIG 42 -#define EG_VS_SHADER__SQ_PGM_START_VS 43 -#define EG_VS_SHADER__SQ_PGM_RESOURCES_VS 44 -#define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS 45 -#define EG_VS_SHADER__SQ_PGM_START_FS 46 -#define EG_VS_SHADER__SQ_PGM_RESOURCES_FS 47 -#define EG_VS_SHADER_SIZE 48 -#define EG_VS_SHADER_PM4 128 - -/* EG_PS_SHADER */ -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 -#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 -#define EG_PS_SHADER__SPI_THREAD_GROUPING 32 -#define EG_PS_SHADER__SPI_PS_IN_CONTROL_0 33 -#define EG_PS_SHADER__SPI_PS_IN_CONTROL_1 34 -#define EG_PS_SHADER__SPI_INPUT_Z 35 -#define EG_PS_SHADER__SPI_BARYC_CNTL 36 -#define EG_PS_SHADER__SPI_PS_IN_CONTROL_2 37 -#define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL 38 -#define EG_PS_SHADER__SQ_PGM_START_PS 39 -#define EG_PS_SHADER__SQ_PGM_RESOURCES_PS 40 -#define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS 41 -#define EG_PS_SHADER__SQ_PGM_EXPORTS_PS 42 -#define EG_PS_SHADER_SIZE 43 -#define EG_PS_SHADER_PM4 128 - -/* EG_UCP */ -#define EG_UCP__PA_CL_UCP0_X 0 -#define EG_UCP__PA_CL_UCP0_Y 1 -#define EG_UCP__PA_CL_UCP0_Z 2 -#define EG_UCP__PA_CL_UCP0_W 3 -#define EG_UCP__PA_CL_UCP1_X 4 -#define EG_UCP__PA_CL_UCP1_Y 5 -#define EG_UCP__PA_CL_UCP1_Z 6 -#define EG_UCP__PA_CL_UCP1_W 7 -#define EG_UCP__PA_CL_UCP2_X 8 -#define EG_UCP__PA_CL_UCP2_Y 9 -#define EG_UCP__PA_CL_UCP2_Z 10 -#define EG_UCP__PA_CL_UCP2_W 11 -#define EG_UCP__PA_CL_UCP3_X 12 -#define EG_UCP__PA_CL_UCP3_Y 13 -#define EG_UCP__PA_CL_UCP3_Z 14 -#define EG_UCP__PA_CL_UCP3_W 15 -#define EG_UCP__PA_CL_UCP4_X 16 -#define EG_UCP__PA_CL_UCP4_Y 17 -#define EG_UCP__PA_CL_UCP4_Z 18 -#define EG_UCP__PA_CL_UCP4_W 19 -#define EG_UCP__PA_CL_UCP5_X 20 -#define EG_UCP__PA_CL_UCP5_Y 21 -#define EG_UCP__PA_CL_UCP5_Z 22 -#define EG_UCP__PA_CL_UCP5_W 23 -#define EG_UCP_SIZE 24 -#define EG_UCP_PM4 128 - -/* EG_VS_CBUF */ -#define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0 -#define EG_VS_CBUF__ALU_CONST_CACHE_VS_0 1 -#define EG_VS_CBUF_SIZE 2 -#define EG_VS_CBUF_PM4 128 - -/* EG_PS_CBUF */ -#define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0 -#define EG_PS_CBUF__ALU_CONST_CACHE_PS_0 1 -#define EG_PS_CBUF_SIZE 2 -#define EG_PS_CBUF_PM4 128 - -/* EG_PS_RESOURCE */ -#define EG_PS_RESOURCE__RESOURCE0_WORD0 0 -#define EG_PS_RESOURCE__RESOURCE0_WORD1 1 -#define EG_PS_RESOURCE__RESOURCE0_WORD2 2 -#define EG_PS_RESOURCE__RESOURCE0_WORD3 3 -#define EG_PS_RESOURCE__RESOURCE0_WORD4 4 -#define EG_PS_RESOURCE__RESOURCE0_WORD5 5 -#define EG_PS_RESOURCE__RESOURCE0_WORD6 6 -#define EG_PS_RESOURCE__RESOURCE0_WORD7 7 -#define EG_PS_RESOURCE_SIZE 8 -#define EG_PS_RESOURCE_PM4 128 - -/* EG_VS_RESOURCE */ -#define EG_VS_RESOURCE__RESOURCE160_WORD0 0 -#define EG_VS_RESOURCE__RESOURCE160_WORD1 1 -#define EG_VS_RESOURCE__RESOURCE160_WORD2 2 -#define EG_VS_RESOURCE__RESOURCE160_WORD3 3 -#define EG_VS_RESOURCE__RESOURCE160_WORD4 4 -#define EG_VS_RESOURCE__RESOURCE160_WORD5 5 -#define EG_VS_RESOURCE__RESOURCE160_WORD6 6 -#define EG_VS_RESOURCE__RESOURCE160_WORD7 7 -#define EG_VS_RESOURCE_SIZE 8 -#define EG_VS_RESOURCE_PM4 128 - -/* EG_FS_RESOURCE */ -#define EG_FS_RESOURCE__RESOURCE320_WORD0 0 -#define EG_FS_RESOURCE__RESOURCE320_WORD1 1 -#define EG_FS_RESOURCE__RESOURCE320_WORD2 2 -#define EG_FS_RESOURCE__RESOURCE320_WORD3 3 -#define EG_FS_RESOURCE__RESOURCE320_WORD4 4 -#define EG_FS_RESOURCE__RESOURCE320_WORD5 5 -#define EG_FS_RESOURCE__RESOURCE320_WORD6 6 -#define EG_FS_RESOURCE__RESOURCE320_WORD7 7 -#define EG_FS_RESOURCE_SIZE 8 -#define EG_FS_RESOURCE_PM4 128 - -/* EG_GS_RESOURCE */ -#define EG_GS_RESOURCE__RESOURCE336_WORD0 0 -#define EG_GS_RESOURCE__RESOURCE336_WORD1 1 -#define EG_GS_RESOURCE__RESOURCE336_WORD2 2 -#define EG_GS_RESOURCE__RESOURCE336_WORD3 3 -#define EG_GS_RESOURCE__RESOURCE336_WORD4 4 -#define EG_GS_RESOURCE__RESOURCE336_WORD5 5 -#define EG_GS_RESOURCE__RESOURCE336_WORD6 6 -#define EG_GS_RESOURCE__RESOURCE336_WORD7 7 -#define EG_GS_RESOURCE_SIZE 8 -#define EG_GS_RESOURCE_PM4 128 - -/* EG_PS_SAMPLER */ -#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 -#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 -#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 -#define EG_PS_SAMPLER_SIZE 3 -#define EG_PS_SAMPLER_PM4 128 - -/* EG_VS_SAMPLER */ -#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 -#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 -#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 -#define EG_VS_SAMPLER_SIZE 3 -#define EG_VS_SAMPLER_PM4 128 - -/* EG_GS_SAMPLER */ -#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 -#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 -#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 -#define EG_GS_SAMPLER_SIZE 3 -#define EG_GS_SAMPLER_PM4 128 - -/* EG_PS_SAMPLER_BORDER */ -#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_INDEX 0 -#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 1 -#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 2 -#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 3 -#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 4 -#define EG_PS_SAMPLER_BORDER_SIZE 5 -#define EG_PS_SAMPLER_BORDER_PM4 128 - -/* EG_VS_SAMPLER_BORDER */ -#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_INDEX 0 -#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 1 -#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 2 -#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 3 -#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 4 -#define EG_VS_SAMPLER_BORDER_SIZE 5 -#define EG_VS_SAMPLER_BORDER_PM4 128 - -/* EG_GS_SAMPLER_BORDER */ -#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_INDEX 0 -#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 1 -#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 2 -#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 3 -#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 4 -#define EG_GS_SAMPLER_BORDER_SIZE 5 -#define EG_GS_SAMPLER_BORDER_PM4 128 - -/* EG_CB */ -#define EG_CB__CB_COLOR0_BASE 0 -#define EG_CB__CB_COLOR0_PITCH 1 -#define EG_CB__CB_COLOR0_SLICE 2 -#define EG_CB__CB_COLOR0_VIEW 3 -#define EG_CB__CB_COLOR0_INFO 4 -#define EG_CB__CB_COLOR0_ATTRIB 5 -#define EG_CB__CB_COLOR0_DIM 6 -#define EG_CB_SIZE 7 -#define EG_CB_PM4 128 - -/* EG_DB */ -#define EG_DB__DB_HTILE_DATA_BASE 0 -#define EG_DB__DB_Z_INFO 1 -#define EG_DB__DB_STENCIL_INFO 2 -#define EG_DB__DB_DEPTH_SIZE 3 -#define EG_DB__DB_DEPTH_SLICE 4 -#define EG_DB__DB_DEPTH_VIEW 5 -#define EG_DB__DB_HTILE_SURFACE 6 -#define EG_DB__DB_Z_READ_BASE 7 -#define EG_DB__DB_STENCIL_READ_BASE 8 -#define EG_DB__DB_Z_WRITE_BASE 9 -#define EG_DB__DB_STENCIL_WRITE_BASE 10 -#define EG_DB_SIZE 11 -#define EG_DB_PM4 128 - -/* EG_VGT */ -#define EG_VGT__VGT_PRIMITIVE_TYPE 0 -#define EG_VGT__VGT_MAX_VTX_INDX 1 -#define EG_VGT__VGT_MIN_VTX_INDX 2 -#define EG_VGT__VGT_INDX_OFFSET 3 -#define EG_VGT__VGT_DMA_INDEX_TYPE 4 -#define EG_VGT__VGT_PRIMITIVEID_EN 5 -#define EG_VGT__VGT_DMA_NUM_INSTANCES 6 -#define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN 7 -#define EG_VGT__VGT_INSTANCE_STEP_RATE_0 8 -#define EG_VGT__VGT_INSTANCE_STEP_RATE_1 9 -#define EG_VGT_SIZE 10 -#define EG_VGT_PM4 128 - -/* EG_DRAW */ -#define EG_DRAW__VGT_NUM_INDICES 0 -#define EG_DRAW__VGT_DMA_BASE_HI 1 -#define EG_DRAW__VGT_DMA_BASE 2 -#define EG_DRAW__VGT_DRAW_INITIATOR 3 -#define EG_DRAW_SIZE 4 -#define EG_DRAW_PM4 128 - -/* EG_VGT_EVENT */ -#define EG_VGT_EVENT__VGT_EVENT_INITIATOR 0 -#define EG_VGT_EVENT_SIZE 1 -#define EG_VGT_EVENT_PM4 128 - -/* EG_CB_FLUSH */ -#define EG_CB_FLUSH_SIZE 0 -#define EG_CB_FLUSH_PM4 128 - -/* EG_DB_FLUSH */ -#define EG_DB_FLUSH_SIZE 0 -#define EG_DB_FLUSH_PM4 128 - diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 61de24b31ae..54e339fbefe 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -602,26 +602,24 @@ static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, return 0; } -static int reserve_cfile(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan) +static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan) { - int res, resmatch = -1, resempty = -1; - for (res = 3; res >= 0; --res) { - if (bs->hw_cfile_addr[res] == -1) - resempty = res; - else if (bs->hw_cfile_addr[res] == sel && - bs->hw_cfile_elem[res] == chan) - resmatch = res; + int res, num_res = 4; + if (bc->chiprev >= CHIPREV_R700) { + num_res = 2; + chan /= 2; } - if (resmatch != -1) - return 0; // Read for this scalar element already reserved, nothing to do here. - else if (resempty != -1) { - bs->hw_cfile_addr[resempty] = sel; - bs->hw_cfile_elem[resempty] = chan; - } else { - // All cfile read ports are used, cannot reference vector element - return -1; + for (res = 0; res < num_res; ++res) { + if (bs->hw_cfile_addr[res] == -1) { + bs->hw_cfile_addr[res] = sel; + bs->hw_cfile_elem[res] = chan; + return 0; + } else if (bs->hw_cfile_addr[res] == sel && + bs->hw_cfile_elem[res] == chan) + return 0; // Read for this scalar element already reserved, nothing to do here. } - return 0; + // All cfile read ports are used, cannot reference vector element + return -1; } static int is_gpr(unsigned sel) @@ -667,7 +665,7 @@ static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu, return r; } } else if (is_cfile(sel)) { - r = reserve_cfile(bs, sel, elem); + r = reserve_cfile(bc, bs, sel, elem); if (r) return r; } @@ -694,7 +692,7 @@ static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu, const_count++; } if (is_cfile(sel)) { - r = reserve_cfile(bs, sel, elem); + r = reserve_cfile(bc, bs, sel, elem); if (r) return r; } @@ -915,6 +913,7 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5], int i, j, r, src, num_src; int num_once_inst = 0; + int have_mova = 0, have_rel = 0; r = assign_alu_units(bc, alu_prev, prev); if (r) @@ -929,6 +928,12 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5], return 0; if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral)) return 0; + if (is_alu_mova_inst(bc, prev[i])) { + if (have_rel) + return 0; + have_mova = 1; + } + num_once_inst += is_alu_once_inst(bc, prev[i]); } if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral)) return 0; @@ -936,7 +941,6 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5], // let's check used slots if (prev[i] && !slots[i]) { result[i] = prev[i]; - num_once_inst += is_alu_once_inst(bc, prev[i]); continue; } else if (prev[i] && slots[i]) { if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) { @@ -962,6 +966,12 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5], num_src = r600_bc_get_num_operands(bc, alu); for (src = 0; src < num_src; ++src) { + if (alu->src[src].rel) { + if (have_mova) + return 0; + have_rel = 1; + } + // constants doesn't matter if (!is_gpr(alu->src[src].sel)) continue; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index ad14dbe14f4..68b625cc3b4 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -288,6 +288,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_STREAM_OUTPUT: case PIPE_CAP_PRIMITIVE_RESTART: case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */ + case PIPE_CAP_INSTANCED_DRAWING: return 0; /* Texturing. */ diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 2112a40f696..7f74fda0daf 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -241,7 +241,7 @@ int r600_conv_pipe_prim(unsigned pprim, unsigned *prim); void r600_init_screen_texture_functions(struct pipe_screen *screen); void r600_init_surface_functions(struct r600_pipe_context *r600); uint32_t r600_translate_texformat(enum pipe_format format, - const unsigned char *swizzle_view, + const unsigned char *swizzle_view, uint32_t *word4_p, uint32_t *yuv_format_p); unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, unsigned level, unsigned layer); diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 106852c1082..c982471a04f 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -1822,7 +1822,9 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); - alu.src[0].sel = src_gpr; + r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]); + if (r) + return r; alu.src[0].chan = tgsi_chan(&inst->Src[0], i); alu.dst.sel = ctx->temp_reg; alu.dst.chan = i; @@ -2471,7 +2473,7 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx) alu.dst.chan = 0; alu.dst.sel = ctx->temp_reg; alu.dst.write = 1; - r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU)); + r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; memset(&alu, 0, sizeof(struct r600_bc_alu)); @@ -2482,7 +2484,7 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx) alu.src[0].sel = ctx->temp_reg; alu.src[0].chan = 0; alu.last = 1; - r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU)); + r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; return 0; @@ -2515,7 +2517,7 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx) alu.last = 1; - r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU)); + r = r600_bc_add_alu(ctx->bc, &alu); if (r) return r; ctx->bc->cf_last->r6xx_uses_waterfall = 1; diff --git a/src/gallium/drivers/r600/r600_states_inc.h b/src/gallium/drivers/r600/r600_states_inc.h deleted file mode 100644 index 1c8075ebdb5..00000000000 --- a/src/gallium/drivers/r600/r600_states_inc.h +++ /dev/null @@ -1,543 +0,0 @@ -/* This file is autogenerated from r600_states.h - do not edit directly */ -/* autogenerating script is gen_r600_states.py */ - -/* R600_CONFIG */ -#define R600_CONFIG__SQ_CONFIG 0 -#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 -#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2 -#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3 -#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4 -#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5 -#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 -#define R600_CONFIG__TA_CNTL_AUX 7 -#define R600_CONFIG__VC_ENHANCE 8 -#define R600_CONFIG__DB_DEBUG 9 -#define R600_CONFIG__DB_WATERMARKS 10 -#define R600_CONFIG__SX_MISC 11 -#define R600_CONFIG__SPI_THREAD_GROUPING 12 -#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 13 -#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 14 -#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 15 -#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 16 -#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 17 -#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 18 -#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 19 -#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 20 -#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 21 -#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 22 -#define R600_CONFIG__VGT_HOS_CNTL 23 -#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 24 -#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 25 -#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 26 -#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 27 -#define R600_CONFIG__VGT_GROUP_FIRST_DECR 28 -#define R600_CONFIG__VGT_GROUP_DECR 29 -#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 30 -#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 31 -#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 32 -#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 33 -#define R600_CONFIG__VGT_GS_MODE 34 -#define R600_CONFIG__PA_SC_MODE_CNTL 35 -#define R600_CONFIG__VGT_STRMOUT_EN 36 -#define R600_CONFIG__VGT_REUSE_OFF 37 -#define R600_CONFIG__VGT_VTX_CNT_EN 38 -#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 39 -#define R600_CONFIG_SIZE 40 -#define R600_CONFIG_PM4 128 - -/* R600_CB_CNTL */ -#define R600_CB_CNTL__CB_CLEAR_RED 0 -#define R600_CB_CNTL__CB_CLEAR_GREEN 1 -#define R600_CB_CNTL__CB_CLEAR_BLUE 2 -#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 -#define R600_CB_CNTL__CB_SHADER_MASK 4 -#define R600_CB_CNTL__CB_TARGET_MASK 5 -#define R600_CB_CNTL__CB_FOG_RED 6 -#define R600_CB_CNTL__CB_FOG_GREEN 7 -#define R600_CB_CNTL__CB_FOG_BLUE 8 -#define R600_CB_CNTL__CB_COLOR_CONTROL 9 -#define R600_CB_CNTL__PA_SC_AA_CONFIG 10 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12 -#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13 -#define R600_CB_CNTL__CB_CLRCMP_SRC 14 -#define R600_CB_CNTL__CB_CLRCMP_DST 15 -#define R600_CB_CNTL__CB_CLRCMP_MSK 16 -#define R600_CB_CNTL__PA_SC_AA_MASK 17 -#define R600_CB_CNTL__CB_SHADER_CONTROL 18 -#define R600_CB_CNTL_SIZE 19 -#define R600_CB_CNTL_PM4 128 - -/* R600_RASTERIZER */ -#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0 -#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1 -#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2 -#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3 -#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4 -#define R600_RASTERIZER__PA_SU_POINT_SIZE 5 -#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6 -#define R600_RASTERIZER__PA_SU_LINE_CNTL 7 -#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8 -#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9 -#define R600_RASTERIZER__PA_SC_LINE_CNTL 10 -#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 -#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 -#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 -#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 -#define R600_RASTERIZER_SIZE 21 -#define R600_RASTERIZER_PM4 128 - -/* R600_VIEWPORT */ -#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 -#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 -#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 -#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 -#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 -#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 -#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 -#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 -#define R600_VIEWPORT__PA_CL_VTE_CNTL 8 -#define R600_VIEWPORT_SIZE 9 -#define R600_VIEWPORT_PM4 128 - -/* R600_SCISSOR */ -#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 -#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 -#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 -#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13 -#define R600_SCISSOR__PA_SC_EDGERULE 14 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 -#define R600_SCISSOR_SIZE 19 -#define R600_SCISSOR_PM4 128 - -/* R600_BLEND */ -#define R600_BLEND__CB_BLEND_RED 0 -#define R600_BLEND__CB_BLEND_GREEN 1 -#define R600_BLEND__CB_BLEND_BLUE 2 -#define R600_BLEND__CB_BLEND_ALPHA 3 -#define R600_BLEND__CB_BLEND0_CONTROL 4 -#define R600_BLEND__CB_BLEND1_CONTROL 5 -#define R600_BLEND__CB_BLEND2_CONTROL 6 -#define R600_BLEND__CB_BLEND3_CONTROL 7 -#define R600_BLEND__CB_BLEND4_CONTROL 8 -#define R600_BLEND__CB_BLEND5_CONTROL 9 -#define R600_BLEND__CB_BLEND6_CONTROL 10 -#define R600_BLEND__CB_BLEND7_CONTROL 11 -#define R600_BLEND__CB_BLEND_CONTROL 12 -#define R600_BLEND_SIZE 13 -#define R600_BLEND_PM4 128 - -/* R600_DSA */ -#define R600_DSA__DB_STENCIL_CLEAR 0 -#define R600_DSA__DB_DEPTH_CLEAR 1 -#define R600_DSA__SX_ALPHA_TEST_CONTROL 2 -#define R600_DSA__DB_STENCILREFMASK 3 -#define R600_DSA__DB_STENCILREFMASK_BF 4 -#define R600_DSA__SX_ALPHA_REF 5 -#define R600_DSA__SPI_FOG_FUNC_SCALE 6 -#define R600_DSA__SPI_FOG_FUNC_BIAS 7 -#define R600_DSA__SPI_FOG_CNTL 8 -#define R600_DSA__DB_DEPTH_CONTROL 9 -#define R600_DSA__DB_SHADER_CONTROL 10 -#define R600_DSA__DB_RENDER_CONTROL 11 -#define R600_DSA__DB_RENDER_OVERRIDE 12 -#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13 -#define R600_DSA__DB_PRELOAD_CONTROL 14 -#define R600_DSA__DB_ALPHA_TO_MASK 15 -#define R600_DSA_SIZE 16 -#define R600_DSA_PM4 128 - -/* R600_VS_SHADER */ -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30 -#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31 -#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32 -#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33 -#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34 -#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35 -#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36 -#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37 -#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38 -#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39 -#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40 -#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41 -#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42 -#define R600_VS_SHADER__SQ_PGM_START_VS 43 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44 -#define R600_VS_SHADER__SQ_PGM_START_FS 45 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48 -#define R600_VS_SHADER_SIZE 49 -#define R600_VS_SHADER_PM4 128 - -/* R600_PS_SHADER */ -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 -#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33 -#define R600_PS_SHADER__SPI_INPUT_Z 34 -#define R600_PS_SHADER__SQ_PGM_START_PS 35 -#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36 -#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37 -#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38 -#define R600_PS_SHADER_SIZE 39 -#define R600_PS_SHADER_PM4 128 - -/* R600_VS_CBUF */ -#define R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0 -#define R600_VS_CBUF__ALU_CONST_CACHE_VS_0 1 -#define R600_VS_CBUF_SIZE 2 -#define R600_VS_CBUF_PM4 128 - -/* R600_PS_CBUF */ -#define R600_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0 -#define R600_PS_CBUF__ALU_CONST_CACHE_PS_0 1 -#define R600_PS_CBUF_SIZE 2 -#define R600_PS_CBUF_PM4 128 - -/* R600_PS_CONSTANT */ -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2 -#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3 -#define R600_PS_CONSTANT_SIZE 4 -#define R600_PS_CONSTANT_PM4 128 - -/* R600_VS_CONSTANT */ -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2 -#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3 -#define R600_VS_CONSTANT_SIZE 4 -#define R600_VS_CONSTANT_PM4 128 - -/* R600_UCP */ -#define R600_UCP__PA_CL_UCP0_X 0 -#define R600_UCP__PA_CL_UCP0_Y 1 -#define R600_UCP__PA_CL_UCP0_Z 2 -#define R600_UCP__PA_CL_UCP0_W 3 -#define R600_UCP__PA_CL_UCP1_X 4 -#define R600_UCP__PA_CL_UCP1_Y 5 -#define R600_UCP__PA_CL_UCP1_Z 6 -#define R600_UCP__PA_CL_UCP1_W 7 -#define R600_UCP__PA_CL_UCP2_X 8 -#define R600_UCP__PA_CL_UCP2_Y 9 -#define R600_UCP__PA_CL_UCP2_Z 10 -#define R600_UCP__PA_CL_UCP2_W 11 -#define R600_UCP__PA_CL_UCP3_X 12 -#define R600_UCP__PA_CL_UCP3_Y 13 -#define R600_UCP__PA_CL_UCP3_Z 14 -#define R600_UCP__PA_CL_UCP3_W 15 -#define R600_UCP__PA_CL_UCP4_X 16 -#define R600_UCP__PA_CL_UCP4_Y 17 -#define R600_UCP__PA_CL_UCP4_Z 18 -#define R600_UCP__PA_CL_UCP4_W 19 -#define R600_UCP__PA_CL_UCP5_X 20 -#define R600_UCP__PA_CL_UCP5_Y 21 -#define R600_UCP__PA_CL_UCP5_Z 22 -#define R600_UCP__PA_CL_UCP5_W 23 -#define R600_UCP_SIZE 24 -#define R600_UCP_PM4 128 - -/* R600_PS_RESOURCE */ -#define R600_PS_RESOURCE__RESOURCE0_WORD0 0 -#define R600_PS_RESOURCE__RESOURCE0_WORD1 1 -#define R600_PS_RESOURCE__RESOURCE0_WORD2 2 -#define R600_PS_RESOURCE__RESOURCE0_WORD3 3 -#define R600_PS_RESOURCE__RESOURCE0_WORD4 4 -#define R600_PS_RESOURCE__RESOURCE0_WORD5 5 -#define R600_PS_RESOURCE__RESOURCE0_WORD6 6 -#define R600_PS_RESOURCE_SIZE 7 -#define R600_PS_RESOURCE_PM4 128 - -/* R600_VS_RESOURCE */ -#define R600_VS_RESOURCE__RESOURCE160_WORD0 0 -#define R600_VS_RESOURCE__RESOURCE160_WORD1 1 -#define R600_VS_RESOURCE__RESOURCE160_WORD2 2 -#define R600_VS_RESOURCE__RESOURCE160_WORD3 3 -#define R600_VS_RESOURCE__RESOURCE160_WORD4 4 -#define R600_VS_RESOURCE__RESOURCE160_WORD5 5 -#define R600_VS_RESOURCE__RESOURCE160_WORD6 6 -#define R600_VS_RESOURCE_SIZE 7 -#define R600_VS_RESOURCE_PM4 128 - -/* R600_FS_RESOURCE */ -#define R600_FS_RESOURCE__RESOURCE320_WORD0 0 -#define R600_FS_RESOURCE__RESOURCE320_WORD1 1 -#define R600_FS_RESOURCE__RESOURCE320_WORD2 2 -#define R600_FS_RESOURCE__RESOURCE320_WORD3 3 -#define R600_FS_RESOURCE__RESOURCE320_WORD4 4 -#define R600_FS_RESOURCE__RESOURCE320_WORD5 5 -#define R600_FS_RESOURCE__RESOURCE320_WORD6 6 -#define R600_FS_RESOURCE_SIZE 7 -#define R600_FS_RESOURCE_PM4 128 - -/* R600_GS_RESOURCE */ -#define R600_GS_RESOURCE__RESOURCE336_WORD0 0 -#define R600_GS_RESOURCE__RESOURCE336_WORD1 1 -#define R600_GS_RESOURCE__RESOURCE336_WORD2 2 -#define R600_GS_RESOURCE__RESOURCE336_WORD3 3 -#define R600_GS_RESOURCE__RESOURCE336_WORD4 4 -#define R600_GS_RESOURCE__RESOURCE336_WORD5 5 -#define R600_GS_RESOURCE__RESOURCE336_WORD6 6 -#define R600_GS_RESOURCE_SIZE 7 -#define R600_GS_RESOURCE_PM4 128 - -/* R600_PS_SAMPLER */ -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 -#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 -#define R600_PS_SAMPLER_SIZE 3 -#define R600_PS_SAMPLER_PM4 128 - -/* R600_VS_SAMPLER */ -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 -#define R600_VS_SAMPLER_SIZE 3 -#define R600_VS_SAMPLER_PM4 128 - -/* R600_GS_SAMPLER */ -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 -#define R600_GS_SAMPLER_SIZE 3 -#define R600_GS_SAMPLER_PM4 128 - -/* R600_PS_SAMPLER_BORDER */ -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 -#define R600_PS_SAMPLER_BORDER_SIZE 4 -#define R600_PS_SAMPLER_BORDER_PM4 128 - -/* R600_VS_SAMPLER_BORDER */ -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 -#define R600_VS_SAMPLER_BORDER_SIZE 4 -#define R600_VS_SAMPLER_BORDER_PM4 128 - -/* R600_GS_SAMPLER_BORDER */ -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 -#define R600_GS_SAMPLER_BORDER_SIZE 4 -#define R600_GS_SAMPLER_BORDER_PM4 128 - -/* R600_CB0 */ -#define R600_CB0__CB_COLOR0_BASE 0 -#define R600_CB0__CB_COLOR0_INFO 1 -#define R600_CB0__CB_COLOR0_SIZE 2 -#define R600_CB0__CB_COLOR0_VIEW 3 -#define R600_CB0__CB_COLOR0_FRAG 4 -#define R600_CB0__CB_COLOR0_TILE 5 -#define R600_CB0__CB_COLOR0_MASK 6 -#define R600_CB0_SIZE 7 -#define R600_CB0_PM4 128 - -/* R600_CB1 */ -#define R600_CB1__CB_COLOR1_BASE 0 -#define R600_CB1__CB_COLOR1_INFO 1 -#define R600_CB1__CB_COLOR1_SIZE 2 -#define R600_CB1__CB_COLOR1_VIEW 3 -#define R600_CB1__CB_COLOR1_FRAG 4 -#define R600_CB1__CB_COLOR1_TILE 5 -#define R600_CB1__CB_COLOR1_MASK 6 -#define R600_CB1_SIZE 7 -#define R600_CB1_PM4 128 - -/* R600_CB2 */ -#define R600_CB2__CB_COLOR2_BASE 0 -#define R600_CB2__CB_COLOR2_INFO 1 -#define R600_CB2__CB_COLOR2_SIZE 2 -#define R600_CB2__CB_COLOR2_VIEW 3 -#define R600_CB2__CB_COLOR2_FRAG 4 -#define R600_CB2__CB_COLOR2_TILE 5 -#define R600_CB2__CB_COLOR2_MASK 6 -#define R600_CB2_SIZE 7 -#define R600_CB2_PM4 128 - -/* R600_CB3 */ -#define R600_CB3__CB_COLOR3_BASE 0 -#define R600_CB3__CB_COLOR3_INFO 1 -#define R600_CB3__CB_COLOR3_SIZE 2 -#define R600_CB3__CB_COLOR3_VIEW 3 -#define R600_CB3__CB_COLOR3_FRAG 4 -#define R600_CB3__CB_COLOR3_TILE 5 -#define R600_CB3__CB_COLOR3_MASK 6 -#define R600_CB3_SIZE 7 -#define R600_CB3_PM4 128 - -/* R600_CB4 */ -#define R600_CB4__CB_COLOR4_BASE 0 -#define R600_CB4__CB_COLOR4_INFO 1 -#define R600_CB4__CB_COLOR4_SIZE 2 -#define R600_CB4__CB_COLOR4_VIEW 3 -#define R600_CB4__CB_COLOR4_FRAG 4 -#define R600_CB4__CB_COLOR4_TILE 5 -#define R600_CB4__CB_COLOR4_MASK 6 -#define R600_CB4_SIZE 7 -#define R600_CB4_PM4 128 - -/* R600_CB5 */ -#define R600_CB5__CB_COLOR5_BASE 0 -#define R600_CB5__CB_COLOR5_INFO 1 -#define R600_CB5__CB_COLOR5_SIZE 2 -#define R600_CB5__CB_COLOR5_VIEW 3 -#define R600_CB5__CB_COLOR5_FRAG 4 -#define R600_CB5__CB_COLOR5_TILE 5 -#define R600_CB5__CB_COLOR5_MASK 6 -#define R600_CB5_SIZE 7 -#define R600_CB5_PM4 128 - -/* R600_CB6 */ -#define R600_CB6__CB_COLOR6_BASE 0 -#define R600_CB6__CB_COLOR6_INFO 1 -#define R600_CB6__CB_COLOR6_SIZE 2 -#define R600_CB6__CB_COLOR6_VIEW 3 -#define R600_CB6__CB_COLOR6_FRAG 4 -#define R600_CB6__CB_COLOR6_TILE 5 -#define R600_CB6__CB_COLOR6_MASK 6 -#define R600_CB6_SIZE 7 -#define R600_CB6_PM4 128 - -/* R600_CB7 */ -#define R600_CB7__CB_COLOR7_BASE 0 -#define R600_CB7__CB_COLOR7_INFO 1 -#define R600_CB7__CB_COLOR7_SIZE 2 -#define R600_CB7__CB_COLOR7_VIEW 3 -#define R600_CB7__CB_COLOR7_FRAG 4 -#define R600_CB7__CB_COLOR7_TILE 5 -#define R600_CB7__CB_COLOR7_MASK 6 -#define R600_CB7_SIZE 7 -#define R600_CB7_PM4 128 - -/* R600_DB */ -#define R600_DB__DB_DEPTH_BASE 0 -#define R600_DB__DB_DEPTH_SIZE 1 -#define R600_DB__DB_DEPTH_VIEW 2 -#define R600_DB__DB_DEPTH_INFO 3 -#define R600_DB__DB_HTILE_SURFACE 4 -#define R600_DB__DB_PREFETCH_LIMIT 5 -#define R600_DB_SIZE 6 -#define R600_DB_PM4 128 - -/* R600_VGT */ -#define R600_VGT__VGT_PRIMITIVE_TYPE 0 -#define R600_VGT__VGT_MAX_VTX_INDX 1 -#define R600_VGT__VGT_MIN_VTX_INDX 2 -#define R600_VGT__VGT_INDX_OFFSET 3 -#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4 -#define R600_VGT__VGT_DMA_INDEX_TYPE 5 -#define R600_VGT__VGT_PRIMITIVEID_EN 6 -#define R600_VGT__VGT_DMA_NUM_INSTANCES 7 -#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8 -#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9 -#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10 -#define R600_VGT_SIZE 11 -#define R600_VGT_PM4 128 - -/* R600_DRAW */ -#define R600_DRAW__VGT_NUM_INDICES 0 -#define R600_DRAW__VGT_DMA_BASE_HI 1 -#define R600_DRAW__VGT_DMA_BASE 2 -#define R600_DRAW__VGT_DRAW_INITIATOR 3 -#define R600_DRAW_SIZE 4 -#define R600_DRAW_PM4 128 - -/* R600_VGT_EVENT */ -#define R600_VGT_EVENT__VGT_EVENT_INITIATOR 0 -#define R600_VGT_EVENT_SIZE 1 -#define R600_VGT_EVENT_PM4 128 - -/* R600_CB_FLUSH */ -#define R600_CB_FLUSH_SIZE 0 -#define R600_CB_FLUSH_PM4 128 - -/* R600_DB_FLUSH */ -#define R600_DB_FLUSH_SIZE 0 -#define R600_DB_FLUSH_PM4 128 - diff --git a/src/gallium/drivers/softpipe/sp_context.c b/src/gallium/drivers/softpipe/sp_context.c index f3489c1c793..fe54f92addf 100644 --- a/src/gallium/drivers/softpipe/sp_context.c +++ b/src/gallium/drivers/softpipe/sp_context.c @@ -91,10 +91,17 @@ softpipe_destroy( struct pipe_context *pipe ) if (softpipe->draw) draw_destroy( softpipe->draw ); - softpipe->quad.shade->destroy( softpipe->quad.shade ); - softpipe->quad.depth_test->destroy( softpipe->quad.depth_test ); - softpipe->quad.blend->destroy( softpipe->quad.blend ); - softpipe->quad.pstipple->destroy( softpipe->quad.pstipple ); + if (softpipe->quad.shade) + softpipe->quad.shade->destroy( softpipe->quad.shade ); + + if (softpipe->quad.depth_test) + softpipe->quad.depth_test->destroy( softpipe->quad.depth_test ); + + if (softpipe->quad.blend) + softpipe->quad.blend->destroy( softpipe->quad.blend ); + + if (softpipe->quad.pstipple) + softpipe->quad.pstipple->destroy( softpipe->quad.pstipple ); for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) { sp_destroy_tile_cache(softpipe->cbuf_cache[i]); @@ -105,8 +112,8 @@ softpipe_destroy( struct pipe_context *pipe ) pipe_surface_reference(&softpipe->framebuffer.zsbuf, NULL); for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { - sp_destroy_tex_tile_cache(softpipe->tex_cache[i]); - pipe_sampler_view_reference(&softpipe->sampler_views[i], NULL); + sp_destroy_tex_tile_cache(softpipe->fragment_tex_cache[i]); + pipe_sampler_view_reference(&softpipe->fragment_sampler_views[i], NULL); } for (i = 0; i < PIPE_MAX_VERTEX_SAMPLERS; i++) { @@ -174,8 +181,8 @@ softpipe_is_resource_referenced( struct pipe_context *pipe, /* check if any of the tex_cache textures are this texture */ for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { - if (softpipe->tex_cache[i] && - softpipe->tex_cache[i]->texture == texture) + if (softpipe->fragment_tex_cache[i] && + softpipe->fragment_tex_cache[i]->texture == texture) return PIPE_REFERENCED_FOR_READ; } for (i = 0; i < PIPE_MAX_VERTEX_SAMPLERS; i++) { @@ -262,13 +269,22 @@ softpipe_create_context( struct pipe_screen *screen, softpipe->cbuf_cache[i] = sp_create_tile_cache( &softpipe->pipe ); softpipe->zsbuf_cache = sp_create_tile_cache( &softpipe->pipe ); - for (i = 0; i < PIPE_MAX_SAMPLERS; i++) - softpipe->tex_cache[i] = sp_create_tex_tile_cache( &softpipe->pipe ); + for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { + softpipe->fragment_tex_cache[i] = sp_create_tex_tile_cache( &softpipe->pipe ); + if (!softpipe->fragment_tex_cache[i]) + goto fail; + } + for (i = 0; i < PIPE_MAX_VERTEX_SAMPLERS; i++) { softpipe->vertex_tex_cache[i] = sp_create_tex_tile_cache( &softpipe->pipe ); + if (!softpipe->vertex_tex_cache[i]) + goto fail; } + for (i = 0; i < PIPE_MAX_GEOMETRY_SAMPLERS; i++) { softpipe->geometry_tex_cache[i] = sp_create_tex_tile_cache( &softpipe->pipe ); + if (!softpipe->geometry_tex_cache[i]) + goto fail; } softpipe->fs_machine = tgsi_exec_machine_create(); diff --git a/src/gallium/drivers/softpipe/sp_context.h b/src/gallium/drivers/softpipe/sp_context.h index 903574b7e19..035d712d17c 100644 --- a/src/gallium/drivers/softpipe/sp_context.h +++ b/src/gallium/drivers/softpipe/sp_context.h @@ -77,7 +77,7 @@ struct softpipe_context { struct pipe_framebuffer_state framebuffer; struct pipe_poly_stipple poly_stipple; struct pipe_scissor_state scissor; - struct pipe_sampler_view *sampler_views[PIPE_MAX_SAMPLERS]; + struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS]; struct pipe_sampler_view *vertex_sampler_views[PIPE_MAX_VERTEX_SAMPLERS]; struct pipe_sampler_view *geometry_sampler_views[PIPE_MAX_GEOMETRY_SAMPLERS]; struct pipe_viewport_state viewport; @@ -174,7 +174,7 @@ struct softpipe_context { struct softpipe_tile_cache *zsbuf_cache; unsigned tex_timestamp; - struct softpipe_tex_tile_cache *tex_cache[PIPE_MAX_SAMPLERS]; + struct softpipe_tex_tile_cache *fragment_tex_cache[PIPE_MAX_SAMPLERS]; struct softpipe_tex_tile_cache *vertex_tex_cache[PIPE_MAX_VERTEX_SAMPLERS]; struct softpipe_tex_tile_cache *geometry_tex_cache[PIPE_MAX_GEOMETRY_SAMPLERS]; diff --git a/src/gallium/drivers/softpipe/sp_flush.c b/src/gallium/drivers/softpipe/sp_flush.c index 4258395063b..d422cb17a4b 100644 --- a/src/gallium/drivers/softpipe/sp_flush.c +++ b/src/gallium/drivers/softpipe/sp_flush.c @@ -52,7 +52,7 @@ softpipe_flush( struct pipe_context *pipe, if (flags & PIPE_FLUSH_TEXTURE_CACHE) { for (i = 0; i < softpipe->num_sampler_views; i++) { - sp_flush_tex_tile_cache(softpipe->tex_cache[i]); + sp_flush_tex_tile_cache(softpipe->fragment_tex_cache[i]); } for (i = 0; i < softpipe->num_vertex_sampler_views; i++) { sp_flush_tex_tile_cache(softpipe->vertex_tex_cache[i]); diff --git a/src/gallium/drivers/softpipe/sp_state_derived.c b/src/gallium/drivers/softpipe/sp_state_derived.c index bf4c12701af..f9590eb0b24 100644 --- a/src/gallium/drivers/softpipe/sp_state_derived.c +++ b/src/gallium/drivers/softpipe/sp_state_derived.c @@ -200,8 +200,8 @@ update_tgsi_samplers( struct softpipe_context *softpipe ) softpipe_reset_sampler_variants( softpipe ); for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { - struct softpipe_tex_tile_cache *tc = softpipe->tex_cache[i]; - if (tc->texture) { + struct softpipe_tex_tile_cache *tc = softpipe->fragment_tex_cache[i]; + if (tc && tc->texture) { struct softpipe_resource *spt = softpipe_resource(tc->texture); if (spt->timestamp != tc->timestamp) { sp_tex_tile_cache_validate_texture( tc ); @@ -216,7 +216,7 @@ update_tgsi_samplers( struct softpipe_context *softpipe ) for (i = 0; i < PIPE_MAX_VERTEX_SAMPLERS; i++) { struct softpipe_tex_tile_cache *tc = softpipe->vertex_tex_cache[i]; - if (tc->texture) { + if (tc && tc->texture) { struct softpipe_resource *spt = softpipe_resource(tc->texture); if (spt->timestamp != tc->timestamp) { @@ -229,7 +229,7 @@ update_tgsi_samplers( struct softpipe_context *softpipe ) for (i = 0; i < PIPE_MAX_GEOMETRY_SAMPLERS; i++) { struct softpipe_tex_tile_cache *tc = softpipe->geometry_tex_cache[i]; - if (tc->texture) { + if (tc && tc->texture) { struct softpipe_resource *spt = softpipe_resource(tc->texture); if (spt->timestamp != tc->timestamp) { diff --git a/src/gallium/drivers/softpipe/sp_state_sampler.c b/src/gallium/drivers/softpipe/sp_state_sampler.c index cfa211b60a0..38943563800 100644 --- a/src/gallium/drivers/softpipe/sp_state_sampler.c +++ b/src/gallium/drivers/softpipe/sp_state_sampler.c @@ -67,8 +67,8 @@ softpipe_create_sampler_state(struct pipe_context *pipe, static void -softpipe_bind_sampler_states(struct pipe_context *pipe, - unsigned num, void **sampler) +softpipe_bind_fragment_sampler_states(struct pipe_context *pipe, + unsigned num, void **sampler) { struct softpipe_context *softpipe = softpipe_context(pipe); unsigned i; @@ -181,9 +181,9 @@ softpipe_sampler_view_destroy(struct pipe_context *pipe, static void -softpipe_set_sampler_views(struct pipe_context *pipe, - unsigned num, - struct pipe_sampler_view **views) +softpipe_set_fragment_sampler_views(struct pipe_context *pipe, + unsigned num, + struct pipe_sampler_view **views) { struct softpipe_context *softpipe = softpipe_context(pipe); uint i; @@ -192,7 +192,8 @@ softpipe_set_sampler_views(struct pipe_context *pipe, /* Check for no-op */ if (num == softpipe->num_sampler_views && - !memcmp(softpipe->sampler_views, views, num * sizeof(struct pipe_sampler_view *))) + !memcmp(softpipe->fragment_sampler_views, views, + num * sizeof(struct pipe_sampler_view *))) return; draw_flush(softpipe->draw); @@ -200,8 +201,8 @@ softpipe_set_sampler_views(struct pipe_context *pipe, for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { struct pipe_sampler_view *view = i < num ? views[i] : NULL; - pipe_sampler_view_reference(&softpipe->sampler_views[i], view); - sp_tex_tile_cache_set_sampler_view(softpipe->tex_cache[i], view); + pipe_sampler_view_reference(&softpipe->fragment_sampler_views[i], view); + sp_tex_tile_cache_set_sampler_view(softpipe->fragment_tex_cache[i], view); } softpipe->num_sampler_views = num; @@ -290,10 +291,9 @@ static struct sp_sampler_variant * get_sampler_variant( unsigned unit, struct sp_sampler *sampler, struct pipe_sampler_view *view, - struct pipe_resource *resource, unsigned processor ) { - struct softpipe_resource *sp_texture = softpipe_resource(resource); + struct softpipe_resource *sp_texture = softpipe_resource(view->texture); struct sp_sampler_variant *v = NULL; union sp_sampler_key key; @@ -343,68 +343,47 @@ softpipe_reset_sampler_variants(struct softpipe_context *softpipe) */ for (i = 0; i <= softpipe->vs->max_sampler; i++) { if (softpipe->vertex_samplers[i]) { - struct pipe_resource *texture = NULL; - - if (softpipe->vertex_sampler_views[i]) { - texture = softpipe->vertex_sampler_views[i]->texture; - } - softpipe->tgsi.vert_samplers_list[i] = get_sampler_variant( i, sp_sampler(softpipe->vertex_samplers[i]), softpipe->vertex_sampler_views[i], - texture, TGSI_PROCESSOR_VERTEX ); - sp_sampler_variant_bind_texture( softpipe->tgsi.vert_samplers_list[i], - softpipe->vertex_tex_cache[i], - texture ); + sp_sampler_variant_bind_view( softpipe->tgsi.vert_samplers_list[i], + softpipe->vertex_tex_cache[i], + softpipe->vertex_sampler_views[i] ); } } if (softpipe->gs) { for (i = 0; i <= softpipe->gs->max_sampler; i++) { if (softpipe->geometry_samplers[i]) { - struct pipe_resource *texture = NULL; - - if (softpipe->geometry_sampler_views[i]) { - texture = softpipe->geometry_sampler_views[i]->texture; - } - softpipe->tgsi.geom_samplers_list[i] = get_sampler_variant( i, sp_sampler(softpipe->geometry_samplers[i]), softpipe->geometry_sampler_views[i], - texture, TGSI_PROCESSOR_GEOMETRY ); - sp_sampler_variant_bind_texture( + sp_sampler_variant_bind_view( softpipe->tgsi.geom_samplers_list[i], softpipe->geometry_tex_cache[i], - texture ); + softpipe->geometry_sampler_views[i] ); } } } for (i = 0; i <= softpipe->fs->info.file_max[TGSI_FILE_SAMPLER]; i++) { if (softpipe->sampler[i]) { - struct pipe_resource *texture = NULL; - - if (softpipe->sampler_views[i]) { - texture = softpipe->sampler_views[i]->texture; - } - softpipe->tgsi.frag_samplers_list[i] = get_sampler_variant( i, sp_sampler(softpipe->sampler[i]), - softpipe->sampler_views[i], - texture, + softpipe->fragment_sampler_views[i], TGSI_PROCESSOR_FRAGMENT ); - sp_sampler_variant_bind_texture( softpipe->tgsi.frag_samplers_list[i], - softpipe->tex_cache[i], - texture ); + sp_sampler_variant_bind_view( softpipe->tgsi.frag_samplers_list[i], + softpipe->fragment_tex_cache[i], + softpipe->fragment_sampler_views[i] ); } } } @@ -429,12 +408,12 @@ void softpipe_init_sampler_funcs(struct pipe_context *pipe) { pipe->create_sampler_state = softpipe_create_sampler_state; - pipe->bind_fragment_sampler_states = softpipe_bind_sampler_states; + pipe->bind_fragment_sampler_states = softpipe_bind_fragment_sampler_states; pipe->bind_vertex_sampler_states = softpipe_bind_vertex_sampler_states; pipe->bind_geometry_sampler_states = softpipe_bind_geometry_sampler_states; pipe->delete_sampler_state = softpipe_delete_sampler_state; - pipe->set_fragment_sampler_views = softpipe_set_sampler_views; + pipe->set_fragment_sampler_views = softpipe_set_fragment_sampler_views; pipe->set_vertex_sampler_views = softpipe_set_vertex_sampler_views; pipe->set_geometry_sampler_views = softpipe_set_geometry_sampler_views; diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c index cbc40d4b446..242c27c7ebd 100644 --- a/src/gallium/drivers/softpipe/sp_tex_sample.c +++ b/src/gallium/drivers/softpipe/sp_tex_sample.c @@ -550,7 +550,7 @@ compute_lambda_1d(const struct sp_sampler_variant *samp, const float t[QUAD_SIZE], const float p[QUAD_SIZE]) { - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; float dsdx = fabsf(s[QUAD_BOTTOM_RIGHT] - s[QUAD_BOTTOM_LEFT]); float dsdy = fabsf(s[QUAD_TOP_LEFT] - s[QUAD_BOTTOM_LEFT]); float rho = MAX2(dsdx, dsdy) * texture->width0; @@ -565,7 +565,7 @@ compute_lambda_2d(const struct sp_sampler_variant *samp, const float t[QUAD_SIZE], const float p[QUAD_SIZE]) { - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; float dsdx = fabsf(s[QUAD_BOTTOM_RIGHT] - s[QUAD_BOTTOM_LEFT]); float dsdy = fabsf(s[QUAD_TOP_LEFT] - s[QUAD_BOTTOM_LEFT]); float dtdx = fabsf(t[QUAD_BOTTOM_RIGHT] - t[QUAD_BOTTOM_LEFT]); @@ -584,7 +584,7 @@ compute_lambda_3d(const struct sp_sampler_variant *samp, const float t[QUAD_SIZE], const float p[QUAD_SIZE]) { - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; float dsdx = fabsf(s[QUAD_BOTTOM_RIGHT] - s[QUAD_BOTTOM_LEFT]); float dsdy = fabsf(s[QUAD_TOP_LEFT] - s[QUAD_BOTTOM_LEFT]); float dtdx = fabsf(t[QUAD_BOTTOM_RIGHT] - t[QUAD_BOTTOM_LEFT]); @@ -654,7 +654,7 @@ static INLINE const float * get_texel_2d(const struct sp_sampler_variant *samp, union tex_tile_address addr, int x, int y) { - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level = addr.bits.level; if (x < 0 || x >= (int) u_minify(texture->width0, level) || @@ -747,7 +747,7 @@ static INLINE const float * get_texel_3d(const struct sp_sampler_variant *samp, union tex_tile_address addr, int x, int y, int z) { - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level = addr.bits.level; if (x < 0 || x >= (int) u_minify(texture->width0, level) || @@ -959,7 +959,7 @@ img_filter_1d_nearest(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width; int x[4]; @@ -999,7 +999,7 @@ img_filter_2d_nearest(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width, height; int x[4], y[4]; @@ -1051,7 +1051,7 @@ img_filter_cube_nearest(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; const unsigned *faces = samp->faces; /* zero when not cube-mapping */ unsigned level0, j; int width, height; @@ -1095,7 +1095,7 @@ img_filter_3d_nearest(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width, height, depth; int x[4], y[4], z[4]; @@ -1137,7 +1137,7 @@ img_filter_1d_linear(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width; int x0[4], x1[4]; @@ -1177,7 +1177,7 @@ img_filter_2d_linear(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width, height; int x0[4], y0[4], x1[4], y1[4]; @@ -1224,7 +1224,7 @@ img_filter_cube_linear(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; const unsigned *faces = samp->faces; /* zero when not cube-mapping */ unsigned level0, j; int width, height; @@ -1273,7 +1273,7 @@ img_filter_3d_linear(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { const struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; unsigned level0, j; int width, height, depth; int x0[4], x1[4], y0[4], y1[4], z0[4], z1[4]; @@ -1349,7 +1349,7 @@ mip_filter_linear(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; int level0; float lambda; float lod[QUAD_SIZE]; @@ -1416,7 +1416,7 @@ mip_filter_nearest(struct tgsi_sampler *tgsi_sampler, float rgba[NUM_CHANNELS][QUAD_SIZE]) { struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; float lambda; float lod[QUAD_SIZE]; @@ -1500,7 +1500,7 @@ mip_filter_linear_2d_linear_repeat_POT( float rgba[NUM_CHANNELS][QUAD_SIZE]) { struct sp_sampler_variant *samp = sp_sampler_variant(tgsi_sampler); - const struct pipe_resource *texture = samp->texture; + const struct pipe_resource *texture = samp->view->texture; int level0; float lambda; float lod[QUAD_SIZE]; @@ -1990,13 +1990,14 @@ get_img_filter(const union sp_sampler_key key, * Bind the given texture object and texture cache to the sampler variant. */ void -sp_sampler_variant_bind_texture( struct sp_sampler_variant *samp, - struct softpipe_tex_tile_cache *tex_cache, - const struct pipe_resource *texture ) +sp_sampler_variant_bind_view( struct sp_sampler_variant *samp, + struct softpipe_tex_tile_cache *tex_cache, + const struct pipe_sampler_view *view ) { const struct pipe_sampler_state *sampler = samp->sampler; + const struct pipe_resource *texture = view->texture; - samp->texture = texture; + samp->view = view; samp->cache = tex_cache; samp->xpot = util_unsigned_logbase2( texture->width0 ); samp->ypot = util_unsigned_logbase2( texture->height0 ); diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.h b/src/gallium/drivers/softpipe/sp_tex_sample.h index ed99006ab02..f0b867edc6e 100644 --- a/src/gallium/drivers/softpipe/sp_tex_sample.h +++ b/src/gallium/drivers/softpipe/sp_tex_sample.h @@ -89,7 +89,7 @@ struct sp_sampler_variant /* Currently bound texture: */ - const struct pipe_resource *texture; + const struct pipe_sampler_view *view; struct softpipe_tex_tile_cache *cache; unsigned processor; @@ -132,9 +132,9 @@ struct sp_sampler_variant * sp_create_sampler_variant( const struct pipe_sampler_state *sampler, const union sp_sampler_key key ); -void sp_sampler_variant_bind_texture( struct sp_sampler_variant *variant, - struct softpipe_tex_tile_cache *tex_cache, - const struct pipe_resource *tex ); +void sp_sampler_variant_bind_view( struct sp_sampler_variant *variant, + struct softpipe_tex_tile_cache *tex_cache, + const struct pipe_sampler_view *view ); void sp_sampler_variant_destroy( struct sp_sampler_variant * ); |