2 files changed, 1 insertions, 53 deletions

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 105a1b2a878..76913914b38 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -308,7 +308,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
 			}
 
 			mtilew = (8 * rsrc->surface.bankw *
-				  sctx->screen->b.tiling_info.num_channels) *
+				  sctx->screen->b.info.num_tile_pipes) *
 				rsrc->surface.mtilea;
 			assert(!(mtilew & (mtilew - 1)));
 			mtileh = (8 * rsrc->surface.bankh * num_banks) /
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 4ed8415e242..2599197ee73 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -552,57 +552,6 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 	r600_destroy_common_screen(&sscreen->b);
 }
 
-#define SI_TILE_MODE_COLOR_2D_8BPP  14
-
-/* Initialize pipe config. This is especially important for GPUs
- * with 16 pipes and more where it's initialized incorrectly by
- * the TILING_CONFIG ioctl. */
-static bool si_initialize_pipe_config(struct si_screen *sscreen)
-{
-	unsigned mode2d;
-
-	/* This is okay, because there can be no 2D tiling without
-	 * the tile mode array, so we won't need the pipe config.
-	 * Return "success".
-	 */
-	if (!sscreen->b.info.si_tile_mode_array_valid)
-		return true;
-
-	/* The same index is used for the 2D mode on CIK too. */
-	mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
-
-	switch (G_009910_PIPE_CONFIG(mode2d)) {
-	case V_02803C_ADDR_SURF_P2:
-		sscreen->b.tiling_info.num_channels = 2;
-		break;
-	case V_02803C_X_ADDR_SURF_P4_8X16:
-	case V_02803C_X_ADDR_SURF_P4_16X16:
-	case V_02803C_X_ADDR_SURF_P4_16X32:
-	case V_02803C_X_ADDR_SURF_P4_32X32:
-		sscreen->b.tiling_info.num_channels = 4;
-		break;
-	case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
-	case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
-	case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
-	case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
-	case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
-	case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
-	case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
-		sscreen->b.tiling_info.num_channels = 8;
-		break;
-	case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
-	case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
-		sscreen->b.tiling_info.num_channels = 16;
-		break;
-	default:
-		assert(0);
-		fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
-			G_009910_PIPE_CONFIG(mode2d));
-		return false;
-	}
-	return true;
-}
-
 static bool si_init_gs_info(struct si_screen *sscreen)
 {
 	switch (sscreen->b.family) {
@@ -647,7 +596,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 	sscreen->b.b.resource_create = r600_resource_create_common;
 
 	if (!r600_common_screen_init(&sscreen->b, ws) ||
-	    !si_initialize_pipe_config(sscreen) ||
 	    !si_init_gs_info(sscreen)) {
 		FREE(sscreen);
 		return NULL;