diff options
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index a395ec4f2d1..7eac477327a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2480,13 +2480,13 @@ static void si_delete_sampler_state(struct pipe_context *ctx, void *state) * Constants */ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, - struct pipe_constant_buffer *cb) + struct pipe_constant_buffer *cb) { struct r600_context *rctx = (struct r600_context *)ctx; struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL; struct si_pm4_state *pm4; - uint64_t va_offset; - uint32_t reg, offset; + uint32_t offset; + uint64_t va; /* Note that the state tracker can unbind constant buffers by * passing NULL here. @@ -2501,23 +2501,33 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset); else offset = 0; - va_offset = r600_resource_va(ctx->screen, (void*)rbuffer); - va_offset += offset; + va = r600_resource_va(ctx->screen, (void*)rbuffer); + va += offset; si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); + si_pm4_sh_data_begin(pm4); + + /* Fill in a T# buffer resource description */ + si_pm4_sh_data_add(pm4, va); + si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) | + S_008F04_STRIDE(0))); + si_pm4_sh_data_add(pm4, cb->buffer_size); + si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | + S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | + S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | + S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | + S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | + S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32)); + switch (shader) { case PIPE_SHADER_VERTEX: - reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4; - si_pm4_set_reg(pm4, reg, va_offset); - si_pm4_set_reg(pm4, reg + 4, va_offset >> 32); + si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST); si_pm4_set_state(rctx, vs_const, pm4); break; case PIPE_SHADER_FRAGMENT: - reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4; - si_pm4_set_reg(pm4, reg, va_offset); - si_pm4_set_reg(pm4, reg + 4, va_offset >> 32); + si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST); si_pm4_set_state(rctx, ps_const, pm4); break; |